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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: niu_rdmc_shadow_ram_ctrl.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module niu_rdmc_shadow_ram_ctrl ( | |
36 | clk, | |
37 | reset, | |
38 | shadw_wr_en, | |
39 | shadw_wr_even, | |
40 | shadw_wr_ptr0, | |
41 | shadw_wr_ptr1, | |
42 | shadw_wr_ptr2, | |
43 | shadw_wr_ptr3, | |
44 | shadw_wr_ptr4, | |
45 | shadw_wr_ptr5, | |
46 | shadw_wr_ptr6, | |
47 | shadw_wr_ptr7, | |
48 | shadw_wr_ptr8, | |
49 | shadw_wr_ptr9, | |
50 | shadw_wr_ptr10, | |
51 | shadw_wr_ptr11, | |
52 | shadw_wr_ptr12, | |
53 | shadw_wr_ptr13, | |
54 | shadw_wr_ptr14, | |
55 | shadw_wr_ptr15, | |
56 | shadw_rd_ptr0, | |
57 | shadw_rd_ptr1, | |
58 | shadw_rd_ptr2, | |
59 | shadw_rd_ptr3, | |
60 | shadw_rd_ptr4, | |
61 | shadw_rd_ptr5, | |
62 | shadw_rd_ptr6, | |
63 | shadw_rd_ptr7, | |
64 | shadw_rd_ptr8, | |
65 | shadw_rd_ptr9, | |
66 | shadw_rd_ptr10, | |
67 | shadw_rd_ptr11, | |
68 | shadw_rd_ptr12, | |
69 | shadw_rd_ptr13, | |
70 | shadw_rd_ptr14, | |
71 | shadw_rd_ptr15, | |
72 | muxed_data_err_r2, | |
73 | rdmc_meta0_wr_transfer_comp_int, | |
74 | rcr_wrbk_data, | |
75 | rcr_wrbk_sched, | |
76 | rdmc_rcr_req_accept, | |
77 | shadw_rd_strobe, | |
78 | ||
79 | data_err_event, | |
80 | shadw_wr_strobe, | |
81 | shadw_wr_addr, | |
82 | shadw_wr_data, | |
83 | shadw_rd_addr | |
84 | ||
85 | ); | |
86 | ||
87 | ||
88 | ||
89 | input clk; | |
90 | input reset; | |
91 | input[15:0] shadw_wr_en; | |
92 | input[15:0] shadw_wr_even; | |
93 | input[7:0] shadw_wr_ptr0; | |
94 | input[7:0] shadw_wr_ptr1; | |
95 | input[7:0] shadw_wr_ptr2; | |
96 | input[7:0] shadw_wr_ptr3; | |
97 | input[7:0] shadw_wr_ptr4; | |
98 | input[7:0] shadw_wr_ptr5; | |
99 | input[7:0] shadw_wr_ptr6; | |
100 | input[7:0] shadw_wr_ptr7; | |
101 | input[7:0] shadw_wr_ptr8; | |
102 | input[7:0] shadw_wr_ptr9; | |
103 | input[7:0] shadw_wr_ptr10; | |
104 | input[7:0] shadw_wr_ptr11; | |
105 | input[7:0] shadw_wr_ptr12; | |
106 | input[7:0] shadw_wr_ptr13; | |
107 | input[7:0] shadw_wr_ptr14; | |
108 | input[7:0] shadw_wr_ptr15; | |
109 | input[7:0] shadw_rd_ptr0; | |
110 | input[7:0] shadw_rd_ptr1; | |
111 | input[7:0] shadw_rd_ptr2; | |
112 | input[7:0] shadw_rd_ptr3; | |
113 | input[7:0] shadw_rd_ptr4; | |
114 | input[7:0] shadw_rd_ptr5; | |
115 | input[7:0] shadw_rd_ptr6; | |
116 | input[7:0] shadw_rd_ptr7; | |
117 | input[7:0] shadw_rd_ptr8; | |
118 | input[7:0] shadw_rd_ptr9; | |
119 | input[7:0] shadw_rd_ptr10; | |
120 | input[7:0] shadw_rd_ptr11; | |
121 | input[7:0] shadw_rd_ptr12; | |
122 | input[7:0] shadw_rd_ptr13; | |
123 | input[7:0] shadw_rd_ptr14; | |
124 | input[7:0] shadw_rd_ptr15; | |
125 | input muxed_data_err_r2; | |
126 | input rdmc_meta0_wr_transfer_comp_int; | |
127 | input[63:0] rcr_wrbk_data; | |
128 | input[15:0] rcr_wrbk_sched; | |
129 | input rdmc_rcr_req_accept; | |
130 | input shadw_rd_strobe; | |
131 | ||
132 | output data_err_event; | |
133 | output shadw_wr_strobe; | |
134 | output[7:0] shadw_wr_addr; | |
135 | output[147:0] shadw_wr_data; | |
136 | output[7:0] shadw_rd_addr; | |
137 | ||
138 | reg shadw_wr_strobe; | |
139 | reg[7:0] shadw_wr_addr; | |
140 | reg[147:0] shadw_wr_data; | |
141 | reg[7:0] shadw_rd_addr; | |
142 | ||
143 | reg shadw_wr_even_r; | |
144 | ||
145 | reg[15:0] shadw_wr_en_dly; | |
146 | reg[71:0] rcr_wrbk_data_sav_array[0:15]; | |
147 | ||
148 | integer i; | |
149 | ||
150 | wire[71:0] rcr_wrbk_data_sav = {72{shadw_wr_en_dly[0]}} & rcr_wrbk_data_sav_array[0] | | |
151 | {72{shadw_wr_en_dly[1]}} & rcr_wrbk_data_sav_array[1] | | |
152 | {72{shadw_wr_en_dly[2]}} & rcr_wrbk_data_sav_array[2] | | |
153 | {72{shadw_wr_en_dly[3]}} & rcr_wrbk_data_sav_array[3] | | |
154 | {72{shadw_wr_en_dly[4]}} & rcr_wrbk_data_sav_array[4] | | |
155 | {72{shadw_wr_en_dly[5]}} & rcr_wrbk_data_sav_array[5] | | |
156 | {72{shadw_wr_en_dly[6]}} & rcr_wrbk_data_sav_array[6] | | |
157 | {72{shadw_wr_en_dly[7]}} & rcr_wrbk_data_sav_array[7] | | |
158 | {72{shadw_wr_en_dly[8]}} & rcr_wrbk_data_sav_array[8] | | |
159 | {72{shadw_wr_en_dly[9]}} & rcr_wrbk_data_sav_array[9] | | |
160 | {72{shadw_wr_en_dly[10]}} & rcr_wrbk_data_sav_array[10] | | |
161 | {72{shadw_wr_en_dly[11]}} & rcr_wrbk_data_sav_array[11] | | |
162 | {72{shadw_wr_en_dly[12]}} & rcr_wrbk_data_sav_array[12] | | |
163 | {72{shadw_wr_en_dly[13]}} & rcr_wrbk_data_sav_array[13] | | |
164 | {72{shadw_wr_en_dly[14]}} & rcr_wrbk_data_sav_array[14] | | |
165 | {72{shadw_wr_en_dly[15]}} & rcr_wrbk_data_sav_array[15]; | |
166 | ||
167 | wire[7:0] shadw_wr_addr_tmp = {8{shadw_wr_en[0]}} & shadw_wr_ptr0 | | |
168 | {8{shadw_wr_en[1]}} & shadw_wr_ptr1 | | |
169 | {8{shadw_wr_en[2]}} & shadw_wr_ptr2 | | |
170 | {8{shadw_wr_en[3]}} & shadw_wr_ptr3 | | |
171 | {8{shadw_wr_en[4]}} & shadw_wr_ptr4 | | |
172 | {8{shadw_wr_en[5]}} & shadw_wr_ptr5 | | |
173 | {8{shadw_wr_en[6]}} & shadw_wr_ptr6 | | |
174 | {8{shadw_wr_en[7]}} & shadw_wr_ptr7 | | |
175 | {8{shadw_wr_en[8]}} & shadw_wr_ptr8 | | |
176 | {8{shadw_wr_en[9]}} & shadw_wr_ptr9 | | |
177 | {8{shadw_wr_en[10]}} & shadw_wr_ptr10 | | |
178 | {8{shadw_wr_en[11]}} & shadw_wr_ptr11 | | |
179 | {8{shadw_wr_en[12]}} & shadw_wr_ptr12 | | |
180 | {8{shadw_wr_en[13]}} & shadw_wr_ptr13 | | |
181 | {8{shadw_wr_en[14]}} & shadw_wr_ptr14 | | |
182 | {8{shadw_wr_en[15]}} & shadw_wr_ptr15; | |
183 | ||
184 | ||
185 | wire[7:0] shadw_rd_addr_tmp = {8{rcr_wrbk_sched[0]}} & shadw_rd_ptr0 | | |
186 | {8{rcr_wrbk_sched[1]}} & shadw_rd_ptr1 | | |
187 | {8{rcr_wrbk_sched[2]}} & shadw_rd_ptr2 | | |
188 | {8{rcr_wrbk_sched[3]}} & shadw_rd_ptr3 | | |
189 | {8{rcr_wrbk_sched[4]}} & shadw_rd_ptr4 | | |
190 | {8{rcr_wrbk_sched[5]}} & shadw_rd_ptr5 | | |
191 | {8{rcr_wrbk_sched[6]}} & shadw_rd_ptr6 | | |
192 | {8{rcr_wrbk_sched[7]}} & shadw_rd_ptr7 | | |
193 | {8{rcr_wrbk_sched[8]}} & shadw_rd_ptr8 | | |
194 | {8{rcr_wrbk_sched[9]}} & shadw_rd_ptr9 | | |
195 | {8{rcr_wrbk_sched[10]}} & shadw_rd_ptr10 | | |
196 | {8{rcr_wrbk_sched[11]}} & shadw_rd_ptr11 | | |
197 | {8{rcr_wrbk_sched[12]}} & shadw_rd_ptr12 | | |
198 | {8{rcr_wrbk_sched[13]}} & shadw_rd_ptr13 | | |
199 | {8{rcr_wrbk_sched[14]}} & shadw_rd_ptr14 | | |
200 | {8{rcr_wrbk_sched[15]}} & shadw_rd_ptr15; | |
201 | ||
202 | wire[63:0] new_rcr_wrbk_data = {rcr_wrbk_data[63:55], muxed_data_err_r2, rcr_wrbk_data[53:0]}; | |
203 | wire[7:0] new_parity_bits = {^new_rcr_wrbk_data[63:56], | |
204 | ^new_rcr_wrbk_data[55:48], | |
205 | ^new_rcr_wrbk_data[47:40], | |
206 | ^new_rcr_wrbk_data[39:32], | |
207 | ^new_rcr_wrbk_data[31:24], | |
208 | ^new_rcr_wrbk_data[23:16], | |
209 | ^new_rcr_wrbk_data[15:8], | |
210 | ^new_rcr_wrbk_data[7:0]}; | |
211 | ||
212 | ||
213 | wire[147:0] rcr_wrbk_data_tmp1 = {new_parity_bits, rcr_wrbk_data_sav[71:64], 4'b0, new_rcr_wrbk_data, rcr_wrbk_data_sav[63:0]}; | |
214 | wire[147:0] rcr_wrbk_data_tmp2 = {8'b0, new_parity_bits, 4'b0, 64'b0, new_rcr_wrbk_data[63:0]}; | |
215 | wire[147:0] shadw_wr_data_in = shadw_wr_even_r ? rcr_wrbk_data_tmp1 : rcr_wrbk_data_tmp2; | |
216 | ||
217 | wire shadw_wr_even_tmp = |(shadw_wr_en & shadw_wr_even); | |
218 | wire shadw_wr_en_all = |shadw_wr_en; | |
219 | wire shadw_wr_en_dly_all = |shadw_wr_en_dly; | |
220 | ||
221 | ||
222 | always @ (posedge clk) | |
223 | if (reset) | |
224 | shadw_wr_strobe <= 1'b0; | |
225 | else | |
226 | shadw_wr_strobe <= rdmc_meta0_wr_transfer_comp_int & shadw_wr_en_dly_all; | |
227 | ||
228 | always @ (posedge clk) | |
229 | if (reset) | |
230 | shadw_wr_even_r <= 1'b0; | |
231 | else if (shadw_wr_en_all) | |
232 | shadw_wr_even_r <= shadw_wr_even_tmp; | |
233 | else | |
234 | shadw_wr_even_r <= shadw_wr_even_r; | |
235 | ||
236 | always @ (posedge clk) | |
237 | if (reset) | |
238 | shadw_wr_addr <= 8'b0; | |
239 | else if (shadw_wr_en_all) | |
240 | shadw_wr_addr <= shadw_wr_addr_tmp; | |
241 | else | |
242 | shadw_wr_addr <= shadw_wr_addr; | |
243 | ||
244 | ||
245 | always @ (posedge clk) | |
246 | if (reset) | |
247 | shadw_wr_data <= 148'b0; | |
248 | else if (rdmc_meta0_wr_transfer_comp_int) | |
249 | shadw_wr_data <= shadw_wr_data_in; | |
250 | else | |
251 | shadw_wr_data <= shadw_wr_data; | |
252 | ||
253 | ||
254 | always @ (posedge clk) | |
255 | if (reset) | |
256 | shadw_rd_addr <= 8'b0; | |
257 | else if (rdmc_rcr_req_accept) | |
258 | shadw_rd_addr <= shadw_rd_addr_tmp; | |
259 | else if (shadw_rd_strobe) | |
260 | shadw_rd_addr <= shadw_rd_addr + 8'd1; | |
261 | else | |
262 | shadw_rd_addr <= shadw_rd_addr; | |
263 | ||
264 | ||
265 | wire data_err_event = rdmc_meta0_wr_transfer_comp_int & muxed_data_err_r2; | |
266 | ||
267 | always @ (posedge clk) | |
268 | if (reset) | |
269 | shadw_wr_en_dly <= 16'b0; | |
270 | else if (shadw_wr_en_all) | |
271 | shadw_wr_en_dly <= shadw_wr_en[15:0]; | |
272 | else if (rdmc_meta0_wr_transfer_comp_int) | |
273 | shadw_wr_en_dly <= 16'b0; | |
274 | else | |
275 | shadw_wr_en_dly <= shadw_wr_en_dly; | |
276 | ||
277 | always @ (posedge clk) | |
278 | if (rdmc_meta0_wr_transfer_comp_int) | |
279 | begin | |
280 | for (i=0; i<=15; i=i+1) | |
281 | if (shadw_wr_en_dly[i]) | |
282 | rcr_wrbk_data_sav_array[i] <= {new_parity_bits, new_rcr_wrbk_data}; | |
283 | else | |
284 | rcr_wrbk_data_sav_array[i] <= rcr_wrbk_data_sav_array[i]; | |
285 | end | |
286 | ||
287 | endmodule | |
288 | ||
289 | ||
290 | ||
291 | ||
292 | ||
293 | ||
294 | ||
295 |