[OpenSPARC-T2-DV] / design / sys / iop / niu / rtl / niu_rdmc_wr_dp_sm.v

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: niu_rdmc_wr_dp_sm.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module niu_rdmc_wr_dp_sm (
				clk,
				reset,
				full_hdr_r1,
				ipp_data_req_dly2,
				rdmc_wr_req_accept_hdr,
				rdmc_wr_req_accept_zcp,
				muxed_ipp_data_ack,
				rdmc_cal_eop_r,
				ipp_next_eop,
				ipp_fzcp_eop,
				pkt_req_cnt_done,
				pkt_req_cnt_done_r,
				pkt_req_cnt_done_r1,
				pkt_req_cnt_done_r2,
				jmb_pkt_type,
				zcopy_mode,
				zcp_wr_type,

				offset_reg_en,
				offset_sel,
				wr_idle_state,
				rdmc_wr_data_sel,
				rdmc_wr_data_valid_sm,
				rdmc_wr_data_comp_sm,
				rdmc_wr_last_comp_sm,
				jmb_wr_cycle_sm,
				wr_dp_sm_state
				);

input		clk;
input		reset;
input		full_hdr_r1;
input		ipp_data_req_dly2;
input		rdmc_wr_req_accept_hdr;
input		rdmc_wr_req_accept_zcp;
input		muxed_ipp_data_ack;
input		rdmc_cal_eop_r;
input		ipp_next_eop;
input		ipp_fzcp_eop;
input		pkt_req_cnt_done;
input		pkt_req_cnt_done_r;
input		pkt_req_cnt_done_r1;
input		pkt_req_cnt_done_r2;
input[1:0]	jmb_pkt_type;		//01:use one buf, 10:use two buf, 11:use three buf
input		zcopy_mode;
input[1:0]	zcp_wr_type;		//00:one dmaw, ... 11:four dmaw

output		offset_reg_en;
output[1:0]	offset_sel;
output		wr_idle_state;
output[1:0]	rdmc_wr_data_sel;
output		rdmc_wr_data_valid_sm;
output		rdmc_wr_data_comp_sm;
output		rdmc_wr_last_comp_sm;
output		jmb_wr_cycle_sm;
output[4:0]	wr_dp_sm_state;

reg             offset_reg_en;
reg[1:0]        offset_sel;
reg		wr_idle_state;
reg             ready_cycle;
reg[1:0]        rdmc_wr_data_sel;
reg             rdmc_wr_data_valid_sm;
reg             rdmc_wr_data_comp_sm;
reg		rdmc_wr_last_comp_sm;
reg             inc_zcp_wr_cnt;
reg             jmb_pkt_done_sm;
reg		jmb_wr_cycle_sm;
reg[4:0]        state;
reg[4:0]        next_state;

reg		ready_cycle_reg;
reg		is_rdmc_wr_req_accept;
reg[1:0]	zcp_wr_cnt;
reg		jmb_pkt_done;

wire[4:0]	wr_dp_sm_state = state;
wire		zcp_wr_done;


parameter

IDLE			= 5'd16,
READY			= 5'd0,
FIRST_HDR		= 5'd1,
JMB_WR_DATA		= 5'd2,
WR_DATA			= 5'd3,
WAIT_DATA_LAST		= 5'd4,
WR_DATA_LAST		= 5'd5,
ZCP_WR_HDR		= 5'd6,
WAIT_ZCP_HDR_LAST	= 5'd7,
ZCP_WR_HDR_LAST		= 5'd8,
ZCP_READY		= 5'd9,
ZCP_WR_MID		= 5'd10,
WAIT_ZCP_MID_LAST	= 5'd11,
ZCP_WR_MID_LAST		= 5'd12,
ZCP_WR_DATA		= 5'd13,
WAIT_ZCP_DATA_LAST	= 5'd14,
ZCP_WR_DATA_LAST	= 5'd15; 

always @ (state or full_hdr_r1 or ipp_data_req_dly2 or
	  jmb_pkt_type or jmb_pkt_done or 
	  zcopy_mode or zcp_wr_done or
	  rdmc_wr_req_accept_hdr or rdmc_wr_req_accept_zcp or 
	  is_rdmc_wr_req_accept or muxed_ipp_data_ack or
	  pkt_req_cnt_done or pkt_req_cnt_done_r or
	  pkt_req_cnt_done_r1 or pkt_req_cnt_done_r2 or
	  rdmc_cal_eop_r or ipp_next_eop or ipp_fzcp_eop) 
	 
begin

	offset_reg_en		= 1'b0;
	offset_sel		= 2'b00;
	wr_idle_state		= 1'b0;
	ready_cycle		= 1'b0;
	rdmc_wr_data_sel	= 2'b00;
	rdmc_wr_data_valid_sm	= 1'b0;
	rdmc_wr_data_comp_sm	= 1'b0;
	rdmc_wr_last_comp_sm	= 1'b0;
	inc_zcp_wr_cnt		= 1'b0;
	jmb_pkt_done_sm		= 1'b0;
	jmb_wr_cycle_sm		= 1'b0;
	next_state		= 5'b0;

case (state)	//synopsys parallel_case full_case

IDLE:
begin
	wr_idle_state		= 1'b1;
	if (rdmc_wr_req_accept_hdr)
	begin
		offset_reg_en	= 1'b1;
		offset_sel	= 2'b00;
		next_state	= READY;
	end
	else
		next_state	= state;
end

READY:
begin
	ready_cycle	= 1'b1;
	if (ipp_data_req_dly2 & full_hdr_r1)
	begin
		rdmc_wr_data_sel        = 2'b00;
        	rdmc_wr_data_valid_sm   = 1'b1;
        	next_state              = FIRST_HDR;
	end
	else if (muxed_ipp_data_ack & ipp_data_req_dly2)
	begin
		rdmc_wr_data_sel        = 2'b01;
                rdmc_wr_data_valid_sm   = 1'b1;
		if (zcopy_mode)
			next_state	= ZCP_WR_HDR;
		else if (jmb_pkt_type[1]) 
			next_state	= JMB_WR_DATA;
		else
                	next_state      = WR_DATA;
	end
	else
		next_state		= state;
end


FIRST_HDR:
begin
	rdmc_wr_data_sel	= 2'b01;
	rdmc_wr_data_valid_sm	= 1'b1;
	if (jmb_pkt_type[1])	
		 next_state	= JMB_WR_DATA;
	else
		next_state	= WR_DATA;
end

JMB_WR_DATA:
begin
	jmb_wr_cycle_sm		= 1'b1;
	if (muxed_ipp_data_ack & pkt_req_cnt_done_r2 & rdmc_cal_eop_r)//second buf has only one transfer,
	begin							//no need to read ipp
		rdmc_wr_data_sel        = 2'b10;
                rdmc_wr_data_valid_sm   = 1'b1;
                rdmc_wr_data_comp_sm    = 1'b1;
                next_state              = WAIT_DATA_LAST;
        end

	else if (muxed_ipp_data_ack & pkt_req_cnt_done_r2 & jmb_pkt_type[0] & !jmb_pkt_done)
        begin
                rdmc_wr_data_sel        = 2'b10;
                rdmc_wr_data_valid_sm   = 1'b1;
                rdmc_wr_data_comp_sm    = 1'b1;
		jmb_pkt_done_sm		= 1'b1;
                next_state              = state;
        end

	else if (muxed_ipp_data_ack & pkt_req_cnt_done_r2)
	begin
		rdmc_wr_data_sel        = 2'b10;
                rdmc_wr_data_valid_sm   = 1'b1;
                rdmc_wr_data_comp_sm    = 1'b1;
                next_state              = WR_DATA;
        end
	else if (muxed_ipp_data_ack)
        begin
                rdmc_wr_data_sel        = 2'b10;
                rdmc_wr_data_valid_sm   = 1'b1;
                next_state              = state;
	end
	else
	begin
                rdmc_wr_data_sel        = 2'b10;
                rdmc_wr_data_valid_sm   = 1'b0;
                next_state              = state;
        end
end

WR_DATA:
begin
	if (muxed_ipp_data_ack & rdmc_cal_eop_r & pkt_req_cnt_done_r1)
	begin
		rdmc_wr_data_sel	= 2'b10;
		rdmc_wr_data_valid_sm	= 1'b1;
		next_state		= WR_DATA_LAST;
	end
	else if (muxed_ipp_data_ack & rdmc_cal_eop_r & pkt_req_cnt_done_r2)
	begin
		rdmc_wr_data_sel	= 2'b10;
		rdmc_wr_data_valid_sm	= 1'b1;
		rdmc_wr_data_comp_sm	= 1'b1;
		rdmc_wr_last_comp_sm	= 1'b1;
		if (rdmc_wr_req_accept_hdr | is_rdmc_wr_req_accept)
			next_state	= READY;
		else
			next_state	= IDLE;
	end
	else if (muxed_ipp_data_ack & rdmc_cal_eop_r)
	begin
		rdmc_wr_data_sel        = 2'b10;
                rdmc_wr_data_valid_sm   = 1'b1;
                next_state              = WAIT_DATA_LAST;
	end
	else if (muxed_ipp_data_ack)
	begin
		rdmc_wr_data_sel	= 2'b10;
		rdmc_wr_data_valid_sm	= 1'b1;
		next_state		= state;
	end
	else
	begin
		rdmc_wr_data_sel	= 2'b10;
		rdmc_wr_data_valid_sm	= 1'b0;
		next_state		= state;
	end
end

WAIT_DATA_LAST:
begin
	if (pkt_req_cnt_done_r | pkt_req_cnt_done_r1 | pkt_req_cnt_done)
		next_state	= WR_DATA_LAST;
	else
		next_state	= state; 
end

WR_DATA_LAST:
begin
                rdmc_wr_data_sel        = 2'b10;
                rdmc_wr_data_valid_sm   = 1'b1;
                rdmc_wr_data_comp_sm    = 1'b1;
		rdmc_wr_last_comp_sm	= 1'b1;
                if (rdmc_wr_req_accept_hdr | is_rdmc_wr_req_accept)
                        next_state      = READY;
                else
                        next_state      = IDLE;
end

ZCP_WR_HDR:
begin
	if (muxed_ipp_data_ack & ipp_fzcp_eop & pkt_req_cnt_done_r1)
        begin
                rdmc_wr_data_sel        = 2'b10;
                rdmc_wr_data_valid_sm   = 1'b1;
                next_state              = ZCP_WR_HDR_LAST;
        end
        else if (muxed_ipp_data_ack & ipp_fzcp_eop & pkt_req_cnt_done_r2)
        begin
                rdmc_wr_data_sel        = 2'b10;
                rdmc_wr_data_valid_sm   = 1'b1;
                rdmc_wr_data_comp_sm    = 1'b1;
		offset_reg_en		= 1'b1;
		offset_sel		= 2'b01;
                next_state      	= ZCP_READY;
        end
        else if (muxed_ipp_data_ack & ipp_fzcp_eop)
        begin
                rdmc_wr_data_sel        = 2'b10;
                rdmc_wr_data_valid_sm   = 1'b1;
                next_state              = WAIT_ZCP_HDR_LAST;
        end
        else if (muxed_ipp_data_ack)
        begin
                rdmc_wr_data_sel        = 2'b10;
                rdmc_wr_data_valid_sm   = 1'b1;
                next_state              = state;
        end
        else
        begin
                rdmc_wr_data_sel        = 2'b10;
                rdmc_wr_data_valid_sm   = 1'b0;
                next_state              = state;
        end
end

WAIT_ZCP_HDR_LAST:
begin
        if (pkt_req_cnt_done_r | pkt_req_cnt_done_r1 | pkt_req_cnt_done)
                next_state      = ZCP_WR_HDR_LAST;
        else
                next_state      = state;
end

ZCP_WR_HDR_LAST:
begin
                rdmc_wr_data_sel        = 2'b10;
                rdmc_wr_data_valid_sm   = 1'b1;
                rdmc_wr_data_comp_sm    = 1'b1;
		offset_reg_en           = 1'b1;
                offset_sel              = 2'b01;
                next_state      	= ZCP_READY;
end

ZCP_READY:
begin
	if (rdmc_wr_req_accept_zcp & zcp_wr_done & ipp_next_eop) 
		next_state	= WAIT_ZCP_DATA_LAST;
	else if (rdmc_wr_req_accept_zcp & zcp_wr_done)
		next_state	= ZCP_WR_DATA;
	else if (rdmc_wr_req_accept_zcp & ipp_next_eop)
	begin
		inc_zcp_wr_cnt	= 1'b1;
		next_state	= WAIT_ZCP_MID_LAST;
	end
	else if (rdmc_wr_req_accept_zcp)
	begin
		inc_zcp_wr_cnt	= 1'b1;
		next_state	= ZCP_WR_MID;
	end
	else
		next_state	= state;
end

ZCP_WR_MID:
begin
	if (muxed_ipp_data_ack & ipp_fzcp_eop & pkt_req_cnt_done_r1)
        begin
                rdmc_wr_data_sel        = 2'b10;
                rdmc_wr_data_valid_sm   = 1'b1;
                next_state              = ZCP_WR_MID_LAST;
        end
        else if (muxed_ipp_data_ack & ipp_fzcp_eop & pkt_req_cnt_done_r2)
        begin
                rdmc_wr_data_sel        = 2'b10;
                rdmc_wr_data_valid_sm   = 1'b1;
                rdmc_wr_data_comp_sm    = 1'b1;
		offset_reg_en   	= 1'b1;
                offset_sel      	= 2'b10;
                next_state              = ZCP_READY;
        end
        else if (muxed_ipp_data_ack & ipp_fzcp_eop)
        begin
                rdmc_wr_data_sel        = 2'b10;
                rdmc_wr_data_valid_sm   = 1'b1;
                next_state              = WAIT_ZCP_MID_LAST;
        end
        else if (muxed_ipp_data_ack)
        begin
                rdmc_wr_data_sel        = 2'b10;
                rdmc_wr_data_valid_sm   = 1'b1;
                next_state              = state;
        end
        else
        begin
                rdmc_wr_data_sel        = 2'b10;
                rdmc_wr_data_valid_sm   = 1'b0;
                next_state              = state;
        end
end

WAIT_ZCP_MID_LAST:
begin
        if (pkt_req_cnt_done_r | pkt_req_cnt_done_r1 | pkt_req_cnt_done)
                next_state      = ZCP_WR_MID_LAST;
        else
                next_state      = state;
end

ZCP_WR_MID_LAST:
begin
                rdmc_wr_data_sel        = 2'b10;
                rdmc_wr_data_valid_sm   = 1'b1;
                rdmc_wr_data_comp_sm    = 1'b1;
		offset_reg_en           = 1'b1;
                offset_sel              = 2'b10;
                next_state              = ZCP_READY;
end

ZCP_WR_DATA:
begin
        if (muxed_ipp_data_ack & ipp_fzcp_eop & pkt_req_cnt_done_r1)
        begin
                rdmc_wr_data_sel        = 2'b10;
                rdmc_wr_data_valid_sm   = 1'b1;
                next_state              = ZCP_WR_DATA_LAST;
        end
        else if (muxed_ipp_data_ack & ipp_fzcp_eop & pkt_req_cnt_done_r2)
        begin
                rdmc_wr_data_sel        = 2'b10;
                rdmc_wr_data_valid_sm   = 1'b1;
                rdmc_wr_data_comp_sm    = 1'b1;
		rdmc_wr_last_comp_sm	= 1'b1;
		offset_reg_en           = 1'b1;
                offset_sel              = 2'b00;

		if (rdmc_wr_req_accept_hdr | is_rdmc_wr_req_accept)
			next_state	= READY;
		else
                	next_state      = IDLE;
        end
        else if (muxed_ipp_data_ack & ipp_fzcp_eop)
        begin
                rdmc_wr_data_sel        = 2'b10;
                rdmc_wr_data_valid_sm   = 1'b1;
                next_state              = WAIT_ZCP_DATA_LAST;
        end
        else if (muxed_ipp_data_ack)
        begin
                rdmc_wr_data_sel        = 2'b10;
                rdmc_wr_data_valid_sm   = 1'b1;
                next_state              = state;
        end
        else
        begin
                rdmc_wr_data_sel        = 2'b10;
                rdmc_wr_data_valid_sm   = 1'b0;
                next_state              = state;
        end
end

WAIT_ZCP_DATA_LAST:
begin
        if (pkt_req_cnt_done_r | pkt_req_cnt_done_r1 | pkt_req_cnt_done)
                next_state      = ZCP_WR_DATA_LAST;
        else
                next_state      = state;
end

ZCP_WR_DATA_LAST:
begin
                rdmc_wr_data_sel        = 2'b10;
                rdmc_wr_data_valid_sm   = 1'b1;
                rdmc_wr_data_comp_sm    = 1'b1;
		rdmc_wr_last_comp_sm	= 1'b1;
		offset_reg_en           = 1'b1;
                offset_sel              = 2'b00;

		if (rdmc_wr_req_accept_hdr | is_rdmc_wr_req_accept)
                        next_state      = READY;
                else
                        next_state      = IDLE;
end


default:
		next_state	= IDLE;

endcase
end


always @ (posedge clk)
if (reset)
        state <= IDLE;
else
        state <= next_state;

always @ (posedge clk)
if (reset)
	ready_cycle_reg <= 1'b0;
else 
	ready_cycle_reg <= ready_cycle;

wire	ready_cycle_p = ready_cycle & !ready_cycle_reg;

always @ (posedge clk)
if (reset)
	is_rdmc_wr_req_accept <= 1'b0;
else if (rdmc_wr_req_accept_hdr)
	is_rdmc_wr_req_accept <= 1'b1;
else if (ready_cycle_p)
	is_rdmc_wr_req_accept <= 1'b0;
else
	is_rdmc_wr_req_accept <= is_rdmc_wr_req_accept;

always @ (posedge clk)
if (reset)
	zcp_wr_cnt <= 2'b0;
else if (ready_cycle)
	zcp_wr_cnt <= 2'b0;
else if (inc_zcp_wr_cnt)
	zcp_wr_cnt <= zcp_wr_cnt + 2'd1;
else
	zcp_wr_cnt <= zcp_wr_cnt;
	
assign zcp_wr_done = (zcp_wr_cnt == zcp_wr_type);

always @ (posedge clk)
if (reset)
        jmb_pkt_done <= 1'b0;
else if (ready_cycle)
        jmb_pkt_done <= 1'b0;
else if (jmb_pkt_done_sm)
        jmb_pkt_done <= 1'b1;
else
        jmb_pkt_done <= jmb_pkt_done;


endmodule
Commit	Line	Data
86530b38 AT	1	// ========== Copyright Header Begin ==========================================
	2	//
	3	// OpenSPARC T2 Processor File: niu_rdmc_wr_dp_sm.v
	4	// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
	5	// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
	6	//
	7	// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
	8	//
	9	// This program is free software; you can redistribute it and/or modify
	10	// it under the terms of the GNU General Public License as published by
	11	// the Free Software Foundation; version 2 of the License.
	12	//
	13	// This program is distributed in the hope that it will be useful,
	14	// but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	// GNU General Public License for more details.
	17	//
	18	// You should have received a copy of the GNU General Public License
	19	// along with this program; if not, write to the Free Software
	20	// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	21	//
	22	// For the avoidance of doubt, and except that if any non-GPL license
	23	// choice is available it will apply instead, Sun elects to use only
	24	// the General Public License version 2 (GPLv2) at this time for any
	25	// software where a choice of GPL license versions is made
	26	// available with the language indicating that GPLv2 or any later version
	27	// may be used, or where a choice of which version of the GPL is applied is
	28	// otherwise unspecified.
	29	//
	30	// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
	31	// CA 95054 USA or visit www.sun.com if you need additional information or
	32	// have any questions.
	33	//
	34	// ========== Copyright Header End ============================================
	35	module niu_rdmc_wr_dp_sm (
	36	clk,
	37	reset,
	38	full_hdr_r1,
	39	ipp_data_req_dly2,
	40	rdmc_wr_req_accept_hdr,
	41	rdmc_wr_req_accept_zcp,
	42	muxed_ipp_data_ack,
	43	rdmc_cal_eop_r,
	44	ipp_next_eop,
	45	ipp_fzcp_eop,
	46	pkt_req_cnt_done,
	47	pkt_req_cnt_done_r,
	48	pkt_req_cnt_done_r1,
	49	pkt_req_cnt_done_r2,
	50	jmb_pkt_type,
	51	zcopy_mode,
	52	zcp_wr_type,
	53
	54	offset_reg_en,
	55	offset_sel,
	56	wr_idle_state,
	57	rdmc_wr_data_sel,
	58	rdmc_wr_data_valid_sm,
	59	rdmc_wr_data_comp_sm,
	60	rdmc_wr_last_comp_sm,
	61	jmb_wr_cycle_sm,
	62	wr_dp_sm_state
	63	);
	64
65	input clk;
66	input reset;
67	input full_hdr_r1;
68	input ipp_data_req_dly2;
69	input rdmc_wr_req_accept_hdr;
70	input rdmc_wr_req_accept_zcp;
71	input muxed_ipp_data_ack;
72	input rdmc_cal_eop_r;
73	input ipp_next_eop;
74	input ipp_fzcp_eop;
75	input pkt_req_cnt_done;
76	input pkt_req_cnt_done_r;
77	input pkt_req_cnt_done_r1;
78	input pkt_req_cnt_done_r2;
79	input[1:0] jmb_pkt_type; //01:use one buf, 10:use two buf, 11:use three buf
80	input zcopy_mode;
81	input[1:0] zcp_wr_type; //00:one dmaw, ... 11:four dmaw
82
83	output offset_reg_en;
84	output[1:0] offset_sel;
85	output wr_idle_state;
86	output[1:0] rdmc_wr_data_sel;
87	output rdmc_wr_data_valid_sm;
88	output rdmc_wr_data_comp_sm;
89	output rdmc_wr_last_comp_sm;
90	output jmb_wr_cycle_sm;
91	output[4:0] wr_dp_sm_state;
92
93	reg offset_reg_en;
94	reg[1:0] offset_sel;
95	reg wr_idle_state;
96	reg ready_cycle;
97	reg[1:0] rdmc_wr_data_sel;
98	reg rdmc_wr_data_valid_sm;
99	reg rdmc_wr_data_comp_sm;
100	reg rdmc_wr_last_comp_sm;
101	reg inc_zcp_wr_cnt;
102	reg jmb_pkt_done_sm;
103	reg jmb_wr_cycle_sm;
104	reg[4:0] state;
105	reg[4:0] next_state;
106
107	reg ready_cycle_reg;
108	reg is_rdmc_wr_req_accept;
109	reg[1:0] zcp_wr_cnt;
110	reg jmb_pkt_done;
111
112	wire[4:0] wr_dp_sm_state = state;
113	wire zcp_wr_done;
114
115
116	parameter
117
118	IDLE = 5'd16,
119	READY = 5'd0,
120	FIRST_HDR = 5'd1,
121	JMB_WR_DATA = 5'd2,
122	WR_DATA = 5'd3,
123	WAIT_DATA_LAST = 5'd4,
124	WR_DATA_LAST = 5'd5,
125	ZCP_WR_HDR = 5'd6,
126	WAIT_ZCP_HDR_LAST = 5'd7,
127	ZCP_WR_HDR_LAST = 5'd8,
128	ZCP_READY = 5'd9,
129	ZCP_WR_MID = 5'd10,
130	WAIT_ZCP_MID_LAST = 5'd11,
131	ZCP_WR_MID_LAST = 5'd12,
132	ZCP_WR_DATA = 5'd13,
133	WAIT_ZCP_DATA_LAST = 5'd14,
134	ZCP_WR_DATA_LAST = 5'd15;
135
136	always @ (state or full_hdr_r1 or ipp_data_req_dly2 or
137	jmb_pkt_type or jmb_pkt_done or
138	zcopy_mode or zcp_wr_done or
139	rdmc_wr_req_accept_hdr or rdmc_wr_req_accept_zcp or
140	is_rdmc_wr_req_accept or muxed_ipp_data_ack or
141	pkt_req_cnt_done or pkt_req_cnt_done_r or
142	pkt_req_cnt_done_r1 or pkt_req_cnt_done_r2 or
143	rdmc_cal_eop_r or ipp_next_eop or ipp_fzcp_eop)
144
145	begin
146
147	offset_reg_en = 1'b0;
148	offset_sel = 2'b00;
149	wr_idle_state = 1'b0;
150	ready_cycle = 1'b0;
151	rdmc_wr_data_sel = 2'b00;
152	rdmc_wr_data_valid_sm = 1'b0;
153	rdmc_wr_data_comp_sm = 1'b0;
154	rdmc_wr_last_comp_sm = 1'b0;
155	inc_zcp_wr_cnt = 1'b0;
156	jmb_pkt_done_sm = 1'b0;
157	jmb_wr_cycle_sm = 1'b0;
158	next_state = 5'b0;
159
160	case (state) //synopsys parallel_case full_case
161
162	IDLE:
163	begin
164	wr_idle_state = 1'b1;
165	if (rdmc_wr_req_accept_hdr)
166	begin
167	offset_reg_en = 1'b1;
168	offset_sel = 2'b00;
169	next_state = READY;
170	end
171	else
172	next_state = state;
173	end
174
175	READY:
176	begin
177	ready_cycle = 1'b1;
178	if (ipp_data_req_dly2 & full_hdr_r1)
179	begin
180	rdmc_wr_data_sel = 2'b00;
181	rdmc_wr_data_valid_sm = 1'b1;
182	next_state = FIRST_HDR;
183	end
184	else if (muxed_ipp_data_ack & ipp_data_req_dly2)
185	begin
186	rdmc_wr_data_sel = 2'b01;
187	rdmc_wr_data_valid_sm = 1'b1;
188	if (zcopy_mode)
189	next_state = ZCP_WR_HDR;
190	else if (jmb_pkt_type[1])
191	next_state = JMB_WR_DATA;
192	else
193	next_state = WR_DATA;
194	end
195	else
196	next_state = state;
197	end
198
199
200	FIRST_HDR:
201	begin
202	rdmc_wr_data_sel = 2'b01;
203	rdmc_wr_data_valid_sm = 1'b1;
204	if (jmb_pkt_type[1])
205	next_state = JMB_WR_DATA;
206	else
207	next_state = WR_DATA;
208	end
209
210	JMB_WR_DATA:
211	begin
212	jmb_wr_cycle_sm = 1'b1;
213	if (muxed_ipp_data_ack & pkt_req_cnt_done_r2 & rdmc_cal_eop_r)//second buf has only one transfer,
214	begin //no need to read ipp
215	rdmc_wr_data_sel = 2'b10;
216	rdmc_wr_data_valid_sm = 1'b1;
217	rdmc_wr_data_comp_sm = 1'b1;
218	next_state = WAIT_DATA_LAST;
219	end
220
221	else if (muxed_ipp_data_ack & pkt_req_cnt_done_r2 & jmb_pkt_type[0] & !jmb_pkt_done)
222	begin
223	rdmc_wr_data_sel = 2'b10;
224	rdmc_wr_data_valid_sm = 1'b1;
225	rdmc_wr_data_comp_sm = 1'b1;
226	jmb_pkt_done_sm = 1'b1;
227	next_state = state;
228	end
229
230	else if (muxed_ipp_data_ack & pkt_req_cnt_done_r2)
231	begin
232	rdmc_wr_data_sel = 2'b10;
233	rdmc_wr_data_valid_sm = 1'b1;
234	rdmc_wr_data_comp_sm = 1'b1;
235	next_state = WR_DATA;
236	end
237	else if (muxed_ipp_data_ack)
238	begin
239	rdmc_wr_data_sel = 2'b10;
240	rdmc_wr_data_valid_sm = 1'b1;
241	next_state = state;
242	end
243	else
244	begin
245	rdmc_wr_data_sel = 2'b10;
246	rdmc_wr_data_valid_sm = 1'b0;
247	next_state = state;
248	end
249	end
250
251	WR_DATA:
252	begin
253	if (muxed_ipp_data_ack & rdmc_cal_eop_r & pkt_req_cnt_done_r1)
254	begin
255	rdmc_wr_data_sel = 2'b10;
256	rdmc_wr_data_valid_sm = 1'b1;
257	next_state = WR_DATA_LAST;
258	end
259	else if (muxed_ipp_data_ack & rdmc_cal_eop_r & pkt_req_cnt_done_r2)
260	begin
261	rdmc_wr_data_sel = 2'b10;
262	rdmc_wr_data_valid_sm = 1'b1;
263	rdmc_wr_data_comp_sm = 1'b1;
264	rdmc_wr_last_comp_sm = 1'b1;
265	if (rdmc_wr_req_accept_hdr \| is_rdmc_wr_req_accept)
266	next_state = READY;
267	else
268	next_state = IDLE;
269	end
270	else if (muxed_ipp_data_ack & rdmc_cal_eop_r)
271	begin
272	rdmc_wr_data_sel = 2'b10;
273	rdmc_wr_data_valid_sm = 1'b1;
274	next_state = WAIT_DATA_LAST;
275	end
276	else if (muxed_ipp_data_ack)
277	begin
278	rdmc_wr_data_sel = 2'b10;
279	rdmc_wr_data_valid_sm = 1'b1;
280	next_state = state;
281	end
282	else
283	begin
284	rdmc_wr_data_sel = 2'b10;
285	rdmc_wr_data_valid_sm = 1'b0;
286	next_state = state;
287	end
288	end
289
290	WAIT_DATA_LAST:
291	begin
292	if (pkt_req_cnt_done_r \| pkt_req_cnt_done_r1 \| pkt_req_cnt_done)
293	next_state = WR_DATA_LAST;
294	else
295	next_state = state;
296	end
297
298	WR_DATA_LAST:
299	begin
300	rdmc_wr_data_sel = 2'b10;
301	rdmc_wr_data_valid_sm = 1'b1;
302	rdmc_wr_data_comp_sm = 1'b1;
303	rdmc_wr_last_comp_sm = 1'b1;
304	if (rdmc_wr_req_accept_hdr \| is_rdmc_wr_req_accept)
305	next_state = READY;
306	else
307	next_state = IDLE;
308	end
309
310	ZCP_WR_HDR:
311	begin
312	if (muxed_ipp_data_ack & ipp_fzcp_eop & pkt_req_cnt_done_r1)
313	begin
314	rdmc_wr_data_sel = 2'b10;
315	rdmc_wr_data_valid_sm = 1'b1;
316	next_state = ZCP_WR_HDR_LAST;
317	end
318	else if (muxed_ipp_data_ack & ipp_fzcp_eop & pkt_req_cnt_done_r2)
319	begin
320	rdmc_wr_data_sel = 2'b10;
321	rdmc_wr_data_valid_sm = 1'b1;
322	rdmc_wr_data_comp_sm = 1'b1;
323	offset_reg_en = 1'b1;
324	offset_sel = 2'b01;
325	next_state = ZCP_READY;
326	end
327	else if (muxed_ipp_data_ack & ipp_fzcp_eop)
328	begin
329	rdmc_wr_data_sel = 2'b10;
330	rdmc_wr_data_valid_sm = 1'b1;
331	next_state = WAIT_ZCP_HDR_LAST;
332	end
333	else if (muxed_ipp_data_ack)
334	begin
335	rdmc_wr_data_sel = 2'b10;
336	rdmc_wr_data_valid_sm = 1'b1;
337	next_state = state;
338	end
339	else
340	begin
341	rdmc_wr_data_sel = 2'b10;
342	rdmc_wr_data_valid_sm = 1'b0;
343	next_state = state;
344	end
345	end
346
347	WAIT_ZCP_HDR_LAST:
348	begin
349	if (pkt_req_cnt_done_r \| pkt_req_cnt_done_r1 \| pkt_req_cnt_done)
350	next_state = ZCP_WR_HDR_LAST;
351	else
352	next_state = state;
353	end
354
355	ZCP_WR_HDR_LAST:
356	begin
357	rdmc_wr_data_sel = 2'b10;
358	rdmc_wr_data_valid_sm = 1'b1;
359	rdmc_wr_data_comp_sm = 1'b1;
360	offset_reg_en = 1'b1;
361	offset_sel = 2'b01;
362	next_state = ZCP_READY;
363	end
364
365	ZCP_READY:
366	begin
367	if (rdmc_wr_req_accept_zcp & zcp_wr_done & ipp_next_eop)
368	next_state = WAIT_ZCP_DATA_LAST;
369	else if (rdmc_wr_req_accept_zcp & zcp_wr_done)
370	next_state = ZCP_WR_DATA;
371	else if (rdmc_wr_req_accept_zcp & ipp_next_eop)
372	begin
373	inc_zcp_wr_cnt = 1'b1;
374	next_state = WAIT_ZCP_MID_LAST;
375	end
376	else if (rdmc_wr_req_accept_zcp)
377	begin
378	inc_zcp_wr_cnt = 1'b1;
379	next_state = ZCP_WR_MID;
380	end
381	else
382	next_state = state;
383	end
384
385	ZCP_WR_MID:
386	begin
387	if (muxed_ipp_data_ack & ipp_fzcp_eop & pkt_req_cnt_done_r1)
388	begin
389	rdmc_wr_data_sel = 2'b10;
390	rdmc_wr_data_valid_sm = 1'b1;
391	next_state = ZCP_WR_MID_LAST;
392	end
393	else if (muxed_ipp_data_ack & ipp_fzcp_eop & pkt_req_cnt_done_r2)
394	begin
395	rdmc_wr_data_sel = 2'b10;
396	rdmc_wr_data_valid_sm = 1'b1;
397	rdmc_wr_data_comp_sm = 1'b1;
398	offset_reg_en = 1'b1;
399	offset_sel = 2'b10;
400	next_state = ZCP_READY;
401	end
402	else if (muxed_ipp_data_ack & ipp_fzcp_eop)
403	begin
404	rdmc_wr_data_sel = 2'b10;
405	rdmc_wr_data_valid_sm = 1'b1;
406	next_state = WAIT_ZCP_MID_LAST;
407	end
408	else if (muxed_ipp_data_ack)
409	begin
410	rdmc_wr_data_sel = 2'b10;
411	rdmc_wr_data_valid_sm = 1'b1;
412	next_state = state;
413	end
414	else
415	begin
416	rdmc_wr_data_sel = 2'b10;
417	rdmc_wr_data_valid_sm = 1'b0;
418	next_state = state;
419	end
420	end
421
422	WAIT_ZCP_MID_LAST:
423	begin
424	if (pkt_req_cnt_done_r \| pkt_req_cnt_done_r1 \| pkt_req_cnt_done)
425	next_state = ZCP_WR_MID_LAST;
426	else
427	next_state = state;
428	end
429
430	ZCP_WR_MID_LAST:
431	begin
432	rdmc_wr_data_sel = 2'b10;
433	rdmc_wr_data_valid_sm = 1'b1;
434	rdmc_wr_data_comp_sm = 1'b1;
435	offset_reg_en = 1'b1;
436	offset_sel = 2'b10;
437	next_state = ZCP_READY;
438	end
439
440	ZCP_WR_DATA:
441	begin
442	if (muxed_ipp_data_ack & ipp_fzcp_eop & pkt_req_cnt_done_r1)
443	begin
444	rdmc_wr_data_sel = 2'b10;
445	rdmc_wr_data_valid_sm = 1'b1;
446	next_state = ZCP_WR_DATA_LAST;
447	end
448	else if (muxed_ipp_data_ack & ipp_fzcp_eop & pkt_req_cnt_done_r2)
449	begin
450	rdmc_wr_data_sel = 2'b10;
451	rdmc_wr_data_valid_sm = 1'b1;
452	rdmc_wr_data_comp_sm = 1'b1;
453	rdmc_wr_last_comp_sm = 1'b1;
454	offset_reg_en = 1'b1;
455	offset_sel = 2'b00;
456
457	if (rdmc_wr_req_accept_hdr \| is_rdmc_wr_req_accept)
458	next_state = READY;
459	else
460	next_state = IDLE;
461	end
462	else if (muxed_ipp_data_ack & ipp_fzcp_eop)
463	begin
464	rdmc_wr_data_sel = 2'b10;
465	rdmc_wr_data_valid_sm = 1'b1;
466	next_state = WAIT_ZCP_DATA_LAST;
467	end
468	else if (muxed_ipp_data_ack)
469	begin
470	rdmc_wr_data_sel = 2'b10;
471	rdmc_wr_data_valid_sm = 1'b1;
472	next_state = state;
473	end
474	else
475	begin
476	rdmc_wr_data_sel = 2'b10;
477	rdmc_wr_data_valid_sm = 1'b0;
478	next_state = state;
479	end
480	end
481
482	WAIT_ZCP_DATA_LAST:
483	begin
484	if (pkt_req_cnt_done_r \| pkt_req_cnt_done_r1 \| pkt_req_cnt_done)
485	next_state = ZCP_WR_DATA_LAST;
486	else
487	next_state = state;
488	end
489
490	ZCP_WR_DATA_LAST:
491	begin
492	rdmc_wr_data_sel = 2'b10;
493	rdmc_wr_data_valid_sm = 1'b1;
494	rdmc_wr_data_comp_sm = 1'b1;
495	rdmc_wr_last_comp_sm = 1'b1;
496	offset_reg_en = 1'b1;
497	offset_sel = 2'b00;
498
499	if (rdmc_wr_req_accept_hdr \| is_rdmc_wr_req_accept)
500	next_state = READY;
501	else
502	next_state = IDLE;
503	end
504
505
506	default:
507	next_state = IDLE;
508
509	endcase
510	end
511
512
513	always @ (posedge clk)
514	if (reset)
515	state <= IDLE;
516	else
517	state <= next_state;
518
519	always @ (posedge clk)
520	if (reset)
521	ready_cycle_reg <= 1'b0;
522	else
523	ready_cycle_reg <= ready_cycle;
524
525	wire ready_cycle_p = ready_cycle & !ready_cycle_reg;
526
527	always @ (posedge clk)
528	if (reset)
529	is_rdmc_wr_req_accept <= 1'b0;
530	else if (rdmc_wr_req_accept_hdr)
531	is_rdmc_wr_req_accept <= 1'b1;
532	else if (ready_cycle_p)
533	is_rdmc_wr_req_accept <= 1'b0;
534	else
535	is_rdmc_wr_req_accept <= is_rdmc_wr_req_accept;
536
537	always @ (posedge clk)
538	if (reset)
539	zcp_wr_cnt <= 2'b0;
540	else if (ready_cycle)
541	zcp_wr_cnt <= 2'b0;
542	else if (inc_zcp_wr_cnt)
543	zcp_wr_cnt <= zcp_wr_cnt + 2'd1;
544	else
545	zcp_wr_cnt <= zcp_wr_cnt;
546
547	assign zcp_wr_done = (zcp_wr_cnt == zcp_wr_type);
548
549	always @ (posedge clk)
550	if (reset)
551	jmb_pkt_done <= 1'b0;
552	else if (ready_cycle)
553	jmb_pkt_done <= 1'b0;
554	else if (jmb_pkt_done_sm)
555	jmb_pkt_done <= 1'b1;
556	else
557	jmb_pkt_done <= jmb_pkt_done;
558
559
560
561	endmodule
562
563
564
565
566