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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: niu_regin_sram_model.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | /************************************************************************* | |
36 | * | |
37 | * File Name : niu_regin_sram_model | |
38 | * Author Name : John Lo | |
39 | * Description : A parameterizable register in SRAM model. | |
40 | * Parent Module: | |
41 | * Child Module: | |
42 | * Interface Mod: | |
43 | * Date Created : 4/15/2004 | |
44 | * | |
45 | * Copyright (c) 2020, Sun Microsystems, Inc. | |
46 | * Sun Proprietary and Confidential | |
47 | * | |
48 | * Modification : | |
49 | * | |
50 | * Synthesis Notes: | |
51 | * | |
52 | *************************************************************************/ | |
53 | ||
54 | module niu_regin_sram_model ( | |
55 | din, | |
56 | we, | |
57 | waddr, | |
58 | clk, | |
59 | re, | |
60 | raddr, | |
61 | dout | |
62 | ); | |
63 | ||
64 | parameter WIDTH = 16, // Width (# of bits) | |
65 | ADDR_BITS = 4, // number of address bits | |
66 | DEPTH = 1<<ADDR_BITS; // number of entries | |
67 | ||
68 | //====================================================================== | |
69 | // Input/Outputs declarations | |
70 | //====================================================================== | |
71 | ||
72 | input [WIDTH-1:0] din; // data in | |
73 | input we; // Write strobe | |
74 | input [ADDR_BITS-1:0] waddr; // write address | |
75 | input clk; // Clock | |
76 | input re; // read enable | |
77 | input [ADDR_BITS-1:0] raddr; // read address | |
78 | output [WIDTH-1:0] dout; | |
79 | ||
80 | wire [WIDTH-1:0] dout; | |
81 | ||
82 | // The memory array | |
83 | reg [WIDTH-1:0] mem [DEPTH-1:0]; | |
84 | reg [ADDR_BITS-1:0] raddr_reg; // read address | |
85 | wire [ADDR_BITS-1:0] raddr; // read address | |
86 | ||
87 | // latch read address | |
88 | always @(posedge clk) | |
89 | if (re) | |
90 | raddr_reg <= raddr; | |
91 | else | |
92 | raddr_reg <= raddr_reg; | |
93 | ||
94 | // Output mux | |
95 | assign dout = mem[raddr_reg]; | |
96 | ||
97 | // verilint 257 off | |
98 | // verilint 280 off | |
99 | // verilint 548 off | |
100 | // verilint 193 off | |
101 | // verilint 529 off | |
102 | ||
103 | //latch write data | |
104 | always @(posedge clk) | |
105 | begin | |
106 | if (we) | |
107 | mem[waddr] <= din; | |
108 | else | |
109 | ; | |
110 | end | |
111 | ||
112 | //---------------------------------------------------------------------- | |
113 | // Debugging stuff | |
114 | // verilint translate off | |
115 | // synopsys translate_off | |
116 | //simtech modcovoff -bpe | |
117 | `ifdef DEBUG | |
118 | ||
119 | wire [WIDTH-1:0] peek_0 = mem[0]; | |
120 | wire [WIDTH-1:0] peek_1 = mem[1]; | |
121 | wire [WIDTH-1:0] peek_2 = mem[2]; | |
122 | wire [WIDTH-1:0] peek_3 = mem[3]; | |
123 | wire [WIDTH-1:0] peek_4 = mem[4]; | |
124 | wire [WIDTH-1:0] peek_5 = mem[5]; | |
125 | wire [WIDTH-1:0] peek_6 = mem[6]; | |
126 | wire [WIDTH-1:0] peek_7 = mem[7]; | |
127 | wire [WIDTH-1:0] peek_8 = mem[8]; | |
128 | wire [WIDTH-1:0] peek_9 = mem[9]; | |
129 | wire [WIDTH-1:0] peek_10 = mem[10]; | |
130 | wire [WIDTH-1:0] peek_11 = mem[11]; | |
131 | wire [WIDTH-1:0] peek_12 = mem[12]; | |
132 | wire [WIDTH-1:0] peek_13 = mem[13]; | |
133 | wire [WIDTH-1:0] peek_14 = mem[14]; | |
134 | wire [WIDTH-1:0] peek_15 = mem[15]; | |
135 | ||
136 | integer i; | |
137 | ||
138 | task dump; | |
139 | begin | |
140 | $display("========================================"); | |
141 | $display("Register Array Memory dump. Width=%0d, Depth=%0d",WIDTH,DEPTH); | |
142 | `ifdef VERILOG | |
143 | $showscopes; | |
144 | `endif | |
145 | for (i=0; i<DEPTH; i=i+1) begin | |
146 | $display("#%0x: mem(%x)",i,mem[i]); | |
147 | end | |
148 | $display("========================================"); | |
149 | ||
150 | end | |
151 | endtask | |
152 | ||
153 | ||
154 | `endif // DEBUG | |
155 | // synopsys translate_on | |
156 | // verilint translate on | |
157 | //simtech modcovon -bpe | |
158 | ||
159 | ||
160 | endmodule // niu_regin_sram_model | |
161 | ||
162 | ||
163 |