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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: niu_scam_ary.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | ||
36 | /********************************************************** | |
37 | *********************************************************** | |
38 | ||
39 | Project : Niu | |
40 | ||
41 | File name : niu_scam_ary.v | |
42 | ||
43 | Module(s) name : niu_scam_ary | |
44 | ||
45 | Parent modules : niu_scam.v | |
46 | ||
47 | Child modules : | |
48 | ||
49 | Author's name : George Chu | |
50 | ||
51 | Date : April. 2004 | |
52 | ||
53 | Description : | |
54 | ||
55 | Synthesis Notes: | |
56 | ||
57 | Modification History: | |
58 | Date Description | |
59 | ---- ----------- | |
60 | ||
61 | ************************************************************ | |
62 | ***********************************************************/ | |
63 | ||
64 | `timescale 1ns/10ps | |
65 | ||
66 | module niu_scam_ary ( | |
67 | data_inp_d, | |
68 | wt_data, | |
69 | wt_mask, | |
70 | rd_data, | |
71 | rd_mask, | |
72 | cam_index_d, | |
73 | reset, | |
74 | cam_clk, | |
75 | match_array, | |
76 | msk_dat_out); | |
77 | ||
78 | input [199:0] data_inp_d; // compare_data/pio_data_input, registered | |
79 | input wt_data; // if 1, pio writes to cam's data plane. | |
80 | input wt_mask; // if 1, pio writes to cam's mask plane. | |
81 | input rd_data; // if 1, pio reads from cam's data plane. | |
82 | input rd_mask; // if 1, pio reads from cam's mask plane. | |
83 | input [6:0] cam_index_d; // pio access address, registered | |
84 | input reset; | |
85 | input cam_clk; // tcam internal clock | |
86 | output [127:0] match_array; // matched entries | |
87 | output [199:0] msk_dat_out; // pio data read out of cam's mask or data plane | |
88 | ||
89 | reg [127:0] match_array; | |
90 | reg [199:0] msk_dat_out; | |
91 | ||
92 | `ifdef SYN_NIU_WITHOUT_RAM | |
93 | ||
94 | always @ (posedge cam_clk) | |
95 | if (wt_data || wt_mask || rd_data || rd_mask || reset) | |
96 | msk_dat_out <= data_inp_d; | |
97 | else | |
98 | msk_dat_out <= msk_dat_out; | |
99 | ||
100 | always @(posedge cam_clk) | |
101 | begin | |
102 | match_array <= {121'h0,cam_index_d[6:0]}; | |
103 | end | |
104 | ||
105 | `else | |
106 | reg [199:0] n_msk_dat_out; | |
107 | ||
108 | reg [199:0] mem_data [0:127]; | |
109 | wire [199:0] mem_data_out; | |
110 | ||
111 | reg [199:0] mem_mask [0:127]; | |
112 | wire [199:0] mem_mask_out; | |
113 | ||
114 | reg [7:0] entry; | |
115 | reg [127:0] match_entry; | |
116 | ||
117 | /*************** memory ***********************************/ | |
118 | always @(posedge cam_clk) | |
119 | if (wt_data) | |
120 | mem_data[cam_index_d] <= #1 data_inp_d[199:0]; | |
121 | else | |
122 | mem_data[cam_index_d] <= #1 mem_data[cam_index_d]; | |
123 | ||
124 | assign mem_data_out = mem_data[cam_index_d]; | |
125 | ||
126 | /*--------------------------------------------------------*/ | |
127 | always @(posedge cam_clk) | |
128 | if (wt_mask) | |
129 | mem_mask[cam_index_d] <= #1 data_inp_d[199:0]; | |
130 | else | |
131 | mem_mask[cam_index_d] <= #1 mem_mask[cam_index_d]; | |
132 | ||
133 | assign mem_mask_out = mem_mask[cam_index_d]; | |
134 | ||
135 | /*************** compare **********************************/ | |
136 | always @(posedge cam_clk) begin | |
137 | entry = 8'h0; | |
138 | match_entry = 128'h0; | |
139 | if (reset) begin | |
140 | match_array <= 128'h0; | |
141 | end | |
142 | else begin | |
143 | while (entry < 8'h80) begin | |
144 | match_entry[entry] = ((data_inp_d&mem_mask[entry])==(mem_data[entry]&mem_mask[entry])); | |
145 | entry = entry[7:0] + 8'h1; | |
146 | end | |
147 | match_array <= match_entry[127:0]; | |
148 | end | |
149 | end | |
150 | ||
151 | /*************** read out *********************************/ | |
152 | always @(rd_data or rd_mask or | |
153 | mem_data_out or mem_mask_out or | |
154 | msk_dat_out) begin | |
155 | case ({rd_data,rd_mask}) //synopsys parallel_case | |
156 | (2'b10): n_msk_dat_out = mem_data_out[199:0]; | |
157 | (2'b01): n_msk_dat_out = mem_mask_out[199:0]; | |
158 | default: n_msk_dat_out = msk_dat_out[199:0]; | |
159 | endcase | |
160 | end | |
161 | ||
162 | always @(posedge cam_clk) begin | |
163 | begin | |
164 | msk_dat_out <= n_msk_dat_out[199:0]; | |
165 | end | |
166 | end | |
167 | /*************** compare **********************************/ | |
168 | ||
169 | `endif | |
170 | ||
171 | endmodule |