Initial commit of OpenSPARC T2 design and verification files.

[OpenSPARC-T2-DV] / design / sys / iop / niu / rtl / niu_smx_arb_2c.v

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// OpenSPARC T2 Processor File: niu_smx_arb_2c.v
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module niu_smx_arb_2c(
/*AUTOARG*/
   // Outputs
   ack_a, ack_b, selout, 
   // Inputs
   clk, reset_l, req_a, req_b, muxin_a, muxin_b
   );
		// arb 2 clients


parameter MUX_WIDTH= 6;

	// req needs to go down on nxt cycle after seeing ack
input clk;
input reset_l;

input req_a;	
input req_b;

input [MUX_WIDTH-1:0] muxin_a;
input [MUX_WIDTH-1:0] muxin_b;

output ack_a;	// pulse
output ack_b;
output [MUX_WIDTH-1:0] selout;

reg a_first, a_first_n;
reg ack_a, ack_b;
reg [MUX_WIDTH-1:0] selout;


always @(posedge clk) begin
  if(!reset_l) begin
    a_first<= `SMX_PD 1'b0;
  end
  else begin
    a_first<= `SMX_PD a_first_n;
  end
end

always @(/*AUTOSENSE*/a_first or muxin_a or muxin_b or req_a or req_b) begin
  case({req_a, req_b})
    2'b00: begin	
	     ack_a= 1'b0;
	     ack_b= 1'b0;
	     a_first_n= a_first;
	     selout= muxin_a;
	   end
    2'b01: begin	
	     ack_a= 1'b0;
	     ack_b= 1'b1;
	     a_first_n= 1'b1;
	     selout= muxin_b;
	   end
    2'b10: begin	
	     ack_a= 1'b1;
	     ack_b= 1'b0;
	     a_first_n= 1'b0;
	     selout= muxin_a;
	   end
    2'b11: begin	
	     ack_a= a_first;
	     ack_b= ~a_first;
	     a_first_n= ~a_first;
	     selout= (a_first)? muxin_a : muxin_b;
	   end
    default: begin
	       ack_a= 1'b0;
	       ack_b= 1'b0;
	       a_first_n= a_first;
	       selout= muxin_a;
	     end
   endcase
end

endmodule