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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: niu_smx_ff_ram32x144.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | ||
36 | module niu_smx_ff_ram32x144( | |
37 | /*AUTOARG*/ | |
38 | // Outputs | |
39 | full, empty, rdata, mb0_smx_store_32x146_scan_out, | |
40 | niu_mb0_smx_store_data_out, | |
41 | // Inputs | |
42 | clk, iol2clk, reset_l, wr, wdata, rd, tcu_aclk, tcu_bclk, | |
43 | tcu_se_scancollar_in, | |
44 | tcu_array_wr_inhibit, mb0_smx_store_32x146_scan_in, | |
45 | niu_mb0_smx_store_32x146_wdata, niu_mb0_smx_store_32x146_rd_addr, | |
46 | niu_mb0_smx_store_32x146_wr_addr, niu_mb0_smx_store_32x146_wr_en, | |
47 | niu_mb0_smx_store_32x146_rd_en, niu_mb0_run | |
48 | ); | |
49 | ||
50 | ||
51 | parameter DATA_WIDTH= 144; | |
52 | parameter ADDR_WIDTH= 5; | |
53 | ||
54 | // fifo if | |
55 | input clk; | |
56 | input iol2clk; | |
57 | input reset_l; | |
58 | ||
59 | input wr; | |
60 | input [DATA_WIDTH-1:0] wdata; | |
61 | output full; | |
62 | ||
63 | input rd; | |
64 | output empty; | |
65 | output [DATA_WIDTH-1:0] rdata; | |
66 | ||
67 | // mbist if | |
68 | input tcu_aclk; | |
69 | input tcu_bclk; | |
70 | input tcu_se_scancollar_in; | |
71 | input tcu_array_wr_inhibit; | |
72 | input mb0_smx_store_32x146_scan_in; | |
73 | output mb0_smx_store_32x146_scan_out; | |
74 | ||
75 | input [7:0] niu_mb0_smx_store_32x146_wdata; | |
76 | input [4:0] niu_mb0_smx_store_32x146_rd_addr; | |
77 | input [4:0] niu_mb0_smx_store_32x146_wr_addr; | |
78 | input niu_mb0_smx_store_32x146_wr_en; | |
79 | input niu_mb0_smx_store_32x146_rd_en; | |
80 | input niu_mb0_run; | |
81 | ||
82 | output [145:0] niu_mb0_smx_store_data_out; | |
83 | ||
84 | ||
85 | wire [DATA_WIDTH-1:0] mwdata= wdata; | |
86 | wire [145:0] mrdata; | |
87 | wire [DATA_WIDTH-1:0] rdata= mrdata[143:0]; | |
88 | wire [ADDR_WIDTH-1:0] mwaddr; | |
89 | wire [ADDR_WIDTH-1:0] mraddr; | |
90 | wire mwr; | |
91 | wire mrd; | |
92 | wire [145:0] niu_mb0_smx_store_data_out= mrdata; | |
93 | ||
94 | niu_smx_ff_ctrl #(ADDR_WIDTH) ctrl( | |
95 | .clk (clk), | |
96 | .reset_l (reset_l), | |
97 | .wr (wr), | |
98 | .rd (rd), | |
99 | .full (full), | |
100 | .empty (empty), | |
101 | .mwr (mwr), | |
102 | .mwaddr (mwaddr[ADDR_WIDTH-1:0]), | |
103 | .mrd (mrd), | |
104 | .mraddr (mraddr[ADDR_WIDTH-1:0]) | |
105 | ); | |
106 | ||
107 | /* | |
108 | uncomment later ???? | |
109 | niu_ram_32_146 ram( | |
110 | .clk (clk), | |
111 | .wt_enable (mwr), | |
112 | .addr_wt (mwaddr[ADDR_WIDTH-1:0]), | |
113 | .data_inp ({2'h0, mwdata[DATA_WIDTH-1:0]}), | |
114 | .cs_rd (mrd), | |
115 | .addr_rd (mraddr[ADDR_WIDTH-1:0]), | |
116 | .data_out (mrdata[145:0]) | |
117 | ); | |
118 | */ | |
119 | ||
120 | wire [145:0] concat_niu_mb0_smx_store_32x146_wdata={ | |
121 | niu_mb0_smx_store_32x146_wdata[1:0], | |
122 | niu_mb0_smx_store_32x146_wdata, | |
123 | niu_mb0_smx_store_32x146_wdata, | |
124 | niu_mb0_smx_store_32x146_wdata, | |
125 | niu_mb0_smx_store_32x146_wdata, | |
126 | niu_mb0_smx_store_32x146_wdata, | |
127 | niu_mb0_smx_store_32x146_wdata, | |
128 | niu_mb0_smx_store_32x146_wdata, | |
129 | niu_mb0_smx_store_32x146_wdata, | |
130 | niu_mb0_smx_store_32x146_wdata, | |
131 | niu_mb0_smx_store_32x146_wdata, | |
132 | niu_mb0_smx_store_32x146_wdata, | |
133 | niu_mb0_smx_store_32x146_wdata, | |
134 | niu_mb0_smx_store_32x146_wdata, | |
135 | niu_mb0_smx_store_32x146_wdata, | |
136 | niu_mb0_smx_store_32x146_wdata, | |
137 | niu_mb0_smx_store_32x146_wdata, | |
138 | niu_mb0_smx_store_32x146_wdata, | |
139 | niu_mb0_smx_store_32x146_wdata | |
140 | }; | |
141 | ||
142 | wire mb0_smx_store_32x146_scan_out; | |
143 | ||
144 | niu_ram_32_146 ram( | |
145 | .tcu_aclk (tcu_aclk), | |
146 | .tcu_bclk (tcu_bclk), | |
147 | .tcu_se_scancollar_in (tcu_se_scancollar_in), | |
148 | .tcu_array_wr_inhibit (tcu_array_wr_inhibit), | |
149 | .scan_in (mb0_smx_store_32x146_scan_in), | |
150 | .scan_out (mb0_smx_store_32x146_scan_out), | |
151 | .mbi_wdata (concat_niu_mb0_smx_store_32x146_wdata [145:0]), | |
152 | .mbi_rd_adr (niu_mb0_smx_store_32x146_rd_addr [4:0]), | |
153 | .mbi_wr_adr (niu_mb0_smx_store_32x146_wr_addr [4:0]), | |
154 | .mbi_wr_en (niu_mb0_smx_store_32x146_wr_en), | |
155 | .mbi_rd_en (niu_mb0_smx_store_32x146_rd_en), | |
156 | .mbi_run (niu_mb0_run), | |
157 | .clk (iol2clk), | |
158 | .wt_enable (mwr), | |
159 | .addr_wt (mwaddr[ADDR_WIDTH-1:0]), | |
160 | .data_inp ({2'h0, mwdata[DATA_WIDTH-1:0]}), | |
161 | .cs_rd (mrd), | |
162 | .addr_rd (mraddr[ADDR_WIDTH-1:0]), | |
163 | .data_out (mrdata[145:0]) | |
164 | ); | |
165 | ||
166 | ||
167 | /* | |
168 | niu_smx_regfl #(DATA_WIDTH,ADDR_WIDTH) regfl( | |
169 | .clk (clk), | |
170 | .reset_l (reset_l), | |
171 | .wr (mwr), | |
172 | .addr_wr (mwaddr[ADDR_WIDTH-1:0]), | |
173 | .data_wr (mwdata[DATA_WIDTH-1:0]), | |
174 | .rd (mrd), | |
175 | .addr_rd (mraddr[ADDR_WIDTH-1:0]), | |
176 | .data_rd (mrdata[DATA_WIDTH-1:0]) | |
177 | ); | |
178 | */ | |
179 | ||
180 | endmodule | |
181 | ||
182 | /* | |
183 | // if need ram, need to explicitly specify | |
184 | module niu_smx_ff_66bx16( | |
185 | ); | |
186 | ||
187 | parameter DATA_WIDTH= 128; | |
188 | parameter ADDR_WIDTH= 4; | |
189 | ||
190 | // fifo if | |
191 | input clk; | |
192 | input reset_l; | |
193 | ||
194 | input wr; | |
195 | input [DATA_WIDTH-1:0] wdata; | |
196 | output full; | |
197 | ||
198 | input rd; | |
199 | output empty; | |
200 | output [DATA_WIDTH-1:0]rdata; | |
201 | ||
202 | wire [DATA_WIDTH-1:0] mwdata= wdata; | |
203 | wire [DATA_WIDTH-1:0] mrdata; | |
204 | wire [DATA_WIDTH-1:0] rdata= mrdata; | |
205 | ||
206 | niu_smx_ff_ctrl #(DATA_WIDTH,ADDR_WIDTH) ctrl( | |
207 | .clk (clk), | |
208 | .reset_l (reset_l), | |
209 | .wr (wr), | |
210 | .rd (rd), | |
211 | .full (full), | |
212 | .empty (empty), | |
213 | .mwr (mwr), | |
214 | .mwaddr (mwaddr[ADDR_WIDTH-1:0]), | |
215 | .mrd (mrd), | |
216 | .mraddr (mraddr[ADDR_WIDTH-1:0]) | |
217 | ); | |
218 | ||
219 | ||
220 | niu_smx_regfl regfl(DATA_WIDTH,ADDR_WIDTH) regfl | |
221 | .clk (clk), | |
222 | .reset_l (reset_l), | |
223 | .wr (mwr), | |
224 | .addr_wr (mwaddr[ADDR_WIDTH-1:0]), | |
225 | .data_wr (mwdata[DATA_WIDTH-1:0]), | |
226 | .rd (mrd), | |
227 | .addr_rd (mraddr[ADDR_WIDTH-1:0]), | |
228 | .data_rd (mrdata[DATA_WIDTH-1:0]) | |
229 | ); | |
230 | ||
231 | endmodule | |
232 | */ | |
233 | ||
234 |