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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: niu_smx_ff_regfl.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | ||
36 | module niu_smx_ff_regfl( | |
37 | /*AUTOARG*/ | |
38 | // Outputs | |
39 | full, empty, rdata, | |
40 | // Inputs | |
41 | clk, reset_l, wr, wdata, rd | |
42 | ); | |
43 | ||
44 | // synopsys template | |
45 | ||
46 | parameter DATA_WIDTH= 128; | |
47 | parameter ADDR_WIDTH= 4; | |
48 | ||
49 | // fifo if | |
50 | input clk; | |
51 | input reset_l; | |
52 | ||
53 | input wr; | |
54 | input [DATA_WIDTH-1:0] wdata; | |
55 | output full; | |
56 | ||
57 | input rd; | |
58 | output empty; | |
59 | output [DATA_WIDTH-1:0] rdata; | |
60 | ||
61 | wire [DATA_WIDTH-1:0] mwdata= wdata; | |
62 | wire [DATA_WIDTH-1:0] mrdata; | |
63 | wire [DATA_WIDTH-1:0] rdata= mrdata; | |
64 | wire [ADDR_WIDTH-1:0] mwaddr; | |
65 | wire [ADDR_WIDTH-1:0] mraddr; | |
66 | wire mwr; | |
67 | wire mrd; | |
68 | ||
69 | niu_smx_ff_ctrl #(ADDR_WIDTH) ctrl( | |
70 | .clk (clk), | |
71 | .reset_l (reset_l), | |
72 | .wr (wr), | |
73 | .rd (rd), | |
74 | .full (full), | |
75 | .empty (empty), | |
76 | .mwr (mwr), | |
77 | .mwaddr (mwaddr[ADDR_WIDTH-1:0]), | |
78 | .mrd (mrd), | |
79 | .mraddr (mraddr[ADDR_WIDTH-1:0]) | |
80 | ); | |
81 | ||
82 | ||
83 | niu_smx_regfl #(DATA_WIDTH,ADDR_WIDTH) regfl( | |
84 | .clk (clk), | |
85 | .reset_l (reset_l), | |
86 | .wr (mwr), | |
87 | .addr_wr (mwaddr[ADDR_WIDTH-1:0]), | |
88 | .data_wr (mwdata[DATA_WIDTH-1:0]), | |
89 | .rd (mrd), | |
90 | .addr_rd (mraddr[ADDR_WIDTH-1:0]), | |
91 | .data_rd (mrdata[DATA_WIDTH-1:0]) | |
92 | ); | |
93 | ||
94 | endmodule | |
95 | ||
96 | /* | |
97 | // if need ram, need to explicitly specify | |
98 | module niu_smx_ff_66bx16( | |
99 | ); | |
100 | ||
101 | parameter DATA_WIDTH= 128; | |
102 | parameter ADDR_WIDTH= 4; | |
103 | ||
104 | // fifo if | |
105 | input clk; | |
106 | input reset_l; | |
107 | ||
108 | input wr; | |
109 | input [DATA_WIDTH-1:0] wdata; | |
110 | output full; | |
111 | ||
112 | input rd; | |
113 | output empty; | |
114 | output [DATA_WIDTH-1:0]rdata; | |
115 | ||
116 | wire [DATA_WIDTH-1:0] mwdata= wdata; | |
117 | wire [DATA_WIDTH-1:0] mrdata; | |
118 | wire [DATA_WIDTH-1:0] rdata= mrdata; | |
119 | ||
120 | niu_smx_ff_ctrl #(DATA_WIDTH,ADDR_WIDTH) ctrl( | |
121 | .clk (clk), | |
122 | .reset_l (reset_l), | |
123 | .wr (wr), | |
124 | .rd (rd), | |
125 | .full (full), | |
126 | .empty (empty), | |
127 | .mwr (mwr), | |
128 | .mwaddr (mwaddr[ADDR_WIDTH-1:0]), | |
129 | .mrd (mrd), | |
130 | .mraddr (mraddr[ADDR_WIDTH-1:0]) | |
131 | ); | |
132 | ||
133 | ||
134 | niu_smx_regfl regfl(DATA_WIDTH,ADDR_WIDTH) regfl | |
135 | .clk (clk), | |
136 | .reset_l (reset_l), | |
137 | .wr (mwr), | |
138 | .addr_wr (mwaddr[ADDR_WIDTH-1:0]), | |
139 | .data_wr (mwdata[DATA_WIDTH-1:0]), | |
140 | .rd (mrd), | |
141 | .addr_rd (mraddr[ADDR_WIDTH-1:0]), | |
142 | .data_rd (mrdata[DATA_WIDTH-1:0]) | |
143 | ); | |
144 | ||
145 | endmodule | |
146 | */ |