Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / design / sys / iop / niu / rtl / niu_smx_gen_siudp.v
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3// OpenSPARC T2 Processor File: niu_smx_gen_siudp.v
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35
36// generate data parity per N2 ras
37
38module niu_smx_gen_siudp(
39 data,
40 parity
41);
42
43
44input [127:0] data;
45output [7:0] parity;
46
47wire [15:0] e0_data={
48 data[30], data[28],
49 data[26], data[24],
50 data[22], data[20],
51 data[18], data[16],
52 data[14], data[12],
53 data[10], data[8],
54 data[6], data[4],
55 data[2], data[0]
56 };
57wire [15:0] e1_data={
58 data[62], data[60],
59 data[58], data[56],
60 data[54], data[52],
61 data[50], data[48],
62 data[46], data[44],
63 data[42], data[40],
64 data[38], data[36],
65 data[34], data[32]
66 };
67wire [15:0] e2_data={
68 data[94], data[92],
69 data[90], data[88],
70 data[86], data[84],
71 data[82], data[80],
72 data[78], data[76],
73 data[74], data[72],
74 data[70], data[68],
75 data[66], data[64]
76 };
77wire [15:0] e3_data={
78 data[126], data[124],
79 data[122], data[120],
80 data[118], data[116],
81 data[114], data[112],
82 data[110], data[108],
83 data[106], data[104],
84 data[102], data[100],
85 data[98], data[96]
86 };
87
88wire [15:0] o0_data={
89 data[31], data[29],
90 data[27], data[25],
91 data[23], data[21],
92 data[19], data[17],
93 data[15], data[13],
94 data[11], data[9],
95 data[7], data[5],
96 data[3], data[1]
97 };
98wire [15:0] o1_data={
99 data[63], data[61],
100 data[59], data[57],
101 data[55], data[53],
102 data[51], data[49],
103 data[47], data[45],
104 data[43], data[41],
105 data[39], data[37],
106 data[35], data[33]
107 };
108wire [15:0] o2_data={
109 data[95], data[93],
110 data[91], data[89],
111 data[87], data[85],
112 data[83], data[81],
113 data[79], data[77],
114 data[75], data[73],
115 data[71], data[69],
116 data[67], data[65]
117 };
118wire [15:0] o3_data={
119 data[127], data[125],
120 data[123], data[121],
121 data[119], data[117],
122 data[115], data[113],
123 data[111], data[109],
124 data[107], data[105],
125 data[103], data[101],
126 data[99], data[97]
127 };
128
129
130wire [7:0] parity;
131
132assign parity[0]= ~(^e0_data);
133assign parity[2]= ~(^e1_data);
134assign parity[4]= ~(^e2_data);
135assign parity[6]= ~(^e3_data);
136
137assign parity[1]= ~(^o0_data);
138assign parity[3]= ~(^o1_data);
139assign parity[5]= ~(^o2_data);
140assign parity[7]= ~(^o3_data);
141
142
143endmodule