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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: niu_smx_timeout_hdlr.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | ||
36 | module niu_smx_timeout_hdlr( | |
37 | /*AUTOARG*/ | |
38 | // Outputs | |
39 | timeout_rst, timeout_rst_addr, tohdl_cmdl_req, tohdl_cmdl_cmd, | |
40 | tohdl_cmdl_addr, tohdl_cmdl_len, tohdl_cmdl_xid, tohdl_cmdl_port, | |
41 | tohdl_cmdl_dma, tohdl_cmdl_client, tohdl_xtb_rd, tohdl_xtb_raddr, | |
42 | smx_nc_err, tohdl_set_intr, tohdl_intr_status, | |
43 | // Inputs | |
44 | clk, reset_l, timeout_rdata_bus, cmdl_tohdl_ack, tohdl_xtb_rdata, | |
45 | tohdl_xtb_rd_ack, tohdl_xtb_rdata_err | |
46 | ); | |
47 | ||
48 | input clk; | |
49 | input reset_l; | |
50 | ||
51 | input [63:0] timeout_rdata_bus; | |
52 | output timeout_rst; | |
53 | output [5:0] timeout_rst_addr; | |
54 | ||
55 | output tohdl_cmdl_req; | |
56 | output [7:0] tohdl_cmdl_cmd; | |
57 | output [63:0] tohdl_cmdl_addr; | |
58 | output [13:0] tohdl_cmdl_len; | |
59 | output [5:0] tohdl_cmdl_xid; | |
60 | output [1:0] tohdl_cmdl_port; | |
61 | output [4:0] tohdl_cmdl_dma; | |
62 | output [7:0] tohdl_cmdl_client; | |
63 | input cmdl_tohdl_ack; | |
64 | ||
65 | output tohdl_xtb_rd; | |
66 | output [5:0] tohdl_xtb_raddr; | |
67 | input [118:0] tohdl_xtb_rdata; // {xtb_rdata}; rcvcnt not part of | |
68 | input tohdl_xtb_rd_ack; // rst client rd signal | |
69 | input tohdl_xtb_rdata_err; | |
70 | ||
71 | output smx_nc_err; // non-recoverable; level | |
72 | // reset by reset_l only | |
73 | ||
74 | output tohdl_set_intr; | |
75 | output [5:0] tohdl_intr_status; | |
76 | ||
77 | parameter s0= 3'h0, | |
78 | s1= 3'h1, | |
79 | s2= 3'h2, | |
80 | s3= 3'h3, | |
81 | s4= 3'h4, | |
82 | s5= 3'h5; | |
83 | ||
84 | wire [3:0] to_grp_15= timeout_rdata_bus[63:60]; | |
85 | wire [3:0] to_grp_14= timeout_rdata_bus[59:56]; | |
86 | wire [3:0] to_grp_13= timeout_rdata_bus[55:52]; | |
87 | wire [3:0] to_grp_12= timeout_rdata_bus[51:48]; | |
88 | wire [3:0] to_grp_11= timeout_rdata_bus[47:44]; | |
89 | wire [3:0] to_grp_10= timeout_rdata_bus[43:40]; | |
90 | wire [3:0] to_grp_9= timeout_rdata_bus[39:36]; | |
91 | wire [3:0] to_grp_8= timeout_rdata_bus[35:32]; | |
92 | wire [3:0] to_grp_7= timeout_rdata_bus[31:28]; | |
93 | wire [3:0] to_grp_6= timeout_rdata_bus[27:24]; | |
94 | wire [3:0] to_grp_5= timeout_rdata_bus[23:20]; | |
95 | wire [3:0] to_grp_4= timeout_rdata_bus[19:16]; | |
96 | wire [3:0] to_grp_3= timeout_rdata_bus[15:12]; | |
97 | wire [3:0] to_grp_2= timeout_rdata_bus[11:8]; | |
98 | wire [3:0] to_grp_1= timeout_rdata_bus[7:4]; | |
99 | wire [3:0] to_grp_0= timeout_rdata_bus[3:0]; | |
100 | ||
101 | wire [15:0] to_grp_n= { | |
102 | |timeout_rdata_bus[63:60], |timeout_rdata_bus[59:56], | |
103 | |timeout_rdata_bus[55:52], |timeout_rdata_bus[51:48], | |
104 | |timeout_rdata_bus[47:44], |timeout_rdata_bus[43:40], | |
105 | |timeout_rdata_bus[39:36], |timeout_rdata_bus[35:32], | |
106 | |timeout_rdata_bus[31:28], |timeout_rdata_bus[27:24], | |
107 | |timeout_rdata_bus[23:20], |timeout_rdata_bus[19:16], | |
108 | |timeout_rdata_bus[15:12], |timeout_rdata_bus[11:8], | |
109 | |timeout_rdata_bus[7:4], |timeout_rdata_bus[3:0]}; | |
110 | wire any_to_n= |timeout_rdata_bus; | |
111 | ||
112 | function [1:0] map_addr; | |
113 | input [3:0] bus; | |
114 | begin | |
115 | if(bus[0]) map_addr= 2'h0; | |
116 | else if(bus[1]) map_addr= 2'h1; | |
117 | else if(bus[2]) map_addr= 2'h2; | |
118 | else if(bus[3]) map_addr= 2'h3; | |
119 | else map_addr= 2'h0; | |
120 | end | |
121 | endfunction | |
122 | ||
123 | wire [1:0] map_addr_0_n= map_addr(to_grp_0); | |
124 | wire [1:0] map_addr_1_n= map_addr(to_grp_1); | |
125 | wire [1:0] map_addr_2_n= map_addr(to_grp_2); | |
126 | wire [1:0] map_addr_3_n= map_addr(to_grp_3); | |
127 | wire [1:0] map_addr_4_n= map_addr(to_grp_4); | |
128 | wire [1:0] map_addr_5_n= map_addr(to_grp_5); | |
129 | wire [1:0] map_addr_6_n= map_addr(to_grp_6); | |
130 | wire [1:0] map_addr_7_n= map_addr(to_grp_7); | |
131 | wire [1:0] map_addr_8_n= map_addr(to_grp_8); | |
132 | wire [1:0] map_addr_9_n= map_addr(to_grp_9); | |
133 | wire [1:0] map_addr_10_n= map_addr(to_grp_10); | |
134 | wire [1:0] map_addr_11_n= map_addr(to_grp_11); | |
135 | wire [1:0] map_addr_12_n= map_addr(to_grp_12); | |
136 | wire [1:0] map_addr_13_n= map_addr(to_grp_13); | |
137 | wire [1:0] map_addr_14_n= map_addr(to_grp_14); | |
138 | wire [1:0] map_addr_15_n= map_addr(to_grp_15); | |
139 | ||
140 | reg [3:0] grpcnt; | |
141 | reg [5:0] tid_addr; // {grpcnt, sel_map_addr_n} | |
142 | reg [1:0] sel_map_addr_n; | |
143 | ||
144 | reg inc_grpcnt_n; | |
145 | reg ld_tid_addr_n; | |
146 | reg ld_cmd_n; | |
147 | reg timeout_rst_n, timeout_rst; // pulse | |
148 | reg smx_nc_err_n, smx_nc_err; // level | |
149 | reg tohdl_xtb_rd_n, tohdl_xtb_rd; // level | |
150 | reg tohdl_cmdl_req_n, tohdl_cmdl_req; // level | |
151 | reg [2:0] to_ns, to_cs; | |
152 | reg tohdl_set_intr_n; | |
153 | wire tohdl_set_intr= tohdl_set_intr_n; | |
154 | wire [5:0] tohdl_intr_status= tid_addr; | |
155 | ||
156 | ||
157 | always @(/*AUTOSENSE*/any_to_n or cmdl_tohdl_ack or grpcnt | |
158 | or smx_nc_err or to_cs or to_grp_n or tohdl_cmdl_req | |
159 | or tohdl_xtb_rd or tohdl_xtb_rd_ack or tohdl_xtb_rdata_err) begin | |
160 | to_ns= to_cs; | |
161 | inc_grpcnt_n= 1'b0; | |
162 | ld_tid_addr_n= 1'b0; | |
163 | tohdl_xtb_rd_n= tohdl_xtb_rd; | |
164 | tohdl_cmdl_req_n= tohdl_cmdl_req; | |
165 | ld_cmd_n= 1'b0; | |
166 | timeout_rst_n= 1'b0; | |
167 | tohdl_set_intr_n= 1'b0; | |
168 | smx_nc_err_n= smx_nc_err; | |
169 | case(to_cs) | |
170 | s0: begin // wait any timeout | |
171 | if(any_to_n) begin | |
172 | to_ns= s1; | |
173 | end | |
174 | end | |
175 | s1: begin // grp cnt sample | |
176 | if(to_grp_n[grpcnt]) begin | |
177 | ld_tid_addr_n= 1'b1; | |
178 | inc_grpcnt_n= 1'b1; // inc for next round | |
179 | to_ns= s2; | |
180 | end | |
181 | else begin | |
182 | inc_grpcnt_n= 1'b1; | |
183 | to_ns= (any_to_n)? s0 : s1; | |
184 | end | |
185 | end | |
186 | s2: begin // serve tid_addr ({grpcnt, sel_map_addr_n}) | |
187 | // tid_addr must be valid at s2,s3,s4 | |
188 | // rd xtb | |
189 | tohdl_xtb_rd_n= 1'b1; | |
190 | timeout_rst_n= 1'b1; // rst timeout bit | |
191 | to_ns= s3; | |
192 | end | |
193 | s3: begin // wait xtb | |
194 | if(tohdl_xtb_rd_ack) begin | |
195 | tohdl_xtb_rd_n= 1'b0; | |
196 | if(tohdl_xtb_rdata_err) begin | |
197 | smx_nc_err_n= 1'b1; // uncorrectable | |
198 | tohdl_set_intr_n= 1'b1; | |
199 | to_ns= s5; | |
200 | end | |
201 | else begin | |
202 | tohdl_cmdl_req_n= 1'b1; | |
203 | ld_cmd_n= 1'b1; | |
204 | to_ns= s4; | |
205 | end | |
206 | end | |
207 | end | |
208 | s4: begin // wait cmdl ack | |
209 | if(cmdl_tohdl_ack) begin | |
210 | tohdl_cmdl_req_n= 1'b0; | |
211 | to_ns= (any_to_n)? s0: s1; | |
212 | end | |
213 | end | |
214 | s5: begin // xid err | |
215 | // remain here | |
216 | to_ns= to_cs; | |
217 | end | |
218 | endcase | |
219 | end | |
220 | ||
221 | always @ ( /*AUTOSENSE*/grpcnt or map_addr_0_n or map_addr_10_n | |
222 | or map_addr_11_n or map_addr_12_n or map_addr_13_n | |
223 | or map_addr_14_n or map_addr_15_n or map_addr_1_n | |
224 | or map_addr_2_n or map_addr_3_n or map_addr_4_n | |
225 | or map_addr_5_n or map_addr_6_n or map_addr_7_n | |
226 | or map_addr_8_n or map_addr_9_n) begin | |
227 | case(grpcnt) | |
228 | 4'h0: sel_map_addr_n= map_addr_0_n; | |
229 | 4'h1: sel_map_addr_n= map_addr_1_n; | |
230 | 4'h2: sel_map_addr_n= map_addr_2_n; | |
231 | 4'h3: sel_map_addr_n= map_addr_3_n; | |
232 | 4'h4: sel_map_addr_n= map_addr_4_n; | |
233 | 4'h5: sel_map_addr_n= map_addr_5_n; | |
234 | 4'h6: sel_map_addr_n= map_addr_6_n; | |
235 | 4'h7: sel_map_addr_n= map_addr_7_n; | |
236 | 4'h8: sel_map_addr_n= map_addr_8_n; | |
237 | 4'h9: sel_map_addr_n= map_addr_9_n; | |
238 | 4'ha: sel_map_addr_n= map_addr_10_n; | |
239 | 4'hb: sel_map_addr_n= map_addr_11_n; | |
240 | 4'hc: sel_map_addr_n= map_addr_12_n; | |
241 | 4'hd: sel_map_addr_n= map_addr_13_n; | |
242 | 4'he: sel_map_addr_n= map_addr_14_n; | |
243 | 4'hf: sel_map_addr_n= map_addr_15_n; | |
244 | endcase | |
245 | end | |
246 | ||
247 | wire [5:0] tohdl_xtb_raddr= tid_addr; | |
248 | wire [63:0] tohdl_cmdl_addr_n= tohdl_xtb_rdata[`SMX_XTB_POS_ADDR]; | |
249 | wire [13:0] tohdl_cmdl_len_n= tohdl_xtb_rdata[`SMX_XTB_POS_LEN]; | |
250 | wire [1:0] tohdl_cmdl_port_n= tohdl_xtb_rdata[`SMX_XTB_POS_PORT]; | |
251 | wire [4:0] tohdl_cmdl_dma_n= tohdl_xtb_rdata[`SMX_XTB_POS_DMA]; | |
252 | wire [7:0] tohdl_cmdl_client_n= tohdl_xtb_rdata[`SMX_XTB_POS_CLIENT]; | |
253 | wire [5:0] tohdl_cmdl_xid_n= tid_addr; | |
254 | wire [5:0] timeout_rst_addr= tid_addr; | |
255 | ||
256 | reg [63:0] tohdl_cmdl_addr; | |
257 | reg [13:0] tohdl_cmdl_len; | |
258 | reg [1:0] tohdl_cmdl_port; | |
259 | reg [4:0] tohdl_cmdl_dma; | |
260 | reg [7:0] tohdl_cmdl_client; | |
261 | reg [5:0] tohdl_cmdl_xid; | |
262 | reg [7:0] tohdl_cmdl_cmd; | |
263 | ||
264 | ||
265 | always @(posedge clk) begin | |
266 | if(!reset_l) begin | |
267 | timeout_rst<= `SMX_PD 1'b0; | |
268 | smx_nc_err<= `SMX_PD 1'b0; | |
269 | tohdl_xtb_rd<= `SMX_PD 1'b0; | |
270 | tohdl_cmdl_req<= `SMX_PD 1'b0; | |
271 | to_cs<= `SMX_PD s0; | |
272 | grpcnt<= `SMX_PD 4'h0; | |
273 | end | |
274 | else begin | |
275 | timeout_rst<= `SMX_PD timeout_rst_n; | |
276 | smx_nc_err<= `SMX_PD smx_nc_err_n; | |
277 | tohdl_xtb_rd<= `SMX_PD tohdl_xtb_rd_n; | |
278 | tohdl_cmdl_req<= `SMX_PD tohdl_cmdl_req_n; | |
279 | to_cs<= `SMX_PD to_ns; | |
280 | if(inc_grpcnt_n) grpcnt<= `SMX_PD grpcnt + 1'b1; | |
281 | end | |
282 | end | |
283 | ||
284 | always @(posedge clk) begin | |
285 | if(ld_tid_addr_n) tid_addr<= `SMX_PD {grpcnt, sel_map_addr_n}; | |
286 | if(ld_cmd_n) begin | |
287 | tohdl_cmdl_addr<= `SMX_PD tohdl_cmdl_addr_n; | |
288 | tohdl_cmdl_len<= `SMX_PD tohdl_cmdl_len_n; | |
289 | tohdl_cmdl_port<= `SMX_PD tohdl_cmdl_port_n; | |
290 | tohdl_cmdl_dma<= `SMX_PD tohdl_cmdl_dma_n; | |
291 | tohdl_cmdl_client<= `SMX_PD tohdl_cmdl_client_n; | |
292 | tohdl_cmdl_xid<= `SMX_PD tohdl_cmdl_xid_n; | |
293 | tohdl_cmdl_cmd<= `SMX_PD {3'h0, 2'b00,`SMX_CMD_COMP_WITHOUT_DATA}; | |
294 | // error type= 2'b11; | |
295 | end | |
296 | end | |
297 | ||
298 | endmodule | |
299 | ||
300 |