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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: niu_tdmc_addrcalc.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | ||
36 | ||
37 | `include "txc_defines.h" | |
38 | `include "niu_dmc_reg_defines.h" | |
39 | module niu_tdmc_addrcalc (/*AUTOJUNK*/ | |
40 | // Outputs | |
41 | NoOfFreeSpaceInCache, DMA_AddressToReq_ff, | |
42 | ShadowRingWrap, NoOfDescInMem, NoOfDescLeft, | |
43 | // Inputs | |
44 | LatchDMAPtrs, DMANumToReq, tx_rng_tail_dma0, | |
45 | ShadowRingCurrentPtr_DMA0, DMA0_EmptySpace, DMA0_RingLength, | |
46 | DMA0_Ring_Wrapped, DMA0_Address, tx_rng_tail_dma1, | |
47 | ShadowRingCurrentPtr_DMA1, DMA1_EmptySpace, DMA1_RingLength, | |
48 | DMA1_Ring_Wrapped, DMA1_Address, tx_rng_tail_dma2, | |
49 | ShadowRingCurrentPtr_DMA2, DMA2_EmptySpace, DMA2_RingLength, | |
50 | DMA2_Ring_Wrapped, DMA2_Address, tx_rng_tail_dma3, | |
51 | ShadowRingCurrentPtr_DMA3, DMA3_EmptySpace, DMA3_RingLength, | |
52 | DMA3_Ring_Wrapped, DMA3_Address, tx_rng_tail_dma4, | |
53 | ShadowRingCurrentPtr_DMA4, DMA4_EmptySpace, DMA4_RingLength, | |
54 | DMA4_Ring_Wrapped, DMA4_Address, tx_rng_tail_dma5, | |
55 | ShadowRingCurrentPtr_DMA5, DMA5_EmptySpace, DMA5_RingLength, | |
56 | DMA5_Ring_Wrapped, DMA5_Address, tx_rng_tail_dma6, | |
57 | ShadowRingCurrentPtr_DMA6, DMA6_EmptySpace, DMA6_RingLength, | |
58 | DMA6_Ring_Wrapped, DMA6_Address, tx_rng_tail_dma7, | |
59 | ShadowRingCurrentPtr_DMA7, DMA7_EmptySpace, DMA7_RingLength, | |
60 | DMA7_Ring_Wrapped, DMA7_Address, tx_rng_tail_dma8, | |
61 | ShadowRingCurrentPtr_DMA8, DMA8_EmptySpace, DMA8_RingLength, | |
62 | DMA8_Ring_Wrapped, DMA8_Address, tx_rng_tail_dma9, | |
63 | ShadowRingCurrentPtr_DMA9, DMA9_EmptySpace, DMA9_RingLength, | |
64 | DMA9_Ring_Wrapped, DMA9_Address, tx_rng_tail_dma10, | |
65 | ShadowRingCurrentPtr_DMA10, DMA10_EmptySpace, DMA10_RingLength, | |
66 | DMA10_Ring_Wrapped, DMA10_Address, tx_rng_tail_dma11, | |
67 | ShadowRingCurrentPtr_DMA11, DMA11_EmptySpace, DMA11_RingLength, | |
68 | DMA11_Ring_Wrapped, DMA11_Address, tx_rng_tail_dma12, | |
69 | ShadowRingCurrentPtr_DMA12, DMA12_EmptySpace, DMA12_RingLength, | |
70 | DMA12_Ring_Wrapped, DMA12_Address, tx_rng_tail_dma13, | |
71 | ShadowRingCurrentPtr_DMA13, DMA13_EmptySpace, DMA13_RingLength, | |
72 | DMA13_Ring_Wrapped, DMA13_Address, tx_rng_tail_dma14, | |
73 | ShadowRingCurrentPtr_DMA14, DMA14_EmptySpace, DMA14_RingLength, | |
74 | DMA14_Ring_Wrapped, DMA14_Address, tx_rng_tail_dma15, | |
75 | ShadowRingCurrentPtr_DMA15, DMA15_EmptySpace, DMA15_RingLength, | |
76 | DMA15_Ring_Wrapped, DMA15_Address, | |
77 | `ifdef NEPTUNE | |
78 | ||
79 | tx_rng_tail_dma16, | |
80 | ShadowRingCurrentPtr_DMA16, DMA16_EmptySpace, DMA16_RingLength, | |
81 | DMA16_Ring_Wrapped, DMA16_Address, tx_rng_tail_dma17, | |
82 | ShadowRingCurrentPtr_DMA17, DMA17_EmptySpace, DMA17_RingLength, | |
83 | DMA17_Ring_Wrapped, DMA17_Address, tx_rng_tail_dma18, | |
84 | ShadowRingCurrentPtr_DMA18, DMA18_EmptySpace, DMA18_RingLength, | |
85 | DMA18_Ring_Wrapped, DMA18_Address, tx_rng_tail_dma19, | |
86 | ShadowRingCurrentPtr_DMA19, DMA19_EmptySpace, DMA19_RingLength, | |
87 | DMA19_Ring_Wrapped, DMA19_Address, tx_rng_tail_dma20, | |
88 | ShadowRingCurrentPtr_DMA20, DMA20_EmptySpace, DMA20_RingLength, | |
89 | DMA20_Ring_Wrapped, DMA20_Address, tx_rng_tail_dma21, | |
90 | ShadowRingCurrentPtr_DMA21, DMA21_EmptySpace, DMA21_RingLength, | |
91 | DMA21_Ring_Wrapped, DMA21_Address, tx_rng_tail_dma22, | |
92 | ShadowRingCurrentPtr_DMA22, DMA22_EmptySpace, DMA22_RingLength, | |
93 | DMA22_Ring_Wrapped, DMA22_Address, tx_rng_tail_dma23, | |
94 | ShadowRingCurrentPtr_DMA23, DMA23_EmptySpace, DMA23_RingLength, | |
95 | DMA23_Ring_Wrapped, DMA23_Address, | |
96 | `else | |
97 | `endif // !ifdef CHANNELS_16 | |
98 | SysClk, Reset_L | |
99 | ); | |
100 | ||
101 | output [4:0] NoOfFreeSpaceInCache ; | |
102 | output [63:0] DMA_AddressToReq_ff ; | |
103 | output ShadowRingWrap ; | |
104 | ||
105 | output [`PTR_WIDTH - 1:0] NoOfDescInMem; | |
106 | output [`PTR_WIDTH - 1:0] NoOfDescLeft; | |
107 | ||
108 | input LatchDMAPtrs; | |
109 | input [4:0] DMANumToReq; | |
110 | ||
111 | input [`PTR_WIDTH :0] tx_rng_tail_dma0; | |
112 | input [`PTR_WIDTH - 1:0] ShadowRingCurrentPtr_DMA0; | |
113 | input [3:0] DMA0_EmptySpace; | |
114 | input [`PTR_WIDTH - 1:0] DMA0_RingLength; | |
115 | input DMA0_Ring_Wrapped; | |
116 | input [63:0] DMA0_Address; | |
117 | input [`PTR_WIDTH :0] tx_rng_tail_dma1; | |
118 | input [`PTR_WIDTH - 1:0] ShadowRingCurrentPtr_DMA1; | |
119 | input [3:0] DMA1_EmptySpace; | |
120 | input [`PTR_WIDTH - 1:0] DMA1_RingLength; | |
121 | input DMA1_Ring_Wrapped; | |
122 | input [63:0] DMA1_Address; | |
123 | input [`PTR_WIDTH :0] tx_rng_tail_dma2; | |
124 | input [`PTR_WIDTH - 1:0] ShadowRingCurrentPtr_DMA2; | |
125 | input [3:0] DMA2_EmptySpace; | |
126 | input [`PTR_WIDTH - 1:0] DMA2_RingLength; | |
127 | input DMA2_Ring_Wrapped; | |
128 | input [63:0] DMA2_Address; | |
129 | input [`PTR_WIDTH :0] tx_rng_tail_dma3; | |
130 | input [`PTR_WIDTH - 1:0] ShadowRingCurrentPtr_DMA3; | |
131 | input [3:0] DMA3_EmptySpace; | |
132 | input [`PTR_WIDTH - 1:0] DMA3_RingLength; | |
133 | input DMA3_Ring_Wrapped; | |
134 | input [63:0] DMA3_Address; | |
135 | input [`PTR_WIDTH :0] tx_rng_tail_dma4; | |
136 | input [`PTR_WIDTH - 1:0] ShadowRingCurrentPtr_DMA4; | |
137 | input [3:0] DMA4_EmptySpace; | |
138 | input [`PTR_WIDTH - 1:0] DMA4_RingLength; | |
139 | input DMA4_Ring_Wrapped; | |
140 | input [63:0] DMA4_Address; | |
141 | input [`PTR_WIDTH :0] tx_rng_tail_dma5; | |
142 | input [`PTR_WIDTH - 1:0] ShadowRingCurrentPtr_DMA5; | |
143 | input [3:0] DMA5_EmptySpace; | |
144 | input [`PTR_WIDTH - 1:0] DMA5_RingLength; | |
145 | input DMA5_Ring_Wrapped; | |
146 | input [63:0] DMA5_Address; | |
147 | input [`PTR_WIDTH :0] tx_rng_tail_dma6; | |
148 | input [`PTR_WIDTH - 1:0] ShadowRingCurrentPtr_DMA6; | |
149 | input [3:0] DMA6_EmptySpace; | |
150 | input [`PTR_WIDTH - 1:0] DMA6_RingLength; | |
151 | input DMA6_Ring_Wrapped; | |
152 | input [63:0] DMA6_Address; | |
153 | input [`PTR_WIDTH :0] tx_rng_tail_dma7; | |
154 | input [`PTR_WIDTH - 1:0] ShadowRingCurrentPtr_DMA7; | |
155 | input [3:0] DMA7_EmptySpace; | |
156 | input [`PTR_WIDTH - 1:0] DMA7_RingLength; | |
157 | input DMA7_Ring_Wrapped; | |
158 | input [63:0] DMA7_Address; | |
159 | input [`PTR_WIDTH :0] tx_rng_tail_dma8; | |
160 | input [`PTR_WIDTH - 1:0] ShadowRingCurrentPtr_DMA8; | |
161 | input [3:0] DMA8_EmptySpace; | |
162 | input [`PTR_WIDTH - 1:0] DMA8_RingLength; | |
163 | input DMA8_Ring_Wrapped; | |
164 | input [63:0] DMA8_Address; | |
165 | input [`PTR_WIDTH :0] tx_rng_tail_dma9; | |
166 | input [`PTR_WIDTH - 1:0] ShadowRingCurrentPtr_DMA9; | |
167 | input [3:0] DMA9_EmptySpace; | |
168 | input [`PTR_WIDTH - 1:0] DMA9_RingLength; | |
169 | input DMA9_Ring_Wrapped; | |
170 | input [63:0] DMA9_Address; | |
171 | input [`PTR_WIDTH :0] tx_rng_tail_dma10; | |
172 | input [`PTR_WIDTH - 1:0] ShadowRingCurrentPtr_DMA10; | |
173 | input [3:0] DMA10_EmptySpace; | |
174 | input [`PTR_WIDTH - 1:0] DMA10_RingLength; | |
175 | input DMA10_Ring_Wrapped; | |
176 | input [63:0] DMA10_Address; | |
177 | input [`PTR_WIDTH :0] tx_rng_tail_dma11; | |
178 | input [`PTR_WIDTH - 1:0] ShadowRingCurrentPtr_DMA11; | |
179 | input [3:0] DMA11_EmptySpace; | |
180 | input [`PTR_WIDTH - 1:0] DMA11_RingLength; | |
181 | input DMA11_Ring_Wrapped; | |
182 | input [63:0] DMA11_Address; | |
183 | input [`PTR_WIDTH :0] tx_rng_tail_dma12; | |
184 | input [`PTR_WIDTH - 1:0] ShadowRingCurrentPtr_DMA12; | |
185 | input [3:0] DMA12_EmptySpace; | |
186 | input [`PTR_WIDTH - 1:0] DMA12_RingLength; | |
187 | input DMA12_Ring_Wrapped; | |
188 | input [63:0] DMA12_Address; | |
189 | input [`PTR_WIDTH :0] tx_rng_tail_dma13; | |
190 | input [`PTR_WIDTH - 1:0] ShadowRingCurrentPtr_DMA13; | |
191 | input [3:0] DMA13_EmptySpace; | |
192 | input [`PTR_WIDTH - 1:0] DMA13_RingLength; | |
193 | input DMA13_Ring_Wrapped; | |
194 | input [63:0] DMA13_Address; | |
195 | input [`PTR_WIDTH :0] tx_rng_tail_dma14; | |
196 | input [`PTR_WIDTH - 1:0] ShadowRingCurrentPtr_DMA14; | |
197 | input [3:0] DMA14_EmptySpace; | |
198 | input [`PTR_WIDTH - 1:0] DMA14_RingLength; | |
199 | input DMA14_Ring_Wrapped; | |
200 | input [63:0] DMA14_Address; | |
201 | input [`PTR_WIDTH :0] tx_rng_tail_dma15; | |
202 | input [`PTR_WIDTH - 1:0] ShadowRingCurrentPtr_DMA15; | |
203 | input [3:0] DMA15_EmptySpace; | |
204 | input [`PTR_WIDTH - 1:0] DMA15_RingLength; | |
205 | input DMA15_Ring_Wrapped; | |
206 | input [63:0] DMA15_Address; | |
207 | `ifdef NEPTUNE | |
208 | ||
209 | input [`PTR_WIDTH :0] tx_rng_tail_dma16; | |
210 | input [`PTR_WIDTH - 1:0] ShadowRingCurrentPtr_DMA16; | |
211 | input [3:0] DMA16_EmptySpace; | |
212 | input [`PTR_WIDTH - 1:0] DMA16_RingLength; | |
213 | input DMA16_Ring_Wrapped; | |
214 | input [63:0] DMA16_Address; | |
215 | input [`PTR_WIDTH :0] tx_rng_tail_dma17; | |
216 | input [`PTR_WIDTH - 1:0] ShadowRingCurrentPtr_DMA17; | |
217 | input [3:0] DMA17_EmptySpace; | |
218 | input [`PTR_WIDTH - 1:0] DMA17_RingLength; | |
219 | input DMA17_Ring_Wrapped; | |
220 | input [63:0] DMA17_Address; | |
221 | input [`PTR_WIDTH :0] tx_rng_tail_dma18; | |
222 | input [`PTR_WIDTH - 1:0] ShadowRingCurrentPtr_DMA18; | |
223 | input [3:0] DMA18_EmptySpace; | |
224 | input [`PTR_WIDTH - 1:0] DMA18_RingLength; | |
225 | input DMA18_Ring_Wrapped; | |
226 | input [63:0] DMA18_Address; | |
227 | input [`PTR_WIDTH :0] tx_rng_tail_dma19; | |
228 | input [`PTR_WIDTH - 1:0] ShadowRingCurrentPtr_DMA19; | |
229 | input [3:0] DMA19_EmptySpace; | |
230 | input [`PTR_WIDTH - 1:0] DMA19_RingLength; | |
231 | input DMA19_Ring_Wrapped; | |
232 | input [63:0] DMA19_Address; | |
233 | input [`PTR_WIDTH :0] tx_rng_tail_dma20; | |
234 | input [`PTR_WIDTH - 1:0] ShadowRingCurrentPtr_DMA20; | |
235 | input [3:0] DMA20_EmptySpace; | |
236 | input [`PTR_WIDTH - 1:0] DMA20_RingLength; | |
237 | input DMA20_Ring_Wrapped; | |
238 | input [63:0] DMA20_Address; | |
239 | input [`PTR_WIDTH :0] tx_rng_tail_dma21; | |
240 | input [`PTR_WIDTH - 1:0] ShadowRingCurrentPtr_DMA21; | |
241 | input [3:0] DMA21_EmptySpace; | |
242 | input [`PTR_WIDTH - 1:0] DMA21_RingLength; | |
243 | input DMA21_Ring_Wrapped; | |
244 | input [63:0] DMA21_Address; | |
245 | input [`PTR_WIDTH :0] tx_rng_tail_dma22; | |
246 | input [`PTR_WIDTH - 1:0] ShadowRingCurrentPtr_DMA22; | |
247 | input [3:0] DMA22_EmptySpace; | |
248 | input [`PTR_WIDTH - 1:0] DMA22_RingLength; | |
249 | input DMA22_Ring_Wrapped; | |
250 | input [63:0] DMA22_Address; | |
251 | input [`PTR_WIDTH :0] tx_rng_tail_dma23; | |
252 | input [`PTR_WIDTH - 1:0] ShadowRingCurrentPtr_DMA23; | |
253 | input [3:0] DMA23_EmptySpace; | |
254 | input [`PTR_WIDTH - 1:0] DMA23_RingLength; | |
255 | input DMA23_Ring_Wrapped; | |
256 | input [63:0] DMA23_Address; | |
257 | ||
258 | `else | |
259 | `endif | |
260 | ||
261 | ||
262 | input SysClk; | |
263 | input Reset_L; | |
264 | ||
265 | reg [4:0] NoOfFreeSpaceInCache ; | |
266 | reg ShadowRingWrap ; | |
267 | reg [63:0] DMA_AddressToReq_ff ; | |
268 | ||
269 | reg [`PTR_WIDTH - 1:0] NoOfDescInMem; | |
270 | reg [`PTR_WIDTH - 1:0] NoOfDescLeft; | |
271 | ||
272 | ||
273 | ||
274 | reg [`PTR_WIDTH - 1:0] NoOfDescInMem_DMA0; | |
275 | reg [`PTR_WIDTH - 1:0] NoOfDescLeft_DMA0; | |
276 | // code for different logic for pointer wrap arounds | |
277 | always@(posedge SysClk) | |
278 | if(!Reset_L) begin | |
279 | NoOfDescInMem_DMA0 <= `PTR_WIDTH'h0; | |
280 | NoOfDescLeft_DMA0 <= `PTR_WIDTH'h0; | |
281 | end else begin | |
282 | NoOfDescInMem_DMA0 <= ~DMA0_Ring_Wrapped ? ( tx_rng_tail_dma0[`PTR_WIDTH - 1:0] - ShadowRingCurrentPtr_DMA0 ) : ( DMA0_RingLength - (ShadowRingCurrentPtr_DMA0 - tx_rng_tail_dma0[`PTR_WIDTH - 1:0] )); | |
283 | NoOfDescLeft_DMA0 <= DMA0_RingLength - ShadowRingCurrentPtr_DMA0 ; | |
284 | end // always@ (... | |
285 | ||
286 | reg [`PTR_WIDTH - 1:0] NoOfDescInMem_DMA1; | |
287 | reg [`PTR_WIDTH - 1:0] NoOfDescLeft_DMA1; | |
288 | // code for different logic for pointer wrap arounds | |
289 | always@(posedge SysClk) | |
290 | if(!Reset_L) begin | |
291 | NoOfDescInMem_DMA1 <= `PTR_WIDTH'h0; | |
292 | NoOfDescLeft_DMA1 <= `PTR_WIDTH'h0; | |
293 | end else begin | |
294 | NoOfDescInMem_DMA1 <= ~DMA1_Ring_Wrapped ? ( tx_rng_tail_dma1[`PTR_WIDTH - 1:0] - ShadowRingCurrentPtr_DMA1 ) : ( DMA1_RingLength - (ShadowRingCurrentPtr_DMA1 - tx_rng_tail_dma1[`PTR_WIDTH - 1:0] )); | |
295 | NoOfDescLeft_DMA1 <= DMA1_RingLength - ShadowRingCurrentPtr_DMA1 ; | |
296 | end // always@ (... | |
297 | ||
298 | reg [`PTR_WIDTH - 1:0] NoOfDescInMem_DMA2; | |
299 | reg [`PTR_WIDTH - 1:0] NoOfDescLeft_DMA2; | |
300 | // code for different logic for pointer wrap arounds | |
301 | always@(posedge SysClk) | |
302 | if(!Reset_L) begin | |
303 | NoOfDescInMem_DMA2 <= `PTR_WIDTH'h0; | |
304 | NoOfDescLeft_DMA2 <= `PTR_WIDTH'h0; | |
305 | end else begin | |
306 | NoOfDescInMem_DMA2 <= ~DMA2_Ring_Wrapped ? ( tx_rng_tail_dma2[`PTR_WIDTH - 1:0] - ShadowRingCurrentPtr_DMA2 ) : ( DMA2_RingLength - (ShadowRingCurrentPtr_DMA2 - tx_rng_tail_dma2[`PTR_WIDTH - 1:0] )); | |
307 | NoOfDescLeft_DMA2 <= DMA2_RingLength - ShadowRingCurrentPtr_DMA2 ; | |
308 | end // always@ (... | |
309 | ||
310 | reg [`PTR_WIDTH - 1:0] NoOfDescInMem_DMA3; | |
311 | reg [`PTR_WIDTH - 1:0] NoOfDescLeft_DMA3; | |
312 | // code for different logic for pointer wrap arounds | |
313 | always@(posedge SysClk) | |
314 | if(!Reset_L) begin | |
315 | NoOfDescInMem_DMA3 <= `PTR_WIDTH'h0; | |
316 | NoOfDescLeft_DMA3 <= `PTR_WIDTH'h0; | |
317 | end else begin | |
318 | NoOfDescInMem_DMA3 <= ~DMA3_Ring_Wrapped ? ( tx_rng_tail_dma3[`PTR_WIDTH - 1:0] - ShadowRingCurrentPtr_DMA3 ) : ( DMA3_RingLength - (ShadowRingCurrentPtr_DMA3 - tx_rng_tail_dma3[`PTR_WIDTH - 1:0] )); | |
319 | NoOfDescLeft_DMA3 <= DMA3_RingLength - ShadowRingCurrentPtr_DMA3 ; | |
320 | end // always@ (... | |
321 | ||
322 | reg [`PTR_WIDTH - 1:0] NoOfDescInMem_DMA4; | |
323 | reg [`PTR_WIDTH - 1:0] NoOfDescLeft_DMA4; | |
324 | // code for different logic for pointer wrap arounds | |
325 | always@(posedge SysClk) | |
326 | if(!Reset_L) begin | |
327 | NoOfDescInMem_DMA4 <= `PTR_WIDTH'h0; | |
328 | NoOfDescLeft_DMA4 <= `PTR_WIDTH'h0; | |
329 | end else begin | |
330 | NoOfDescInMem_DMA4 <= ~DMA4_Ring_Wrapped ? ( tx_rng_tail_dma4[`PTR_WIDTH - 1:0] - ShadowRingCurrentPtr_DMA4 ) : ( DMA4_RingLength - (ShadowRingCurrentPtr_DMA4 - tx_rng_tail_dma4[`PTR_WIDTH - 1:0] )); | |
331 | NoOfDescLeft_DMA4 <= DMA4_RingLength - ShadowRingCurrentPtr_DMA4 ; | |
332 | end // always@ (... | |
333 | ||
334 | reg [`PTR_WIDTH - 1:0] NoOfDescInMem_DMA5; | |
335 | reg [`PTR_WIDTH - 1:0] NoOfDescLeft_DMA5; | |
336 | // code for different logic for pointer wrap arounds | |
337 | always@(posedge SysClk) | |
338 | if(!Reset_L) begin | |
339 | NoOfDescInMem_DMA5 <= `PTR_WIDTH'h0; | |
340 | NoOfDescLeft_DMA5 <= `PTR_WIDTH'h0; | |
341 | end else begin | |
342 | NoOfDescInMem_DMA5 <= ~DMA5_Ring_Wrapped ? ( tx_rng_tail_dma5[`PTR_WIDTH - 1:0] - ShadowRingCurrentPtr_DMA5 ) : ( DMA5_RingLength - (ShadowRingCurrentPtr_DMA5 - tx_rng_tail_dma5[`PTR_WIDTH - 1:0] )); | |
343 | NoOfDescLeft_DMA5 <= DMA5_RingLength - ShadowRingCurrentPtr_DMA5 ; | |
344 | end // always@ (... | |
345 | ||
346 | reg [`PTR_WIDTH - 1:0] NoOfDescInMem_DMA6; | |
347 | reg [`PTR_WIDTH - 1:0] NoOfDescLeft_DMA6; | |
348 | // code for different logic for pointer wrap arounds | |
349 | always@(posedge SysClk) | |
350 | if(!Reset_L) begin | |
351 | NoOfDescInMem_DMA6 <= `PTR_WIDTH'h0; | |
352 | NoOfDescLeft_DMA6 <= `PTR_WIDTH'h0; | |
353 | end else begin | |
354 | NoOfDescInMem_DMA6 <= ~DMA6_Ring_Wrapped ? ( tx_rng_tail_dma6[`PTR_WIDTH - 1:0] - ShadowRingCurrentPtr_DMA6 ) : ( DMA6_RingLength - (ShadowRingCurrentPtr_DMA6 - tx_rng_tail_dma6[`PTR_WIDTH - 1:0] )); | |
355 | NoOfDescLeft_DMA6 <= DMA6_RingLength - ShadowRingCurrentPtr_DMA6 ; | |
356 | end // always@ (... | |
357 | ||
358 | reg [`PTR_WIDTH - 1:0] NoOfDescInMem_DMA7; | |
359 | reg [`PTR_WIDTH - 1:0] NoOfDescLeft_DMA7; | |
360 | // code for different logic for pointer wrap arounds | |
361 | always@(posedge SysClk) | |
362 | if(!Reset_L) begin | |
363 | NoOfDescInMem_DMA7 <= `PTR_WIDTH'h0; | |
364 | NoOfDescLeft_DMA7 <= `PTR_WIDTH'h0; | |
365 | end else begin | |
366 | NoOfDescInMem_DMA7 <= ~DMA7_Ring_Wrapped ? ( tx_rng_tail_dma7[`PTR_WIDTH - 1:0] - ShadowRingCurrentPtr_DMA7 ) : ( DMA7_RingLength - (ShadowRingCurrentPtr_DMA7 - tx_rng_tail_dma7[`PTR_WIDTH - 1:0] )); | |
367 | NoOfDescLeft_DMA7 <= DMA7_RingLength - ShadowRingCurrentPtr_DMA7 ; | |
368 | end // always@ (... | |
369 | ||
370 | reg [`PTR_WIDTH - 1:0] NoOfDescInMem_DMA8; | |
371 | reg [`PTR_WIDTH - 1:0] NoOfDescLeft_DMA8; | |
372 | // code for different logic for pointer wrap arounds | |
373 | always@(posedge SysClk) | |
374 | if(!Reset_L) begin | |
375 | NoOfDescInMem_DMA8 <= `PTR_WIDTH'h0; | |
376 | NoOfDescLeft_DMA8 <= `PTR_WIDTH'h0; | |
377 | end else begin | |
378 | NoOfDescInMem_DMA8 <= ~DMA8_Ring_Wrapped ? ( tx_rng_tail_dma8[`PTR_WIDTH - 1:0] - ShadowRingCurrentPtr_DMA8 ) : ( DMA8_RingLength - (ShadowRingCurrentPtr_DMA8 - tx_rng_tail_dma8[`PTR_WIDTH - 1:0] )); | |
379 | NoOfDescLeft_DMA8 <= DMA8_RingLength - ShadowRingCurrentPtr_DMA8 ; | |
380 | end // always@ (... | |
381 | ||
382 | reg [`PTR_WIDTH - 1:0] NoOfDescInMem_DMA9; | |
383 | reg [`PTR_WIDTH - 1:0] NoOfDescLeft_DMA9; | |
384 | // code for different logic for pointer wrap arounds | |
385 | always@(posedge SysClk) | |
386 | if(!Reset_L) begin | |
387 | NoOfDescInMem_DMA9 <= `PTR_WIDTH'h0; | |
388 | NoOfDescLeft_DMA9 <= `PTR_WIDTH'h0; | |
389 | end else begin | |
390 | NoOfDescInMem_DMA9 <= ~DMA9_Ring_Wrapped ? ( tx_rng_tail_dma9[`PTR_WIDTH - 1:0] - ShadowRingCurrentPtr_DMA9 ) : ( DMA9_RingLength - (ShadowRingCurrentPtr_DMA9 - tx_rng_tail_dma9[`PTR_WIDTH - 1:0] )); | |
391 | NoOfDescLeft_DMA9 <= DMA9_RingLength - ShadowRingCurrentPtr_DMA9 ; | |
392 | end // always@ (... | |
393 | ||
394 | reg [`PTR_WIDTH - 1:0] NoOfDescInMem_DMA10; | |
395 | reg [`PTR_WIDTH - 1:0] NoOfDescLeft_DMA10; | |
396 | // code for different logic for pointer wrap arounds | |
397 | always@(posedge SysClk) | |
398 | if(!Reset_L) begin | |
399 | NoOfDescInMem_DMA10 <= `PTR_WIDTH'h0; | |
400 | NoOfDescLeft_DMA10 <= `PTR_WIDTH'h0; | |
401 | end else begin | |
402 | NoOfDescInMem_DMA10 <= ~DMA10_Ring_Wrapped ? ( tx_rng_tail_dma10[`PTR_WIDTH - 1:0] - ShadowRingCurrentPtr_DMA10 ) : ( DMA10_RingLength - (ShadowRingCurrentPtr_DMA10 - tx_rng_tail_dma10[`PTR_WIDTH - 1:0] )); | |
403 | NoOfDescLeft_DMA10 <= DMA10_RingLength - ShadowRingCurrentPtr_DMA10 ; | |
404 | end // always@ (... | |
405 | ||
406 | reg [`PTR_WIDTH - 1:0] NoOfDescInMem_DMA11; | |
407 | reg [`PTR_WIDTH - 1:0] NoOfDescLeft_DMA11; | |
408 | // code for different logic for pointer wrap arounds | |
409 | always@(posedge SysClk) | |
410 | if(!Reset_L) begin | |
411 | NoOfDescInMem_DMA11 <= `PTR_WIDTH'h0; | |
412 | NoOfDescLeft_DMA11 <= `PTR_WIDTH'h0; | |
413 | end else begin | |
414 | NoOfDescInMem_DMA11 <= ~DMA11_Ring_Wrapped ? ( tx_rng_tail_dma11[`PTR_WIDTH - 1:0] - ShadowRingCurrentPtr_DMA11 ) : ( DMA11_RingLength - (ShadowRingCurrentPtr_DMA11 - tx_rng_tail_dma11[`PTR_WIDTH - 1:0] )); | |
415 | NoOfDescLeft_DMA11 <= DMA11_RingLength - ShadowRingCurrentPtr_DMA11 ; | |
416 | end // always@ (... | |
417 | ||
418 | reg [`PTR_WIDTH - 1:0] NoOfDescInMem_DMA12; | |
419 | reg [`PTR_WIDTH - 1:0] NoOfDescLeft_DMA12; | |
420 | // code for different logic for pointer wrap arounds | |
421 | always@(posedge SysClk) | |
422 | if(!Reset_L) begin | |
423 | NoOfDescInMem_DMA12 <= `PTR_WIDTH'h0; | |
424 | NoOfDescLeft_DMA12 <= `PTR_WIDTH'h0; | |
425 | end else begin | |
426 | NoOfDescInMem_DMA12 <= ~DMA12_Ring_Wrapped ? ( tx_rng_tail_dma12[`PTR_WIDTH - 1:0] - ShadowRingCurrentPtr_DMA12 ) : ( DMA12_RingLength - (ShadowRingCurrentPtr_DMA12 - tx_rng_tail_dma12[`PTR_WIDTH - 1:0] )); | |
427 | NoOfDescLeft_DMA12 <= DMA12_RingLength - ShadowRingCurrentPtr_DMA12 ; | |
428 | end // always@ (... | |
429 | ||
430 | reg [`PTR_WIDTH - 1:0] NoOfDescInMem_DMA13; | |
431 | reg [`PTR_WIDTH - 1:0] NoOfDescLeft_DMA13; | |
432 | // code for different logic for pointer wrap arounds | |
433 | always@(posedge SysClk) | |
434 | if(!Reset_L) begin | |
435 | NoOfDescInMem_DMA13 <= `PTR_WIDTH'h0; | |
436 | NoOfDescLeft_DMA13 <= `PTR_WIDTH'h0; | |
437 | end else begin | |
438 | NoOfDescInMem_DMA13 <= ~DMA13_Ring_Wrapped ? ( tx_rng_tail_dma13[`PTR_WIDTH - 1:0] - ShadowRingCurrentPtr_DMA13 ) : ( DMA13_RingLength - (ShadowRingCurrentPtr_DMA13 - tx_rng_tail_dma13[`PTR_WIDTH - 1:0] )); | |
439 | NoOfDescLeft_DMA13 <= DMA13_RingLength - ShadowRingCurrentPtr_DMA13 ; | |
440 | end // always@ (... | |
441 | ||
442 | reg [`PTR_WIDTH - 1:0] NoOfDescInMem_DMA14; | |
443 | reg [`PTR_WIDTH - 1:0] NoOfDescLeft_DMA14; | |
444 | // code for different logic for pointer wrap arounds | |
445 | always@(posedge SysClk) | |
446 | if(!Reset_L) begin | |
447 | NoOfDescInMem_DMA14 <= `PTR_WIDTH'h0; | |
448 | NoOfDescLeft_DMA14 <= `PTR_WIDTH'h0; | |
449 | end else begin | |
450 | NoOfDescInMem_DMA14 <= ~DMA14_Ring_Wrapped ? ( tx_rng_tail_dma14[`PTR_WIDTH - 1:0] - ShadowRingCurrentPtr_DMA14 ) : ( DMA14_RingLength - (ShadowRingCurrentPtr_DMA14 - tx_rng_tail_dma14[`PTR_WIDTH - 1:0] )); | |
451 | NoOfDescLeft_DMA14 <= DMA14_RingLength - ShadowRingCurrentPtr_DMA14 ; | |
452 | end // always@ (... | |
453 | ||
454 | reg [`PTR_WIDTH - 1:0] NoOfDescInMem_DMA15; | |
455 | reg [`PTR_WIDTH - 1:0] NoOfDescLeft_DMA15; | |
456 | // code for different logic for pointer wrap arounds | |
457 | always@(posedge SysClk) | |
458 | if(!Reset_L) begin | |
459 | NoOfDescInMem_DMA15 <= `PTR_WIDTH'h0; | |
460 | NoOfDescLeft_DMA15 <= `PTR_WIDTH'h0; | |
461 | end else begin | |
462 | NoOfDescInMem_DMA15 <= ~DMA15_Ring_Wrapped ? ( tx_rng_tail_dma15[`PTR_WIDTH - 1:0] - ShadowRingCurrentPtr_DMA15 ) : ( DMA15_RingLength - (ShadowRingCurrentPtr_DMA15 - tx_rng_tail_dma15[`PTR_WIDTH - 1:0] )); | |
463 | NoOfDescLeft_DMA15 <= DMA15_RingLength - ShadowRingCurrentPtr_DMA15 ; | |
464 | end // always@ (... | |
465 | ||
466 | `ifdef NEPTUNE | |
467 | reg [`PTR_WIDTH - 1:0] NoOfDescInMem_DMA16; | |
468 | reg [`PTR_WIDTH - 1:0] NoOfDescLeft_DMA16; | |
469 | always@(posedge SysClk) | |
470 | if(!Reset_L) begin | |
471 | NoOfDescInMem_DMA16 <= `PTR_WIDTH'h0; | |
472 | NoOfDescLeft_DMA16 <= `PTR_WIDTH'h0; | |
473 | end else begin | |
474 | NoOfDescInMem_DMA16 <= ~DMA16_Ring_Wrapped ? ( tx_rng_tail_dma16[`PTR_WIDTH - 1:0] - ShadowRingCurrentPtr_DMA16 ) : ( DMA16_RingLength - (ShadowRingCurrentPtr_DMA16 - tx_rng_tail_dma16[`PTR_WIDTH - 1:0] )); | |
475 | NoOfDescLeft_DMA16 <= DMA16_RingLength - ShadowRingCurrentPtr_DMA16 ; | |
476 | end // always@ (... | |
477 | reg [`PTR_WIDTH - 1:0] NoOfDescInMem_DMA17; | |
478 | reg [`PTR_WIDTH - 1:0] NoOfDescLeft_DMA17; | |
479 | always@(posedge SysClk) | |
480 | if(!Reset_L) begin | |
481 | NoOfDescInMem_DMA17 <= `PTR_WIDTH'h0; | |
482 | NoOfDescLeft_DMA17 <= `PTR_WIDTH'h0; | |
483 | end else begin | |
484 | NoOfDescInMem_DMA17 <= ~DMA17_Ring_Wrapped ? ( tx_rng_tail_dma17[`PTR_WIDTH - 1:0] - ShadowRingCurrentPtr_DMA17 ) : ( DMA17_RingLength - (ShadowRingCurrentPtr_DMA17 - tx_rng_tail_dma17[`PTR_WIDTH - 1:0] )); | |
485 | NoOfDescLeft_DMA17 <= DMA17_RingLength - ShadowRingCurrentPtr_DMA17 ; | |
486 | end // always@ (... | |
487 | reg [`PTR_WIDTH - 1:0] NoOfDescInMem_DMA18; | |
488 | reg [`PTR_WIDTH - 1:0] NoOfDescLeft_DMA18; | |
489 | always@(posedge SysClk) | |
490 | if(!Reset_L) begin | |
491 | NoOfDescInMem_DMA18 <= `PTR_WIDTH'h0; | |
492 | NoOfDescLeft_DMA18 <= `PTR_WIDTH'h0; | |
493 | end else begin | |
494 | NoOfDescInMem_DMA18 <= ~DMA18_Ring_Wrapped ? ( tx_rng_tail_dma18[`PTR_WIDTH - 1:0] - ShadowRingCurrentPtr_DMA18 ) : ( DMA18_RingLength - (ShadowRingCurrentPtr_DMA18 - tx_rng_tail_dma18[`PTR_WIDTH - 1:0] )); | |
495 | NoOfDescLeft_DMA18 <= DMA18_RingLength - ShadowRingCurrentPtr_DMA18 ; | |
496 | end // always@ (... | |
497 | reg [`PTR_WIDTH - 1:0] NoOfDescInMem_DMA19; | |
498 | reg [`PTR_WIDTH - 1:0] NoOfDescLeft_DMA19; | |
499 | always@(posedge SysClk) | |
500 | if(!Reset_L) begin | |
501 | NoOfDescInMem_DMA19 <= `PTR_WIDTH'h0; | |
502 | NoOfDescLeft_DMA19 <= `PTR_WIDTH'h0; | |
503 | end else begin | |
504 | NoOfDescInMem_DMA19 <= ~DMA19_Ring_Wrapped ? ( tx_rng_tail_dma19[`PTR_WIDTH - 1:0] - ShadowRingCurrentPtr_DMA19 ) : ( DMA19_RingLength - (ShadowRingCurrentPtr_DMA19 - tx_rng_tail_dma19[`PTR_WIDTH - 1:0] )); | |
505 | NoOfDescLeft_DMA19 <= DMA19_RingLength - ShadowRingCurrentPtr_DMA19 ; | |
506 | end // always@ (... | |
507 | reg [`PTR_WIDTH - 1:0] NoOfDescInMem_DMA20; | |
508 | reg [`PTR_WIDTH - 1:0] NoOfDescLeft_DMA20; | |
509 | always@(posedge SysClk) | |
510 | if(!Reset_L) begin | |
511 | NoOfDescInMem_DMA20 <= `PTR_WIDTH'h0; | |
512 | NoOfDescLeft_DMA20 <= `PTR_WIDTH'h0; | |
513 | end else begin | |
514 | NoOfDescInMem_DMA20 <= ~DMA20_Ring_Wrapped ? ( tx_rng_tail_dma20[`PTR_WIDTH - 1:0] - ShadowRingCurrentPtr_DMA20 ) : ( DMA20_RingLength - (ShadowRingCurrentPtr_DMA20 - tx_rng_tail_dma20[`PTR_WIDTH - 1:0] )); | |
515 | NoOfDescLeft_DMA20 <= DMA20_RingLength - ShadowRingCurrentPtr_DMA20 ; | |
516 | end // always@ (... | |
517 | reg [`PTR_WIDTH - 1:0] NoOfDescInMem_DMA21; | |
518 | reg [`PTR_WIDTH - 1:0] NoOfDescLeft_DMA21; | |
519 | always@(posedge SysClk) | |
520 | if(!Reset_L) begin | |
521 | NoOfDescInMem_DMA21 <= `PTR_WIDTH'h0; | |
522 | NoOfDescLeft_DMA21 <= `PTR_WIDTH'h0; | |
523 | end else begin | |
524 | NoOfDescInMem_DMA21 <= ~DMA21_Ring_Wrapped ? ( tx_rng_tail_dma21[`PTR_WIDTH - 1:0] - ShadowRingCurrentPtr_DMA21 ) : ( DMA21_RingLength - (ShadowRingCurrentPtr_DMA21 - tx_rng_tail_dma21[`PTR_WIDTH - 1:0] )); | |
525 | NoOfDescLeft_DMA21 <= DMA21_RingLength - ShadowRingCurrentPtr_DMA21 ; | |
526 | end // always@ (... | |
527 | reg [`PTR_WIDTH - 1:0] NoOfDescInMem_DMA22; | |
528 | reg [`PTR_WIDTH - 1:0] NoOfDescLeft_DMA22; | |
529 | always@(posedge SysClk) | |
530 | if(!Reset_L) begin | |
531 | NoOfDescInMem_DMA22 <= `PTR_WIDTH'h0; | |
532 | NoOfDescLeft_DMA22 <= `PTR_WIDTH'h0; | |
533 | end else begin | |
534 | NoOfDescInMem_DMA22 <= ~DMA22_Ring_Wrapped ? ( tx_rng_tail_dma22[`PTR_WIDTH - 1:0] - ShadowRingCurrentPtr_DMA22 ) : ( DMA22_RingLength - (ShadowRingCurrentPtr_DMA22 - tx_rng_tail_dma22[`PTR_WIDTH - 1:0] )); | |
535 | NoOfDescLeft_DMA22 <= DMA22_RingLength - ShadowRingCurrentPtr_DMA22 ; | |
536 | end // always@ (... | |
537 | reg [`PTR_WIDTH - 1:0] NoOfDescInMem_DMA23; | |
538 | reg [`PTR_WIDTH - 1:0] NoOfDescLeft_DMA23; | |
539 | always@(posedge SysClk) | |
540 | if(!Reset_L) begin | |
541 | NoOfDescInMem_DMA23 <= `PTR_WIDTH'h0; | |
542 | NoOfDescLeft_DMA23 <= `PTR_WIDTH'h0; | |
543 | end else begin | |
544 | NoOfDescInMem_DMA23 <= ~DMA23_Ring_Wrapped ? ( tx_rng_tail_dma23[`PTR_WIDTH - 1:0] - ShadowRingCurrentPtr_DMA23 ) : ( DMA23_RingLength - (ShadowRingCurrentPtr_DMA23 - tx_rng_tail_dma23[`PTR_WIDTH - 1:0] )); | |
545 | NoOfDescLeft_DMA23 <= DMA23_RingLength - ShadowRingCurrentPtr_DMA23 ; | |
546 | end // always@ (... | |
547 | `else | |
548 | `endif | |
549 | ||
550 | // this will change to accomodate new ptr manipulations | |
551 | ||
552 | //--add here | |
553 | // synopsys infer_mux "dma_addr_calc_mux" | |
554 | always@(posedge SysClk ) | |
555 | if (!Reset_L) begin | |
556 | NoOfFreeSpaceInCache <= 5'h0; | |
557 | DMA_AddressToReq_ff <= 64'h0; | |
558 | NoOfDescInMem <= `PTR_WIDTH'h0; | |
559 | NoOfDescLeft <= `PTR_WIDTH'h0; | |
560 | ShadowRingWrap <= 1'b0; | |
561 | end else begin | |
562 | if(LatchDMAPtrs) begin:dma_addr_calc_mux | |
563 | case(DMANumToReq) // synopsys full_case parallel_case | |
564 | ||
565 | ||
566 | `DMA_CHANNEL_ZERO: begin | |
567 | NoOfDescInMem <= NoOfDescInMem_DMA0; | |
568 | NoOfDescLeft <= NoOfDescLeft_DMA0; | |
569 | NoOfFreeSpaceInCache <= {DMA0_EmptySpace,1'b0}; | |
570 | ShadowRingWrap <= DMA0_Ring_Wrapped; | |
571 | DMA_AddressToReq_ff <= DMA0_Address ; | |
572 | end | |
573 | `DMA_CHANNEL_ONE: begin | |
574 | NoOfDescInMem <= NoOfDescInMem_DMA1; | |
575 | NoOfDescLeft <= NoOfDescLeft_DMA1; | |
576 | NoOfFreeSpaceInCache <= {DMA1_EmptySpace,1'b0}; | |
577 | ShadowRingWrap <= DMA1_Ring_Wrapped; | |
578 | DMA_AddressToReq_ff <= DMA1_Address ; | |
579 | end | |
580 | `DMA_CHANNEL_TWO: begin | |
581 | NoOfDescInMem <= NoOfDescInMem_DMA2; | |
582 | NoOfDescLeft <= NoOfDescLeft_DMA2; | |
583 | NoOfFreeSpaceInCache <= {DMA2_EmptySpace,1'b0}; | |
584 | ShadowRingWrap <= DMA2_Ring_Wrapped; | |
585 | DMA_AddressToReq_ff <= DMA2_Address ; | |
586 | end | |
587 | `DMA_CHANNEL_THREE: begin | |
588 | NoOfDescInMem <= NoOfDescInMem_DMA3; | |
589 | NoOfDescLeft <= NoOfDescLeft_DMA3; | |
590 | NoOfFreeSpaceInCache <= {DMA3_EmptySpace,1'b0}; | |
591 | ShadowRingWrap <= DMA3_Ring_Wrapped; | |
592 | DMA_AddressToReq_ff <= DMA3_Address ; | |
593 | end | |
594 | `DMA_CHANNEL_FOUR: begin | |
595 | NoOfDescInMem <= NoOfDescInMem_DMA4; | |
596 | NoOfDescLeft <= NoOfDescLeft_DMA4; | |
597 | NoOfFreeSpaceInCache <= {DMA4_EmptySpace,1'b0}; | |
598 | ShadowRingWrap <= DMA4_Ring_Wrapped; | |
599 | DMA_AddressToReq_ff <= DMA4_Address ; | |
600 | end | |
601 | `DMA_CHANNEL_FIVE: begin | |
602 | NoOfDescInMem <= NoOfDescInMem_DMA5; | |
603 | NoOfDescLeft <= NoOfDescLeft_DMA5; | |
604 | NoOfFreeSpaceInCache <= {DMA5_EmptySpace,1'b0}; | |
605 | ShadowRingWrap <= DMA5_Ring_Wrapped; | |
606 | DMA_AddressToReq_ff <= DMA5_Address ; | |
607 | end | |
608 | `DMA_CHANNEL_SIX: begin | |
609 | NoOfDescInMem <= NoOfDescInMem_DMA6; | |
610 | NoOfDescLeft <= NoOfDescLeft_DMA6; | |
611 | NoOfFreeSpaceInCache <= {DMA6_EmptySpace,1'b0}; | |
612 | ShadowRingWrap <= DMA6_Ring_Wrapped; | |
613 | DMA_AddressToReq_ff <= DMA6_Address ; | |
614 | end | |
615 | `DMA_CHANNEL_SEVEN: begin | |
616 | NoOfDescInMem <= NoOfDescInMem_DMA7; | |
617 | NoOfDescLeft <= NoOfDescLeft_DMA7; | |
618 | NoOfFreeSpaceInCache <= {DMA7_EmptySpace,1'b0}; | |
619 | ShadowRingWrap <= DMA7_Ring_Wrapped; | |
620 | DMA_AddressToReq_ff <= DMA7_Address ; | |
621 | end | |
622 | `DMA_CHANNEL_EIGHT: begin | |
623 | NoOfDescInMem <= NoOfDescInMem_DMA8; | |
624 | NoOfDescLeft <= NoOfDescLeft_DMA8; | |
625 | NoOfFreeSpaceInCache <= {DMA8_EmptySpace,1'b0}; | |
626 | ShadowRingWrap <= DMA8_Ring_Wrapped; | |
627 | DMA_AddressToReq_ff <= DMA8_Address ; | |
628 | end | |
629 | `DMA_CHANNEL_NINE: begin | |
630 | NoOfDescInMem <= NoOfDescInMem_DMA9; | |
631 | NoOfDescLeft <= NoOfDescLeft_DMA9; | |
632 | NoOfFreeSpaceInCache <= {DMA9_EmptySpace,1'b0}; | |
633 | ShadowRingWrap <= DMA9_Ring_Wrapped; | |
634 | DMA_AddressToReq_ff <= DMA9_Address ; | |
635 | end | |
636 | `DMA_CHANNEL_TEN: begin | |
637 | NoOfDescInMem <= NoOfDescInMem_DMA10; | |
638 | NoOfDescLeft <= NoOfDescLeft_DMA10; | |
639 | NoOfFreeSpaceInCache <= {DMA10_EmptySpace,1'b0}; | |
640 | ShadowRingWrap <= DMA10_Ring_Wrapped; | |
641 | DMA_AddressToReq_ff <= DMA10_Address ; | |
642 | end | |
643 | `DMA_CHANNEL_ELEVEN: begin | |
644 | NoOfDescInMem <= NoOfDescInMem_DMA11; | |
645 | NoOfDescLeft <= NoOfDescLeft_DMA11; | |
646 | NoOfFreeSpaceInCache <= {DMA11_EmptySpace,1'b0}; | |
647 | ShadowRingWrap <= DMA11_Ring_Wrapped; | |
648 | DMA_AddressToReq_ff <= DMA11_Address ; | |
649 | end | |
650 | `DMA_CHANNEL_TWELVE: begin | |
651 | NoOfDescInMem <= NoOfDescInMem_DMA12; | |
652 | NoOfDescLeft <= NoOfDescLeft_DMA12; | |
653 | NoOfFreeSpaceInCache <= {DMA12_EmptySpace,1'b0}; | |
654 | ShadowRingWrap <= DMA12_Ring_Wrapped; | |
655 | DMA_AddressToReq_ff <= DMA12_Address ; | |
656 | end | |
657 | `DMA_CHANNEL_THIRTEEN: begin | |
658 | NoOfDescInMem <= NoOfDescInMem_DMA13; | |
659 | NoOfDescLeft <= NoOfDescLeft_DMA13; | |
660 | NoOfFreeSpaceInCache <= {DMA13_EmptySpace,1'b0}; | |
661 | ShadowRingWrap <= DMA13_Ring_Wrapped; | |
662 | DMA_AddressToReq_ff <= DMA13_Address ; | |
663 | end | |
664 | `DMA_CHANNEL_FOURTEEN: begin | |
665 | NoOfDescInMem <= NoOfDescInMem_DMA14; | |
666 | NoOfDescLeft <= NoOfDescLeft_DMA14; | |
667 | NoOfFreeSpaceInCache <= {DMA14_EmptySpace,1'b0}; | |
668 | ShadowRingWrap <= DMA14_Ring_Wrapped; | |
669 | DMA_AddressToReq_ff <= DMA14_Address ; | |
670 | end | |
671 | `DMA_CHANNEL_FIFTEEN: begin | |
672 | NoOfDescInMem <= NoOfDescInMem_DMA15; | |
673 | NoOfDescLeft <= NoOfDescLeft_DMA15; | |
674 | NoOfFreeSpaceInCache <= {DMA15_EmptySpace,1'b0}; | |
675 | ShadowRingWrap <= DMA15_Ring_Wrapped; | |
676 | DMA_AddressToReq_ff <= DMA15_Address ; | |
677 | end | |
678 | `ifdef NEPTUNE | |
679 | ||
680 | `DMA_CHANNEL_SIXTEEN: begin | |
681 | NoOfDescInMem <= NoOfDescInMem_DMA16; | |
682 | NoOfDescLeft <= NoOfDescLeft_DMA16; | |
683 | NoOfFreeSpaceInCache <= {DMA16_EmptySpace,1'b0}; | |
684 | ShadowRingWrap <= DMA16_Ring_Wrapped; | |
685 | DMA_AddressToReq_ff <= DMA16_Address ; | |
686 | end | |
687 | `DMA_CHANNEL_SEVENTEEN: begin | |
688 | NoOfDescInMem <= NoOfDescInMem_DMA17; | |
689 | NoOfDescLeft <= NoOfDescLeft_DMA17; | |
690 | NoOfFreeSpaceInCache <= {DMA17_EmptySpace,1'b0}; | |
691 | ShadowRingWrap <= DMA17_Ring_Wrapped; | |
692 | DMA_AddressToReq_ff <= DMA17_Address ; | |
693 | end | |
694 | `DMA_CHANNEL_EIGHTEEN: begin | |
695 | NoOfDescInMem <= NoOfDescInMem_DMA18; | |
696 | NoOfDescLeft <= NoOfDescLeft_DMA18; | |
697 | NoOfFreeSpaceInCache <= {DMA18_EmptySpace,1'b0}; | |
698 | ShadowRingWrap <= DMA18_Ring_Wrapped; | |
699 | DMA_AddressToReq_ff <= DMA18_Address ; | |
700 | end | |
701 | `DMA_CHANNEL_NINETEEN: begin | |
702 | NoOfDescInMem <= NoOfDescInMem_DMA19; | |
703 | NoOfDescLeft <= NoOfDescLeft_DMA19; | |
704 | NoOfFreeSpaceInCache <= {DMA19_EmptySpace,1'b0}; | |
705 | ShadowRingWrap <= DMA19_Ring_Wrapped; | |
706 | DMA_AddressToReq_ff <= DMA19_Address ; | |
707 | end | |
708 | `DMA_CHANNEL_TWENTY: begin | |
709 | NoOfDescInMem <= NoOfDescInMem_DMA20; | |
710 | NoOfDescLeft <= NoOfDescLeft_DMA20; | |
711 | NoOfFreeSpaceInCache <= {DMA20_EmptySpace,1'b0}; | |
712 | ShadowRingWrap <= DMA20_Ring_Wrapped; | |
713 | DMA_AddressToReq_ff <= DMA20_Address ; | |
714 | end | |
715 | `DMA_CHANNEL_TWENTYONE: begin | |
716 | NoOfDescInMem <= NoOfDescInMem_DMA21; | |
717 | NoOfDescLeft <= NoOfDescLeft_DMA21; | |
718 | NoOfFreeSpaceInCache <= {DMA21_EmptySpace,1'b0}; | |
719 | ShadowRingWrap <= DMA21_Ring_Wrapped; | |
720 | DMA_AddressToReq_ff <= DMA21_Address ; | |
721 | end | |
722 | `DMA_CHANNEL_TWENTYTWO: begin | |
723 | NoOfDescInMem <= NoOfDescInMem_DMA22; | |
724 | NoOfDescLeft <= NoOfDescLeft_DMA22; | |
725 | NoOfFreeSpaceInCache <= {DMA22_EmptySpace,1'b0}; | |
726 | ShadowRingWrap <= DMA22_Ring_Wrapped; | |
727 | DMA_AddressToReq_ff <= DMA22_Address ; | |
728 | end | |
729 | `DMA_CHANNEL_TWENTYTHREE: begin | |
730 | NoOfDescInMem <= NoOfDescInMem_DMA23; | |
731 | NoOfDescLeft <= NoOfDescLeft_DMA23; | |
732 | NoOfFreeSpaceInCache <= {DMA23_EmptySpace,1'b0}; | |
733 | ShadowRingWrap <= DMA23_Ring_Wrapped; | |
734 | DMA_AddressToReq_ff <= DMA23_Address ; | |
735 | end | |
736 | ||
737 | `else | |
738 | `endif | |
739 | ||
740 | ||
741 | default: begin | |
742 | ShadowRingWrap <= 1'b0; | |
743 | NoOfDescInMem <= `PTR_WIDTH'h0; | |
744 | NoOfDescLeft <= `PTR_WIDTH'h0; | |
745 | NoOfFreeSpaceInCache <= 5'h0; | |
746 | DMA_AddressToReq_ff <= 64'h0; | |
747 | end | |
748 | endcase // case(DMANumToReq) | |
749 | end // if (LatchDMAPtrs) | |
750 | end // else: !if(!Reset_L) | |
751 | ||
752 | endmodule // niu_tdmc_addrcalc |