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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: niu_tdmc_cacheparity.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | /********************************************************************* | |
36 | * | |
37 | * | |
38 | * Orignal Author(s): Arvind Srinivasan | |
39 | * Modifier(s): | |
40 | * Project(s): Neptune | |
41 | * | |
42 | * Copyright (c) 2004 Sun Microsystems, Inc. | |
43 | * | |
44 | * All Rights Reserved. | |
45 | * | |
46 | * This verilog model is the confidential and proprietary property of | |
47 | * Sun Microsystems, Inc., and the possession or use of this model | |
48 | * requires a written license from Sun Microsystems, Inc. | |
49 | * | |
50 | **********************************************************************/ | |
51 | ||
52 | `include "txc_defines.h" | |
53 | `include "niu_dmc_reg_defines.h" | |
54 | ||
55 | ||
56 | ||
57 | module niu_tdmc_cacheparity ( /*AUTOARG*/ | |
58 | // Outputs | |
59 | parity, parity_status, data_out, | |
60 | // Inputs | |
61 | SysClk, Reset_L, data_in, parity_corrupt_dma_match, | |
62 | parity_corrupt_config, write_strobe, write_addr, | |
63 | ram_data_out, ram_parity_out | |
64 | ); | |
65 | input SysClk; | |
66 | input Reset_L; | |
67 | ||
68 | input [131:0] data_in; | |
69 | ||
70 | input [31:0] parity_corrupt_dma_match; | |
71 | input [31:0] parity_corrupt_config; | |
72 | input write_strobe; | |
73 | input [2:0] write_addr; | |
74 | ||
75 | output [15:0] parity; | |
76 | ||
77 | output [131:0] data_out; | |
78 | input [131:0] ram_data_out; | |
79 | input [15:0] ram_parity_out; | |
80 | output parity_status; | |
81 | ||
82 | reg [15:0] parity; | |
83 | reg [15:0] parity_out; | |
84 | reg [131:0] data_out; | |
85 | reg [15:0] parity_to_check; | |
86 | ||
87 | reg set_parity_error_dma23; | |
88 | reg set_parity_error_dma22; | |
89 | reg set_parity_error_dma21; | |
90 | reg set_parity_error_dma20; | |
91 | reg set_parity_error_dma19; | |
92 | reg set_parity_error_dma18; | |
93 | reg set_parity_error_dma17; | |
94 | reg set_parity_error_dma16; | |
95 | reg set_parity_error_dma15; | |
96 | reg set_parity_error_dma14; | |
97 | reg set_parity_error_dma13; | |
98 | reg set_parity_error_dma12; | |
99 | reg set_parity_error_dma11; | |
100 | reg set_parity_error_dma10; | |
101 | reg set_parity_error_dma9; | |
102 | reg set_parity_error_dma8; | |
103 | reg set_parity_error_dma7; | |
104 | reg set_parity_error_dma6; | |
105 | reg set_parity_error_dma5; | |
106 | reg set_parity_error_dma4; | |
107 | reg set_parity_error_dma3; | |
108 | reg set_parity_error_dma2; | |
109 | reg set_parity_error_dma1; | |
110 | reg set_parity_error_dma0; | |
111 | reg [23:0] parity_corrupt_config_d; | |
112 | wire corrupt_parity; | |
113 | wire [31:0] set_parity_error; | |
114 | ||
115 | function [15:0] calc_parity ; | |
116 | input [131:0] in; | |
117 | reg calcDataParity0; | |
118 | reg calcDataParity1; | |
119 | reg calcDataParity2; | |
120 | reg calcDataParity3; | |
121 | reg calcDataParity4; | |
122 | reg calcDataParity5; | |
123 | reg calcDataParity6; | |
124 | reg calcDataParity7; | |
125 | reg calcDataParity8; | |
126 | reg calcDataParity9; | |
127 | reg calcDataParity10; | |
128 | reg calcDataParity11; | |
129 | reg calcDataParity12; | |
130 | reg calcDataParity13; | |
131 | reg calcDataParity14; | |
132 | reg calcDataParity15; | |
133 | begin | |
134 | calcDataParity15 = ^in[131:120]; // special case - due to extra 4 bits | |
135 | calcDataParity14 = ^in[119:112]; | |
136 | calcDataParity13 = ^in[111:104]; | |
137 | calcDataParity12 = ^in[103:96]; | |
138 | calcDataParity11 = ^in[95:88]; | |
139 | calcDataParity10 = ^in[87:80]; | |
140 | calcDataParity9 = ^in[79:72]; | |
141 | calcDataParity8 = ^in[71:64]; | |
142 | calcDataParity7 = ^in[63:56]; | |
143 | calcDataParity6 = ^in[55:48]; | |
144 | calcDataParity5 = ^in[47:40]; | |
145 | calcDataParity4 = ^in[39:32]; | |
146 | calcDataParity3 = ^in[31:24]; | |
147 | calcDataParity2 = ^in[23:16]; | |
148 | calcDataParity1 = ^in[15:8]; | |
149 | calcDataParity0 = ^in[7:0]; | |
150 | ||
151 | calc_parity = {calcDataParity15, calcDataParity14, calcDataParity13, calcDataParity12, | |
152 | calcDataParity11, calcDataParity10, calcDataParity9 , calcDataParity8 , | |
153 | calcDataParity7 , calcDataParity6 , calcDataParity5 , calcDataParity4 , | |
154 | calcDataParity3 , calcDataParity2 , calcDataParity1 , calcDataParity0 }; | |
155 | end | |
156 | ||
157 | endfunction // calc_parity | |
158 | ||
159 | always@(posedge SysClk) begin | |
160 | if(!Reset_L) begin | |
161 | parity_corrupt_config_d<= 24'h0; | |
162 | end else begin // if (!Reset_L) | |
163 | parity_corrupt_config_d[`NO_OF_DMAS -1 :0]<= parity_corrupt_config[`NO_OF_DMAS -1 :0] ; | |
164 | end // else: !if(!Reset_L) | |
165 | end // always@ (posedge SysClk) | |
166 | ||
167 | ||
168 | wire corrupt_address; | |
169 | assign corrupt_address = (write_strobe & write_addr[2:0] == 3'h1); | |
170 | ||
171 | always@(posedge SysClk) begin | |
172 | if(!Reset_L) begin | |
173 | set_parity_error_dma0<= 1'h0; | |
174 | end else begin | |
175 | set_parity_error_dma0<= (parity_corrupt_config[0] &~parity_corrupt_config_d[0]) | (set_parity_error_dma0 & ~ (parity_corrupt_dma_match[0] & corrupt_address)); | |
176 | end // else: !if(!Reset_L) | |
177 | end | |
178 | always@(posedge SysClk) begin | |
179 | if(!Reset_L) begin | |
180 | set_parity_error_dma1<= 1'h0; | |
181 | end else begin | |
182 | set_parity_error_dma1<= (parity_corrupt_config[1] &~parity_corrupt_config_d[1]) | (set_parity_error_dma1 & ~(parity_corrupt_dma_match[1] & corrupt_address)); | |
183 | end // else: !if(!Reset_L) | |
184 | end | |
185 | always@(posedge SysClk) begin | |
186 | if(!Reset_L) begin | |
187 | set_parity_error_dma2<= 1'h0; | |
188 | end else begin | |
189 | set_parity_error_dma2<= (parity_corrupt_config[2] &~parity_corrupt_config_d[2]) | (set_parity_error_dma2 & ~(parity_corrupt_dma_match[2] & corrupt_address)); | |
190 | end // else: !if(!Reset_L) | |
191 | end | |
192 | always@(posedge SysClk) begin | |
193 | if(!Reset_L) begin | |
194 | set_parity_error_dma3<= 1'h0; | |
195 | end else begin | |
196 | set_parity_error_dma3<= (parity_corrupt_config[3] &~parity_corrupt_config_d[3]) | (set_parity_error_dma3 & ~(parity_corrupt_dma_match[3] & corrupt_address)); | |
197 | end // else: !if(!Reset_L) | |
198 | end | |
199 | always@(posedge SysClk) begin | |
200 | if(!Reset_L) begin | |
201 | set_parity_error_dma4<= 1'h0; | |
202 | end else begin | |
203 | set_parity_error_dma4<= (parity_corrupt_config[4] &~parity_corrupt_config_d[4]) | (set_parity_error_dma4 & ~(parity_corrupt_dma_match[4] & corrupt_address) ); | |
204 | end // else: !if(!Reset_L) | |
205 | end | |
206 | always@(posedge SysClk) begin | |
207 | if(!Reset_L) begin | |
208 | set_parity_error_dma5<= 1'h0; | |
209 | end else begin | |
210 | set_parity_error_dma5<= (parity_corrupt_config[5] &~parity_corrupt_config_d[5]) | (set_parity_error_dma5 & ~(parity_corrupt_dma_match[5] & corrupt_address) ); | |
211 | end // else: !if(!Reset_L) | |
212 | end | |
213 | always@(posedge SysClk) begin | |
214 | if(!Reset_L) begin | |
215 | set_parity_error_dma6<= 1'h0; | |
216 | end else begin | |
217 | set_parity_error_dma6<= (parity_corrupt_config[6] &~parity_corrupt_config_d[6]) | (set_parity_error_dma6 & ~(parity_corrupt_dma_match[6] & corrupt_address) ); | |
218 | end // else: !if(!Reset_L) | |
219 | end | |
220 | always@(posedge SysClk) begin | |
221 | if(!Reset_L) begin | |
222 | set_parity_error_dma7<= 1'h0; | |
223 | end else begin | |
224 | set_parity_error_dma7<= (parity_corrupt_config[7] &~parity_corrupt_config_d[7]) | (set_parity_error_dma7 & ~(parity_corrupt_dma_match[7] & corrupt_address) ); | |
225 | end // else: !if(!Reset_L) | |
226 | end | |
227 | always@(posedge SysClk) begin | |
228 | if(!Reset_L) begin | |
229 | set_parity_error_dma8<= 1'h0; | |
230 | end else begin | |
231 | set_parity_error_dma8<= (parity_corrupt_config[8] &~parity_corrupt_config_d[8]) | (set_parity_error_dma8 & ~(parity_corrupt_dma_match[8] & corrupt_address) ); | |
232 | end // else: !if(!Reset_L) | |
233 | end | |
234 | always@(posedge SysClk) begin | |
235 | if(!Reset_L) begin | |
236 | set_parity_error_dma9<= 1'h0; | |
237 | end else begin | |
238 | set_parity_error_dma9<= (parity_corrupt_config[9] &~parity_corrupt_config_d[9]) | (set_parity_error_dma9 & ~(parity_corrupt_dma_match[9] & corrupt_address) ); | |
239 | end // else: !if(!Reset_L) | |
240 | end | |
241 | always@(posedge SysClk) begin | |
242 | if(!Reset_L) begin | |
243 | set_parity_error_dma10<= 1'h0; | |
244 | end else begin | |
245 | set_parity_error_dma10<= (parity_corrupt_config[10] &~parity_corrupt_config_d[10]) | (set_parity_error_dma10 & ~(parity_corrupt_dma_match[10] & corrupt_address) ); | |
246 | end // else: !if(!Reset_L) | |
247 | end | |
248 | always@(posedge SysClk) begin | |
249 | if(!Reset_L) begin | |
250 | set_parity_error_dma11<= 1'h0; | |
251 | end else begin | |
252 | set_parity_error_dma11<= (parity_corrupt_config[11] &~parity_corrupt_config_d[11]) | (set_parity_error_dma11 & ~(parity_corrupt_dma_match[11] & corrupt_address)); | |
253 | end // else: !if(!Reset_L) | |
254 | end | |
255 | always@(posedge SysClk) begin | |
256 | if(!Reset_L) begin | |
257 | set_parity_error_dma12<= 1'h0; | |
258 | end else begin | |
259 | set_parity_error_dma12<= (parity_corrupt_config[12] &~parity_corrupt_config_d[12]) | (set_parity_error_dma12 & ~(parity_corrupt_dma_match[12] & corrupt_address) ); | |
260 | end // else: !if(!Reset_L) | |
261 | end | |
262 | always@(posedge SysClk) begin | |
263 | if(!Reset_L) begin | |
264 | set_parity_error_dma13<= 1'h0; | |
265 | end else begin | |
266 | set_parity_error_dma13<= (parity_corrupt_config[13] &~parity_corrupt_config_d[13]) | (set_parity_error_dma13 & ~(parity_corrupt_dma_match[13] & corrupt_address)) ; | |
267 | end // else: !if(!Reset_L) | |
268 | end | |
269 | always@(posedge SysClk) begin | |
270 | if(!Reset_L) begin | |
271 | set_parity_error_dma14<= 1'h0; | |
272 | end else begin | |
273 | set_parity_error_dma14<= (parity_corrupt_config[14] &~parity_corrupt_config_d[14]) | (set_parity_error_dma14 & ~(parity_corrupt_dma_match[14] & corrupt_address)) ; | |
274 | end // else: !if(!Reset_L) | |
275 | end | |
276 | always@(posedge SysClk) begin | |
277 | if(!Reset_L) begin | |
278 | set_parity_error_dma15<= 1'h0; | |
279 | end else begin | |
280 | set_parity_error_dma15<= (parity_corrupt_config[15] &~parity_corrupt_config_d[15]) | (set_parity_error_dma15 & ~(parity_corrupt_dma_match[15] & corrupt_address)) ; | |
281 | end // else: !if(!Reset_L) | |
282 | end | |
283 | always@(posedge SysClk) begin | |
284 | if(!Reset_L) begin | |
285 | set_parity_error_dma16<= 1'h0; | |
286 | end else begin | |
287 | set_parity_error_dma16<= (parity_corrupt_config[16] &~parity_corrupt_config_d[16]) | (set_parity_error_dma16 & ~(parity_corrupt_dma_match[16] & corrupt_address)); | |
288 | end // else: !if(!Reset_L) | |
289 | end | |
290 | always@(posedge SysClk) begin | |
291 | if(!Reset_L) begin | |
292 | set_parity_error_dma17<= 1'h0; | |
293 | end else begin | |
294 | set_parity_error_dma17<= (parity_corrupt_config[17] &~parity_corrupt_config_d[17]) | (set_parity_error_dma17 & ~(parity_corrupt_dma_match[17] & corrupt_address)); | |
295 | end // else: !if(!Reset_L) | |
296 | end | |
297 | always@(posedge SysClk) begin | |
298 | if(!Reset_L) begin | |
299 | set_parity_error_dma18<= 1'h0; | |
300 | end else begin | |
301 | set_parity_error_dma18<= (parity_corrupt_config[18] &~parity_corrupt_config_d[18]) | (set_parity_error_dma18 & ~(parity_corrupt_dma_match[18] & corrupt_address)); | |
302 | end // else: !if(!Reset_L) | |
303 | end | |
304 | always@(posedge SysClk) begin | |
305 | if(!Reset_L) begin | |
306 | set_parity_error_dma19<= 1'h0; | |
307 | end else begin | |
308 | set_parity_error_dma19<= (parity_corrupt_config[19] &~parity_corrupt_config_d[19]) | (set_parity_error_dma19 & ~(parity_corrupt_dma_match[19] & corrupt_address)); | |
309 | end // else: !if(!Reset_L) | |
310 | end | |
311 | always@(posedge SysClk) begin | |
312 | if(!Reset_L) begin | |
313 | set_parity_error_dma20<= 1'h0; | |
314 | end else begin | |
315 | set_parity_error_dma20<= (parity_corrupt_config[20] &~parity_corrupt_config_d[20]) | (set_parity_error_dma20 & ~(parity_corrupt_dma_match[20] & corrupt_address)); | |
316 | end // else: !if(!Reset_L) | |
317 | end | |
318 | always@(posedge SysClk) begin | |
319 | if(!Reset_L) begin | |
320 | set_parity_error_dma21<= 1'h0; | |
321 | end else begin | |
322 | set_parity_error_dma21<= (parity_corrupt_config[21] &~parity_corrupt_config_d[21]) | (set_parity_error_dma21 & ~(parity_corrupt_dma_match[21] & corrupt_address)); | |
323 | end // else: !if(!Reset_L) | |
324 | end | |
325 | always@(posedge SysClk) begin | |
326 | if(!Reset_L) begin | |
327 | set_parity_error_dma22<= 1'h0; | |
328 | end else begin | |
329 | set_parity_error_dma22<= (parity_corrupt_config[22] &~parity_corrupt_config_d[22]) | (set_parity_error_dma22 & ~(parity_corrupt_dma_match[22] & corrupt_address)); | |
330 | end // else: !if(!Reset_L) | |
331 | end | |
332 | always@(posedge SysClk) begin | |
333 | if(!Reset_L) begin | |
334 | set_parity_error_dma23<= 1'h0; | |
335 | end else begin | |
336 | set_parity_error_dma23<= (parity_corrupt_config[23] &~parity_corrupt_config_d[23]) | (set_parity_error_dma23 & ~(parity_corrupt_dma_match[23] & corrupt_address ) ); | |
337 | end // else: !if(!Reset_L) | |
338 | end | |
339 | ||
340 | assign set_parity_error = {8'h0, set_parity_error_dma23, set_parity_error_dma22, set_parity_error_dma21, set_parity_error_dma20, | |
341 | set_parity_error_dma19, set_parity_error_dma18, set_parity_error_dma17, set_parity_error_dma16, | |
342 | set_parity_error_dma15, set_parity_error_dma14, set_parity_error_dma13, set_parity_error_dma12, | |
343 | set_parity_error_dma11, set_parity_error_dma10, set_parity_error_dma9, set_parity_error_dma8, | |
344 | set_parity_error_dma7, set_parity_error_dma6, set_parity_error_dma5, set_parity_error_dma4, | |
345 | set_parity_error_dma3, set_parity_error_dma2, set_parity_error_dma1, set_parity_error_dma0 }; | |
346 | ||
347 | assign corrupt_parity = |({parity_corrupt_dma_match} & parity_corrupt_config & set_parity_error) & corrupt_address ; | |
348 | ||
349 | ||
350 | ||
351 | always@(data_in or corrupt_parity) begin | |
352 | if(corrupt_parity) | |
353 | parity = calc_parity( data_in ) ^ 16'h1; | |
354 | else parity = calc_parity( data_in ); | |
355 | end | |
356 | always@(posedge SysClk) begin | |
357 | if(!Reset_L) begin | |
358 | data_out <= 132'h0; | |
359 | parity_to_check <= 16'h0; | |
360 | end else begin | |
361 | data_out <= ram_data_out; | |
362 | parity_to_check <= ram_parity_out; | |
363 | end | |
364 | end | |
365 | ||
366 | ||
367 | always@(data_out) begin | |
368 | parity_out = calc_parity( data_out ); | |
369 | end | |
370 | ||
371 | assign parity_status = (~((parity_out[15] == parity_to_check[15]) && | |
372 | (parity_out[14] == parity_to_check[14]) && | |
373 | (parity_out[13] == parity_to_check[13]) && | |
374 | (parity_out[12] == parity_to_check[12]) && | |
375 | (parity_out[11] == parity_to_check[11]) && | |
376 | (parity_out[10] == parity_to_check[10]) && | |
377 | (parity_out[9 ] == parity_to_check[9]) && | |
378 | (parity_out[8 ] == parity_to_check[8]) && | |
379 | (parity_out[7 ] == parity_to_check[7]) && | |
380 | (parity_out[6 ] == parity_to_check[6]) && | |
381 | (parity_out[5 ] == parity_to_check[5]) && | |
382 | (parity_out[4 ] == parity_to_check[4]) && | |
383 | (parity_out[3 ] == parity_to_check[3]) && | |
384 | (parity_out[2 ] == parity_to_check[2]) && | |
385 | (parity_out[1 ] == parity_to_check[1]) && | |
386 | (parity_out[0 ] == parity_to_check[0]) | |
387 | ) | |
388 | ); | |
389 | ||
390 | ||
391 | endmodule // niu_tdmc_cacheparity | |
392 | ||
393 |