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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / design / sys / iop / niu / rtl / niu_tdmc_cachewrite.v
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AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: niu_tdmc_cachewrite.v
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
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12//
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15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
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21//
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33//
34// ========== Copyright Header End ============================================
35
36
37
38`include "txc_defines.h"
39`include "niu_dmc_reg_defines.h"
40module niu_tdmc_cachewrite (/*AUTOJUNK*/
41 // Outputs
42 DMC_TxCache_SMX_Resp_Accept, updateCacheWritePtrs,
43 meta_resp_dma_num, meta_resp_address, DMA_TxCacheWritePtr,
44 DMA_TxCacheWrite, NoOfValidEntries, DMA_TxCacheWriteEntriesValid,
45 DMA_TxCacheWriteData, parity_corrupt_dma_match, receivedErrorResp,
46 txpref_dma_nack_resp, txpref_nack_resp, txpref_nack_rd_addr,
47 // Inputs
48 SMX_DMC_TxCache_Resp_Rdy, SMX_DMC_TxCache_Resp_DMA_Num,
49 SMX_DMC_TxCache_Resp_Address, SMX_DMC_TxCache_Trans_Complete,
50 SMX_DMC_TxCache_Resp_Complete, SMX_DMC_TxCache_Resp_ByteEnables,
51 SMX_DMC_TxCache_Resp_Data_Length, SMX_DMC_TxCache_Resp_Data_Valid,
52 SMX_DMC_TxCache_Resp_Data, meta_dmc_resp_cmd,
53 meta_dmc_resp_cmd_status, meta_dmc_data_status,
54 DMA0_CacheWritePtrReOrder, DMA1_CacheWritePtrReOrder,
55 DMA2_CacheWritePtrReOrder, DMA3_CacheWritePtrReOrder,
56 DMA4_CacheWritePtrReOrder, DMA5_CacheWritePtrReOrder,
57 DMA6_CacheWritePtrReOrder, DMA7_CacheWritePtrReOrder,
58 DMA8_CacheWritePtrReOrder, DMA9_CacheWritePtrReOrder,
59 DMA10_CacheWritePtrReOrder, DMA11_CacheWritePtrReOrder,
60 DMA12_CacheWritePtrReOrder, DMA13_CacheWritePtrReOrder,
61 DMA14_CacheWritePtrReOrder, DMA15_CacheWritePtrReOrder,
62`ifdef NEPTUNE
63
64 DMA16_CacheWritePtrReOrder, DMA17_CacheWritePtrReOrder,
65 DMA18_CacheWritePtrReOrder, DMA19_CacheWritePtrReOrder,
66 DMA20_CacheWritePtrReOrder, DMA21_CacheWritePtrReOrder,
67 DMA22_CacheWritePtrReOrder, DMA23_CacheWritePtrReOrder,
68`else
69`endif
70 meta_entries_requested_dma0, meta_entries_requested_dma1,
71 meta_entries_requested_dma2, meta_entries_requested_dma3,
72 meta_entries_requested_dma4, meta_entries_requested_dma5,
73 meta_entries_requested_dma6, meta_entries_requested_dma7,
74 meta_entries_requested_dma8, meta_entries_requested_dma9,
75 meta_entries_requested_dma10, meta_entries_requested_dma11,
76 meta_entries_requested_dma12, meta_entries_requested_dma13,
77 meta_entries_requested_dma14, meta_entries_requested_dma15,
78`ifdef NEPTUNE
79 meta_entries_requested_dma16, meta_entries_requested_dma17,
80 meta_entries_requested_dma18, meta_entries_requested_dma19,
81 meta_entries_requested_dma20, meta_entries_requested_dma21,
82 meta_entries_requested_dma22, meta_entries_requested_dma23,
83`else
84`endif
85 SysClk, Reset_L
86 );
87 output DMC_TxCache_SMX_Resp_Accept;
88 output [`NO_OF_DMAS - 1 :0] updateCacheWritePtrs ;
89 output [4:0] meta_resp_dma_num ;
90 output [3:0] meta_resp_address ;
91
92 output [7:0] DMA_TxCacheWritePtr;
93 output DMA_TxCacheWrite ;
94 output [4:0] NoOfValidEntries ;
95 output [3:0] DMA_TxCacheWriteEntriesValid;
96 output [127:0] DMA_TxCacheWriteData;// ???
97 output [`NO_OF_DMAS - 1:0] parity_corrupt_dma_match;
98 output [`NO_OF_DMAS - 1:0] txpref_dma_nack_resp;
99 output txpref_nack_resp ;
100 output [43:0] txpref_nack_rd_addr;
101 output [`NO_OF_DMAS - 1:0] receivedErrorResp;
102
103 input SMX_DMC_TxCache_Resp_Rdy;
104 input [4:0] SMX_DMC_TxCache_Resp_DMA_Num;
105 input [63:0] SMX_DMC_TxCache_Resp_Address;
106 input SMX_DMC_TxCache_Trans_Complete;
107 input SMX_DMC_TxCache_Resp_Complete;
108 input [15:0] SMX_DMC_TxCache_Resp_ByteEnables;
109 input [13:0] SMX_DMC_TxCache_Resp_Data_Length;
110 input SMX_DMC_TxCache_Resp_Data_Valid;
111 input [127:0] SMX_DMC_TxCache_Resp_Data;// ???
112 input [7:0] meta_dmc_resp_cmd;
113
114 input [3:0] meta_dmc_resp_cmd_status;
115 input [3:0] meta_dmc_data_status;
116
117
118 input [3:0] DMA0_CacheWritePtrReOrder;
119 input [3:0] DMA1_CacheWritePtrReOrder;
120 input [3:0] DMA2_CacheWritePtrReOrder;
121 input [3:0] DMA3_CacheWritePtrReOrder;
122 input [3:0] DMA4_CacheWritePtrReOrder;
123 input [3:0] DMA5_CacheWritePtrReOrder;
124 input [3:0] DMA6_CacheWritePtrReOrder;
125 input [3:0] DMA7_CacheWritePtrReOrder;
126 input [3:0] DMA8_CacheWritePtrReOrder;
127 input [3:0] DMA9_CacheWritePtrReOrder;
128 input [3:0] DMA10_CacheWritePtrReOrder;
129 input [3:0] DMA11_CacheWritePtrReOrder;
130 input [3:0] DMA12_CacheWritePtrReOrder;
131 input [3:0] DMA13_CacheWritePtrReOrder;
132 input [3:0] DMA14_CacheWritePtrReOrder;
133 input [3:0] DMA15_CacheWritePtrReOrder;
134 input [4:0] meta_entries_requested_dma0;
135 input [4:0] meta_entries_requested_dma1;
136 input [4:0] meta_entries_requested_dma2;
137 input [4:0] meta_entries_requested_dma3;
138 input [4:0] meta_entries_requested_dma4;
139 input [4:0] meta_entries_requested_dma5;
140 input [4:0] meta_entries_requested_dma6;
141 input [4:0] meta_entries_requested_dma7;
142 input [4:0] meta_entries_requested_dma8;
143 input [4:0] meta_entries_requested_dma9;
144 input [4:0] meta_entries_requested_dma10;
145 input [4:0] meta_entries_requested_dma11;
146 input [4:0] meta_entries_requested_dma12;
147 input [4:0] meta_entries_requested_dma13;
148 input [4:0] meta_entries_requested_dma14;
149 input [4:0] meta_entries_requested_dma15;
150`ifdef NEPTUNE
151
152 input [3:0] DMA16_CacheWritePtrReOrder;
153 input [3:0] DMA17_CacheWritePtrReOrder;
154 input [3:0] DMA18_CacheWritePtrReOrder;
155 input [3:0] DMA19_CacheWritePtrReOrder;
156 input [3:0] DMA20_CacheWritePtrReOrder;
157 input [3:0] DMA21_CacheWritePtrReOrder;
158 input [3:0] DMA22_CacheWritePtrReOrder;
159 input [3:0] DMA23_CacheWritePtrReOrder;
160
161 input [4:0] meta_entries_requested_dma16;
162 input [4:0] meta_entries_requested_dma17;
163 input [4:0] meta_entries_requested_dma18;
164 input [4:0] meta_entries_requested_dma19;
165 input [4:0] meta_entries_requested_dma20;
166 input [4:0] meta_entries_requested_dma21;
167 input [4:0] meta_entries_requested_dma22;
168 input [4:0] meta_entries_requested_dma23;
169
170`else
171`endif // !ifdef CHANNELS_16
172
173 input SysClk;
174 input Reset_L;
175
176 /*--------------------------------------------------------------*/
177 // Parameters and Defines
178 /*--------------------------------------------------------------*/
179
180 parameter CACHE_WRITE_IDLE = 4'h0,
181 WAIT_FOR_TRANS_COMP = 4'h1,
182 UPDATE_CACHE_STATE = 4'h2;
183
184 reg DMC_TxCache_SMX_Resp_Accept;
185 reg [`NO_OF_DMAS - 1:0] updateCacheWritePtrs ;
186 reg [4:0] meta_resp_dma_num ;
187 reg [3:0] meta_resp_address ;
188 reg [4:0] meta_resp_length;
189
190 reg [4:0] meta_entries_requested_dma;
191 reg [7:0] cmd_received;
192
193 reg [7:0] DMA_TxCacheWritePtr;
194 reg DMA_TxCacheWrite ;
195 reg [3:0] NoOfCacheWrites;
196 reg [4:0] NoOfValidEntries ;
197 reg [3:0] DMA_TxCacheWriteEntriesValid;
198 reg SelectCacheWriteContexts;
199 reg [7:0] DMA_TxCacheWritePtr_n;
200 reg [3:0] TxCacheWriteState;
201 reg [127:0] DMA_TxCacheWriteData;// ???
202 reg [`NO_OF_DMAS - 1:0] DMA_CacheWriteUpdate;
203
204 reg [`NO_OF_DMAS - 1:0] parity_corrupt_dma_match;
205
206 reg [`NO_OF_DMAS - 1:0] txpref_dma_nack_resp;
207 reg [`NO_OF_DMAS - 1:0] receivedErrorResp;
208 reg [`NO_OF_DMAS - 1:0] prev_pending_error;
209 reg txpref_nack_resp ;
210 reg [43:0] txpref_nack_rd_addr;
211 reg resp_error_status;
212 reg update_pending_error_status;
213 reg prev_data_error;
214 reg prev_data_error_dma;
215`ifdef NEPTUNE
216 wire prev_data_error_dma23;
217 wire prev_data_error_dma22;
218 wire prev_data_error_dma21;
219 wire prev_data_error_dma20;
220 wire prev_data_error_dma19;
221 wire prev_data_error_dma18;
222 wire prev_data_error_dma17;
223 wire prev_data_error_dma16;
224`else
225`endif
226 wire prev_data_error_dma15;
227 wire prev_data_error_dma14;
228 wire prev_data_error_dma13;
229 wire prev_data_error_dma12;
230 wire prev_data_error_dma11;
231 wire prev_data_error_dma10;
232 wire prev_data_error_dma9;
233 wire prev_data_error_dma8;
234 wire prev_data_error_dma7;
235 wire prev_data_error_dma6;
236 wire prev_data_error_dma5;
237 wire prev_data_error_dma4;
238 wire prev_data_error_dma3;
239 wire prev_data_error_dma2;
240 wire prev_data_error_dma1;
241 wire prev_data_error_dma0;
242
243 //VCS coverage off
244 // synopsys translate_off
245 reg [192:1] CACHE_DATA_WRITE_STATE;
246
247
248 always @(TxCacheWriteState)
249 begin
250 case(TxCacheWriteState)
251 CACHE_WRITE_IDLE : CACHE_DATA_WRITE_STATE = "CACHE_WRITE_IDLE";
252 UPDATE_CACHE_STATE: CACHE_DATA_WRITE_STATE = "UPDATE_CACHE_STATE";
253 WAIT_FOR_TRANS_COMP : CACHE_DATA_WRITE_STATE = "WAIT_FOR_TRANS_COMP";
254 default : CACHE_DATA_WRITE_STATE = "UNKNOWN";
255 endcase
256 end
257
258 // synopsys translate_on
259 //VCS coverage on
260
261
262
263 /*--------------------------------------------------------------*/
264 // Write Back Data State Machine
265 /*--------------------------------------------------------------*/
266
267 // cache response sm - move to a module
268
269 always@(posedge SysClk )
270 if (!Reset_L) begin
271 TxCacheWriteState <= CACHE_WRITE_IDLE;
272 SelectCacheWriteContexts <= 1'b0;
273 DMC_TxCache_SMX_Resp_Accept <= 1'b0;
274 updateCacheWritePtrs <= `NO_OF_DMAS'b0;
275 meta_resp_length <= 5'h0;
276 meta_resp_dma_num <= 5'h0;
277 meta_resp_address <= 4'h0;
278 cmd_received <= 8'h0;
279 txpref_dma_nack_resp <= `NO_OF_DMAS'h0;
280 receivedErrorResp <= `NO_OF_DMAS'h0;
281 txpref_nack_resp <= 1'b0;
282 resp_error_status <= 1'b0;
283 prev_data_error <= 1'b0;
284 update_pending_error_status <= 1'b0;
285 end else begin
286 case(TxCacheWriteState) // synopsys parallel_case
287 CACHE_WRITE_IDLE: begin
288 updateCacheWritePtrs <= `NO_OF_DMAS'b0;
289 prev_data_error <= 1'b0;
290 update_pending_error_status <= 1'b0;
291 if(SMX_DMC_TxCache_Resp_Rdy) begin
292 // This should happen only if the response ID matches that of the txCache
293 // request else its a bug
294 TxCacheWriteState <= WAIT_FOR_TRANS_COMP;
295 meta_resp_dma_num <= SMX_DMC_TxCache_Resp_DMA_Num;
296 // this gets added to the Anchor address
297 //REORDER
298 meta_resp_address <= SMX_DMC_TxCache_Resp_Address[7:4];// -- for reorder
299 meta_resp_length <= SMX_DMC_TxCache_Resp_Data_Length[7:3];
300 SelectCacheWriteContexts <= 1'b1;
301 DMC_TxCache_SMX_Resp_Accept <= 1'b1;
302 // ERROR - Timeout
303 txpref_nack_rd_addr <= SMX_DMC_TxCache_Resp_Address[43:0];
304 cmd_received <= meta_dmc_resp_cmd;
305 resp_error_status <= (meta_dmc_resp_cmd_status==4'hf) ;
306
307 end else begin // if (SMX_DMC_TxCache_Resp_Rdy)
308 // Just wait
309 meta_resp_length <= 5'h0;
310 meta_resp_dma_num <= 5'h0;
311 TxCacheWriteState <= CACHE_WRITE_IDLE;
312 SelectCacheWriteContexts <= 1'b0;
313 DMC_TxCache_SMX_Resp_Accept <= 1'b0;
314 end // else: !if(SMX_DMC_TxCache_Resp_Rdy)
315 end // case: CACHE_WRITE_IDLE
316 WAIT_FOR_TRANS_COMP: begin
317 SelectCacheWriteContexts <= 1'b0;
318 DMC_TxCache_SMX_Resp_Accept <= 1'b0;
319
320 if(SMX_DMC_TxCache_Trans_Complete & (resp_error_status | ( cmd_received== 8'h6/*COMPLETIONWITHOUTDATA*/)| ( prev_data_error | (meta_dmc_data_status==4'hf)))) begin
321 updateCacheWritePtrs <= `NO_OF_DMAS'h0;
322 txpref_nack_resp <= 1'b1;
323 txpref_dma_nack_resp <= DMA_CacheWriteUpdate;
324 receivedErrorResp <= DMA_CacheWriteUpdate;
325 end else if(SMX_DMC_TxCache_Trans_Complete &~resp_error_status & ( cmd_received== 8'h5/*COMPLETIONWITHDATA*/))
326 updateCacheWritePtrs <= DMA_CacheWriteUpdate;
327 else updateCacheWritePtrs <= `NO_OF_DMAS'h0;
328
329 if(SMX_DMC_TxCache_Trans_Complete | SMX_DMC_TxCache_Resp_Complete ) begin
330 TxCacheWriteState <= UPDATE_CACHE_STATE;
331 update_pending_error_status <= 1'b1;
332 end else begin // if (SMX_DMC_TxCache_Trans_Complete)
333 TxCacheWriteState <= WAIT_FOR_TRANS_COMP;
334 end // else: !if(SMX_DMC_TxCache_Trans_Complete)
335
336 if(SMX_DMC_TxCache_Resp_Data_Valid & (meta_dmc_data_status==4'hf) & ~SMX_DMC_TxCache_Trans_Complete) begin
337 prev_data_error <= prev_data_error| prev_data_error_dma | 1'b1;
338 end else if(SMX_DMC_TxCache_Trans_Complete) begin
339 prev_data_error <= 1'b0;
340 end
341 end // case: WAIT_FOR_TRANS_COMP
342 UPDATE_CACHE_STATE: begin
343 update_pending_error_status <= 1'b0;
344 txpref_dma_nack_resp <= `NO_OF_DMAS'h0;
345 receivedErrorResp <= `NO_OF_DMAS'h0;
346 updateCacheWritePtrs <= `NO_OF_DMAS'b0;
347 txpref_nack_resp <= 1'b0;
348 resp_error_status <= 1'b0;
349 TxCacheWriteState <= CACHE_WRITE_IDLE;
350 end
351
352 endcase // case(TxCacheWriteState)
353
354 end // else: !if(!Reset_L)
355
356
357
358 // common cache engine- module
359
360 always@(posedge SysClk )
361 if (!Reset_L) begin
362 DMA_TxCacheWritePtr_n <= 8'b0;
363 DMA_CacheWriteUpdate <= `NO_OF_DMAS'h0;
364 parity_corrupt_dma_match <= `NO_OF_DMAS'h0;
365 meta_entries_requested_dma <= 5'h0;
366 prev_data_error_dma <= 1'b0;
367 end else begin // if (!Reset_L)
368 if(SelectCacheWriteContexts ) begin
369 case(meta_resp_dma_num) // synopsys full_case parallel_case
370 // REORDER
371 // offset = ( meta_resp_address > anchor_address ) ? ( meta_resp_address - anchor_address ) :
372 // ( 4'h8 - meta_resp_address + anchor_address);;
373 `DMA_CHANNEL_ZERO: begin
374 DMA_TxCacheWritePtr_n <= {5'h0,DMA0_CacheWritePtrReOrder[2:0] } + `DMA0_Cache_OFFSET;
375 meta_entries_requested_dma <= meta_entries_requested_dma0;
376 DMA_CacheWriteUpdate <= `NO_OF_DMAS'h1;
377 parity_corrupt_dma_match <= `NO_OF_DMAS'h1;
378 prev_data_error_dma <= prev_data_error_dma0;
379 end // case: `DMA_CHANNEL_ZERO
380 `DMA_CHANNEL_ONE: begin
381 DMA_TxCacheWritePtr_n <= {5'h0,DMA1_CacheWritePtrReOrder[2:0] } + `DMA1_Cache_OFFSET;
382 meta_entries_requested_dma <= meta_entries_requested_dma1;
383 DMA_CacheWriteUpdate <= `NO_OF_DMAS'h2;
384 parity_corrupt_dma_match <= `NO_OF_DMAS'h2;
385 prev_data_error_dma <= prev_data_error_dma1;
386 end
387 `DMA_CHANNEL_TWO: begin
388 meta_entries_requested_dma <= meta_entries_requested_dma2;
389 DMA_TxCacheWritePtr_n <= {5'h0,DMA2_CacheWritePtrReOrder[2:0] } + `DMA2_Cache_OFFSET;
390 DMA_CacheWriteUpdate <= `NO_OF_DMAS'h4;
391 parity_corrupt_dma_match <= `NO_OF_DMAS'h4;
392 prev_data_error_dma <= prev_data_error_dma2;
393 end
394 `DMA_CHANNEL_THREE: begin
395 meta_entries_requested_dma <= meta_entries_requested_dma3;
396 DMA_TxCacheWritePtr_n <= {5'h0,DMA3_CacheWritePtrReOrder[2:0] } + `DMA3_Cache_OFFSET;
397 DMA_CacheWriteUpdate <= `NO_OF_DMAS'h8;
398 parity_corrupt_dma_match <= `NO_OF_DMAS'h8;
399 prev_data_error_dma <= prev_data_error_dma3;
400 end
401 `DMA_CHANNEL_FOUR: begin
402 meta_entries_requested_dma <= meta_entries_requested_dma4;
403 DMA_TxCacheWritePtr_n <= {5'h0,DMA4_CacheWritePtrReOrder[2:0] } + `DMA4_Cache_OFFSET;
404 DMA_CacheWriteUpdate <= `NO_OF_DMAS'h10;
405 parity_corrupt_dma_match <= `NO_OF_DMAS'h10;
406 prev_data_error_dma <= prev_data_error_dma4;
407 end
408 `DMA_CHANNEL_FIVE: begin
409 meta_entries_requested_dma <= meta_entries_requested_dma5;
410 DMA_TxCacheWritePtr_n <= {5'h0,DMA5_CacheWritePtrReOrder[2:0] } + `DMA5_Cache_OFFSET;
411 DMA_CacheWriteUpdate <= `NO_OF_DMAS'h20;
412 parity_corrupt_dma_match <= `NO_OF_DMAS'h20;
413 prev_data_error_dma <= prev_data_error_dma5;
414 end
415 `DMA_CHANNEL_SIX: begin
416 meta_entries_requested_dma <= meta_entries_requested_dma6;
417 DMA_TxCacheWritePtr_n <= {5'h0,DMA6_CacheWritePtrReOrder[2:0] } + `DMA6_Cache_OFFSET;
418 DMA_CacheWriteUpdate <= `NO_OF_DMAS'h40;
419 parity_corrupt_dma_match <= `NO_OF_DMAS'h40;
420 prev_data_error_dma <= prev_data_error_dma6;
421 end
422 `DMA_CHANNEL_SEVEN: begin
423 meta_entries_requested_dma <= meta_entries_requested_dma7;
424 DMA_TxCacheWritePtr_n <= {5'h0,DMA7_CacheWritePtrReOrder[2:0] } + `DMA7_Cache_OFFSET;
425 DMA_CacheWriteUpdate <= `NO_OF_DMAS'h80;
426 parity_corrupt_dma_match <= `NO_OF_DMAS'h80;
427 prev_data_error_dma <= prev_data_error_dma7;
428 end
429 `DMA_CHANNEL_EIGHT: begin
430 meta_entries_requested_dma <= meta_entries_requested_dma8;
431 DMA_TxCacheWritePtr_n <= {5'h0,DMA8_CacheWritePtrReOrder[2:0] } + `DMA8_Cache_OFFSET;
432 DMA_CacheWriteUpdate <= `NO_OF_DMAS'h100;
433 parity_corrupt_dma_match <= `NO_OF_DMAS'h100;
434 prev_data_error_dma <= prev_data_error_dma8;
435 end
436 `DMA_CHANNEL_NINE: begin
437 meta_entries_requested_dma <= meta_entries_requested_dma9;
438 DMA_TxCacheWritePtr_n <= {5'h0,DMA9_CacheWritePtrReOrder[2:0] } + `DMA9_Cache_OFFSET;
439 DMA_CacheWriteUpdate <= `NO_OF_DMAS'h200;
440 parity_corrupt_dma_match <= `NO_OF_DMAS'h200;
441 prev_data_error_dma <= prev_data_error_dma9;
442 end
443 `DMA_CHANNEL_TEN: begin
444 meta_entries_requested_dma <= meta_entries_requested_dma10;
445 DMA_TxCacheWritePtr_n <= {5'h0,DMA10_CacheWritePtrReOrder[2:0] } + `DMA10_Cache_OFFSET;
446 DMA_CacheWriteUpdate <= `NO_OF_DMAS'h400;
447 parity_corrupt_dma_match <= `NO_OF_DMAS'h400;
448 prev_data_error_dma <= prev_data_error_dma10;
449 end
450 `DMA_CHANNEL_ELEVEN: begin
451 meta_entries_requested_dma <= meta_entries_requested_dma11;
452 DMA_TxCacheWritePtr_n <= {5'h0,DMA11_CacheWritePtrReOrder[2:0] } + `DMA11_Cache_OFFSET;
453 DMA_CacheWriteUpdate <= `NO_OF_DMAS'h800;
454 parity_corrupt_dma_match <= `NO_OF_DMAS'h800;
455 prev_data_error_dma <= prev_data_error_dma11;
456 end
457 `DMA_CHANNEL_TWELVE: begin
458 meta_entries_requested_dma <= meta_entries_requested_dma12;
459 DMA_TxCacheWritePtr_n <= {5'h0,DMA12_CacheWritePtrReOrder[2:0] } + `DMA12_Cache_OFFSET;
460 DMA_CacheWriteUpdate <= `NO_OF_DMAS'h1000;
461 parity_corrupt_dma_match <= `NO_OF_DMAS'h1000;
462 prev_data_error_dma <= prev_data_error_dma12;
463 end
464 `DMA_CHANNEL_THIRTEEN: begin
465 meta_entries_requested_dma <= meta_entries_requested_dma13;
466 DMA_TxCacheWritePtr_n <= {5'h0,DMA13_CacheWritePtrReOrder[2:0] } + `DMA13_Cache_OFFSET;
467 DMA_CacheWriteUpdate <= `NO_OF_DMAS'h2000;
468 parity_corrupt_dma_match <= `NO_OF_DMAS'h2000;
469 prev_data_error_dma <= prev_data_error_dma13;
470 end
471 `DMA_CHANNEL_FOURTEEN: begin
472 meta_entries_requested_dma <= meta_entries_requested_dma14;
473 DMA_TxCacheWritePtr_n <= {5'h0,DMA14_CacheWritePtrReOrder[2:0] } + `DMA14_Cache_OFFSET;
474 DMA_CacheWriteUpdate <= `NO_OF_DMAS'h4000;
475 parity_corrupt_dma_match <=`NO_OF_DMAS'h4000;
476 prev_data_error_dma <= prev_data_error_dma14;
477 end
478 `DMA_CHANNEL_FIFTEEN: begin
479 meta_entries_requested_dma <= meta_entries_requested_dma15;
480 DMA_TxCacheWritePtr_n <= {5'h0,DMA15_CacheWritePtrReOrder[2:0] } + `DMA15_Cache_OFFSET;
481 DMA_CacheWriteUpdate <= `NO_OF_DMAS'h8000;
482 parity_corrupt_dma_match <= `NO_OF_DMAS'h8000;
483 prev_data_error_dma <= prev_data_error_dma15;
484 end
485 `ifdef NEPTUNE
486
487 `DMA_CHANNEL_SIXTEEN: begin
488 meta_entries_requested_dma <= meta_entries_requested_dma16;
489 DMA_TxCacheWritePtr_n <= {5'h0,DMA16_CacheWritePtrReOrder[2:0] } + `DMA16_Cache_OFFSET;
490 DMA_CacheWriteUpdate <= `NO_OF_DMAS'h10000;
491 parity_corrupt_dma_match <= `NO_OF_DMAS'h10000;
492 prev_data_error_dma <= prev_data_error_dma16;
493 end
494 `DMA_CHANNEL_SEVENTEEN: begin
495 meta_entries_requested_dma <= meta_entries_requested_dma17;
496 DMA_TxCacheWritePtr_n <= {5'h0,DMA17_CacheWritePtrReOrder[2:0] } + `DMA17_Cache_OFFSET;
497 DMA_CacheWriteUpdate <= `NO_OF_DMAS'h20000;
498 parity_corrupt_dma_match <=`NO_OF_DMAS'h20000;
499 prev_data_error_dma <= prev_data_error_dma17;
500 end
501 `DMA_CHANNEL_EIGHTEEN: begin
502 meta_entries_requested_dma <= meta_entries_requested_dma18;
503 DMA_TxCacheWritePtr_n <= {5'h0,DMA18_CacheWritePtrReOrder[2:0] } + `DMA18_Cache_OFFSET;
504 DMA_CacheWriteUpdate <= `NO_OF_DMAS'h40000;
505 parity_corrupt_dma_match <= `NO_OF_DMAS'h40000;
506 prev_data_error_dma <= prev_data_error_dma18;
507 end
508 `DMA_CHANNEL_NINETEEN: begin
509 meta_entries_requested_dma <= meta_entries_requested_dma19;
510 DMA_TxCacheWritePtr_n <= {5'h0,DMA19_CacheWritePtrReOrder[2:0] } + `DMA19_Cache_OFFSET;
511 DMA_CacheWriteUpdate <= `NO_OF_DMAS'h80000;
512 parity_corrupt_dma_match <= `NO_OF_DMAS'h80000;
513 prev_data_error_dma <= prev_data_error_dma19;
514 end
515 `DMA_CHANNEL_TWENTY: begin
516 meta_entries_requested_dma <= meta_entries_requested_dma20;
517 DMA_TxCacheWritePtr_n <= {5'h0,DMA20_CacheWritePtrReOrder[2:0] } + `DMA20_Cache_OFFSET;
518 DMA_CacheWriteUpdate <= `NO_OF_DMAS'h100000;
519 parity_corrupt_dma_match <=`NO_OF_DMAS'h100000;
520 prev_data_error_dma <= prev_data_error_dma20;
521 end
522 `DMA_CHANNEL_TWENTYONE: begin
523 meta_entries_requested_dma <= meta_entries_requested_dma21;
524 DMA_TxCacheWritePtr_n <= {5'h0,DMA21_CacheWritePtrReOrder[2:0] } + `DMA21_Cache_OFFSET;
525 DMA_CacheWriteUpdate <= `NO_OF_DMAS'h200000;
526 parity_corrupt_dma_match <= `NO_OF_DMAS'h200000;
527 prev_data_error_dma <= prev_data_error_dma21;
528 end
529 `DMA_CHANNEL_TWENTYTWO: begin
530 meta_entries_requested_dma <= meta_entries_requested_dma22;
531 DMA_TxCacheWritePtr_n <= {5'h0,DMA22_CacheWritePtrReOrder[2:0] } + `DMA22_Cache_OFFSET;
532 DMA_CacheWriteUpdate <= `NO_OF_DMAS'h400000;
533 parity_corrupt_dma_match <= `NO_OF_DMAS'h400000;
534 prev_data_error_dma <= prev_data_error_dma22;
535 end
536 `DMA_CHANNEL_TWENTYTHREE: begin
537 meta_entries_requested_dma <= meta_entries_requested_dma23;
538 DMA_TxCacheWritePtr_n <= {5'h0,DMA23_CacheWritePtrReOrder[2:0] } + `DMA23_Cache_OFFSET;
539 DMA_CacheWriteUpdate <= `NO_OF_DMAS'h800000;
540 parity_corrupt_dma_match <= `NO_OF_DMAS'h800000;
541 prev_data_error_dma <= prev_data_error_dma23;
542 end
543 `else
544 `endif // !ifdef CHANNELS_16
545 default: begin
546 DMA_TxCacheWritePtr_n <= 8'h0;
547 meta_entries_requested_dma <= 5'h0;
548 DMA_CacheWriteUpdate <= `NO_OF_DMAS'h0;
549 parity_corrupt_dma_match <= `NO_OF_DMAS'h0;
550 prev_data_error_dma <= 1'b0;
551 end
552
553
554 //
555 endcase // case(DMC_TxCache_SMX_Req_DMA_Num)
556 end
557 end // else: !if(!Reset_L)
558
559 `ifdef NEPTUNE
560 assign {prev_data_error_dma23, prev_data_error_dma22, prev_data_error_dma21, prev_data_error_dma20,
561 prev_data_error_dma19, prev_data_error_dma18, prev_data_error_dma17, prev_data_error_dma16,
562 prev_data_error_dma15, prev_data_error_dma14, prev_data_error_dma13, prev_data_error_dma12,
563 prev_data_error_dma11, prev_data_error_dma10, prev_data_error_dma9, prev_data_error_dma8,
564 prev_data_error_dma7, prev_data_error_dma6, prev_data_error_dma5, prev_data_error_dma4,
565 prev_data_error_dma3, prev_data_error_dma2, prev_data_error_dma1, prev_data_error_dma0 } = prev_pending_error;
566 `else
567 assign {prev_data_error_dma15, prev_data_error_dma14, prev_data_error_dma13, prev_data_error_dma12,
568 prev_data_error_dma11, prev_data_error_dma10, prev_data_error_dma9, prev_data_error_dma8,
569 prev_data_error_dma7, prev_data_error_dma6, prev_data_error_dma5, prev_data_error_dma4,
570 prev_data_error_dma3, prev_data_error_dma2, prev_data_error_dma1, prev_data_error_dma0 } = prev_pending_error;
571 `endif
572
573 always@(posedge SysClk )
574 if (!Reset_L) begin
575 prev_pending_error<=`NO_OF_DMAS'h0;
576 end else begin
577 if(update_pending_error_status ) begin
578 case(meta_resp_dma_num) // synopsys full_case parallel_case
579 `DMA_CHANNEL_ZERO: prev_pending_error[0] <= prev_data_error;
580 `DMA_CHANNEL_ONE: prev_pending_error[1] <= prev_data_error;
581 `DMA_CHANNEL_TWO: prev_pending_error[2] <= prev_data_error;
582 `DMA_CHANNEL_THREE: prev_pending_error[3] <= prev_data_error;
583 `DMA_CHANNEL_FOUR: prev_pending_error[4] <= prev_data_error;
584 `DMA_CHANNEL_FIVE: prev_pending_error[5] <= prev_data_error;
585 `DMA_CHANNEL_SIX: prev_pending_error[6] <= prev_data_error;
586 `DMA_CHANNEL_SEVEN: prev_pending_error[7] <= prev_data_error;
587 `DMA_CHANNEL_EIGHT: prev_pending_error[8] <= prev_data_error;
588 `DMA_CHANNEL_NINE: prev_pending_error[9] <= prev_data_error;
589 `DMA_CHANNEL_TEN: prev_pending_error[10] <= prev_data_error;
590 `DMA_CHANNEL_ELEVEN: prev_pending_error[11] <= prev_data_error;
591 `DMA_CHANNEL_TWELVE: prev_pending_error[12] <= prev_data_error;
592 `DMA_CHANNEL_THIRTEEN: prev_pending_error[13] <= prev_data_error;
593 `DMA_CHANNEL_FOURTEEN: prev_pending_error[14] <= prev_data_error;
594 `DMA_CHANNEL_FIFTEEN: prev_pending_error[15] <= prev_data_error;
595`ifdef NEPTUNE
596 `DMA_CHANNEL_SIXTEEN: prev_pending_error[16] <= prev_data_error;
597 `DMA_CHANNEL_SEVENTEEN: prev_pending_error[17] <= prev_data_error;
598 `DMA_CHANNEL_EIGHTEEN: prev_pending_error[18] <= prev_data_error;
599 `DMA_CHANNEL_NINETEEN: prev_pending_error[19] <= prev_data_error;
600 `DMA_CHANNEL_TWENTY: prev_pending_error[20] <= prev_data_error;
601 `DMA_CHANNEL_TWENTYONE: prev_pending_error[21] <= prev_data_error;
602 `DMA_CHANNEL_TWENTYTWO: prev_pending_error[22] <= prev_data_error;
603 `DMA_CHANNEL_TWENTYTHREE: prev_pending_error[23] <= prev_data_error;
604`endif
605 default: prev_pending_error<=`NO_OF_DMAS'h0;
606 endcase // case(meta_resp_dma_num)
607 end // if (SelectCacheWriteContexts )
608 end // else: !if(!Reset_L)
609
610
611 // cache pointer module
612
613 always@(posedge SysClk )
614 if (!Reset_L) begin
615 DMA_TxCacheWritePtr <= 8'b0;
616 DMA_TxCacheWrite <= 1'b0;
617 NoOfCacheWrites <= 4'b0;
618 NoOfValidEntries <= 5'b0;
619 DMA_TxCacheWriteEntriesValid <= 4'h0;
620
621 end // if (!Reset_L)
622 else begin
623 if(SelectCacheWriteContexts) begin
624 NoOfCacheWrites <= 4'b0;
625 NoOfValidEntries <= 5'b0;
626 DMA_TxCacheWrite <= 1'b0;
627 end else begin
628 if( SMX_DMC_TxCache_Resp_Data_Valid & ( meta_dmc_data_status!=4'hf) ) begin // if (!Reset_L)
629 DMA_TxCacheWrite <= 1'b1;
630 DMA_TxCacheWritePtr <= {DMA_TxCacheWritePtr_n[7:3], (DMA_TxCacheWritePtr_n[2:0] + NoOfCacheWrites[2:0]) };
631 DMA_TxCacheWriteData <= SMX_DMC_TxCache_Resp_Data; // ???? size
632 DMA_TxCacheWriteEntriesValid <= {2'h0,(|SMX_DMC_TxCache_Resp_ByteEnables[15:8]) ,(|SMX_DMC_TxCache_Resp_ByteEnables[7:0])};
633 NoOfCacheWrites <= NoOfCacheWrites + 1; // just to keep track of how many bytes have been written
634 NoOfValidEntries <= meta_entries_requested_dma;
635 // synopsys translate_off
636 if(~SMX_DMC_TxCache_Resp_ByteEnables[8] & ~SMX_DMC_TxCache_Resp_ByteEnables[0])
637 $display(" %m : Time - %t Byte Enables into TDMC not set correctly!! ERROR ",$time);
638 if(NoOfCacheWrites > 8 ) begin
639 $display("ERROR -- %m Time - %t, No of cache writes in TMDC - %d ",$time,NoOfCacheWrites);
640 end
641 // synopsys translate_on
642 end else begin // if ( SMX_DMC_TxCache_Resp_Data_Valid)
643 DMA_TxCacheWrite <= 1'b0;
644 end // else: !if( SMX_DMC_TxCache_Resp_Data_Valid)
645 end // else: !if(SelectCacheWriteContexts)
646 end // else: !if(!Reset_L)
647 // cache pointer module
648endmodule // niu_tdmc_cachewrite
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