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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: niu_tdmc_debug.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | /********************************************************************* | |
36 | * | |
37 | * niu_tdmc_debug..v | |
38 | * | |
39 | * NIU TDMC Top Level Debug Module | |
40 | * | |
41 | * Orignal Author(s): Arvind Srinivasan | |
42 | * Modifier(s): | |
43 | * Project(s): Neptune/Niagara 2 | |
44 | * | |
45 | * Copyright (c) 2004 Sun Microsystems, Inc. | |
46 | * | |
47 | * All Rights Reserved. | |
48 | * | |
49 | * This verilog model is the confidential and proprietary property of | |
50 | * Sun Microsystems, Inc., and the possession or use of this model | |
51 | * requires a written license from Sun Microsystems, Inc. | |
52 | * | |
53 | **********************************************************************/ | |
54 | ||
55 | `include "timescale.v" | |
56 | ||
57 | module niu_tdmc_debug( /*AUTOARG*/ | |
58 | // Outputs | |
59 | tdmc_debug_port, | |
60 | // Inputs | |
61 | SysClk, Reset_L, debug_select, training_vector, TxCacheFetchState, | |
62 | ||
63 | dma0_debug_port, dma1_debug_port, dma2_debug_port, dma3_debug_port, | |
64 | dma4_debug_port, dma5_debug_port, dma6_debug_port, dma7_debug_port, | |
65 | dma8_debug_port, dma9_debug_port, dma10_debug_port, dma11_debug_port, | |
66 | dma12_debug_port, dma13_debug_port, dma14_debug_port, dma15_debug_port, | |
67 | ||
68 | `ifdef NEPTUNE | |
69 | dma16_debug_port, dma17_debug_port, dma18_debug_port, dma19_debug_port, | |
70 | dma20_debug_port, dma21_debug_port, dma22_debug_port, dma23_debug_port, | |
71 | `else | |
72 | `endif | |
73 | mbox_debug_state | |
74 | ); | |
75 | ||
76 | `include "txc_defines.h" | |
77 | ||
78 | // Global Signals | |
79 | input SysClk; | |
80 | input Reset_L; | |
81 | ||
82 | // To Debug Module | |
83 | output [31:0] tdmc_debug_port; | |
84 | ||
85 | reg [31:0] tdmc_debug_port; | |
86 | ||
87 | // From Control Regs | |
88 | input [5:0] debug_select ; | |
89 | input [31:0] training_vector ; | |
90 | input [3:0] TxCacheFetchState; | |
91 | input [11:0] mbox_debug_state; | |
92 | ||
93 | input[31:0] dma0_debug_port; | |
94 | input[31:0] dma1_debug_port; | |
95 | input[31:0] dma2_debug_port; | |
96 | input[31:0] dma3_debug_port; | |
97 | input[31:0] dma4_debug_port; | |
98 | input[31:0] dma5_debug_port; | |
99 | input[31:0] dma6_debug_port; | |
100 | input[31:0] dma7_debug_port; | |
101 | input[31:0] dma8_debug_port; | |
102 | input[31:0] dma9_debug_port; | |
103 | input[31:0] dma10_debug_port; | |
104 | input[31:0] dma11_debug_port; | |
105 | input[31:0] dma12_debug_port; | |
106 | input[31:0] dma13_debug_port; | |
107 | input[31:0] dma14_debug_port; | |
108 | input[31:0] dma15_debug_port; | |
109 | ||
110 | `ifdef NEPTUNE | |
111 | input[31:0] dma16_debug_port; | |
112 | input[31:0] dma17_debug_port; | |
113 | input[31:0] dma18_debug_port; | |
114 | input[31:0] dma19_debug_port; | |
115 | input[31:0] dma20_debug_port; | |
116 | input[31:0] dma21_debug_port; | |
117 | input[31:0] dma22_debug_port; | |
118 | input[31:0] dma23_debug_port; | |
119 | ||
120 | `else | |
121 | `endif | |
122 | ||
123 | /*--------------------------------------------------------------*/ | |
124 | // Debug Block | |
125 | /*--------------------------------------------------------------*/ | |
126 | ||
127 | ||
128 | always @(posedge SysClk) | |
129 | if (!Reset_L) tdmc_debug_port <= #`SD 32'h0; | |
130 | else | |
131 | case(debug_select) | |
132 | 6'h0: tdmc_debug_port <= #`SD 32'h0; | |
133 | `TDMC_CACHE_FETCH_STATE: tdmc_debug_port <= #`SD {28'h0,TxCacheFetchState}; | |
134 | `TDMC_MBOX_STATE: tdmc_debug_port <= #`SD {20'h0,mbox_debug_state}; | |
135 | `TDMC_DMA0_DEBUG_SEL: tdmc_debug_port<= #`SD dma0_debug_port; | |
136 | `TDMC_DMA1_DEBUG_SEL: tdmc_debug_port<= #`SD dma1_debug_port; | |
137 | `TDMC_DMA2_DEBUG_SEL: tdmc_debug_port<= #`SD dma2_debug_port; | |
138 | `TDMC_DMA3_DEBUG_SEL: tdmc_debug_port<= #`SD dma3_debug_port; | |
139 | `TDMC_DMA4_DEBUG_SEL: tdmc_debug_port<= #`SD dma4_debug_port; | |
140 | `TDMC_DMA5_DEBUG_SEL: tdmc_debug_port<= #`SD dma5_debug_port; | |
141 | `TDMC_DMA6_DEBUG_SEL: tdmc_debug_port<= #`SD dma6_debug_port; | |
142 | `TDMC_DMA7_DEBUG_SEL: tdmc_debug_port<= #`SD dma7_debug_port; | |
143 | `TDMC_DMA8_DEBUG_SEL: tdmc_debug_port<= #`SD dma8_debug_port; | |
144 | `TDMC_DMA9_DEBUG_SEL: tdmc_debug_port<= #`SD dma9_debug_port; | |
145 | `TDMC_DMA10_DEBUG_SEL: tdmc_debug_port<= #`SD dma10_debug_port; | |
146 | `TDMC_DMA11_DEBUG_SEL: tdmc_debug_port<= #`SD dma11_debug_port; | |
147 | `TDMC_DMA12_DEBUG_SEL: tdmc_debug_port<= #`SD dma12_debug_port; | |
148 | `TDMC_DMA13_DEBUG_SEL: tdmc_debug_port<= #`SD dma13_debug_port; | |
149 | `TDMC_DMA14_DEBUG_SEL: tdmc_debug_port<= #`SD dma14_debug_port; | |
150 | `TDMC_DMA15_DEBUG_SEL: tdmc_debug_port<= #`SD dma15_debug_port; | |
151 | ||
152 | `ifdef NEPTUNE | |
153 | `TDMC_DMA16_DEBUG_SEL: tdmc_debug_port<= #`SD dma16_debug_port; | |
154 | `TDMC_DMA17_DEBUG_SEL: tdmc_debug_port<= #`SD dma17_debug_port; | |
155 | `TDMC_DMA18_DEBUG_SEL: tdmc_debug_port<= #`SD dma18_debug_port; | |
156 | `TDMC_DMA19_DEBUG_SEL: tdmc_debug_port<= #`SD dma19_debug_port; | |
157 | `TDMC_DMA20_DEBUG_SEL: tdmc_debug_port<= #`SD dma20_debug_port; | |
158 | `TDMC_DMA21_DEBUG_SEL: tdmc_debug_port<= #`SD dma21_debug_port; | |
159 | `TDMC_DMA22_DEBUG_SEL: tdmc_debug_port<= #`SD dma22_debug_port; | |
160 | `TDMC_DMA23_DEBUG_SEL: tdmc_debug_port<= #`SD dma23_debug_port; | |
161 | `else | |
162 | `endif | |
163 | `TDMC_TRAINING_SET: tdmc_debug_port <= #`SD ~tdmc_debug_port; | |
164 | `TDMC_TRAINING_LOAD: tdmc_debug_port <= #`SD training_vector; | |
165 | ||
166 | default: tdmc_debug_port <= tdmc_debug_port; | |
167 | ||
168 | endcase | |
169 | ||
170 | endmodule |