Initial commit of OpenSPARC T2 design and verification files.

[OpenSPARC-T2-DV] / design / sys / iop / niu / rtl / niu_tdmc_reset.v

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// OpenSPARC T2 Processor File: niu_tdmc_reset.v
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/*********************************************************************
 *
 *  niu_tdmc_reset.v
 *
 *  Reset Block, includes LogicVision Reset Gating 
 *
 *  Orignal Author(s):   Rahoul Puri
 *  Modifier(s):	Arvind Srinivasan
 *  Project(s):          Neptune/Niagara 2
 *
 *  Copyright (c) 2003   Sun Microsystems, Inc.
 *
 *  All Rights Reserved.
 *
 *  This verilog model is the confidential and proprietary property of
 *  Sun Microsystems, Inc., and the possession or use of this model
 *  requires a written license from Sun Microsystems, Inc.
 *
 **********************************************************************/

`timescale 1ns/100ps

module niu_tdmc_reset (
        SysClk,
        niu_reset_l,
	`ifdef NEPTUNE
	`else
	sram_reset,
	`endif
        Reset_L
       );

`include "txc_defines.h"

// Clock & Reset
input   SysClk;
input   niu_reset_l;
`ifdef NEPTUNE
`else
output sram_reset;
`endif

output  Reset_L;

/*--------------------------------------------------------------*/
// Registers & Wires
/*--------------------------------------------------------------*/
   reg 	resetDlyOneCycle_l;
   wire Reset_L;
   wire Reset_L_prebuf;
`ifdef NEPTUNE
`else
   wire sram_reset;
`endif

/*--------------------------------------------------------------*/
// Assigns
/*--------------------------------------------------------------*/
assign Reset_L_prebuf = resetDlyOneCycle_l;

 
`ifdef NEPTUNE
      assign Reset_L = Reset_L_prebuf;
`else
   assign Reset_L = Reset_L_prebuf;
   assign sram_reset = ~Reset_L;
`endif
  

/*--------------------------------------------------------------*/
// Control Logic
/*--------------------------------------------------------------*/
 always @ (posedge SysClk)
   begin
     resetDlyOneCycle_l <= #`SD niu_reset_l;
   end
  
endmodule