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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: niu_txc.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | /********************************************************************* | |
36 | * | |
37 | * niu_txc.v | |
38 | * | |
39 | * TXC Engine Core | |
40 | * | |
41 | * Orignal Author (s): Rahoul Puri | |
42 | * Modifier (s): | |
43 | * Project (s): Neptune | |
44 | * | |
45 | * Copyright (c) 2004 Sun Microsystems, Inc. | |
46 | * | |
47 | * All Rights Reserved. | |
48 | * | |
49 | * This verilog model is the confidential and proprietary property of | |
50 | * Sun Microsystems, Inc., and the possession or use of this model | |
51 | * requires a written license from Sun Microsystems, Inc. | |
52 | * | |
53 | **********************************************************************/ | |
54 | ||
55 | module niu_txc ( | |
56 | niu_clk, | |
57 | niu_reset_l, | |
58 | txc_debug_port, | |
59 | ||
60 | `ifdef NEPTUNE | |
61 | `else | |
62 | iol2clk, | |
63 | l2clk_2x, | |
64 | tcu_aclk, | |
65 | tcu_bclk, | |
66 | tcu_mbist_bisi_en, | |
67 | tcu_scan_en, | |
68 | tcu_se_scancollar_in, | |
69 | tcu_se_scancollar_out, | |
70 | tcu_array_wr_inhibit, | |
71 | tcu_mbist_user_mode, | |
72 | tcu_rtx_txc_txe0_mbist_start, | |
73 | rtx_txc_txe0_tcu_mbist_fail, | |
74 | rtx_txc_txe0_tcu_mbist_done, | |
75 | rtx_txc_txe0_mbist_scan_in, | |
76 | rtx_txc_txe0_mbist_scan_out, | |
77 | rtx_txc_txe0_dmo_dout, | |
78 | tcu_rtx_txc_txe1_mbist_start, | |
79 | rtx_txc_txe1_tcu_mbist_fail, | |
80 | rtx_txc_txe1_tcu_mbist_done, | |
81 | rtx_txc_txe1_mbist_scan_in, | |
82 | rtx_txc_txe1_mbist_scan_out, | |
83 | rtx_txc_txe1_dmo_dout, | |
84 | ||
85 | hdr_sram_wr_en_txc0_re, | |
86 | hdr_sram_red_clr_txc0_re, | |
87 | hdr_sram_wr_en_txc0_st, | |
88 | hdr_sram_red_clr_txc0_st, | |
89 | hdr_sram_rid_txc0_re, | |
90 | hdr_sram_rid_txc0_st, | |
91 | hdr_sram_rvalue_txc0_re, | |
92 | hdr_sram_rvalue_txc0_st, | |
93 | sram_hdr_read_data_txc0_re, | |
94 | sram_hdr_read_data_txc0_st, | |
95 | ||
96 | hdr_sram_wr_en_txc1_re, | |
97 | hdr_sram_red_clr_txc1_re, | |
98 | hdr_sram_wr_en_txc1_st, | |
99 | hdr_sram_red_clr_txc1_st, | |
100 | hdr_sram_rid_txc1_re, | |
101 | hdr_sram_rid_txc1_st, | |
102 | hdr_sram_rvalue_txc1_re, | |
103 | hdr_sram_rvalue_txc1_st, | |
104 | sram_hdr_read_data_txc1_re, | |
105 | sram_hdr_read_data_txc1_st, | |
106 | ||
107 | `endif | |
108 | ||
109 | `ifdef NEPTUNE | |
110 | pio_clients_32b, | |
111 | `endif | |
112 | pio_clients_rd, // Slave Read & Write Bar | |
113 | pio_txc_sel, // Slave Sel | |
114 | pio_clients_addr, // Slave Address | |
115 | pio_clients_wdata, // Slave Write Data | |
116 | txc_pio_ack, // Slave PIO Ack | |
117 | txc_pio_err, // Slave PIO Error | |
118 | niu_txc_interrupts, // TXC Interrupts | |
119 | txc_pio_rdata, // Slave Read Data | |
120 | ||
121 | mac_txc_req0, | |
122 | txc_mac_ack0, | |
123 | txc_mac_tag0, | |
124 | txc_mac_abort0, | |
125 | txc_mac_stat0, | |
126 | txc_mac_data0, | |
127 | ||
128 | mac_txc_req1, | |
129 | txc_mac_ack1, | |
130 | txc_mac_tag1, | |
131 | txc_mac_abort1, | |
132 | txc_mac_stat1, | |
133 | txc_mac_data1, | |
134 | ||
135 | `ifdef NEPTUNE | |
136 | mac_txc_req2, | |
137 | txc_mac_ack2, | |
138 | txc_mac_tag2, | |
139 | txc_mac_data2, | |
140 | ||
141 | mac_txc_req3, | |
142 | txc_mac_ack3, | |
143 | txc_mac_tag3, | |
144 | txc_mac_data3, | |
145 | `endif | |
146 | txc_dmc_p0_pkt_size_err, | |
147 | txc_dmc_p0_dma_pkt_size_err, | |
148 | txc_dmc_p0_pkt_size_err_addr, | |
149 | ||
150 | txc_dmc_p1_pkt_size_err, | |
151 | txc_dmc_p1_dma_pkt_size_err, | |
152 | txc_dmc_p1_pkt_size_err_addr, | |
153 | ||
154 | `ifdef NEPTUNE | |
155 | txc_dmc_p2_pkt_size_err, | |
156 | txc_dmc_p2_dma_pkt_size_err, | |
157 | txc_dmc_p2_pkt_size_err_addr, | |
158 | txc_dmc_p3_pkt_size_err, | |
159 | txc_dmc_p3_dma_pkt_size_err, | |
160 | txc_dmc_p3_pkt_size_err_addr, | |
161 | `endif | |
162 | txc_dmc_nack_pkt_rd, | |
163 | txc_dmc_dma_nack_pkt_rd, | |
164 | txc_dmc_nack_pkt_rd_addr, | |
165 | ||
166 | dmc_txc_tx_addr_md, | |
167 | ||
168 | dmc_txc_dma0_active, | |
169 | dmc_txc_dma0_eoflist, | |
170 | dmc_txc_dma0_error, | |
171 | dmc_txc_dma0_gotnxtdesc, | |
172 | dmc_txc_dma0_cacheready, | |
173 | dmc_txc_dma0_partial, | |
174 | dmc_txc_dma0_reset_scheduled, | |
175 | dmc_txc_dma0_func_num, | |
176 | dmc_txc_dma0_page_handle, | |
177 | dmc_txc_dma0_descriptor, | |
178 | txc_dmc_dma0_getnxtdesc, | |
179 | txc_dmc_dma0_inc_head, | |
180 | txc_dmc_dma0_reset_done, | |
181 | txc_dmc_dma0_mark_bit, | |
182 | txc_dmc_dma0_inc_pkt_cnt, | |
183 | ||
184 | dmc_txc_dma1_active, | |
185 | dmc_txc_dma1_eoflist, | |
186 | dmc_txc_dma1_error, | |
187 | dmc_txc_dma1_gotnxtdesc, | |
188 | dmc_txc_dma1_cacheready, | |
189 | dmc_txc_dma1_partial, | |
190 | dmc_txc_dma1_reset_scheduled, | |
191 | dmc_txc_dma1_func_num, | |
192 | dmc_txc_dma1_page_handle, | |
193 | dmc_txc_dma1_descriptor, | |
194 | txc_dmc_dma1_getnxtdesc, | |
195 | txc_dmc_dma1_inc_head, | |
196 | txc_dmc_dma1_reset_done, | |
197 | txc_dmc_dma1_mark_bit, | |
198 | txc_dmc_dma1_inc_pkt_cnt, | |
199 | ||
200 | dmc_txc_dma2_active, | |
201 | dmc_txc_dma2_eoflist, | |
202 | dmc_txc_dma2_error, | |
203 | dmc_txc_dma2_gotnxtdesc, | |
204 | dmc_txc_dma2_cacheready, | |
205 | dmc_txc_dma2_partial, | |
206 | dmc_txc_dma2_reset_scheduled, | |
207 | dmc_txc_dma2_func_num, | |
208 | dmc_txc_dma2_page_handle, | |
209 | dmc_txc_dma2_descriptor, | |
210 | txc_dmc_dma2_getnxtdesc, | |
211 | txc_dmc_dma2_inc_head, | |
212 | txc_dmc_dma2_reset_done, | |
213 | txc_dmc_dma2_mark_bit, | |
214 | txc_dmc_dma2_inc_pkt_cnt, | |
215 | ||
216 | dmc_txc_dma3_active, | |
217 | dmc_txc_dma3_eoflist, | |
218 | dmc_txc_dma3_error, | |
219 | dmc_txc_dma3_gotnxtdesc, | |
220 | dmc_txc_dma3_cacheready, | |
221 | dmc_txc_dma3_partial, | |
222 | dmc_txc_dma3_reset_scheduled, | |
223 | dmc_txc_dma3_func_num, | |
224 | dmc_txc_dma3_page_handle, | |
225 | dmc_txc_dma3_descriptor, | |
226 | txc_dmc_dma3_getnxtdesc, | |
227 | txc_dmc_dma3_inc_head, | |
228 | txc_dmc_dma3_reset_done, | |
229 | txc_dmc_dma3_mark_bit, | |
230 | txc_dmc_dma3_inc_pkt_cnt, | |
231 | ||
232 | dmc_txc_dma4_active, | |
233 | dmc_txc_dma4_eoflist, | |
234 | dmc_txc_dma4_error, | |
235 | dmc_txc_dma4_gotnxtdesc, | |
236 | dmc_txc_dma4_cacheready, | |
237 | dmc_txc_dma4_partial, | |
238 | dmc_txc_dma4_reset_scheduled, | |
239 | dmc_txc_dma4_func_num, | |
240 | dmc_txc_dma4_page_handle, | |
241 | dmc_txc_dma4_descriptor, | |
242 | txc_dmc_dma4_getnxtdesc, | |
243 | txc_dmc_dma4_inc_head, | |
244 | txc_dmc_dma4_reset_done, | |
245 | txc_dmc_dma4_mark_bit, | |
246 | txc_dmc_dma4_inc_pkt_cnt, | |
247 | ||
248 | dmc_txc_dma5_active, | |
249 | dmc_txc_dma5_eoflist, | |
250 | dmc_txc_dma5_error, | |
251 | dmc_txc_dma5_gotnxtdesc, | |
252 | dmc_txc_dma5_cacheready, | |
253 | dmc_txc_dma5_partial, | |
254 | dmc_txc_dma5_reset_scheduled, | |
255 | dmc_txc_dma5_func_num, | |
256 | dmc_txc_dma5_page_handle, | |
257 | dmc_txc_dma5_descriptor, | |
258 | txc_dmc_dma5_getnxtdesc, | |
259 | txc_dmc_dma5_inc_head, | |
260 | txc_dmc_dma5_reset_done, | |
261 | txc_dmc_dma5_mark_bit, | |
262 | txc_dmc_dma5_inc_pkt_cnt, | |
263 | ||
264 | dmc_txc_dma6_active, | |
265 | dmc_txc_dma6_eoflist, | |
266 | dmc_txc_dma6_error, | |
267 | dmc_txc_dma6_gotnxtdesc, | |
268 | dmc_txc_dma6_cacheready, | |
269 | dmc_txc_dma6_partial, | |
270 | dmc_txc_dma6_reset_scheduled, | |
271 | dmc_txc_dma6_func_num, | |
272 | dmc_txc_dma6_page_handle, | |
273 | dmc_txc_dma6_descriptor, | |
274 | txc_dmc_dma6_getnxtdesc, | |
275 | txc_dmc_dma6_inc_head, | |
276 | txc_dmc_dma6_reset_done, | |
277 | txc_dmc_dma6_mark_bit, | |
278 | txc_dmc_dma6_inc_pkt_cnt, | |
279 | ||
280 | dmc_txc_dma7_active, | |
281 | dmc_txc_dma7_eoflist, | |
282 | dmc_txc_dma7_error, | |
283 | dmc_txc_dma7_gotnxtdesc, | |
284 | dmc_txc_dma7_cacheready, | |
285 | dmc_txc_dma7_partial, | |
286 | dmc_txc_dma7_reset_scheduled, | |
287 | dmc_txc_dma7_func_num, | |
288 | dmc_txc_dma7_page_handle, | |
289 | dmc_txc_dma7_descriptor, | |
290 | txc_dmc_dma7_getnxtdesc, | |
291 | txc_dmc_dma7_inc_head, | |
292 | txc_dmc_dma7_reset_done, | |
293 | txc_dmc_dma7_mark_bit, | |
294 | txc_dmc_dma7_inc_pkt_cnt, | |
295 | ||
296 | dmc_txc_dma8_active, | |
297 | dmc_txc_dma8_eoflist, | |
298 | dmc_txc_dma8_error, | |
299 | dmc_txc_dma8_gotnxtdesc, | |
300 | dmc_txc_dma8_cacheready, | |
301 | dmc_txc_dma8_partial, | |
302 | dmc_txc_dma8_reset_scheduled, | |
303 | dmc_txc_dma8_func_num, | |
304 | dmc_txc_dma8_page_handle, | |
305 | dmc_txc_dma8_descriptor, | |
306 | txc_dmc_dma8_getnxtdesc, | |
307 | txc_dmc_dma8_inc_head, | |
308 | txc_dmc_dma8_reset_done, | |
309 | txc_dmc_dma8_mark_bit, | |
310 | txc_dmc_dma8_inc_pkt_cnt, | |
311 | ||
312 | dmc_txc_dma9_active, | |
313 | dmc_txc_dma9_eoflist, | |
314 | dmc_txc_dma9_error, | |
315 | dmc_txc_dma9_gotnxtdesc, | |
316 | dmc_txc_dma9_cacheready, | |
317 | dmc_txc_dma9_partial, | |
318 | dmc_txc_dma9_reset_scheduled, | |
319 | dmc_txc_dma9_func_num, | |
320 | dmc_txc_dma9_page_handle, | |
321 | dmc_txc_dma9_descriptor, | |
322 | txc_dmc_dma9_getnxtdesc, | |
323 | txc_dmc_dma9_inc_head, | |
324 | txc_dmc_dma9_reset_done, | |
325 | txc_dmc_dma9_mark_bit, | |
326 | txc_dmc_dma9_inc_pkt_cnt, | |
327 | ||
328 | dmc_txc_dma10_active, | |
329 | dmc_txc_dma10_eoflist, | |
330 | dmc_txc_dma10_error, | |
331 | dmc_txc_dma10_gotnxtdesc, | |
332 | dmc_txc_dma10_cacheready, | |
333 | dmc_txc_dma10_partial, | |
334 | dmc_txc_dma10_reset_scheduled, | |
335 | dmc_txc_dma10_func_num, | |
336 | dmc_txc_dma10_page_handle, | |
337 | dmc_txc_dma10_descriptor, | |
338 | txc_dmc_dma10_getnxtdesc, | |
339 | txc_dmc_dma10_inc_head, | |
340 | txc_dmc_dma10_reset_done, | |
341 | txc_dmc_dma10_mark_bit, | |
342 | txc_dmc_dma10_inc_pkt_cnt, | |
343 | ||
344 | dmc_txc_dma11_active, | |
345 | dmc_txc_dma11_eoflist, | |
346 | dmc_txc_dma11_error, | |
347 | dmc_txc_dma11_gotnxtdesc, | |
348 | dmc_txc_dma11_cacheready, | |
349 | dmc_txc_dma11_partial, | |
350 | dmc_txc_dma11_reset_scheduled, | |
351 | dmc_txc_dma11_func_num, | |
352 | dmc_txc_dma11_page_handle, | |
353 | dmc_txc_dma11_descriptor, | |
354 | txc_dmc_dma11_getnxtdesc, | |
355 | txc_dmc_dma11_inc_head, | |
356 | txc_dmc_dma11_reset_done, | |
357 | txc_dmc_dma11_mark_bit, | |
358 | txc_dmc_dma11_inc_pkt_cnt, | |
359 | ||
360 | dmc_txc_dma12_active, | |
361 | dmc_txc_dma12_eoflist, | |
362 | dmc_txc_dma12_error, | |
363 | dmc_txc_dma12_gotnxtdesc, | |
364 | dmc_txc_dma12_cacheready, | |
365 | dmc_txc_dma12_partial, | |
366 | dmc_txc_dma12_reset_scheduled, | |
367 | dmc_txc_dma12_func_num, | |
368 | dmc_txc_dma12_page_handle, | |
369 | dmc_txc_dma12_descriptor, | |
370 | txc_dmc_dma12_getnxtdesc, | |
371 | txc_dmc_dma12_inc_head, | |
372 | txc_dmc_dma12_reset_done, | |
373 | txc_dmc_dma12_mark_bit, | |
374 | txc_dmc_dma12_inc_pkt_cnt, | |
375 | ||
376 | dmc_txc_dma13_active, | |
377 | dmc_txc_dma13_eoflist, | |
378 | dmc_txc_dma13_error, | |
379 | dmc_txc_dma13_gotnxtdesc, | |
380 | dmc_txc_dma13_cacheready, | |
381 | dmc_txc_dma13_partial, | |
382 | dmc_txc_dma13_reset_scheduled, | |
383 | dmc_txc_dma13_func_num, | |
384 | dmc_txc_dma13_page_handle, | |
385 | dmc_txc_dma13_descriptor, | |
386 | txc_dmc_dma13_getnxtdesc, | |
387 | txc_dmc_dma13_inc_head, | |
388 | txc_dmc_dma13_reset_done, | |
389 | txc_dmc_dma13_mark_bit, | |
390 | txc_dmc_dma13_inc_pkt_cnt, | |
391 | ||
392 | dmc_txc_dma14_active, | |
393 | dmc_txc_dma14_eoflist, | |
394 | dmc_txc_dma14_error, | |
395 | dmc_txc_dma14_gotnxtdesc, | |
396 | dmc_txc_dma14_cacheready, | |
397 | dmc_txc_dma14_partial, | |
398 | dmc_txc_dma14_reset_scheduled, | |
399 | dmc_txc_dma14_func_num, | |
400 | dmc_txc_dma14_page_handle, | |
401 | dmc_txc_dma14_descriptor, | |
402 | txc_dmc_dma14_getnxtdesc, | |
403 | txc_dmc_dma14_inc_head, | |
404 | txc_dmc_dma14_reset_done, | |
405 | txc_dmc_dma14_mark_bit, | |
406 | txc_dmc_dma14_inc_pkt_cnt, | |
407 | ||
408 | dmc_txc_dma15_active, | |
409 | dmc_txc_dma15_eoflist, | |
410 | dmc_txc_dma15_error, | |
411 | dmc_txc_dma15_gotnxtdesc, | |
412 | dmc_txc_dma15_cacheready, | |
413 | dmc_txc_dma15_partial, | |
414 | dmc_txc_dma15_reset_scheduled, | |
415 | dmc_txc_dma15_func_num, | |
416 | dmc_txc_dma15_page_handle, | |
417 | dmc_txc_dma15_descriptor, | |
418 | txc_dmc_dma15_getnxtdesc, | |
419 | txc_dmc_dma15_inc_head, | |
420 | txc_dmc_dma15_reset_done, | |
421 | txc_dmc_dma15_mark_bit, | |
422 | txc_dmc_dma15_inc_pkt_cnt, | |
423 | ||
424 | `ifdef NEPTUNE | |
425 | dmc_txc_dma16_active, | |
426 | dmc_txc_dma16_eoflist, | |
427 | dmc_txc_dma16_error, | |
428 | dmc_txc_dma16_gotnxtdesc, | |
429 | dmc_txc_dma16_cacheready, | |
430 | dmc_txc_dma16_partial, | |
431 | dmc_txc_dma16_reset_scheduled, | |
432 | dmc_txc_dma16_func_num, | |
433 | dmc_txc_dma16_page_handle, | |
434 | dmc_txc_dma16_descriptor, | |
435 | txc_dmc_dma16_getnxtdesc, | |
436 | txc_dmc_dma16_inc_head, | |
437 | txc_dmc_dma16_reset_done, | |
438 | txc_dmc_dma16_mark_bit, | |
439 | txc_dmc_dma16_inc_pkt_cnt, | |
440 | ||
441 | dmc_txc_dma17_active, | |
442 | dmc_txc_dma17_eoflist, | |
443 | dmc_txc_dma17_error, | |
444 | dmc_txc_dma17_gotnxtdesc, | |
445 | dmc_txc_dma17_cacheready, | |
446 | dmc_txc_dma17_partial, | |
447 | dmc_txc_dma17_reset_scheduled, | |
448 | dmc_txc_dma17_func_num, | |
449 | dmc_txc_dma17_page_handle, | |
450 | dmc_txc_dma17_descriptor, | |
451 | txc_dmc_dma17_getnxtdesc, | |
452 | txc_dmc_dma17_inc_head, | |
453 | txc_dmc_dma17_reset_done, | |
454 | txc_dmc_dma17_mark_bit, | |
455 | txc_dmc_dma17_inc_pkt_cnt, | |
456 | ||
457 | dmc_txc_dma18_active, | |
458 | dmc_txc_dma18_eoflist, | |
459 | dmc_txc_dma18_error, | |
460 | dmc_txc_dma18_gotnxtdesc, | |
461 | dmc_txc_dma18_cacheready, | |
462 | dmc_txc_dma18_partial, | |
463 | dmc_txc_dma18_reset_scheduled, | |
464 | dmc_txc_dma18_func_num, | |
465 | dmc_txc_dma18_page_handle, | |
466 | dmc_txc_dma18_descriptor, | |
467 | txc_dmc_dma18_getnxtdesc, | |
468 | txc_dmc_dma18_inc_head, | |
469 | txc_dmc_dma18_reset_done, | |
470 | txc_dmc_dma18_mark_bit, | |
471 | txc_dmc_dma18_inc_pkt_cnt, | |
472 | ||
473 | dmc_txc_dma19_active, | |
474 | dmc_txc_dma19_eoflist, | |
475 | dmc_txc_dma19_error, | |
476 | dmc_txc_dma19_gotnxtdesc, | |
477 | dmc_txc_dma19_cacheready, | |
478 | dmc_txc_dma19_partial, | |
479 | dmc_txc_dma19_reset_scheduled, | |
480 | dmc_txc_dma19_func_num, | |
481 | dmc_txc_dma19_page_handle, | |
482 | dmc_txc_dma19_descriptor, | |
483 | txc_dmc_dma19_getnxtdesc, | |
484 | txc_dmc_dma19_inc_head, | |
485 | txc_dmc_dma19_reset_done, | |
486 | txc_dmc_dma19_mark_bit, | |
487 | txc_dmc_dma19_inc_pkt_cnt, | |
488 | ||
489 | dmc_txc_dma20_active, | |
490 | dmc_txc_dma20_eoflist, | |
491 | dmc_txc_dma20_error, | |
492 | dmc_txc_dma20_gotnxtdesc, | |
493 | dmc_txc_dma20_cacheready, | |
494 | dmc_txc_dma20_partial, | |
495 | dmc_txc_dma20_reset_scheduled, | |
496 | dmc_txc_dma20_func_num, | |
497 | dmc_txc_dma20_page_handle, | |
498 | dmc_txc_dma20_descriptor, | |
499 | txc_dmc_dma20_getnxtdesc, | |
500 | txc_dmc_dma20_inc_head, | |
501 | txc_dmc_dma20_reset_done, | |
502 | txc_dmc_dma20_mark_bit, | |
503 | txc_dmc_dma20_inc_pkt_cnt, | |
504 | ||
505 | dmc_txc_dma21_active, | |
506 | dmc_txc_dma21_eoflist, | |
507 | dmc_txc_dma21_error, | |
508 | dmc_txc_dma21_gotnxtdesc, | |
509 | dmc_txc_dma21_cacheready, | |
510 | dmc_txc_dma21_partial, | |
511 | dmc_txc_dma21_reset_scheduled, | |
512 | dmc_txc_dma21_func_num, | |
513 | dmc_txc_dma21_page_handle, | |
514 | dmc_txc_dma21_descriptor, | |
515 | txc_dmc_dma21_getnxtdesc, | |
516 | txc_dmc_dma21_inc_head, | |
517 | txc_dmc_dma21_reset_done, | |
518 | txc_dmc_dma21_mark_bit, | |
519 | txc_dmc_dma21_inc_pkt_cnt, | |
520 | ||
521 | dmc_txc_dma22_active, | |
522 | dmc_txc_dma22_eoflist, | |
523 | dmc_txc_dma22_error, | |
524 | dmc_txc_dma22_gotnxtdesc, | |
525 | dmc_txc_dma22_cacheready, | |
526 | dmc_txc_dma22_partial, | |
527 | dmc_txc_dma22_reset_scheduled, | |
528 | dmc_txc_dma22_func_num, | |
529 | dmc_txc_dma22_page_handle, | |
530 | dmc_txc_dma22_descriptor, | |
531 | txc_dmc_dma22_getnxtdesc, | |
532 | txc_dmc_dma22_inc_head, | |
533 | txc_dmc_dma22_reset_done, | |
534 | txc_dmc_dma22_mark_bit, | |
535 | txc_dmc_dma22_inc_pkt_cnt, | |
536 | ||
537 | dmc_txc_dma23_active, | |
538 | dmc_txc_dma23_eoflist, | |
539 | dmc_txc_dma23_error, | |
540 | dmc_txc_dma23_gotnxtdesc, | |
541 | dmc_txc_dma23_cacheready, | |
542 | dmc_txc_dma23_partial, | |
543 | dmc_txc_dma23_reset_scheduled, | |
544 | dmc_txc_dma23_func_num, | |
545 | dmc_txc_dma23_page_handle, | |
546 | dmc_txc_dma23_descriptor, | |
547 | txc_dmc_dma23_getnxtdesc, | |
548 | txc_dmc_dma23_inc_head, | |
549 | txc_dmc_dma23_reset_done, | |
550 | txc_dmc_dma23_mark_bit, | |
551 | txc_dmc_dma23_inc_pkt_cnt, | |
552 | `endif | |
553 | ||
554 | arb1_txc_req_accept, | |
555 | arb1_txc_req_transid, | |
556 | txc_arb1_req, | |
557 | txc_arb1_req_func_num, | |
558 | txc_arb1_req_port_num, | |
559 | txc_arb1_req_dma_num, | |
560 | txc_arb1_req_cmd, | |
561 | txc_arb1_req_length, | |
562 | txc_arb1_req_address, | |
563 | ||
564 | meta_dmc_resp_ready, | |
565 | meta_dmc_resp_complete, | |
566 | meta_dmc_resp_transfer_cmpl, | |
567 | meta_dmc_data_valid, | |
568 | meta_dmc_resp_client, | |
569 | meta_dmc_resp_port_num, | |
570 | meta_dmc_resp_cmd_status, | |
571 | meta_dmc_resp_data_status, | |
572 | meta_dmc_resp_dma_num, | |
573 | meta_dmc_resp_transID, | |
574 | meta_dmc_resp_cmd, | |
575 | meta_dmc_resp_byteenable, | |
576 | meta_dmc_resp_length, | |
577 | meta_dmc_resp_address, | |
578 | meta_dmc_data, | |
579 | dmc_meta_resp_accept | |
580 | ); | |
581 | ||
582 | `include "txc_defines.h" | |
583 | ||
584 | // Global Signals | |
585 | input niu_clk; | |
586 | input niu_reset_l; | |
587 | ||
588 | // L2Clk, SRAM and Membist N2 Signals | |
589 | `ifdef NEPTUNE | |
590 | `else | |
591 | input iol2clk; | |
592 | input l2clk_2x; | |
593 | input tcu_aclk; | |
594 | input tcu_bclk; | |
595 | input tcu_mbist_bisi_en; | |
596 | input tcu_scan_en; | |
597 | input tcu_se_scancollar_in; | |
598 | input tcu_se_scancollar_out; | |
599 | input tcu_array_wr_inhibit; | |
600 | input tcu_mbist_user_mode; | |
601 | ||
602 | input tcu_rtx_txc_txe0_mbist_start; | |
603 | input rtx_txc_txe0_mbist_scan_in; | |
604 | ||
605 | output rtx_txc_txe0_tcu_mbist_fail; | |
606 | output rtx_txc_txe0_tcu_mbist_done; | |
607 | output rtx_txc_txe0_mbist_scan_out; | |
608 | output [39:0] rtx_txc_txe0_dmo_dout; | |
609 | ||
610 | wire rtx_txc_txe0_mb1_run; | |
611 | wire rtx_txc_txe0_mb1_xmit_store_rd_en; | |
612 | wire rtx_txc_txe0_mb1_xmit_store_wr_en; | |
613 | wire rtx_txc_txe0_mb1_xmit_realign_rd_en; | |
614 | wire rtx_txc_txe0_mb1_xmit_realign_wr_en; | |
615 | wire [7:0] rtx_txc_txe0_mb1_wdata; | |
616 | wire [9:0] rtx_txc_txe0_mb1_addr; | |
617 | ||
618 | input tcu_rtx_txc_txe1_mbist_start; | |
619 | input rtx_txc_txe1_mbist_scan_in; | |
620 | ||
621 | output rtx_txc_txe1_tcu_mbist_fail; | |
622 | output rtx_txc_txe1_tcu_mbist_done; | |
623 | output rtx_txc_txe1_mbist_scan_out; | |
624 | output [39:0] rtx_txc_txe1_dmo_dout; | |
625 | ||
626 | wire rtx_txc_txe1_mb1_run; | |
627 | wire rtx_txc_txe1_mb1_xmit_store_rd_en; | |
628 | wire rtx_txc_txe1_mb1_xmit_store_wr_en; | |
629 | wire rtx_txc_txe1_mb1_xmit_realign_rd_en; | |
630 | wire rtx_txc_txe1_mb1_xmit_realign_wr_en; | |
631 | wire [7:0] rtx_txc_txe1_mb1_wdata; | |
632 | wire [9:0] rtx_txc_txe1_mb1_addr; | |
633 | ||
634 | input hdr_sram_wr_en_txc0_re; | |
635 | input hdr_sram_red_clr_txc0_re; | |
636 | input hdr_sram_wr_en_txc0_st; | |
637 | input hdr_sram_red_clr_txc0_st; | |
638 | input [2:0] hdr_sram_rid_txc0_re; | |
639 | input [2:0] hdr_sram_rid_txc0_st; | |
640 | input [6:0] hdr_sram_rvalue_txc0_re; | |
641 | input [6:0] hdr_sram_rvalue_txc0_st; | |
642 | ||
643 | output [6:0] sram_hdr_read_data_txc0_re; | |
644 | output [6:0] sram_hdr_read_data_txc0_st; | |
645 | ||
646 | input hdr_sram_wr_en_txc1_re; | |
647 | input hdr_sram_red_clr_txc1_re; | |
648 | input hdr_sram_wr_en_txc1_st; | |
649 | input hdr_sram_red_clr_txc1_st; | |
650 | input [2:0] hdr_sram_rid_txc1_re; | |
651 | input [2:0] hdr_sram_rid_txc1_st; | |
652 | input [6:0] hdr_sram_rvalue_txc1_re; | |
653 | input [6:0] hdr_sram_rvalue_txc1_st; | |
654 | ||
655 | output [6:0] sram_hdr_read_data_txc1_re; | |
656 | output [6:0] sram_hdr_read_data_txc1_st; | |
657 | ||
658 | `endif | |
659 | ||
660 | // Debug Interface | |
661 | output [31:0] txc_debug_port; | |
662 | ||
663 | // Slave Interface | |
664 | `ifdef NEPTUNE | |
665 | input pio_clients_32b; | |
666 | `endif | |
667 | input pio_clients_rd; | |
668 | input pio_txc_sel; | |
669 | input [19:0] pio_clients_addr; | |
670 | input [31:0] pio_clients_wdata; | |
671 | ||
672 | output txc_pio_ack; | |
673 | output txc_pio_err; | |
674 | output niu_txc_interrupts; | |
675 | output [63:0] txc_pio_rdata; | |
676 | ||
677 | // MAC Port Zero Interface | |
678 | input mac_txc_req0; | |
679 | ||
680 | output txc_mac_ack0; | |
681 | output txc_mac_tag0; | |
682 | output txc_mac_abort0; | |
683 | output [3:0] txc_mac_stat0; | |
684 | output [63:0] txc_mac_data0; | |
685 | ||
686 | // MAC Port One Interface | |
687 | input mac_txc_req1; | |
688 | ||
689 | output txc_mac_ack1; | |
690 | output txc_mac_tag1; | |
691 | output txc_mac_abort1; | |
692 | output [3:0] txc_mac_stat1; | |
693 | output [63:0] txc_mac_data1; | |
694 | ||
695 | `ifdef NEPTUNE | |
696 | // MAC Port Two Interface | |
697 | input mac_txc_req2; | |
698 | ||
699 | output txc_mac_ack2; | |
700 | output txc_mac_tag2; | |
701 | output [63:0] txc_mac_data2; | |
702 | ||
703 | // MAC Port Three Interface | |
704 | input mac_txc_req3; | |
705 | ||
706 | output txc_mac_ack3; | |
707 | output [63:0] txc_mac_data3; | |
708 | output txc_mac_tag3; | |
709 | `endif | |
710 | ||
711 | // TXC- TDMC -Error Interface | |
712 | output txc_dmc_p0_pkt_size_err; | |
713 | output [43:0] txc_dmc_p0_pkt_size_err_addr; | |
714 | ||
715 | output txc_dmc_p1_pkt_size_err; | |
716 | output [43:0] txc_dmc_p1_pkt_size_err_addr; | |
717 | ||
718 | output txc_dmc_nack_pkt_rd; | |
719 | output [43:0] txc_dmc_nack_pkt_rd_addr; | |
720 | ||
721 | `ifdef NEPTUNE | |
722 | output [23:0] txc_dmc_p0_dma_pkt_size_err; | |
723 | output [23:0] txc_dmc_p1_dma_pkt_size_err; | |
724 | ||
725 | output txc_dmc_p2_pkt_size_err; | |
726 | output [23:0] txc_dmc_p2_dma_pkt_size_err; | |
727 | output [43:0] txc_dmc_p2_pkt_size_err_addr; | |
728 | ||
729 | output txc_dmc_p3_pkt_size_err; | |
730 | output [23:0] txc_dmc_p3_dma_pkt_size_err; | |
731 | output [43:0] txc_dmc_p3_pkt_size_err_addr; | |
732 | ||
733 | output [23:0] txc_dmc_dma_nack_pkt_rd; | |
734 | ||
735 | `else | |
736 | output [15:0] txc_dmc_p0_dma_pkt_size_err; | |
737 | output [15:0] txc_dmc_p1_dma_pkt_size_err; | |
738 | output [15:0] txc_dmc_dma_nack_pkt_rd; | |
739 | ||
740 | wire [7:0] dummy_txc_dmc_p0_dma_pkt_size_err; | |
741 | wire [7:0] dummy_txc_dmc_p1_dma_pkt_size_err; | |
742 | wire [7:0] dummy_txc_dmc_dma_nack_pkt_rd; | |
743 | `endif | |
744 | ||
745 | // Tx DMA Cache | |
746 | input dmc_txc_tx_addr_md; | |
747 | ||
748 | // DMA0 | |
749 | input dmc_txc_dma0_active; | |
750 | input dmc_txc_dma0_eoflist; | |
751 | input dmc_txc_dma0_error; | |
752 | input dmc_txc_dma0_gotnxtdesc; | |
753 | input dmc_txc_dma0_cacheready; | |
754 | input dmc_txc_dma0_partial; | |
755 | input dmc_txc_dma0_reset_scheduled; | |
756 | input [1:0] dmc_txc_dma0_func_num; | |
757 | input [19:0] dmc_txc_dma0_page_handle; | |
758 | input [63:0] dmc_txc_dma0_descriptor; | |
759 | ||
760 | output txc_dmc_dma0_getnxtdesc; | |
761 | output txc_dmc_dma0_inc_head; | |
762 | output txc_dmc_dma0_reset_done; | |
763 | output txc_dmc_dma0_mark_bit; | |
764 | output txc_dmc_dma0_inc_pkt_cnt; | |
765 | ||
766 | // DMA1 | |
767 | input dmc_txc_dma1_active; | |
768 | input dmc_txc_dma1_eoflist; | |
769 | input dmc_txc_dma1_error; | |
770 | input dmc_txc_dma1_gotnxtdesc; | |
771 | input dmc_txc_dma1_cacheready; | |
772 | input dmc_txc_dma1_partial; | |
773 | input dmc_txc_dma1_reset_scheduled; | |
774 | input [1:0] dmc_txc_dma1_func_num; | |
775 | input [19:0] dmc_txc_dma1_page_handle; | |
776 | input [63:0] dmc_txc_dma1_descriptor; | |
777 | ||
778 | output txc_dmc_dma1_getnxtdesc; | |
779 | output txc_dmc_dma1_inc_head; | |
780 | output txc_dmc_dma1_reset_done; | |
781 | output txc_dmc_dma1_mark_bit; | |
782 | output txc_dmc_dma1_inc_pkt_cnt; | |
783 | ||
784 | // DMA2 | |
785 | input dmc_txc_dma2_active; | |
786 | input dmc_txc_dma2_eoflist; | |
787 | input dmc_txc_dma2_error; | |
788 | input dmc_txc_dma2_gotnxtdesc; | |
789 | input dmc_txc_dma2_cacheready; | |
790 | input dmc_txc_dma2_partial; | |
791 | input dmc_txc_dma2_reset_scheduled; | |
792 | input [1:0] dmc_txc_dma2_func_num; | |
793 | input [19:0] dmc_txc_dma2_page_handle; | |
794 | input [63:0] dmc_txc_dma2_descriptor; | |
795 | ||
796 | output txc_dmc_dma2_getnxtdesc; | |
797 | output txc_dmc_dma2_inc_head; | |
798 | output txc_dmc_dma2_reset_done; | |
799 | output txc_dmc_dma2_mark_bit; | |
800 | output txc_dmc_dma2_inc_pkt_cnt; | |
801 | ||
802 | // DMA3 | |
803 | input dmc_txc_dma3_active; | |
804 | input dmc_txc_dma3_eoflist; | |
805 | input dmc_txc_dma3_error; | |
806 | input dmc_txc_dma3_gotnxtdesc; | |
807 | input dmc_txc_dma3_cacheready; | |
808 | input dmc_txc_dma3_partial; | |
809 | input dmc_txc_dma3_reset_scheduled; | |
810 | input [1:0] dmc_txc_dma3_func_num; | |
811 | input [19:0] dmc_txc_dma3_page_handle; | |
812 | input [63:0] dmc_txc_dma3_descriptor; | |
813 | ||
814 | output txc_dmc_dma3_getnxtdesc; | |
815 | output txc_dmc_dma3_inc_head; | |
816 | output txc_dmc_dma3_reset_done; | |
817 | output txc_dmc_dma3_mark_bit; | |
818 | output txc_dmc_dma3_inc_pkt_cnt; | |
819 | ||
820 | // DMA4 | |
821 | input dmc_txc_dma4_active; | |
822 | input dmc_txc_dma4_eoflist; | |
823 | input dmc_txc_dma4_error; | |
824 | input dmc_txc_dma4_gotnxtdesc; | |
825 | input dmc_txc_dma4_cacheready; | |
826 | input dmc_txc_dma4_partial; | |
827 | input dmc_txc_dma4_reset_scheduled; | |
828 | input [1:0] dmc_txc_dma4_func_num; | |
829 | input [19:0] dmc_txc_dma4_page_handle; | |
830 | input [63:0] dmc_txc_dma4_descriptor; | |
831 | ||
832 | output txc_dmc_dma4_getnxtdesc; | |
833 | output txc_dmc_dma4_inc_head; | |
834 | output txc_dmc_dma4_reset_done; | |
835 | output txc_dmc_dma4_mark_bit; | |
836 | output txc_dmc_dma4_inc_pkt_cnt; | |
837 | ||
838 | // DMA5 | |
839 | input dmc_txc_dma5_active; | |
840 | input dmc_txc_dma5_eoflist; | |
841 | input dmc_txc_dma5_error; | |
842 | input dmc_txc_dma5_gotnxtdesc; | |
843 | input dmc_txc_dma5_cacheready; | |
844 | input dmc_txc_dma5_partial; | |
845 | input dmc_txc_dma5_reset_scheduled; | |
846 | input [1:0] dmc_txc_dma5_func_num; | |
847 | input [19:0] dmc_txc_dma5_page_handle; | |
848 | input [63:0] dmc_txc_dma5_descriptor; | |
849 | ||
850 | output txc_dmc_dma5_getnxtdesc; | |
851 | output txc_dmc_dma5_inc_head; | |
852 | output txc_dmc_dma5_reset_done; | |
853 | output txc_dmc_dma5_mark_bit; | |
854 | output txc_dmc_dma5_inc_pkt_cnt; | |
855 | ||
856 | // DMA6 | |
857 | input dmc_txc_dma6_active; | |
858 | input dmc_txc_dma6_eoflist; | |
859 | input dmc_txc_dma6_error; | |
860 | input dmc_txc_dma6_gotnxtdesc; | |
861 | input dmc_txc_dma6_cacheready; | |
862 | input dmc_txc_dma6_partial; | |
863 | input dmc_txc_dma6_reset_scheduled; | |
864 | input [1:0] dmc_txc_dma6_func_num; | |
865 | input [19:0] dmc_txc_dma6_page_handle; | |
866 | input [63:0] dmc_txc_dma6_descriptor; | |
867 | ||
868 | output txc_dmc_dma6_getnxtdesc; | |
869 | output txc_dmc_dma6_inc_head; | |
870 | output txc_dmc_dma6_reset_done; | |
871 | output txc_dmc_dma6_mark_bit; | |
872 | output txc_dmc_dma6_inc_pkt_cnt; | |
873 | ||
874 | // DMA7 | |
875 | input dmc_txc_dma7_active; | |
876 | input dmc_txc_dma7_eoflist; | |
877 | input dmc_txc_dma7_error; | |
878 | input dmc_txc_dma7_gotnxtdesc; | |
879 | input dmc_txc_dma7_cacheready; | |
880 | input dmc_txc_dma7_partial; | |
881 | input dmc_txc_dma7_reset_scheduled; | |
882 | input [1:0] dmc_txc_dma7_func_num; | |
883 | input [19:0] dmc_txc_dma7_page_handle; | |
884 | input [63:0] dmc_txc_dma7_descriptor; | |
885 | ||
886 | output txc_dmc_dma7_getnxtdesc; | |
887 | output txc_dmc_dma7_inc_head; | |
888 | output txc_dmc_dma7_reset_done; | |
889 | output txc_dmc_dma7_mark_bit; | |
890 | output txc_dmc_dma7_inc_pkt_cnt; | |
891 | ||
892 | // DMA8 | |
893 | input dmc_txc_dma8_active; | |
894 | input dmc_txc_dma8_eoflist; | |
895 | input dmc_txc_dma8_error; | |
896 | input dmc_txc_dma8_gotnxtdesc; | |
897 | input dmc_txc_dma8_cacheready; | |
898 | input dmc_txc_dma8_partial; | |
899 | input dmc_txc_dma8_reset_scheduled; | |
900 | input [1:0] dmc_txc_dma8_func_num; | |
901 | input [19:0] dmc_txc_dma8_page_handle; | |
902 | input [63:0] dmc_txc_dma8_descriptor; | |
903 | ||
904 | output txc_dmc_dma8_getnxtdesc; | |
905 | output txc_dmc_dma8_inc_head; | |
906 | output txc_dmc_dma8_reset_done; | |
907 | output txc_dmc_dma8_mark_bit; | |
908 | output txc_dmc_dma8_inc_pkt_cnt; | |
909 | ||
910 | // DMA9 | |
911 | input dmc_txc_dma9_active; | |
912 | input dmc_txc_dma9_eoflist; | |
913 | input dmc_txc_dma9_error; | |
914 | input dmc_txc_dma9_gotnxtdesc; | |
915 | input dmc_txc_dma9_cacheready; | |
916 | input dmc_txc_dma9_partial; | |
917 | input dmc_txc_dma9_reset_scheduled; | |
918 | input [1:0] dmc_txc_dma9_func_num; | |
919 | input [19:0] dmc_txc_dma9_page_handle; | |
920 | input [63:0] dmc_txc_dma9_descriptor; | |
921 | ||
922 | output txc_dmc_dma9_getnxtdesc; | |
923 | output txc_dmc_dma9_inc_head; | |
924 | output txc_dmc_dma9_reset_done; | |
925 | output txc_dmc_dma9_mark_bit; | |
926 | output txc_dmc_dma9_inc_pkt_cnt; | |
927 | ||
928 | // DMA10 | |
929 | input dmc_txc_dma10_active; | |
930 | input dmc_txc_dma10_eoflist; | |
931 | input dmc_txc_dma10_error; | |
932 | input dmc_txc_dma10_gotnxtdesc; | |
933 | input dmc_txc_dma10_cacheready; | |
934 | input dmc_txc_dma10_partial; | |
935 | input dmc_txc_dma10_reset_scheduled; | |
936 | input [1:0] dmc_txc_dma10_func_num; | |
937 | input [19:0] dmc_txc_dma10_page_handle; | |
938 | input [63:0] dmc_txc_dma10_descriptor; | |
939 | ||
940 | output txc_dmc_dma10_getnxtdesc; | |
941 | output txc_dmc_dma10_inc_head; | |
942 | output txc_dmc_dma10_reset_done; | |
943 | output txc_dmc_dma10_mark_bit; | |
944 | output txc_dmc_dma10_inc_pkt_cnt; | |
945 | ||
946 | // DMA11 | |
947 | input dmc_txc_dma11_active; | |
948 | input dmc_txc_dma11_eoflist; | |
949 | input dmc_txc_dma11_error; | |
950 | input dmc_txc_dma11_gotnxtdesc; | |
951 | input dmc_txc_dma11_cacheready; | |
952 | input dmc_txc_dma11_partial; | |
953 | input dmc_txc_dma11_reset_scheduled; | |
954 | input [1:0] dmc_txc_dma11_func_num; | |
955 | input [19:0] dmc_txc_dma11_page_handle; | |
956 | input [63:0] dmc_txc_dma11_descriptor; | |
957 | ||
958 | output txc_dmc_dma11_getnxtdesc; | |
959 | output txc_dmc_dma11_inc_head; | |
960 | output txc_dmc_dma11_reset_done; | |
961 | output txc_dmc_dma11_mark_bit; | |
962 | output txc_dmc_dma11_inc_pkt_cnt; | |
963 | ||
964 | // DMA12 | |
965 | input dmc_txc_dma12_active; | |
966 | input dmc_txc_dma12_eoflist; | |
967 | input dmc_txc_dma12_error; | |
968 | input dmc_txc_dma12_gotnxtdesc; | |
969 | input dmc_txc_dma12_cacheready; | |
970 | input dmc_txc_dma12_partial; | |
971 | input dmc_txc_dma12_reset_scheduled; | |
972 | input [1:0] dmc_txc_dma12_func_num; | |
973 | input [19:0] dmc_txc_dma12_page_handle; | |
974 | input [63:0] dmc_txc_dma12_descriptor; | |
975 | ||
976 | output txc_dmc_dma12_getnxtdesc; | |
977 | output txc_dmc_dma12_inc_head; | |
978 | output txc_dmc_dma12_reset_done; | |
979 | output txc_dmc_dma12_mark_bit; | |
980 | output txc_dmc_dma12_inc_pkt_cnt; | |
981 | ||
982 | // DMA13 | |
983 | input dmc_txc_dma13_active; | |
984 | input dmc_txc_dma13_eoflist; | |
985 | input dmc_txc_dma13_error; | |
986 | input dmc_txc_dma13_gotnxtdesc; | |
987 | input dmc_txc_dma13_cacheready; | |
988 | input dmc_txc_dma13_partial; | |
989 | input dmc_txc_dma13_reset_scheduled; | |
990 | input [1:0] dmc_txc_dma13_func_num; | |
991 | input [19:0] dmc_txc_dma13_page_handle; | |
992 | input [63:0] dmc_txc_dma13_descriptor; | |
993 | ||
994 | output txc_dmc_dma13_getnxtdesc; | |
995 | output txc_dmc_dma13_inc_head; | |
996 | output txc_dmc_dma13_reset_done; | |
997 | output txc_dmc_dma13_mark_bit; | |
998 | output txc_dmc_dma13_inc_pkt_cnt; | |
999 | ||
1000 | // DMA14 | |
1001 | input dmc_txc_dma14_active; | |
1002 | input dmc_txc_dma14_eoflist; | |
1003 | input dmc_txc_dma14_error; | |
1004 | input dmc_txc_dma14_gotnxtdesc; | |
1005 | input dmc_txc_dma14_cacheready; | |
1006 | input dmc_txc_dma14_partial; | |
1007 | input dmc_txc_dma14_reset_scheduled; | |
1008 | input [1:0] dmc_txc_dma14_func_num; | |
1009 | input [19:0] dmc_txc_dma14_page_handle; | |
1010 | input [63:0] dmc_txc_dma14_descriptor; | |
1011 | ||
1012 | output txc_dmc_dma14_getnxtdesc; | |
1013 | output txc_dmc_dma14_inc_head; | |
1014 | output txc_dmc_dma14_reset_done; | |
1015 | output txc_dmc_dma14_mark_bit; | |
1016 | output txc_dmc_dma14_inc_pkt_cnt; | |
1017 | ||
1018 | // DMA15 | |
1019 | input dmc_txc_dma15_active; | |
1020 | input dmc_txc_dma15_eoflist; | |
1021 | input dmc_txc_dma15_error; | |
1022 | input dmc_txc_dma15_gotnxtdesc; | |
1023 | input dmc_txc_dma15_cacheready; | |
1024 | input dmc_txc_dma15_partial; | |
1025 | input dmc_txc_dma15_reset_scheduled; | |
1026 | input [1:0] dmc_txc_dma15_func_num; | |
1027 | input [19:0] dmc_txc_dma15_page_handle; | |
1028 | input [63:0] dmc_txc_dma15_descriptor; | |
1029 | ||
1030 | output txc_dmc_dma15_getnxtdesc; | |
1031 | output txc_dmc_dma15_inc_head; | |
1032 | output txc_dmc_dma15_reset_done; | |
1033 | output txc_dmc_dma15_mark_bit; | |
1034 | output txc_dmc_dma15_inc_pkt_cnt; | |
1035 | ||
1036 | `ifdef NEPTUNE | |
1037 | // DMA16 | |
1038 | input dmc_txc_dma16_active; | |
1039 | input dmc_txc_dma16_eoflist; | |
1040 | input dmc_txc_dma16_error; | |
1041 | input dmc_txc_dma16_gotnxtdesc; | |
1042 | input dmc_txc_dma16_cacheready; | |
1043 | input dmc_txc_dma16_partial; | |
1044 | input dmc_txc_dma16_reset_scheduled; | |
1045 | input [1:0] dmc_txc_dma16_func_num; | |
1046 | input [19:0] dmc_txc_dma16_page_handle; | |
1047 | input [63:0] dmc_txc_dma16_descriptor; | |
1048 | ||
1049 | output txc_dmc_dma16_getnxtdesc; | |
1050 | output txc_dmc_dma16_inc_head; | |
1051 | output txc_dmc_dma16_reset_done; | |
1052 | output txc_dmc_dma16_mark_bit; | |
1053 | output txc_dmc_dma16_inc_pkt_cnt; | |
1054 | ||
1055 | // DMA17 | |
1056 | input dmc_txc_dma17_active; | |
1057 | input dmc_txc_dma17_eoflist; | |
1058 | input dmc_txc_dma17_error; | |
1059 | input dmc_txc_dma17_gotnxtdesc; | |
1060 | input dmc_txc_dma17_cacheready; | |
1061 | input dmc_txc_dma17_partial; | |
1062 | input dmc_txc_dma17_reset_scheduled; | |
1063 | input [1:0] dmc_txc_dma17_func_num; | |
1064 | input [19:0] dmc_txc_dma17_page_handle; | |
1065 | input [63:0] dmc_txc_dma17_descriptor; | |
1066 | ||
1067 | output txc_dmc_dma17_getnxtdesc; | |
1068 | output txc_dmc_dma17_inc_head; | |
1069 | output txc_dmc_dma17_reset_done; | |
1070 | output txc_dmc_dma17_mark_bit; | |
1071 | output txc_dmc_dma17_inc_pkt_cnt; | |
1072 | ||
1073 | // DMA18 | |
1074 | input dmc_txc_dma18_active; | |
1075 | input dmc_txc_dma18_eoflist; | |
1076 | input dmc_txc_dma18_error; | |
1077 | input dmc_txc_dma18_gotnxtdesc; | |
1078 | input dmc_txc_dma18_cacheready; | |
1079 | input dmc_txc_dma18_partial; | |
1080 | input dmc_txc_dma18_reset_scheduled; | |
1081 | input [1:0] dmc_txc_dma18_func_num; | |
1082 | input [19:0] dmc_txc_dma18_page_handle; | |
1083 | input [63:0] dmc_txc_dma18_descriptor; | |
1084 | ||
1085 | output txc_dmc_dma18_getnxtdesc; | |
1086 | output txc_dmc_dma18_inc_head; | |
1087 | output txc_dmc_dma18_reset_done; | |
1088 | output txc_dmc_dma18_mark_bit; | |
1089 | output txc_dmc_dma18_inc_pkt_cnt; | |
1090 | ||
1091 | // DMA19 | |
1092 | input dmc_txc_dma19_active; | |
1093 | input dmc_txc_dma19_eoflist; | |
1094 | input dmc_txc_dma19_error; | |
1095 | input dmc_txc_dma19_gotnxtdesc; | |
1096 | input dmc_txc_dma19_cacheready; | |
1097 | input dmc_txc_dma19_partial; | |
1098 | input dmc_txc_dma19_reset_scheduled; | |
1099 | input [1:0] dmc_txc_dma19_func_num; | |
1100 | input [19:0] dmc_txc_dma19_page_handle; | |
1101 | input [63:0] dmc_txc_dma19_descriptor; | |
1102 | ||
1103 | output txc_dmc_dma19_getnxtdesc; | |
1104 | output txc_dmc_dma19_inc_head; | |
1105 | output txc_dmc_dma19_reset_done; | |
1106 | output txc_dmc_dma19_mark_bit; | |
1107 | output txc_dmc_dma19_inc_pkt_cnt; | |
1108 | ||
1109 | // DMA20 | |
1110 | input dmc_txc_dma20_active; | |
1111 | input dmc_txc_dma20_eoflist; | |
1112 | input dmc_txc_dma20_error; | |
1113 | input dmc_txc_dma20_gotnxtdesc; | |
1114 | input dmc_txc_dma20_cacheready; | |
1115 | input dmc_txc_dma20_partial; | |
1116 | input dmc_txc_dma20_reset_scheduled; | |
1117 | input [1:0] dmc_txc_dma20_func_num; | |
1118 | input [19:0] dmc_txc_dma20_page_handle; | |
1119 | input [63:0] dmc_txc_dma20_descriptor; | |
1120 | ||
1121 | output txc_dmc_dma20_getnxtdesc; | |
1122 | output txc_dmc_dma20_inc_head; | |
1123 | output txc_dmc_dma20_reset_done; | |
1124 | output txc_dmc_dma20_mark_bit; | |
1125 | output txc_dmc_dma20_inc_pkt_cnt; | |
1126 | ||
1127 | // DMA21 | |
1128 | input dmc_txc_dma21_active; | |
1129 | input dmc_txc_dma21_eoflist; | |
1130 | input dmc_txc_dma21_error; | |
1131 | input dmc_txc_dma21_gotnxtdesc; | |
1132 | input dmc_txc_dma21_cacheready; | |
1133 | input dmc_txc_dma21_partial; | |
1134 | input dmc_txc_dma21_reset_scheduled; | |
1135 | input [1:0] dmc_txc_dma21_func_num; | |
1136 | input [19:0] dmc_txc_dma21_page_handle; | |
1137 | input [63:0] dmc_txc_dma21_descriptor; | |
1138 | ||
1139 | output txc_dmc_dma21_getnxtdesc; | |
1140 | output txc_dmc_dma21_inc_head; | |
1141 | output txc_dmc_dma21_reset_done; | |
1142 | output txc_dmc_dma21_mark_bit; | |
1143 | output txc_dmc_dma21_inc_pkt_cnt; | |
1144 | ||
1145 | // DMA22 | |
1146 | input dmc_txc_dma22_active; | |
1147 | input dmc_txc_dma22_eoflist; | |
1148 | input dmc_txc_dma22_error; | |
1149 | input dmc_txc_dma22_gotnxtdesc; | |
1150 | input dmc_txc_dma22_cacheready; | |
1151 | input dmc_txc_dma22_partial; | |
1152 | input dmc_txc_dma22_reset_scheduled; | |
1153 | input [1:0] dmc_txc_dma22_func_num; | |
1154 | input [19:0] dmc_txc_dma22_page_handle; | |
1155 | input [63:0] dmc_txc_dma22_descriptor; | |
1156 | ||
1157 | output txc_dmc_dma22_getnxtdesc; | |
1158 | output txc_dmc_dma22_inc_head; | |
1159 | output txc_dmc_dma22_reset_done; | |
1160 | output txc_dmc_dma22_mark_bit; | |
1161 | output txc_dmc_dma22_inc_pkt_cnt; | |
1162 | ||
1163 | // DMA23 | |
1164 | input dmc_txc_dma23_active; | |
1165 | input dmc_txc_dma23_eoflist; | |
1166 | input dmc_txc_dma23_error; | |
1167 | input dmc_txc_dma23_gotnxtdesc; | |
1168 | input dmc_txc_dma23_cacheready; | |
1169 | input dmc_txc_dma23_partial; | |
1170 | input dmc_txc_dma23_reset_scheduled; | |
1171 | input [1:0] dmc_txc_dma23_func_num; | |
1172 | input [19:0] dmc_txc_dma23_page_handle; | |
1173 | input [63:0] dmc_txc_dma23_descriptor; | |
1174 | ||
1175 | output txc_dmc_dma23_getnxtdesc; | |
1176 | output txc_dmc_dma23_inc_head; | |
1177 | output txc_dmc_dma23_reset_done; | |
1178 | output txc_dmc_dma23_mark_bit; | |
1179 | output txc_dmc_dma23_inc_pkt_cnt; | |
1180 | `else | |
1181 | // DMA16 | |
1182 | wire dmc_txc_dma16_active = 1'b0; | |
1183 | wire dmc_txc_dma16_eoflist = 1'b1; | |
1184 | wire dmc_txc_dma16_error = 1'b0; | |
1185 | wire dmc_txc_dma16_gotnxtdesc = 1'b0; | |
1186 | wire dmc_txc_dma16_cacheready = 1'b0; | |
1187 | wire dmc_txc_dma16_partial = 1'b0; | |
1188 | wire dmc_txc_dma16_reset_scheduled = 1'b0; | |
1189 | wire [1:0] dmc_txc_dma16_func_num = 2'h0; | |
1190 | wire [19:0] dmc_txc_dma16_page_handle = 20'h0; | |
1191 | wire [63:0] dmc_txc_dma16_descriptor = 64'h0; | |
1192 | ||
1193 | wire txc_dmc_dma16_getnxtdesc; | |
1194 | wire txc_dmc_dma16_inc_head; | |
1195 | wire txc_dmc_dma16_reset_done; | |
1196 | wire txc_dmc_dma16_mark_bit; | |
1197 | wire txc_dmc_dma16_inc_pkt_cnt; | |
1198 | ||
1199 | // DMA17 | |
1200 | wire dmc_txc_dma17_active = 1'b0; | |
1201 | wire dmc_txc_dma17_eoflist = 1'b1; | |
1202 | wire dmc_txc_dma17_error = 1'b0; | |
1203 | wire dmc_txc_dma17_gotnxtdesc = 1'b0; | |
1204 | wire dmc_txc_dma17_cacheready = 1'b0; | |
1205 | wire dmc_txc_dma17_partial = 1'b0; | |
1206 | wire dmc_txc_dma17_reset_scheduled = 1'b0; | |
1207 | wire [1:0] dmc_txc_dma17_func_num = 2'h0; | |
1208 | wire [19:0] dmc_txc_dma17_page_handle = 20'h0; | |
1209 | wire [63:0] dmc_txc_dma17_descriptor = 64'h0; | |
1210 | ||
1211 | wire txc_dmc_dma17_getnxtdesc; | |
1212 | wire txc_dmc_dma17_inc_head; | |
1213 | wire txc_dmc_dma17_reset_done; | |
1214 | wire txc_dmc_dma17_mark_bit; | |
1215 | wire txc_dmc_dma17_inc_pkt_cnt; | |
1216 | ||
1217 | // DMA18 | |
1218 | wire dmc_txc_dma18_active = 1'b0; | |
1219 | wire dmc_txc_dma18_eoflist = 1'b1; | |
1220 | wire dmc_txc_dma18_error = 1'b0; | |
1221 | wire dmc_txc_dma18_gotnxtdesc = 1'b0; | |
1222 | wire dmc_txc_dma18_cacheready = 1'b0; | |
1223 | wire dmc_txc_dma18_partial = 1'b0; | |
1224 | wire dmc_txc_dma18_reset_scheduled = 1'b0; | |
1225 | wire [1:0] dmc_txc_dma18_func_num = 2'h0; | |
1226 | wire [19:0] dmc_txc_dma18_page_handle = 20'h0; | |
1227 | wire [63:0] dmc_txc_dma18_descriptor = 64'h0; | |
1228 | ||
1229 | wire txc_dmc_dma18_getnxtdesc; | |
1230 | wire txc_dmc_dma18_inc_head; | |
1231 | wire txc_dmc_dma18_reset_done; | |
1232 | wire txc_dmc_dma18_mark_bit; | |
1233 | wire txc_dmc_dma18_inc_pkt_cnt; | |
1234 | ||
1235 | // DMA19 | |
1236 | wire dmc_txc_dma19_active = 1'b0; | |
1237 | wire dmc_txc_dma19_eoflist = 1'b1; | |
1238 | wire dmc_txc_dma19_error = 1'b0; | |
1239 | wire dmc_txc_dma19_gotnxtdesc = 1'b0; | |
1240 | wire dmc_txc_dma19_cacheready = 1'b0; | |
1241 | wire dmc_txc_dma19_partial = 1'b0; | |
1242 | wire dmc_txc_dma19_reset_scheduled = 1'b0; | |
1243 | wire [1:0] dmc_txc_dma19_func_num = 2'h0; | |
1244 | wire [19:0] dmc_txc_dma19_page_handle = 20'h0; | |
1245 | wire [63:0] dmc_txc_dma19_descriptor = 64'h0; | |
1246 | ||
1247 | wire txc_dmc_dma19_getnxtdesc; | |
1248 | wire txc_dmc_dma19_inc_head; | |
1249 | wire txc_dmc_dma19_reset_done; | |
1250 | wire txc_dmc_dma19_mark_bit; | |
1251 | wire txc_dmc_dma19_inc_pkt_cnt; | |
1252 | ||
1253 | // DMA20 | |
1254 | wire dmc_txc_dma20_active = 1'b0; | |
1255 | wire dmc_txc_dma20_eoflist = 1'b1; | |
1256 | wire dmc_txc_dma20_error = 1'b0; | |
1257 | wire dmc_txc_dma20_gotnxtdesc = 1'b0; | |
1258 | wire dmc_txc_dma20_cacheready = 1'b0; | |
1259 | wire dmc_txc_dma20_partial = 1'b0; | |
1260 | wire dmc_txc_dma20_reset_scheduled = 1'b0; | |
1261 | wire [1:0] dmc_txc_dma20_func_num = 2'h0; | |
1262 | wire [19:0] dmc_txc_dma20_page_handle = 20'h0; | |
1263 | wire [63:0] dmc_txc_dma20_descriptor = 64'h0; | |
1264 | ||
1265 | wire txc_dmc_dma20_getnxtdesc; | |
1266 | wire txc_dmc_dma20_inc_head; | |
1267 | wire txc_dmc_dma20_reset_done; | |
1268 | wire txc_dmc_dma20_mark_bit; | |
1269 | wire txc_dmc_dma20_inc_pkt_cnt; | |
1270 | ||
1271 | // DMA21 | |
1272 | wire dmc_txc_dma21_active = 1'b0; | |
1273 | wire dmc_txc_dma21_eoflist = 1'b1; | |
1274 | wire dmc_txc_dma21_error = 1'b0; | |
1275 | wire dmc_txc_dma21_gotnxtdesc = 1'b0; | |
1276 | wire dmc_txc_dma21_cacheready = 1'b0; | |
1277 | wire dmc_txc_dma21_partial = 1'b0; | |
1278 | wire dmc_txc_dma21_reset_scheduled = 1'b0; | |
1279 | wire [1:0] dmc_txc_dma21_func_num = 2'h0; | |
1280 | wire [19:0] dmc_txc_dma21_page_handle = 20'h0; | |
1281 | wire [63:0] dmc_txc_dma21_descriptor = 64'h0; | |
1282 | ||
1283 | wire txc_dmc_dma21_getnxtdesc; | |
1284 | wire txc_dmc_dma21_inc_head; | |
1285 | wire txc_dmc_dma21_reset_done; | |
1286 | wire txc_dmc_dma21_mark_bit; | |
1287 | wire txc_dmc_dma21_inc_pkt_cnt; | |
1288 | ||
1289 | // DMA22 | |
1290 | wire dmc_txc_dma22_active = 1'b0; | |
1291 | wire dmc_txc_dma22_eoflist = 1'b1; | |
1292 | wire dmc_txc_dma22_error = 1'b0; | |
1293 | wire dmc_txc_dma22_gotnxtdesc = 1'b0; | |
1294 | wire dmc_txc_dma22_cacheready = 1'b0; | |
1295 | wire dmc_txc_dma22_partial = 1'b0; | |
1296 | wire dmc_txc_dma22_reset_scheduled = 1'b0; | |
1297 | wire [1:0] dmc_txc_dma22_func_num = 2'h0; | |
1298 | wire [19:0] dmc_txc_dma22_page_handle = 20'h0; | |
1299 | wire [63:0] dmc_txc_dma22_descriptor = 64'h0; | |
1300 | ||
1301 | wire txc_dmc_dma22_getnxtdesc; | |
1302 | wire txc_dmc_dma22_inc_head; | |
1303 | wire txc_dmc_dma22_reset_done; | |
1304 | wire txc_dmc_dma22_mark_bit; | |
1305 | wire txc_dmc_dma22_inc_pkt_cnt; | |
1306 | ||
1307 | // DMA23 | |
1308 | wire dmc_txc_dma23_active = 1'b0; | |
1309 | wire dmc_txc_dma23_eoflist = 1'b1; | |
1310 | wire dmc_txc_dma23_error = 1'b0; | |
1311 | wire dmc_txc_dma23_gotnxtdesc = 1'b0; | |
1312 | wire dmc_txc_dma23_cacheready = 1'b0; | |
1313 | wire dmc_txc_dma23_partial = 1'b0; | |
1314 | wire dmc_txc_dma23_reset_scheduled = 1'b0; | |
1315 | wire [1:0] dmc_txc_dma23_func_num = 2'h0; | |
1316 | wire [19:0] dmc_txc_dma23_page_handle = 20'h0; | |
1317 | wire [63:0] dmc_txc_dma23_descriptor = 64'h0; | |
1318 | ||
1319 | wire txc_dmc_dma23_getnxtdesc; | |
1320 | wire txc_dmc_dma23_inc_head; | |
1321 | wire txc_dmc_dma23_reset_done; | |
1322 | wire txc_dmc_dma23_mark_bit; | |
1323 | wire txc_dmc_dma23_inc_pkt_cnt; | |
1324 | `endif | |
1325 | ||
1326 | // Tx DMA Request Interface | |
1327 | input arb1_txc_req_accept; | |
1328 | input [5:0] arb1_txc_req_transid; | |
1329 | ||
1330 | output txc_arb1_req; | |
1331 | output [1:0] txc_arb1_req_func_num; | |
1332 | output [1:0] txc_arb1_req_port_num; | |
1333 | output [4:0] txc_arb1_req_dma_num; | |
1334 | output [7:0] txc_arb1_req_cmd; | |
1335 | output [13:0] txc_arb1_req_length; | |
1336 | output [63:0] txc_arb1_req_address; | |
1337 | ||
1338 | // Tx DMA Response Interface | |
1339 | input meta_dmc_resp_ready; | |
1340 | input meta_dmc_resp_complete; | |
1341 | input meta_dmc_resp_transfer_cmpl; | |
1342 | input meta_dmc_data_valid; | |
1343 | input meta_dmc_resp_client; | |
1344 | input [1:0] meta_dmc_resp_port_num; | |
1345 | input [3:0] meta_dmc_resp_cmd_status; | |
1346 | input [3:0] meta_dmc_resp_data_status; | |
1347 | input [4:0] meta_dmc_resp_dma_num; | |
1348 | input [5:0] meta_dmc_resp_transID; | |
1349 | input [7:0] meta_dmc_resp_cmd; | |
1350 | input [15:0] meta_dmc_resp_byteenable; | |
1351 | input [13:0] meta_dmc_resp_length; | |
1352 | input [63:0] meta_dmc_resp_address; | |
1353 | input [127:0] meta_dmc_data; | |
1354 | ||
1355 | output dmc_meta_resp_accept; | |
1356 | ||
1357 | /*--------------------------------------------------------------*/ | |
1358 | // Wires & Registers | |
1359 | /*--------------------------------------------------------------*/ | |
1360 | `ifdef NEPTUNE | |
1361 | `else | |
1362 | wire pio_clients_32b = 1'b0; | |
1363 | `endif | |
1364 | // Reset Block | |
1365 | wire reset_l; | |
1366 | ||
1367 | // Meta Interface buffered | |
1368 | wire dMC_TXC_Resp_Rdy; | |
1369 | wire dMC_TXC_Resp_Complete; | |
1370 | wire dMC_TXC_Trans_Complete; | |
1371 | wire dMC_TXC_Resp_Data_Valid; | |
1372 | wire dMC_TXC_Resp_Client; | |
1373 | wire [1:0] dMC_TXC_Resp_Port_Num; | |
1374 | wire [3:0] dMC_TXC_Resp_Cmd_Status; | |
1375 | wire [3:0] dMC_TXC_Resp_Data_Status; | |
1376 | wire [4:0] dMC_TXC_Resp_DMA_Num; | |
1377 | wire [5:0] dMC_TXC_Resp_TransID; | |
1378 | wire [7:0] dMC_TXC_Resp_Cmd; | |
1379 | wire [13:0] dMC_TXC_Resp_Data_Length; | |
1380 | wire [15:0] dMC_TXC_Resp_ByteEnables; | |
1381 | wire [63:0] dMC_TXC_Resp_Address; | |
1382 | wire [127:0] dMC_TXC_Resp_Data; | |
1383 | ||
1384 | // Control Registers | |
1385 | wire txc_Enabled; | |
1386 | wire flushEngine; | |
1387 | wire [3:0] portSelect_State; | |
1388 | wire [3:0] dataFetch_State; | |
1389 | wire [5:0] debug_select; | |
1390 | wire [31:0] trainingVector; | |
1391 | ||
1392 | // dma contexts | |
1393 | wire dma0_NewMaxBurst; | |
1394 | wire dma1_NewMaxBurst; | |
1395 | wire dma2_NewMaxBurst; | |
1396 | wire dma3_NewMaxBurst; | |
1397 | wire dma4_NewMaxBurst; | |
1398 | wire dma5_NewMaxBurst; | |
1399 | wire dma6_NewMaxBurst; | |
1400 | wire dma7_NewMaxBurst; | |
1401 | wire dma8_NewMaxBurst; | |
1402 | wire dma9_NewMaxBurst; | |
1403 | wire dma10_NewMaxBurst; | |
1404 | wire dma11_NewMaxBurst; | |
1405 | wire dma12_NewMaxBurst; | |
1406 | wire dma13_NewMaxBurst; | |
1407 | wire dma14_NewMaxBurst; | |
1408 | wire dma15_NewMaxBurst; | |
1409 | wire dma16_NewMaxBurst; | |
1410 | wire dma17_NewMaxBurst; | |
1411 | wire dma18_NewMaxBurst; | |
1412 | wire dma19_NewMaxBurst; | |
1413 | wire dma20_NewMaxBurst; | |
1414 | wire dma21_NewMaxBurst; | |
1415 | wire dma22_NewMaxBurst; | |
1416 | wire dma23_NewMaxBurst; | |
1417 | wire [3:0] port_Selected; | |
1418 | wire [19:0] dma0_MaxBurst; | |
1419 | wire [19:0] dma1_MaxBurst; | |
1420 | wire [19:0] dma2_MaxBurst; | |
1421 | wire [19:0] dma3_MaxBurst; | |
1422 | wire [19:0] dma4_MaxBurst; | |
1423 | wire [19:0] dma5_MaxBurst; | |
1424 | wire [19:0] dma6_MaxBurst; | |
1425 | wire [19:0] dma7_MaxBurst; | |
1426 | wire [19:0] dma8_MaxBurst; | |
1427 | wire [19:0] dma9_MaxBurst; | |
1428 | wire [19:0] dma10_MaxBurst; | |
1429 | wire [19:0] dma11_MaxBurst; | |
1430 | wire [19:0] dma12_MaxBurst; | |
1431 | wire [19:0] dma13_MaxBurst; | |
1432 | wire [19:0] dma14_MaxBurst; | |
1433 | wire [19:0] dma15_MaxBurst; | |
1434 | wire [19:0] dma16_MaxBurst; | |
1435 | wire [19:0] dma17_MaxBurst; | |
1436 | wire [19:0] dma18_MaxBurst; | |
1437 | wire [19:0] dma19_MaxBurst; | |
1438 | wire [19:0] dma20_MaxBurst; | |
1439 | wire [19:0] dma21_MaxBurst; | |
1440 | wire [19:0] dma22_MaxBurst; | |
1441 | wire [19:0] dma23_MaxBurst; | |
1442 | ||
1443 | // Port 0 | |
1444 | wire port0_SetGetNextDescDMA0; | |
1445 | wire port0_SetGetNextDescDMA1; | |
1446 | wire port0_SetGetNextDescDMA2; | |
1447 | wire port0_SetGetNextDescDMA3; | |
1448 | wire port0_SetGetNextDescDMA4; | |
1449 | wire port0_SetGetNextDescDMA5; | |
1450 | wire port0_SetGetNextDescDMA6; | |
1451 | wire port0_SetGetNextDescDMA7; | |
1452 | wire port0_SetGetNextDescDMA8; | |
1453 | wire port0_SetGetNextDescDMA9; | |
1454 | wire port0_SetGetNextDescDMA10; | |
1455 | wire port0_SetGetNextDescDMA11; | |
1456 | wire port0_SetGetNextDescDMA12; | |
1457 | wire port0_SetGetNextDescDMA13; | |
1458 | wire port0_SetGetNextDescDMA14; | |
1459 | wire port0_SetGetNextDescDMA15; | |
1460 | wire port0_SetGetNextDescDMA16; | |
1461 | wire port0_SetGetNextDescDMA17; | |
1462 | wire port0_SetGetNextDescDMA18; | |
1463 | wire port0_SetGetNextDescDMA19; | |
1464 | wire port0_SetGetNextDescDMA20; | |
1465 | wire port0_SetGetNextDescDMA21; | |
1466 | wire port0_SetGetNextDescDMA22; | |
1467 | wire port0_SetGetNextDescDMA23; | |
1468 | wire port0_Request; | |
1469 | wire port0_LatchActiveDMA; | |
1470 | wire port0_mac_req; | |
1471 | wire port0_TXC_DMC_Resp_Accept; | |
1472 | wire port0_Enabled; | |
1473 | wire port0_clrMaxBurst; | |
1474 | wire port0_UpdateDMA; | |
1475 | wire port0_ClearStatistics; | |
1476 | wire port0_WrPacketStuffed; | |
1477 | wire port0_WrPacketXmitted; | |
1478 | wire port0_WrPacketRequested; | |
1479 | wire port0_ReOrderFifoDataValid; | |
1480 | wire port0_ReOrderFifoWrite; | |
1481 | wire port0_ReOrderFifoRead; | |
1482 | wire port0_StoreForwardFifoRead; | |
1483 | wire port0_StoreForwardFifoWrite; | |
1484 | wire port0_DMA0_inc_head; | |
1485 | wire port0_DMA0_reset_done; | |
1486 | wire port0_DMA0_mark_bit; | |
1487 | wire port0_DMA0_inc_pkt_cnt; | |
1488 | wire port0_DMA1_inc_head; | |
1489 | wire port0_DMA1_reset_done; | |
1490 | wire port0_DMA1_mark_bit; | |
1491 | wire port0_DMA1_inc_pkt_cnt; | |
1492 | wire port0_DMA2_inc_head; | |
1493 | wire port0_DMA2_reset_done; | |
1494 | wire port0_DMA2_mark_bit; | |
1495 | wire port0_DMA2_inc_pkt_cnt; | |
1496 | wire port0_DMA3_inc_head; | |
1497 | wire port0_DMA3_reset_done; | |
1498 | wire port0_DMA3_mark_bit; | |
1499 | wire port0_DMA3_inc_pkt_cnt; | |
1500 | wire port0_DMA4_inc_head; | |
1501 | wire port0_DMA4_reset_done; | |
1502 | wire port0_DMA4_mark_bit; | |
1503 | wire port0_DMA4_inc_pkt_cnt; | |
1504 | wire port0_DMA5_inc_head; | |
1505 | wire port0_DMA5_reset_done; | |
1506 | wire port0_DMA5_mark_bit; | |
1507 | wire port0_DMA5_inc_pkt_cnt; | |
1508 | wire port0_DMA6_inc_head; | |
1509 | wire port0_DMA6_reset_done; | |
1510 | wire port0_DMA6_mark_bit; | |
1511 | wire port0_DMA6_inc_pkt_cnt; | |
1512 | wire port0_DMA7_inc_head; | |
1513 | wire port0_DMA7_reset_done; | |
1514 | wire port0_DMA7_mark_bit; | |
1515 | wire port0_DMA7_inc_pkt_cnt; | |
1516 | wire port0_DMA8_inc_head; | |
1517 | wire port0_DMA8_reset_done; | |
1518 | wire port0_DMA8_mark_bit; | |
1519 | wire port0_DMA8_inc_pkt_cnt; | |
1520 | wire port0_DMA9_inc_head; | |
1521 | wire port0_DMA9_reset_done; | |
1522 | wire port0_DMA9_mark_bit; | |
1523 | wire port0_DMA9_inc_pkt_cnt; | |
1524 | wire port0_DMA10_inc_head; | |
1525 | wire port0_DMA10_reset_done; | |
1526 | wire port0_DMA10_mark_bit; | |
1527 | wire port0_DMA10_inc_pkt_cnt; | |
1528 | wire port0_DMA11_inc_head; | |
1529 | wire port0_DMA11_reset_done; | |
1530 | wire port0_DMA11_mark_bit; | |
1531 | wire port0_DMA11_inc_pkt_cnt; | |
1532 | wire port0_DMA12_inc_head; | |
1533 | wire port0_DMA12_reset_done; | |
1534 | wire port0_DMA12_mark_bit; | |
1535 | wire port0_DMA12_inc_pkt_cnt; | |
1536 | wire port0_DMA13_inc_head; | |
1537 | wire port0_DMA13_reset_done; | |
1538 | wire port0_DMA13_mark_bit; | |
1539 | wire port0_DMA13_inc_pkt_cnt; | |
1540 | wire port0_DMA14_inc_head; | |
1541 | wire port0_DMA14_reset_done; | |
1542 | wire port0_DMA14_mark_bit; | |
1543 | wire port0_DMA14_inc_pkt_cnt; | |
1544 | wire port0_DMA15_inc_head; | |
1545 | wire port0_DMA15_reset_done; | |
1546 | wire port0_DMA15_mark_bit; | |
1547 | wire port0_DMA15_inc_pkt_cnt; | |
1548 | wire port0_DMA16_inc_head; | |
1549 | wire port0_DMA16_reset_done; | |
1550 | wire port0_DMA16_mark_bit; | |
1551 | wire port0_DMA16_inc_pkt_cnt; | |
1552 | wire port0_DMA17_inc_head; | |
1553 | wire port0_DMA17_reset_done; | |
1554 | wire port0_DMA17_mark_bit; | |
1555 | wire port0_DMA17_inc_pkt_cnt; | |
1556 | wire port0_DMA18_inc_head; | |
1557 | wire port0_DMA18_reset_done; | |
1558 | wire port0_DMA18_mark_bit; | |
1559 | wire port0_DMA18_inc_pkt_cnt; | |
1560 | wire port0_DMA19_inc_head; | |
1561 | wire port0_DMA19_reset_done; | |
1562 | wire port0_DMA19_mark_bit; | |
1563 | wire port0_DMA19_inc_pkt_cnt; | |
1564 | wire port0_DMA20_inc_head; | |
1565 | wire port0_DMA20_reset_done; | |
1566 | wire port0_DMA20_mark_bit; | |
1567 | wire port0_DMA20_inc_pkt_cnt; | |
1568 | wire port0_DMA21_inc_head; | |
1569 | wire port0_DMA21_reset_done; | |
1570 | wire port0_DMA21_mark_bit; | |
1571 | wire port0_DMA21_inc_pkt_cnt; | |
1572 | wire port0_DMA22_inc_head; | |
1573 | wire port0_DMA22_reset_done; | |
1574 | wire port0_DMA22_mark_bit; | |
1575 | wire port0_DMA22_inc_pkt_cnt; | |
1576 | wire port0_DMA23_inc_head; | |
1577 | wire port0_DMA23_reset_done; | |
1578 | wire port0_DMA23_mark_bit; | |
1579 | wire port0_DMA23_inc_pkt_cnt; | |
1580 | wire port0_ReOrder_UnCorrectError; | |
1581 | wire port0_StoreForward_UnCorrectError; | |
1582 | wire port0_ReOrderCorruptECCSingle; | |
1583 | wire port0_ReOrderCorruptECCDouble; | |
1584 | wire port0_StoreForwardCorruptECCSingle; | |
1585 | wire port0_StoreForwardCorruptECCDouble; | |
1586 | wire port0_Nack_Pkt_Rd; | |
1587 | wire port0_PacketAssyDead; | |
1588 | wire port0_ReOrder_Error; | |
1589 | wire port0_WrTidsInUse; | |
1590 | wire port0_WrDuplicateTid; | |
1591 | wire port0_WrUnInitializedTID; | |
1592 | wire port0_WrTimedoutTids; | |
1593 | wire port0_WrReOrderStateLogic; | |
1594 | wire port0_WrReOrderStateControl; | |
1595 | wire port0_WrReOrderStateData0; | |
1596 | wire port0_WrReOrderStateData1; | |
1597 | wire port0_WrReOrderStateData2; | |
1598 | wire port0_WrReOrderStateData3; | |
1599 | wire port0_ReOrder_ClearEccError; | |
1600 | wire port0_WrReOrderEccState; | |
1601 | wire port0_WrReOrderEccData0; | |
1602 | wire port0_WrReOrderEccData1; | |
1603 | wire port0_WrReOrderEccData2; | |
1604 | wire port0_WrReOrderEccData3; | |
1605 | wire port0_WrReOrderEccData4; | |
1606 | wire port0_StoreForward_ClearEccError; | |
1607 | wire port0_WrStoreForwardEccState; | |
1608 | wire port0_WrStoreForwardEccData0; | |
1609 | wire port0_WrStoreForwardEccData1; | |
1610 | wire port0_WrStoreForwardEccData2; | |
1611 | wire port0_WrStoreForwardEccData3; | |
1612 | wire port0_WrStoreForwardEccData4; | |
1613 | wire [1:0] port0_Request_Func_Num; | |
1614 | wire [3:0] port0_GatherRequestCount; | |
1615 | wire [3:0] port0_Anchor_State; | |
1616 | wire [3:0] port0_ReOrder_State; | |
1617 | wire [3:0] port0_Pointer_State; | |
1618 | wire [3:0] port0_PacketAssy_State; | |
1619 | wire [3:0] port0_DRR_ArbState; | |
1620 | wire [3:0] port0_Mac_Xfer_State; | |
1621 | wire [3:0] port0_DataPortReq_State; | |
1622 | wire [3:0] port0_MaxReorderNumber; | |
1623 | wire [4:0] port0_Request_DMA_Num; | |
1624 | wire [9:0] port0_ReOrderWritePtr; | |
1625 | wire [9:0] port0_ReOrderReadPtr; | |
1626 | wire [9:0] port0_StoreForwardReadPtr; | |
1627 | wire [9:0] port0_StoreForwardWritePtr; | |
1628 | wire [11:0] port0_PacketRequestCount; | |
1629 | wire [12:0] port0_Request_Length; | |
1630 | wire [13:0] port0_UpdateDMALength; | |
1631 | wire [15:0] port0_PktErrAbortCount; | |
1632 | wire [15:0] port0_ReOrdersStuffed; | |
1633 | wire [15:0] port0_PacketsTransmitted; | |
1634 | wire [15:0] port0_PacketsStuffed; | |
1635 | wire [15:0] port0_BytesTransmitted; | |
1636 | wire [23:0] port0_UpdateDMANumber; | |
1637 | wire [23:0] port0_DMA_Nack_Pkt_Rd; | |
1638 | wire [23:0] port0_DMA_List; | |
1639 | wire [23:0] port0_ContextActiveList; | |
1640 | wire [31:0] port0_ReOrderEccControl; | |
1641 | wire [31:0] port0_StoreForwardEccControl; | |
1642 | wire [31:0] port0_Sum_prt_state; | |
1643 | wire [31:0] port0_TidsInUse; | |
1644 | wire [31:0] port0_DuplicateTid; | |
1645 | wire [31:0] port0_UnInitializedTID; | |
1646 | wire [31:0] port0_TimedoutTids ; | |
1647 | wire [31:0] port0_ReOrderStateLogic; | |
1648 | wire [31:0] port0_ReOrderStateControl; | |
1649 | wire [31:0] port0_ReOrderStateData0; | |
1650 | wire [31:0] port0_ReOrderStateData1; | |
1651 | wire [31:0] port0_ReOrderStateData2; | |
1652 | wire [31:0] port0_ReOrderStateData3; | |
1653 | wire [31:0] port0_PioDataIn; | |
1654 | wire [31:0] port0_ReOrder_ECC_State; | |
1655 | wire [31:0] port0_StoreForward_ECC_State; | |
1656 | wire [43:0] port0_Nack_Pkt_Rd_Addr; | |
1657 | wire [63:0] port0_Request_Address; | |
1658 | wire [135:0] port0_PacketAssyEngineDataIn; | |
1659 | wire [135:0] port0_PacketAssyEngineDataOut; | |
1660 | wire [135:0] port0_ReOrderEngineDataOut; | |
1661 | wire [135:0] port0_MacXferEngineDataIn; | |
1662 | wire [151:0] port0_ReOrderFifoDataOut; | |
1663 | wire [151:0] port0_ReOrderFifoDataIn; | |
1664 | wire [151:0] port0_StoreForwardFifoDataOut; | |
1665 | wire [151:0] port0_StoreForwardFifoDataIn; | |
1666 | wire [151:0] port0_ReOrder_EccData; | |
1667 | wire [151:0] port0_StoreForward_EccData; | |
1668 | ||
1669 | // Port 1 | |
1670 | wire port1_SetGetNextDescDMA0; | |
1671 | wire port1_SetGetNextDescDMA1; | |
1672 | wire port1_SetGetNextDescDMA2; | |
1673 | wire port1_SetGetNextDescDMA3; | |
1674 | wire port1_SetGetNextDescDMA4; | |
1675 | wire port1_SetGetNextDescDMA5; | |
1676 | wire port1_SetGetNextDescDMA6; | |
1677 | wire port1_SetGetNextDescDMA7; | |
1678 | wire port1_SetGetNextDescDMA8; | |
1679 | wire port1_SetGetNextDescDMA9; | |
1680 | wire port1_SetGetNextDescDMA10; | |
1681 | wire port1_SetGetNextDescDMA11; | |
1682 | wire port1_SetGetNextDescDMA12; | |
1683 | wire port1_SetGetNextDescDMA13; | |
1684 | wire port1_SetGetNextDescDMA14; | |
1685 | wire port1_SetGetNextDescDMA15; | |
1686 | wire port1_SetGetNextDescDMA16; | |
1687 | wire port1_SetGetNextDescDMA17; | |
1688 | wire port1_SetGetNextDescDMA18; | |
1689 | wire port1_SetGetNextDescDMA19; | |
1690 | wire port1_SetGetNextDescDMA20; | |
1691 | wire port1_SetGetNextDescDMA21; | |
1692 | wire port1_SetGetNextDescDMA22; | |
1693 | wire port1_SetGetNextDescDMA23; | |
1694 | wire port1_Request; | |
1695 | wire port1_LatchActiveDMA; | |
1696 | wire port1_mac_req; | |
1697 | wire port1_TXC_DMC_Resp_Accept; | |
1698 | wire port1_Enabled; | |
1699 | wire port1_clrMaxBurst; | |
1700 | wire port1_UpdateDMA; | |
1701 | wire port1_ClearStatistics; | |
1702 | wire port1_WrPacketStuffed; | |
1703 | wire port1_WrPacketXmitted; | |
1704 | wire port1_WrPacketRequested; | |
1705 | wire port1_ReOrderFifoDataValid; | |
1706 | wire port1_ReOrderFifoWrite; | |
1707 | wire port1_ReOrderFifoRead; | |
1708 | wire port1_StoreForwardFifoRead; | |
1709 | wire port1_StoreForwardFifoWrite; | |
1710 | wire port1_DMA0_inc_head; | |
1711 | wire port1_DMA0_reset_done; | |
1712 | wire port1_DMA0_mark_bit; | |
1713 | wire port1_DMA0_inc_pkt_cnt; | |
1714 | wire port1_DMA1_inc_head; | |
1715 | wire port1_DMA1_reset_done; | |
1716 | wire port1_DMA1_mark_bit; | |
1717 | wire port1_DMA1_inc_pkt_cnt; | |
1718 | wire port1_DMA2_inc_head; | |
1719 | wire port1_DMA2_reset_done; | |
1720 | wire port1_DMA2_mark_bit; | |
1721 | wire port1_DMA2_inc_pkt_cnt; | |
1722 | wire port1_DMA3_inc_head; | |
1723 | wire port1_DMA3_reset_done; | |
1724 | wire port1_DMA3_mark_bit; | |
1725 | wire port1_DMA3_inc_pkt_cnt; | |
1726 | wire port1_DMA4_inc_head; | |
1727 | wire port1_DMA4_reset_done; | |
1728 | wire port1_DMA4_mark_bit; | |
1729 | wire port1_DMA4_inc_pkt_cnt; | |
1730 | wire port1_DMA5_inc_head; | |
1731 | wire port1_DMA5_reset_done; | |
1732 | wire port1_DMA5_mark_bit; | |
1733 | wire port1_DMA5_inc_pkt_cnt; | |
1734 | wire port1_DMA6_inc_head; | |
1735 | wire port1_DMA6_reset_done; | |
1736 | wire port1_DMA6_mark_bit; | |
1737 | wire port1_DMA6_inc_pkt_cnt; | |
1738 | wire port1_DMA7_inc_head; | |
1739 | wire port1_DMA7_reset_done; | |
1740 | wire port1_DMA7_mark_bit; | |
1741 | wire port1_DMA7_inc_pkt_cnt; | |
1742 | wire port1_DMA8_inc_head; | |
1743 | wire port1_DMA8_reset_done; | |
1744 | wire port1_DMA8_mark_bit; | |
1745 | wire port1_DMA8_inc_pkt_cnt; | |
1746 | wire port1_DMA9_inc_head; | |
1747 | wire port1_DMA9_reset_done; | |
1748 | wire port1_DMA9_mark_bit; | |
1749 | wire port1_DMA9_inc_pkt_cnt; | |
1750 | wire port1_DMA10_inc_head; | |
1751 | wire port1_DMA10_reset_done; | |
1752 | wire port1_DMA10_mark_bit; | |
1753 | wire port1_DMA10_inc_pkt_cnt; | |
1754 | wire port1_DMA11_inc_head; | |
1755 | wire port1_DMA11_reset_done; | |
1756 | wire port1_DMA11_mark_bit; | |
1757 | wire port1_DMA11_inc_pkt_cnt; | |
1758 | wire port1_DMA12_inc_head; | |
1759 | wire port1_DMA12_reset_done; | |
1760 | wire port1_DMA12_mark_bit; | |
1761 | wire port1_DMA12_inc_pkt_cnt; | |
1762 | wire port1_DMA13_inc_head; | |
1763 | wire port1_DMA13_reset_done; | |
1764 | wire port1_DMA13_mark_bit; | |
1765 | wire port1_DMA13_inc_pkt_cnt; | |
1766 | wire port1_DMA14_inc_head; | |
1767 | wire port1_DMA14_reset_done; | |
1768 | wire port1_DMA14_mark_bit; | |
1769 | wire port1_DMA14_inc_pkt_cnt; | |
1770 | wire port1_DMA15_inc_head; | |
1771 | wire port1_DMA15_reset_done; | |
1772 | wire port1_DMA15_mark_bit; | |
1773 | wire port1_DMA15_inc_pkt_cnt; | |
1774 | wire port1_DMA16_inc_head; | |
1775 | wire port1_DMA16_reset_done; | |
1776 | wire port1_DMA16_mark_bit; | |
1777 | wire port1_DMA16_inc_pkt_cnt; | |
1778 | wire port1_DMA17_inc_head; | |
1779 | wire port1_DMA17_reset_done; | |
1780 | wire port1_DMA17_mark_bit; | |
1781 | wire port1_DMA17_inc_pkt_cnt; | |
1782 | wire port1_DMA18_inc_head; | |
1783 | wire port1_DMA18_reset_done; | |
1784 | wire port1_DMA18_mark_bit; | |
1785 | wire port1_DMA18_inc_pkt_cnt; | |
1786 | wire port1_DMA19_inc_head; | |
1787 | wire port1_DMA19_reset_done; | |
1788 | wire port1_DMA19_mark_bit; | |
1789 | wire port1_DMA19_inc_pkt_cnt; | |
1790 | wire port1_DMA20_inc_head; | |
1791 | wire port1_DMA20_reset_done; | |
1792 | wire port1_DMA20_mark_bit; | |
1793 | wire port1_DMA20_inc_pkt_cnt; | |
1794 | wire port1_DMA21_inc_head; | |
1795 | wire port1_DMA21_reset_done; | |
1796 | wire port1_DMA21_mark_bit; | |
1797 | wire port1_DMA21_inc_pkt_cnt; | |
1798 | wire port1_DMA22_inc_head; | |
1799 | wire port1_DMA22_reset_done; | |
1800 | wire port1_DMA22_mark_bit; | |
1801 | wire port1_DMA22_inc_pkt_cnt; | |
1802 | wire port1_DMA23_inc_head; | |
1803 | wire port1_DMA23_reset_done; | |
1804 | wire port1_DMA23_mark_bit; | |
1805 | wire port1_DMA23_inc_pkt_cnt; | |
1806 | wire port1_ReOrder_UnCorrectError; | |
1807 | wire port1_StoreForward_UnCorrectError; | |
1808 | wire port1_ReOrderCorruptECCSingle; | |
1809 | wire port1_ReOrderCorruptECCDouble; | |
1810 | wire port1_StoreForwardCorruptECCSingle; | |
1811 | wire port1_StoreForwardCorruptECCDouble; | |
1812 | wire port1_Nack_Pkt_Rd; | |
1813 | wire port1_PacketAssyDead; | |
1814 | wire port1_ReOrder_Error; | |
1815 | wire port1_WrTidsInUse; | |
1816 | wire port1_WrDuplicateTid; | |
1817 | wire port1_WrUnInitializedTID; | |
1818 | wire port1_WrTimedoutTids; | |
1819 | wire port1_WrReOrderStateLogic; | |
1820 | wire port1_WrReOrderStateControl; | |
1821 | wire port1_WrReOrderStateData0; | |
1822 | wire port1_WrReOrderStateData1; | |
1823 | wire port1_WrReOrderStateData2; | |
1824 | wire port1_WrReOrderStateData3; | |
1825 | wire port1_ReOrder_ClearEccError; | |
1826 | wire port1_WrReOrderEccState; | |
1827 | wire port1_WrReOrderEccData0; | |
1828 | wire port1_WrReOrderEccData1; | |
1829 | wire port1_WrReOrderEccData2; | |
1830 | wire port1_WrReOrderEccData3; | |
1831 | wire port1_WrReOrderEccData4; | |
1832 | wire port1_StoreForward_ClearEccError; | |
1833 | wire port1_WrStoreForwardEccState; | |
1834 | wire port1_WrStoreForwardEccData0; | |
1835 | wire port1_WrStoreForwardEccData1; | |
1836 | wire port1_WrStoreForwardEccData2; | |
1837 | wire port1_WrStoreForwardEccData3; | |
1838 | wire port1_WrStoreForwardEccData4; | |
1839 | wire [1:0] port1_Request_Func_Num; | |
1840 | wire [3:0] port1_GatherRequestCount; | |
1841 | wire [3:0] port1_Anchor_State; | |
1842 | wire [3:0] port1_ReOrder_State; | |
1843 | wire [3:0] port1_Pointer_State; | |
1844 | wire [3:0] port1_PacketAssy_State; | |
1845 | wire [3:0] port1_DRR_ArbState; | |
1846 | wire [3:0] port1_Mac_Xfer_State; | |
1847 | wire [3:0] port1_DataPortReq_State; | |
1848 | wire [3:0] port1_MaxReorderNumber; | |
1849 | wire [4:0] port1_Request_DMA_Num; | |
1850 | wire [9:0] port1_ReOrderWritePtr; | |
1851 | wire [9:0] port1_ReOrderReadPtr; | |
1852 | wire [9:0] port1_StoreForwardReadPtr; | |
1853 | wire [9:0] port1_StoreForwardWritePtr; | |
1854 | wire [11:0] port1_PacketRequestCount; | |
1855 | wire [12:0] port1_Request_Length; | |
1856 | wire [13:0] port1_UpdateDMALength; | |
1857 | wire [15:0] port1_PktErrAbortCount; | |
1858 | wire [15:0] port1_ReOrdersStuffed; | |
1859 | wire [15:0] port1_PacketsTransmitted; | |
1860 | wire [15:0] port1_PacketsStuffed; | |
1861 | wire [15:0] port1_BytesTransmitted; | |
1862 | wire [23:0] port1_UpdateDMANumber; | |
1863 | wire [23:0] port1_DMA_Nack_Pkt_Rd; | |
1864 | wire [23:0] port1_DMA_List; | |
1865 | wire [23:0] port1_ContextActiveList; | |
1866 | wire [31:0] port1_ReOrderEccControl; | |
1867 | wire [31:0] port1_StoreForwardEccControl; | |
1868 | wire [31:0] port1_Sum_prt_state; | |
1869 | wire [31:0] port1_TidsInUse; | |
1870 | wire [31:0] port1_DuplicateTid; | |
1871 | wire [31:0] port1_UnInitializedTID; | |
1872 | wire [31:0] port1_TimedoutTids ; | |
1873 | wire [31:0] port1_ReOrderStateLogic; | |
1874 | wire [31:0] port1_ReOrderStateControl; | |
1875 | wire [31:0] port1_ReOrderStateData0; | |
1876 | wire [31:0] port1_ReOrderStateData1; | |
1877 | wire [31:0] port1_ReOrderStateData2; | |
1878 | wire [31:0] port1_ReOrderStateData3; | |
1879 | wire [31:0] port1_PioDataIn; | |
1880 | wire [31:0] port1_ReOrder_ECC_State; | |
1881 | wire [31:0] port1_StoreForward_ECC_State; | |
1882 | wire [43:0] port1_Nack_Pkt_Rd_Addr; | |
1883 | wire [63:0] port1_Request_Address; | |
1884 | wire [135:0] port1_PacketAssyEngineDataIn; | |
1885 | wire [135:0] port1_PacketAssyEngineDataOut; | |
1886 | wire [135:0] port1_ReOrderEngineDataOut; | |
1887 | wire [135:0] port1_MacXferEngineDataIn; | |
1888 | wire [151:0] port1_ReOrderFifoDataOut; | |
1889 | wire [151:0] port1_ReOrderFifoDataIn; | |
1890 | wire [151:0] port1_StoreForwardFifoDataOut; | |
1891 | wire [151:0] port1_StoreForwardFifoDataIn; | |
1892 | wire [151:0] port1_ReOrder_EccData; | |
1893 | wire [151:0] port1_StoreForward_EccData; | |
1894 | ||
1895 | `ifdef NEPTUNE | |
1896 | ||
1897 | // Port 2 | |
1898 | wire port2_SetGetNextDescDMA0; | |
1899 | wire port2_SetGetNextDescDMA1; | |
1900 | wire port2_SetGetNextDescDMA2; | |
1901 | wire port2_SetGetNextDescDMA3; | |
1902 | wire port2_SetGetNextDescDMA4; | |
1903 | wire port2_SetGetNextDescDMA5; | |
1904 | wire port2_SetGetNextDescDMA6; | |
1905 | wire port2_SetGetNextDescDMA7; | |
1906 | wire port2_SetGetNextDescDMA8; | |
1907 | wire port2_SetGetNextDescDMA9; | |
1908 | wire port2_SetGetNextDescDMA10; | |
1909 | wire port2_SetGetNextDescDMA11; | |
1910 | wire port2_SetGetNextDescDMA12; | |
1911 | wire port2_SetGetNextDescDMA13; | |
1912 | wire port2_SetGetNextDescDMA14; | |
1913 | wire port2_SetGetNextDescDMA15; | |
1914 | wire port2_SetGetNextDescDMA16; | |
1915 | wire port2_SetGetNextDescDMA17; | |
1916 | wire port2_SetGetNextDescDMA18; | |
1917 | wire port2_SetGetNextDescDMA19; | |
1918 | wire port2_SetGetNextDescDMA20; | |
1919 | wire port2_SetGetNextDescDMA21; | |
1920 | wire port2_SetGetNextDescDMA22; | |
1921 | wire port2_SetGetNextDescDMA23; | |
1922 | wire port2_Request; | |
1923 | wire port2_LatchActiveDMA; | |
1924 | wire port2_mac_req; | |
1925 | wire port2_TXC_DMC_Resp_Accept; | |
1926 | wire port2_Enabled; | |
1927 | wire port2_clrMaxBurst; | |
1928 | wire port2_UpdateDMA; | |
1929 | wire port2_ClearStatistics; | |
1930 | wire port2_WrPacketStuffed; | |
1931 | wire port2_WrPacketXmitted; | |
1932 | wire port2_WrPacketRequested; | |
1933 | wire port2_ReOrderFifoDataValid; | |
1934 | wire port2_ReOrderFifoWrite; | |
1935 | wire port2_ReOrderFifoRead; | |
1936 | wire port2_StoreForwardFifoRead; | |
1937 | wire port2_StoreForwardFifoWrite; | |
1938 | wire port2_DMA0_inc_head; | |
1939 | wire port2_DMA0_reset_done; | |
1940 | wire port2_DMA0_mark_bit; | |
1941 | wire port2_DMA0_inc_pkt_cnt; | |
1942 | wire port2_DMA1_inc_head; | |
1943 | wire port2_DMA1_reset_done; | |
1944 | wire port2_DMA1_mark_bit; | |
1945 | wire port2_DMA1_inc_pkt_cnt; | |
1946 | wire port2_DMA2_inc_head; | |
1947 | wire port2_DMA2_reset_done; | |
1948 | wire port2_DMA2_mark_bit; | |
1949 | wire port2_DMA2_inc_pkt_cnt; | |
1950 | wire port2_DMA3_inc_head; | |
1951 | wire port2_DMA3_reset_done; | |
1952 | wire port2_DMA3_mark_bit; | |
1953 | wire port2_DMA3_inc_pkt_cnt; | |
1954 | wire port2_DMA4_inc_head; | |
1955 | wire port2_DMA4_reset_done; | |
1956 | wire port2_DMA4_mark_bit; | |
1957 | wire port2_DMA4_inc_pkt_cnt; | |
1958 | wire port2_DMA5_inc_head; | |
1959 | wire port2_DMA5_reset_done; | |
1960 | wire port2_DMA5_mark_bit; | |
1961 | wire port2_DMA5_inc_pkt_cnt; | |
1962 | wire port2_DMA6_inc_head; | |
1963 | wire port2_DMA6_reset_done; | |
1964 | wire port2_DMA6_mark_bit; | |
1965 | wire port2_DMA6_inc_pkt_cnt; | |
1966 | wire port2_DMA7_inc_head; | |
1967 | wire port2_DMA7_reset_done; | |
1968 | wire port2_DMA7_mark_bit; | |
1969 | wire port2_DMA7_inc_pkt_cnt; | |
1970 | wire port2_DMA8_inc_head; | |
1971 | wire port2_DMA8_reset_done; | |
1972 | wire port2_DMA8_mark_bit; | |
1973 | wire port2_DMA8_inc_pkt_cnt; | |
1974 | wire port2_DMA9_inc_head; | |
1975 | wire port2_DMA9_reset_done; | |
1976 | wire port2_DMA9_mark_bit; | |
1977 | wire port2_DMA9_inc_pkt_cnt; | |
1978 | wire port2_DMA10_inc_head; | |
1979 | wire port2_DMA10_reset_done; | |
1980 | wire port2_DMA10_mark_bit; | |
1981 | wire port2_DMA10_inc_pkt_cnt; | |
1982 | wire port2_DMA11_inc_head; | |
1983 | wire port2_DMA11_reset_done; | |
1984 | wire port2_DMA11_mark_bit; | |
1985 | wire port2_DMA11_inc_pkt_cnt; | |
1986 | wire port2_DMA12_inc_head; | |
1987 | wire port2_DMA12_reset_done; | |
1988 | wire port2_DMA12_mark_bit; | |
1989 | wire port2_DMA12_inc_pkt_cnt; | |
1990 | wire port2_DMA13_inc_head; | |
1991 | wire port2_DMA13_reset_done; | |
1992 | wire port2_DMA13_mark_bit; | |
1993 | wire port2_DMA13_inc_pkt_cnt; | |
1994 | wire port2_DMA14_inc_head; | |
1995 | wire port2_DMA14_reset_done; | |
1996 | wire port2_DMA14_mark_bit; | |
1997 | wire port2_DMA14_inc_pkt_cnt; | |
1998 | wire port2_DMA15_inc_head; | |
1999 | wire port2_DMA15_reset_done; | |
2000 | wire port2_DMA15_mark_bit; | |
2001 | wire port2_DMA15_inc_pkt_cnt; | |
2002 | wire port2_DMA16_inc_head; | |
2003 | wire port2_DMA16_reset_done; | |
2004 | wire port2_DMA16_mark_bit; | |
2005 | wire port2_DMA16_inc_pkt_cnt; | |
2006 | wire port2_DMA17_inc_head; | |
2007 | wire port2_DMA17_reset_done; | |
2008 | wire port2_DMA17_mark_bit; | |
2009 | wire port2_DMA17_inc_pkt_cnt; | |
2010 | wire port2_DMA18_inc_head; | |
2011 | wire port2_DMA18_reset_done; | |
2012 | wire port2_DMA18_mark_bit; | |
2013 | wire port2_DMA18_inc_pkt_cnt; | |
2014 | wire port2_DMA19_inc_head; | |
2015 | wire port2_DMA19_reset_done; | |
2016 | wire port2_DMA19_mark_bit; | |
2017 | wire port2_DMA19_inc_pkt_cnt; | |
2018 | wire port2_DMA20_inc_head; | |
2019 | wire port2_DMA20_reset_done; | |
2020 | wire port2_DMA20_mark_bit; | |
2021 | wire port2_DMA20_inc_pkt_cnt; | |
2022 | wire port2_DMA21_inc_head; | |
2023 | wire port2_DMA21_reset_done; | |
2024 | wire port2_DMA21_mark_bit; | |
2025 | wire port2_DMA21_inc_pkt_cnt; | |
2026 | wire port2_DMA22_inc_head; | |
2027 | wire port2_DMA22_reset_done; | |
2028 | wire port2_DMA22_mark_bit; | |
2029 | wire port2_DMA22_inc_pkt_cnt; | |
2030 | wire port2_DMA23_inc_head; | |
2031 | wire port2_DMA23_reset_done; | |
2032 | wire port2_DMA23_mark_bit; | |
2033 | wire port2_DMA23_inc_pkt_cnt; | |
2034 | wire port2_ReOrder_UnCorrectError; | |
2035 | wire port2_StoreForward_UnCorrectError; | |
2036 | wire port2_ReOrderCorruptECCSingle; | |
2037 | wire port2_ReOrderCorruptECCDouble; | |
2038 | wire port2_StoreForwardCorruptECCSingle; | |
2039 | wire port2_StoreForwardCorruptECCDouble; | |
2040 | wire port2_Nack_Pkt_Rd; | |
2041 | wire port2_PacketAssyDead; | |
2042 | wire port2_ReOrder_Error; | |
2043 | wire port2_WrTidsInUse; | |
2044 | wire port2_WrDuplicateTid; | |
2045 | wire port2_WrUnInitializedTID; | |
2046 | wire port2_WrTimedoutTids; | |
2047 | wire port2_WrReOrderStateLogic; | |
2048 | wire port2_WrReOrderStateControl; | |
2049 | wire port2_WrReOrderStateData0; | |
2050 | wire port2_WrReOrderStateData1; | |
2051 | wire port2_WrReOrderStateData2; | |
2052 | wire port2_WrReOrderStateData3; | |
2053 | wire port2_ReOrder_ClearEccError; | |
2054 | wire port2_WrReOrderEccState; | |
2055 | wire port2_WrReOrderEccData0; | |
2056 | wire port2_WrReOrderEccData1; | |
2057 | wire port2_WrReOrderEccData2; | |
2058 | wire port2_WrReOrderEccData3; | |
2059 | wire port2_WrReOrderEccData4; | |
2060 | wire port2_StoreForward_ClearEccError; | |
2061 | wire port2_WrStoreForwardEccState; | |
2062 | wire port2_WrStoreForwardEccData0; | |
2063 | wire port2_WrStoreForwardEccData1; | |
2064 | wire port2_WrStoreForwardEccData2; | |
2065 | wire port2_WrStoreForwardEccData3; | |
2066 | wire port2_WrStoreForwardEccData4; | |
2067 | wire [1:0] port2_Request_Func_Num; | |
2068 | wire [3:0] port2_GatherRequestCount; | |
2069 | wire [3:0] port2_Anchor_State; | |
2070 | wire [3:0] port2_ReOrder_State; | |
2071 | wire [3:0] port2_Pointer_State; | |
2072 | wire [3:0] port2_PacketAssy_State; | |
2073 | wire [3:0] port2_DRR_ArbState; | |
2074 | wire [3:0] port2_Mac_Xfer_State; | |
2075 | wire [3:0] port2_DataPortReq_State; | |
2076 | wire [3:0] port2_MaxReorderNumber; | |
2077 | wire [4:0] port2_Request_DMA_Num; | |
2078 | wire [9:0] port2_ReOrderWritePtr; | |
2079 | wire [9:0] port2_ReOrderReadPtr; | |
2080 | wire [9:0] port2_StoreForwardReadPtr; | |
2081 | wire [9:0] port2_StoreForwardWritePtr; | |
2082 | wire [11:0] port2_PacketRequestCount; | |
2083 | wire [12:0] port2_Request_Length; | |
2084 | wire [13:0] port2_UpdateDMALength; | |
2085 | wire [15:0] port2_PktErrAbortCount; | |
2086 | wire [15:0] port2_ReOrdersStuffed; | |
2087 | wire [15:0] port2_PacketsTransmitted; | |
2088 | wire [15:0] port2_PacketsStuffed; | |
2089 | wire [15:0] port2_BytesTransmitted; | |
2090 | wire [23:0] port2_UpdateDMANumber; | |
2091 | wire [23:0] port2_DMA_Nack_Pkt_Rd; | |
2092 | wire [23:0] port2_DMA_List; | |
2093 | wire [23:0] port2_ContextActiveList; | |
2094 | wire [31:0] port2_ReOrderEccControl; | |
2095 | wire [31:0] port2_StoreForwardEccControl; | |
2096 | wire [31:0] port2_Sum_prt_state; | |
2097 | wire [31:0] port2_TidsInUse; | |
2098 | wire [31:0] port2_DuplicateTid; | |
2099 | wire [31:0] port2_UnInitializedTID; | |
2100 | wire [31:0] port2_TimedoutTids ; | |
2101 | wire [31:0] port2_ReOrderStateLogic; | |
2102 | wire [31:0] port2_ReOrderStateControl; | |
2103 | wire [31:0] port2_ReOrderStateData0; | |
2104 | wire [31:0] port2_ReOrderStateData1; | |
2105 | wire [31:0] port2_ReOrderStateData2; | |
2106 | wire [31:0] port2_ReOrderStateData3; | |
2107 | wire [31:0] port2_PioDataIn; | |
2108 | wire [31:0] port2_ReOrder_ECC_State; | |
2109 | wire [31:0] port2_StoreForward_ECC_State; | |
2110 | wire [43:0] port2_Nack_Pkt_Rd_Addr; | |
2111 | wire [63:0] port2_Request_Address; | |
2112 | wire [135:0] port2_PacketAssyEngineDataIn; | |
2113 | wire [135:0] port2_PacketAssyEngineDataOut; | |
2114 | wire [135:0] port2_ReOrderEngineDataOut; | |
2115 | wire [135:0] port2_MacXferEngineDataIn; | |
2116 | wire [151:0] port2_ReOrderFifoDataOut; | |
2117 | wire [151:0] port2_ReOrderFifoDataIn; | |
2118 | wire [151:0] port2_StoreForwardFifoDataOut; | |
2119 | wire [151:0] port2_StoreForwardFifoDataIn; | |
2120 | wire [151:0] port2_ReOrder_EccData; | |
2121 | wire [151:0] port2_StoreForward_EccData; | |
2122 | ||
2123 | // Port 3 | |
2124 | wire port3_SetGetNextDescDMA0; | |
2125 | wire port3_SetGetNextDescDMA1; | |
2126 | wire port3_SetGetNextDescDMA2; | |
2127 | wire port3_SetGetNextDescDMA3; | |
2128 | wire port3_SetGetNextDescDMA4; | |
2129 | wire port3_SetGetNextDescDMA5; | |
2130 | wire port3_SetGetNextDescDMA6; | |
2131 | wire port3_SetGetNextDescDMA7; | |
2132 | wire port3_SetGetNextDescDMA8; | |
2133 | wire port3_SetGetNextDescDMA9; | |
2134 | wire port3_SetGetNextDescDMA10; | |
2135 | wire port3_SetGetNextDescDMA11; | |
2136 | wire port3_SetGetNextDescDMA12; | |
2137 | wire port3_SetGetNextDescDMA13; | |
2138 | wire port3_SetGetNextDescDMA14; | |
2139 | wire port3_SetGetNextDescDMA15; | |
2140 | wire port3_SetGetNextDescDMA16; | |
2141 | wire port3_SetGetNextDescDMA17; | |
2142 | wire port3_SetGetNextDescDMA18; | |
2143 | wire port3_SetGetNextDescDMA19; | |
2144 | wire port3_SetGetNextDescDMA20; | |
2145 | wire port3_SetGetNextDescDMA21; | |
2146 | wire port3_SetGetNextDescDMA22; | |
2147 | wire port3_SetGetNextDescDMA23; | |
2148 | wire port3_Request; | |
2149 | wire port3_LatchActiveDMA; | |
2150 | wire port3_mac_req; | |
2151 | wire port3_TXC_DMC_Resp_Accept; | |
2152 | wire port3_Enabled; | |
2153 | wire port3_clrMaxBurst; | |
2154 | wire port3_UpdateDMA; | |
2155 | wire port3_ClearStatistics; | |
2156 | wire port3_WrPacketStuffed; | |
2157 | wire port3_WrPacketXmitted; | |
2158 | wire port3_WrPacketRequested; | |
2159 | wire port3_ReOrderFifoDataValid; | |
2160 | wire port3_ReOrderFifoWrite; | |
2161 | wire port3_ReOrderFifoRead; | |
2162 | wire port3_StoreForwardFifoRead; | |
2163 | wire port3_StoreForwardFifoWrite; | |
2164 | wire port3_DMA0_inc_head; | |
2165 | wire port3_DMA0_reset_done; | |
2166 | wire port3_DMA0_mark_bit; | |
2167 | wire port3_DMA0_inc_pkt_cnt; | |
2168 | wire port3_DMA1_inc_head; | |
2169 | wire port3_DMA1_reset_done; | |
2170 | wire port3_DMA1_mark_bit; | |
2171 | wire port3_DMA1_inc_pkt_cnt; | |
2172 | wire port3_DMA2_inc_head; | |
2173 | wire port3_DMA2_reset_done; | |
2174 | wire port3_DMA2_mark_bit; | |
2175 | wire port3_DMA2_inc_pkt_cnt; | |
2176 | wire port3_DMA3_inc_head; | |
2177 | wire port3_DMA3_reset_done; | |
2178 | wire port3_DMA3_mark_bit; | |
2179 | wire port3_DMA3_inc_pkt_cnt; | |
2180 | wire port3_DMA4_inc_head; | |
2181 | wire port3_DMA4_reset_done; | |
2182 | wire port3_DMA4_mark_bit; | |
2183 | wire port3_DMA4_inc_pkt_cnt; | |
2184 | wire port3_DMA5_inc_head; | |
2185 | wire port3_DMA5_reset_done; | |
2186 | wire port3_DMA5_mark_bit; | |
2187 | wire port3_DMA5_inc_pkt_cnt; | |
2188 | wire port3_DMA6_inc_head; | |
2189 | wire port3_DMA6_reset_done; | |
2190 | wire port3_DMA6_mark_bit; | |
2191 | wire port3_DMA6_inc_pkt_cnt; | |
2192 | wire port3_DMA7_inc_head; | |
2193 | wire port3_DMA7_reset_done; | |
2194 | wire port3_DMA7_mark_bit; | |
2195 | wire port3_DMA7_inc_pkt_cnt; | |
2196 | wire port3_DMA8_inc_head; | |
2197 | wire port3_DMA8_reset_done; | |
2198 | wire port3_DMA8_mark_bit; | |
2199 | wire port3_DMA8_inc_pkt_cnt; | |
2200 | wire port3_DMA9_inc_head; | |
2201 | wire port3_DMA9_reset_done; | |
2202 | wire port3_DMA9_mark_bit; | |
2203 | wire port3_DMA9_inc_pkt_cnt; | |
2204 | wire port3_DMA10_inc_head; | |
2205 | wire port3_DMA10_reset_done; | |
2206 | wire port3_DMA10_mark_bit; | |
2207 | wire port3_DMA10_inc_pkt_cnt; | |
2208 | wire port3_DMA11_inc_head; | |
2209 | wire port3_DMA11_reset_done; | |
2210 | wire port3_DMA11_mark_bit; | |
2211 | wire port3_DMA11_inc_pkt_cnt; | |
2212 | wire port3_DMA12_inc_head; | |
2213 | wire port3_DMA12_reset_done; | |
2214 | wire port3_DMA12_mark_bit; | |
2215 | wire port3_DMA12_inc_pkt_cnt; | |
2216 | wire port3_DMA13_inc_head; | |
2217 | wire port3_DMA13_reset_done; | |
2218 | wire port3_DMA13_mark_bit; | |
2219 | wire port3_DMA13_inc_pkt_cnt; | |
2220 | wire port3_DMA14_inc_head; | |
2221 | wire port3_DMA14_reset_done; | |
2222 | wire port3_DMA14_mark_bit; | |
2223 | wire port3_DMA14_inc_pkt_cnt; | |
2224 | wire port3_DMA15_inc_head; | |
2225 | wire port3_DMA15_reset_done; | |
2226 | wire port3_DMA15_mark_bit; | |
2227 | wire port3_DMA15_inc_pkt_cnt; | |
2228 | wire port3_DMA16_inc_head; | |
2229 | wire port3_DMA16_reset_done; | |
2230 | wire port3_DMA16_mark_bit; | |
2231 | wire port3_DMA16_inc_pkt_cnt; | |
2232 | wire port3_DMA17_inc_head; | |
2233 | wire port3_DMA17_reset_done; | |
2234 | wire port3_DMA17_mark_bit; | |
2235 | wire port3_DMA17_inc_pkt_cnt; | |
2236 | wire port3_DMA18_inc_head; | |
2237 | wire port3_DMA18_reset_done; | |
2238 | wire port3_DMA18_mark_bit; | |
2239 | wire port3_DMA18_inc_pkt_cnt; | |
2240 | wire port3_DMA19_inc_head; | |
2241 | wire port3_DMA19_reset_done; | |
2242 | wire port3_DMA19_mark_bit; | |
2243 | wire port3_DMA19_inc_pkt_cnt; | |
2244 | wire port3_DMA20_inc_head; | |
2245 | wire port3_DMA20_reset_done; | |
2246 | wire port3_DMA20_mark_bit; | |
2247 | wire port3_DMA20_inc_pkt_cnt; | |
2248 | wire port3_DMA21_inc_head; | |
2249 | wire port3_DMA21_reset_done; | |
2250 | wire port3_DMA21_mark_bit; | |
2251 | wire port3_DMA21_inc_pkt_cnt; | |
2252 | wire port3_DMA22_inc_head; | |
2253 | wire port3_DMA22_reset_done; | |
2254 | wire port3_DMA22_mark_bit; | |
2255 | wire port3_DMA22_inc_pkt_cnt; | |
2256 | wire port3_DMA23_inc_head; | |
2257 | wire port3_DMA23_reset_done; | |
2258 | wire port3_DMA23_mark_bit; | |
2259 | wire port3_DMA23_inc_pkt_cnt; | |
2260 | wire port3_ReOrder_UnCorrectError; | |
2261 | wire port3_StoreForward_UnCorrectError; | |
2262 | wire port3_ReOrderCorruptECCSingle; | |
2263 | wire port3_ReOrderCorruptECCDouble; | |
2264 | wire port3_StoreForwardCorruptECCSingle; | |
2265 | wire port3_StoreForwardCorruptECCDouble; | |
2266 | wire port3_Nack_Pkt_Rd; | |
2267 | wire port3_PacketAssyDead; | |
2268 | wire port3_ReOrder_Error; | |
2269 | wire port3_WrTidsInUse; | |
2270 | wire port3_WrDuplicateTid; | |
2271 | wire port3_WrUnInitializedTID; | |
2272 | wire port3_WrTimedoutTids; | |
2273 | wire port3_WrReOrderStateLogic; | |
2274 | wire port3_WrReOrderStateControl; | |
2275 | wire port3_WrReOrderStateData0; | |
2276 | wire port3_WrReOrderStateData1; | |
2277 | wire port3_WrReOrderStateData2; | |
2278 | wire port3_WrReOrderStateData3; | |
2279 | wire port3_ReOrder_ClearEccError; | |
2280 | wire port3_WrReOrderEccState; | |
2281 | wire port3_WrReOrderEccData0; | |
2282 | wire port3_WrReOrderEccData1; | |
2283 | wire port3_WrReOrderEccData2; | |
2284 | wire port3_WrReOrderEccData3; | |
2285 | wire port3_WrReOrderEccData4; | |
2286 | wire port3_StoreForward_ClearEccError; | |
2287 | wire port3_WrStoreForwardEccState; | |
2288 | wire port3_WrStoreForwardEccData0; | |
2289 | wire port3_WrStoreForwardEccData1; | |
2290 | wire port3_WrStoreForwardEccData2; | |
2291 | wire port3_WrStoreForwardEccData3; | |
2292 | wire port3_WrStoreForwardEccData4; | |
2293 | wire [1:0] port3_Request_Func_Num; | |
2294 | wire [3:0] port3_GatherRequestCount; | |
2295 | wire [3:0] port3_Anchor_State; | |
2296 | wire [3:0] port3_ReOrder_State; | |
2297 | wire [3:0] port3_Pointer_State; | |
2298 | wire [3:0] port3_PacketAssy_State; | |
2299 | wire [3:0] port3_DRR_ArbState; | |
2300 | wire [3:0] port3_Mac_Xfer_State; | |
2301 | wire [3:0] port3_DataPortReq_State; | |
2302 | wire [3:0] port3_MaxReorderNumber; | |
2303 | wire [4:0] port3_Request_DMA_Num; | |
2304 | wire [9:0] port3_ReOrderWritePtr; | |
2305 | wire [9:0] port3_ReOrderReadPtr; | |
2306 | wire [9:0] port3_StoreForwardReadPtr; | |
2307 | wire [9:0] port3_StoreForwardWritePtr; | |
2308 | wire [11:0] port3_PacketRequestCount; | |
2309 | wire [12:0] port3_Request_Length; | |
2310 | wire [13:0] port3_UpdateDMALength; | |
2311 | wire [15:0] port3_PktErrAbortCount; | |
2312 | wire [15:0] port3_ReOrdersStuffed; | |
2313 | wire [15:0] port3_PacketsTransmitted; | |
2314 | wire [15:0] port3_PacketsStuffed; | |
2315 | wire [15:0] port3_BytesTransmitted; | |
2316 | wire [23:0] port3_UpdateDMANumber; | |
2317 | wire [23:0] port3_DMA_Nack_Pkt_Rd; | |
2318 | wire [23:0] port3_DMA_List; | |
2319 | wire [23:0] port3_ContextActiveList; | |
2320 | wire [31:0] port3_ReOrderEccControl; | |
2321 | wire [31:0] port3_StoreForwardEccControl; | |
2322 | wire [31:0] port3_Sum_prt_state; | |
2323 | wire [31:0] port3_TidsInUse; | |
2324 | wire [31:0] port3_DuplicateTid; | |
2325 | wire [31:0] port3_UnInitializedTID; | |
2326 | wire [31:0] port3_TimedoutTids ; | |
2327 | wire [31:0] port3_ReOrderStateLogic; | |
2328 | wire [31:0] port3_ReOrderStateControl; | |
2329 | wire [31:0] port3_ReOrderStateData0; | |
2330 | wire [31:0] port3_ReOrderStateData1; | |
2331 | wire [31:0] port3_ReOrderStateData2; | |
2332 | wire [31:0] port3_ReOrderStateData3; | |
2333 | wire [31:0] port3_PioDataIn; | |
2334 | wire [31:0] port3_ReOrder_ECC_State; | |
2335 | wire [31:0] port3_StoreForward_ECC_State; | |
2336 | wire [43:0] port3_Nack_Pkt_Rd_Addr; | |
2337 | wire [63:0] port3_Request_Address; | |
2338 | wire [135:0] port3_PacketAssyEngineDataIn; | |
2339 | wire [135:0] port3_PacketAssyEngineDataOut; | |
2340 | wire [135:0] port3_ReOrderEngineDataOut; | |
2341 | wire [135:0] port3_MacXferEngineDataIn; | |
2342 | wire [151:0] port3_ReOrderFifoDataOut; | |
2343 | wire [151:0] port3_ReOrderFifoDataIn; | |
2344 | wire [151:0] port3_StoreForwardFifoDataOut; | |
2345 | wire [151:0] port3_StoreForwardFifoDataIn; | |
2346 | wire [151:0] port3_ReOrder_EccData; | |
2347 | wire [151:0] port3_StoreForward_EccData; | |
2348 | ||
2349 | `else | |
2350 | ||
2351 | wire sram_reset; | |
2352 | ||
2353 | `endif | |
2354 | ||
2355 | /*--------------------------------------------------------------*/ | |
2356 | // Overload Parameters | |
2357 | /*--------------------------------------------------------------*/ | |
2358 | parameter REORDER_SIZE_10G = 16, | |
2359 | REORDER_PTR_10G = 4, | |
2360 | REORDER_SIZE_1G = 8, | |
2361 | REORDER_PTR_1G = 3; | |
2362 | ||
2363 | /*--------------------------------------------------------------*/ | |
2364 | // Module Instantiations | |
2365 | /*--------------------------------------------------------------*/ | |
2366 | ||
2367 | niu_txc_Reset niu_txc_Reset ( | |
2368 | .SysClk (niu_clk), | |
2369 | .niu_reset_l (niu_reset_l), | |
2370 | `ifdef NEPTUNE | |
2371 | `else | |
2372 | .sram_reset (sram_reset), | |
2373 | `endif | |
2374 | .reset_l (reset_l) | |
2375 | ); | |
2376 | ||
2377 | niu_txc_mac_ifc niu_txc_mac_ifc ( | |
2378 | .SysClk (niu_clk), | |
2379 | .Reset_L (reset_l), | |
2380 | `ifdef NEPTUNE | |
2381 | .Mac_Txc_Req3 (mac_txc_req3), | |
2382 | .Mac_Req3 (port3_mac_req), | |
2383 | .Mac_Txc_Req2 (mac_txc_req2), | |
2384 | .Mac_Req2 (port2_mac_req), | |
2385 | `endif | |
2386 | .Mac_Txc_Req1 (mac_txc_req1), | |
2387 | .Mac_Req1 (port1_mac_req), | |
2388 | .Mac_Txc_Req0 (mac_txc_req0), | |
2389 | .Mac_Req0 (port0_mac_req) | |
2390 | ); | |
2391 | ||
2392 | niu_txc_meta_resp_ifc niu_txc_meta_resp_ifc ( | |
2393 | .SysClk (niu_clk), | |
2394 | .Reset_L (reset_l), | |
2395 | .meta_dmc_resp_ready (meta_dmc_resp_ready), | |
2396 | .meta_dmc_resp_complete (meta_dmc_resp_complete), | |
2397 | .meta_dmc_resp_transfer_cmpl (meta_dmc_resp_transfer_cmpl), | |
2398 | .meta_dmc_data_valid (meta_dmc_data_valid), | |
2399 | .meta_dmc_resp_client (meta_dmc_resp_client), | |
2400 | .meta_dmc_resp_port_num (meta_dmc_resp_port_num), | |
2401 | .meta_dmc_resp_cmd_status (meta_dmc_resp_cmd_status), | |
2402 | .meta_dmc_resp_data_status (meta_dmc_resp_data_status), | |
2403 | .meta_dmc_resp_dma_num (meta_dmc_resp_dma_num), | |
2404 | .meta_dmc_resp_transID (meta_dmc_resp_transID), | |
2405 | .meta_dmc_resp_cmd (meta_dmc_resp_cmd), | |
2406 | .meta_dmc_resp_byteenable (meta_dmc_resp_byteenable), | |
2407 | .meta_dmc_resp_length (meta_dmc_resp_length), | |
2408 | .meta_dmc_resp_address (meta_dmc_resp_address), | |
2409 | .meta_dmc_data (meta_dmc_data), | |
2410 | .dmc_meta_resp_accept (dmc_meta_resp_accept), | |
2411 | .Port0_TXC_DMC_Resp_Accept (port0_TXC_DMC_Resp_Accept), | |
2412 | .Port1_TXC_DMC_Resp_Accept (port1_TXC_DMC_Resp_Accept), | |
2413 | `ifdef NEPTUNE | |
2414 | .Port2_TXC_DMC_Resp_Accept (port2_TXC_DMC_Resp_Accept), | |
2415 | .Port3_TXC_DMC_Resp_Accept (port3_TXC_DMC_Resp_Accept), | |
2416 | `else | |
2417 | .Port2_TXC_DMC_Resp_Accept (1'b0), | |
2418 | .Port3_TXC_DMC_Resp_Accept (1'b0), | |
2419 | `endif | |
2420 | .DMC_TXC_Resp_Rdy (dMC_TXC_Resp_Rdy), | |
2421 | .DMC_TXC_Resp_Complete (dMC_TXC_Resp_Complete), | |
2422 | .DMC_TXC_Trans_Complete (dMC_TXC_Trans_Complete), | |
2423 | .DMC_TXC_Resp_Data_Valid (dMC_TXC_Resp_Data_Valid), | |
2424 | .DMC_TXC_Resp_Client (dMC_TXC_Resp_Client), | |
2425 | .DMC_TXC_Resp_Port_Num (dMC_TXC_Resp_Port_Num), | |
2426 | .DMC_TXC_Resp_Cmd_Status (dMC_TXC_Resp_Cmd_Status), | |
2427 | .DMC_TXC_Resp_Data_Status (dMC_TXC_Resp_Data_Status), | |
2428 | .DMC_TXC_Resp_DMA_Num (dMC_TXC_Resp_DMA_Num), | |
2429 | .DMC_TXC_Resp_TransID (dMC_TXC_Resp_TransID), | |
2430 | .DMC_TXC_Resp_Cmd (dMC_TXC_Resp_Cmd), | |
2431 | .DMC_TXC_Resp_Data_Length (dMC_TXC_Resp_Data_Length), | |
2432 | .DMC_TXC_Resp_ByteEnables (dMC_TXC_Resp_ByteEnables), | |
2433 | .DMC_TXC_Resp_Address (dMC_TXC_Resp_Address), | |
2434 | .DMC_TXC_Resp_Data (dMC_TXC_Resp_Data) | |
2435 | ); | |
2436 | ||
2437 | niu_txc_dataFetch niu_txc_dataFetch ( | |
2438 | .SysClk (niu_clk), | |
2439 | .Reset_L (reset_l), | |
2440 | .Txc_Enabled (txc_Enabled), | |
2441 | ||
2442 | .DMC_TXC_Tx_Addr_Md (dmc_txc_tx_addr_md), | |
2443 | .DMC_TXC_Req_Ack (arb1_txc_req_accept), | |
2444 | .TXC_DMC_Req (txc_arb1_req), | |
2445 | .TXC_DMC_Req_Cmd (txc_arb1_req_cmd), | |
2446 | .TXC_DMC_Req_Func_Num (txc_arb1_req_func_num), | |
2447 | .TXC_DMC_Req_Port_Num (txc_arb1_req_port_num), | |
2448 | .TXC_DMC_Req_DMA_Num (txc_arb1_req_dma_num), | |
2449 | .TXC_DMC_Req_Length (txc_arb1_req_length), | |
2450 | .TXC_DMC_Req_Address (txc_arb1_req_address), | |
2451 | ||
2452 | .Port_Selected (port_Selected), | |
2453 | ||
2454 | .Port0_Request (port0_Request), | |
2455 | .Port0_Request_Func_Num (port0_Request_Func_Num), | |
2456 | .Port0_Request_DMA_Num (port0_Request_DMA_Num), | |
2457 | .Port0_Request_Length (port0_Request_Length), | |
2458 | .Port0_Request_Address (port0_Request_Address), | |
2459 | .Port1_Request (port1_Request), | |
2460 | .Port1_Request_Func_Num (port1_Request_Func_Num), | |
2461 | .Port1_Request_DMA_Num (port1_Request_DMA_Num), | |
2462 | .Port1_Request_Length (port1_Request_Length), | |
2463 | .Port1_Request_Address (port1_Request_Address), | |
2464 | ||
2465 | `ifdef NEPTUNE | |
2466 | .Port2_Request (port2_Request), | |
2467 | .Port2_Request_Func_Num (port2_Request_Func_Num), | |
2468 | .Port2_Request_DMA_Num (port2_Request_DMA_Num), | |
2469 | .Port2_Request_Length (port2_Request_Length), | |
2470 | .Port2_Request_Address (port2_Request_Address), | |
2471 | .Port3_Request (port3_Request), | |
2472 | .Port3_Request_Func_Num (port3_Request_Func_Num), | |
2473 | .Port3_Request_DMA_Num (port3_Request_DMA_Num), | |
2474 | .Port3_Request_Length (port3_Request_Length), | |
2475 | .Port3_Request_Address (port3_Request_Address), | |
2476 | `else | |
2477 | .Port2_Request (1'h0), | |
2478 | .Port2_Request_Func_Num (2'h0), | |
2479 | .Port2_Request_DMA_Num (5'h0), | |
2480 | .Port2_Request_Length (13'h0), | |
2481 | .Port2_Request_Address (64'h0), | |
2482 | .Port3_Request (1'h0), | |
2483 | .Port3_Request_Func_Num (2'h0), | |
2484 | .Port3_Request_DMA_Num (5'h0), | |
2485 | .Port3_Request_Length (13'h0), | |
2486 | .Port3_Request_Address (64'h0), | |
2487 | `endif | |
2488 | ||
2489 | .PortSelect_State (portSelect_State), | |
2490 | .DataFetch_State (dataFetch_State) | |
2491 | ); | |
2492 | ||
2493 | ||
2494 | niu_txc_packetEngine #(REORDER_SIZE_10G,REORDER_PTR_10G) niu_txc_packetEngine0 ( | |
2495 | .SysClk (niu_clk), | |
2496 | .Reset_L (reset_l), | |
2497 | .PacketAssyDead (port0_PacketAssyDead), | |
2498 | .ReOrder_Error (port0_ReOrder_Error), | |
2499 | .Txc_Enabled (txc_Enabled), | |
2500 | .PortIndentifier (`PORT_ZERO), | |
2501 | .EnableGMACMode (1'b0), | |
2502 | .MAC_Enabled (port0_Enabled), | |
2503 | .FlushEngine (flushEngine), | |
2504 | ||
2505 | .MAC_Req (port0_mac_req), | |
2506 | .MAC_Ack (txc_mac_ack0), | |
2507 | .MAC_Tag (txc_mac_tag0), | |
2508 | .MAC_Status (txc_mac_stat0), | |
2509 | .MAC_Abort (txc_mac_abort0), | |
2510 | .MAC_Data (txc_mac_data0), | |
2511 | ||
2512 | .TidsInUse (port0_TidsInUse), | |
2513 | .DuplicateTid (port0_DuplicateTid), | |
2514 | .UnInitializedTID (port0_UnInitializedTID), | |
2515 | .TimedoutTids (port0_TimedoutTids), | |
2516 | .ReOrderStateLogic (port0_ReOrderStateLogic), | |
2517 | .ReOrderStateControl (port0_ReOrderStateControl), | |
2518 | .ReOrderStateData0 (port0_ReOrderStateData0), | |
2519 | .ReOrderStateData1 (port0_ReOrderStateData1), | |
2520 | .ReOrderStateData2 (port0_ReOrderStateData2), | |
2521 | .ReOrderStateData3 (port0_ReOrderStateData3), | |
2522 | .WrTidsInUse (port0_WrTidsInUse), | |
2523 | .WrDuplicateTid (port0_WrDuplicateTid), | |
2524 | .WrUnInitializedTID (port0_WrUnInitializedTID), | |
2525 | .WrTimedoutTids (port0_WrTimedoutTids), | |
2526 | .WrReOrderStateLogic (port0_WrReOrderStateLogic), | |
2527 | .WrReOrderStateControl (port0_WrReOrderStateControl), | |
2528 | .WrReOrderStateData0 (port0_WrReOrderStateData0), | |
2529 | .WrReOrderStateData1 (port0_WrReOrderStateData1), | |
2530 | .WrReOrderStateData2 (port0_WrReOrderStateData2), | |
2531 | .WrReOrderStateData3 (port0_WrReOrderStateData3), | |
2532 | .PioDataIn (port0_PioDataIn), | |
2533 | ||
2534 | .ClearStatistics (port0_ClearStatistics), | |
2535 | .WrPacketStuffed (port0_WrPacketStuffed), | |
2536 | .WrPacketXmitted (port0_WrPacketXmitted), | |
2537 | .WrPacketRequested (port0_WrPacketRequested), | |
2538 | .GatherRequestCount (port0_GatherRequestCount), | |
2539 | .PacketRequestCount (port0_PacketRequestCount), | |
2540 | .PktErrAbortCount (port0_PktErrAbortCount), | |
2541 | .ReOrdersStuffed (port0_ReOrdersStuffed), | |
2542 | .PacketsStuffed (port0_PacketsStuffed), | |
2543 | .PacketsTransmitted (port0_PacketsTransmitted), | |
2544 | .BytesTransmitted (port0_BytesTransmitted), | |
2545 | ||
2546 | .Pkt_Size_Err (txc_dmc_p0_pkt_size_err), | |
2547 | `ifdef NEPTUNE | |
2548 | .DMA_Pkt_Size_Err (txc_dmc_p0_dma_pkt_size_err), | |
2549 | `else | |
2550 | .DMA_Pkt_Size_Err ({dummy_txc_dmc_p0_dma_pkt_size_err, | |
2551 | txc_dmc_p0_dma_pkt_size_err}), | |
2552 | `endif | |
2553 | .Pkt_Size_Err_Addr (txc_dmc_p0_pkt_size_err_addr), | |
2554 | ||
2555 | .Nack_Pkt_Rd (port0_Nack_Pkt_Rd), | |
2556 | .DMA_Nack_Pkt_Rd (port0_DMA_Nack_Pkt_Rd), | |
2557 | .Nack_Pkt_Rd_Addr (port0_Nack_Pkt_Rd_Addr), | |
2558 | ||
2559 | .DMA0_Active (dmc_txc_dma0_active), | |
2560 | .DMA0_EofList (dmc_txc_dma0_eoflist), | |
2561 | .DMA0_Error (dmc_txc_dma0_error), | |
2562 | .DMA0_CacheReady (dmc_txc_dma0_cacheready), | |
2563 | .DMA0_Partial (dmc_txc_dma0_partial), | |
2564 | .DMA0_Reset_Scheduled (dmc_txc_dma0_reset_scheduled), | |
2565 | .DMA0_GotNxtDesc (dmc_txc_dma0_gotnxtdesc), | |
2566 | .DMA0_Mark (dmc_txc_dma0_descriptor[62]), | |
2567 | .DMA0_SOP (dmc_txc_dma0_descriptor[63]), | |
2568 | .DMA0_Func_Num (dmc_txc_dma0_func_num), | |
2569 | .DMA0_DescList (dmc_txc_dma0_descriptor[61:58]), | |
2570 | .DMA0_Length (dmc_txc_dma0_descriptor[56:44]), | |
2571 | .DMA0_PageHandle (dmc_txc_dma0_page_handle), | |
2572 | .DMA0_Address (dmc_txc_dma0_descriptor[43:0]), | |
2573 | .DMA0_Inc_Head (port0_DMA0_inc_head), | |
2574 | .DMA0_Reset_Done (port0_DMA0_reset_done), | |
2575 | .DMA0_Mark_Bit (port0_DMA0_mark_bit), | |
2576 | .DMA0_Inc_Pkt_Cnt (port0_DMA0_inc_pkt_cnt), | |
2577 | .SetGetNextDescDMA0 (port0_SetGetNextDescDMA0), | |
2578 | .DMA1_Active (dmc_txc_dma1_active), | |
2579 | .DMA1_EofList (dmc_txc_dma1_eoflist), | |
2580 | .DMA1_Error (dmc_txc_dma1_error), | |
2581 | .DMA1_CacheReady (dmc_txc_dma1_cacheready), | |
2582 | .DMA1_Partial (dmc_txc_dma1_partial), | |
2583 | .DMA1_Reset_Scheduled (dmc_txc_dma1_reset_scheduled), | |
2584 | .DMA1_GotNxtDesc (dmc_txc_dma1_gotnxtdesc), | |
2585 | .DMA1_Mark (dmc_txc_dma1_descriptor[62]), | |
2586 | .DMA1_SOP (dmc_txc_dma1_descriptor[63]), | |
2587 | .DMA1_Func_Num (dmc_txc_dma1_func_num), | |
2588 | .DMA1_DescList (dmc_txc_dma1_descriptor[61:58]), | |
2589 | .DMA1_Length (dmc_txc_dma1_descriptor[56:44]), | |
2590 | .DMA1_PageHandle (dmc_txc_dma1_page_handle), | |
2591 | .DMA1_Address (dmc_txc_dma1_descriptor[43:0]), | |
2592 | .DMA1_Inc_Head (port0_DMA1_inc_head), | |
2593 | .DMA1_Reset_Done (port0_DMA1_reset_done), | |
2594 | .DMA1_Mark_Bit (port0_DMA1_mark_bit), | |
2595 | .DMA1_Inc_Pkt_Cnt (port0_DMA1_inc_pkt_cnt), | |
2596 | .SetGetNextDescDMA1 (port0_SetGetNextDescDMA1), | |
2597 | .DMA2_Active (dmc_txc_dma2_active), | |
2598 | .DMA2_EofList (dmc_txc_dma2_eoflist), | |
2599 | .DMA2_Error (dmc_txc_dma2_error), | |
2600 | .DMA2_CacheReady (dmc_txc_dma2_cacheready), | |
2601 | .DMA2_Partial (dmc_txc_dma2_partial), | |
2602 | .DMA2_Reset_Scheduled (dmc_txc_dma2_reset_scheduled), | |
2603 | .DMA2_GotNxtDesc (dmc_txc_dma2_gotnxtdesc), | |
2604 | .DMA2_Mark (dmc_txc_dma2_descriptor[62]), | |
2605 | .DMA2_SOP (dmc_txc_dma2_descriptor[63]), | |
2606 | .DMA2_Func_Num (dmc_txc_dma2_func_num), | |
2607 | .DMA2_DescList (dmc_txc_dma2_descriptor[61:58]), | |
2608 | .DMA2_Length (dmc_txc_dma2_descriptor[56:44]), | |
2609 | .DMA2_PageHandle (dmc_txc_dma2_page_handle), | |
2610 | .DMA2_Address (dmc_txc_dma2_descriptor[43:0]), | |
2611 | .DMA2_Inc_Head (port0_DMA2_inc_head), | |
2612 | .DMA2_Reset_Done (port0_DMA2_reset_done), | |
2613 | .DMA2_Mark_Bit (port0_DMA2_mark_bit), | |
2614 | .DMA2_Inc_Pkt_Cnt (port0_DMA2_inc_pkt_cnt), | |
2615 | .SetGetNextDescDMA2 (port0_SetGetNextDescDMA2), | |
2616 | .DMA3_Active (dmc_txc_dma3_active), | |
2617 | .DMA3_EofList (dmc_txc_dma3_eoflist), | |
2618 | .DMA3_Error (dmc_txc_dma3_error), | |
2619 | .DMA3_CacheReady (dmc_txc_dma3_cacheready), | |
2620 | .DMA3_Partial (dmc_txc_dma3_partial), | |
2621 | .DMA3_Reset_Scheduled (dmc_txc_dma3_reset_scheduled), | |
2622 | .DMA3_GotNxtDesc (dmc_txc_dma3_gotnxtdesc), | |
2623 | .DMA3_Mark (dmc_txc_dma3_descriptor[62]), | |
2624 | .DMA3_SOP (dmc_txc_dma3_descriptor[63]), | |
2625 | .DMA3_Func_Num (dmc_txc_dma3_func_num), | |
2626 | .DMA3_DescList (dmc_txc_dma3_descriptor[61:58]), | |
2627 | .DMA3_Length (dmc_txc_dma3_descriptor[56:44]), | |
2628 | .DMA3_PageHandle (dmc_txc_dma3_page_handle), | |
2629 | .DMA3_Address (dmc_txc_dma3_descriptor[43:0]), | |
2630 | .DMA3_Inc_Head (port0_DMA3_inc_head), | |
2631 | .DMA3_Reset_Done (port0_DMA3_reset_done), | |
2632 | .DMA3_Mark_Bit (port0_DMA3_mark_bit), | |
2633 | .DMA3_Inc_Pkt_Cnt (port0_DMA3_inc_pkt_cnt), | |
2634 | .SetGetNextDescDMA3 (port0_SetGetNextDescDMA3), | |
2635 | .DMA4_Active (dmc_txc_dma4_active), | |
2636 | .DMA4_EofList (dmc_txc_dma4_eoflist), | |
2637 | .DMA4_Error (dmc_txc_dma4_error), | |
2638 | .DMA4_CacheReady (dmc_txc_dma4_cacheready), | |
2639 | .DMA4_Partial (dmc_txc_dma4_partial), | |
2640 | .DMA4_Reset_Scheduled (dmc_txc_dma4_reset_scheduled), | |
2641 | .DMA4_GotNxtDesc (dmc_txc_dma4_gotnxtdesc), | |
2642 | .DMA4_Mark (dmc_txc_dma4_descriptor[62]), | |
2643 | .DMA4_SOP (dmc_txc_dma4_descriptor[63]), | |
2644 | .DMA4_Func_Num (dmc_txc_dma4_func_num), | |
2645 | .DMA4_DescList (dmc_txc_dma4_descriptor[61:58]), | |
2646 | .DMA4_Length (dmc_txc_dma4_descriptor[56:44]), | |
2647 | .DMA4_PageHandle (dmc_txc_dma4_page_handle), | |
2648 | .DMA4_Address (dmc_txc_dma4_descriptor[43:0]), | |
2649 | .DMA4_Inc_Head (port0_DMA4_inc_head), | |
2650 | .DMA4_Reset_Done (port0_DMA4_reset_done), | |
2651 | .DMA4_Mark_Bit (port0_DMA4_mark_bit), | |
2652 | .DMA4_Inc_Pkt_Cnt (port0_DMA4_inc_pkt_cnt), | |
2653 | .SetGetNextDescDMA4 (port0_SetGetNextDescDMA4), | |
2654 | .DMA5_Active (dmc_txc_dma5_active), | |
2655 | .DMA5_EofList (dmc_txc_dma5_eoflist), | |
2656 | .DMA5_Error (dmc_txc_dma5_error), | |
2657 | .DMA5_CacheReady (dmc_txc_dma5_cacheready), | |
2658 | .DMA5_Partial (dmc_txc_dma5_partial), | |
2659 | .DMA5_Reset_Scheduled (dmc_txc_dma5_reset_scheduled), | |
2660 | .DMA5_GotNxtDesc (dmc_txc_dma5_gotnxtdesc), | |
2661 | .DMA5_Mark (dmc_txc_dma5_descriptor[62]), | |
2662 | .DMA5_SOP (dmc_txc_dma5_descriptor[63]), | |
2663 | .DMA5_Func_Num (dmc_txc_dma5_func_num), | |
2664 | .DMA5_DescList (dmc_txc_dma5_descriptor[61:58]), | |
2665 | .DMA5_Length (dmc_txc_dma5_descriptor[56:44]), | |
2666 | .DMA5_PageHandle (dmc_txc_dma5_page_handle), | |
2667 | .DMA5_Address (dmc_txc_dma5_descriptor[43:0]), | |
2668 | .DMA5_Inc_Head (port0_DMA5_inc_head), | |
2669 | .DMA5_Reset_Done (port0_DMA5_reset_done), | |
2670 | .DMA5_Mark_Bit (port0_DMA5_mark_bit), | |
2671 | .DMA5_Inc_Pkt_Cnt (port0_DMA5_inc_pkt_cnt), | |
2672 | .SetGetNextDescDMA5 (port0_SetGetNextDescDMA5), | |
2673 | .DMA6_Active (dmc_txc_dma6_active), | |
2674 | .DMA6_EofList (dmc_txc_dma6_eoflist), | |
2675 | .DMA6_Error (dmc_txc_dma6_error), | |
2676 | .DMA6_CacheReady (dmc_txc_dma6_cacheready), | |
2677 | .DMA6_Partial (dmc_txc_dma6_partial), | |
2678 | .DMA6_Reset_Scheduled (dmc_txc_dma6_reset_scheduled), | |
2679 | .DMA6_GotNxtDesc (dmc_txc_dma6_gotnxtdesc), | |
2680 | .DMA6_Mark (dmc_txc_dma6_descriptor[62]), | |
2681 | .DMA6_SOP (dmc_txc_dma6_descriptor[63]), | |
2682 | .DMA6_Func_Num (dmc_txc_dma6_func_num), | |
2683 | .DMA6_DescList (dmc_txc_dma6_descriptor[61:58]), | |
2684 | .DMA6_Length (dmc_txc_dma6_descriptor[56:44]), | |
2685 | .DMA6_PageHandle (dmc_txc_dma6_page_handle), | |
2686 | .DMA6_Address (dmc_txc_dma6_descriptor[43:0]), | |
2687 | .DMA6_Inc_Head (port0_DMA6_inc_head), | |
2688 | .DMA6_Reset_Done (port0_DMA6_reset_done), | |
2689 | .DMA6_Mark_Bit (port0_DMA6_mark_bit), | |
2690 | .DMA6_Inc_Pkt_Cnt (port0_DMA6_inc_pkt_cnt), | |
2691 | .SetGetNextDescDMA6 (port0_SetGetNextDescDMA6), | |
2692 | .DMA7_Active (dmc_txc_dma7_active), | |
2693 | .DMA7_EofList (dmc_txc_dma7_eoflist), | |
2694 | .DMA7_Error (dmc_txc_dma7_error), | |
2695 | .DMA7_CacheReady (dmc_txc_dma7_cacheready), | |
2696 | .DMA7_Partial (dmc_txc_dma7_partial), | |
2697 | .DMA7_Reset_Scheduled (dmc_txc_dma7_reset_scheduled), | |
2698 | .DMA7_GotNxtDesc (dmc_txc_dma7_gotnxtdesc), | |
2699 | .DMA7_Mark (dmc_txc_dma7_descriptor[62]), | |
2700 | .DMA7_SOP (dmc_txc_dma7_descriptor[63]), | |
2701 | .DMA7_Func_Num (dmc_txc_dma7_func_num), | |
2702 | .DMA7_DescList (dmc_txc_dma7_descriptor[61:58]), | |
2703 | .DMA7_Length (dmc_txc_dma7_descriptor[56:44]), | |
2704 | .DMA7_PageHandle (dmc_txc_dma7_page_handle), | |
2705 | .DMA7_Address (dmc_txc_dma7_descriptor[43:0]), | |
2706 | .DMA7_Inc_Head (port0_DMA7_inc_head), | |
2707 | .DMA7_Reset_Done (port0_DMA7_reset_done), | |
2708 | .DMA7_Mark_Bit (port0_DMA7_mark_bit), | |
2709 | .DMA7_Inc_Pkt_Cnt (port0_DMA7_inc_pkt_cnt), | |
2710 | .SetGetNextDescDMA7 (port0_SetGetNextDescDMA7), | |
2711 | .DMA8_Active (dmc_txc_dma8_active), | |
2712 | .DMA8_EofList (dmc_txc_dma8_eoflist), | |
2713 | .DMA8_Error (dmc_txc_dma8_error), | |
2714 | .DMA8_CacheReady (dmc_txc_dma8_cacheready), | |
2715 | .DMA8_Partial (dmc_txc_dma8_partial), | |
2716 | .DMA8_Reset_Scheduled (dmc_txc_dma8_reset_scheduled), | |
2717 | .DMA8_GotNxtDesc (dmc_txc_dma8_gotnxtdesc), | |
2718 | .DMA8_Mark (dmc_txc_dma8_descriptor[62]), | |
2719 | .DMA8_SOP (dmc_txc_dma8_descriptor[63]), | |
2720 | .DMA8_Func_Num (dmc_txc_dma8_func_num), | |
2721 | .DMA8_DescList (dmc_txc_dma8_descriptor[61:58]), | |
2722 | .DMA8_Length (dmc_txc_dma8_descriptor[56:44]), | |
2723 | .DMA8_PageHandle (dmc_txc_dma8_page_handle), | |
2724 | .DMA8_Address (dmc_txc_dma8_descriptor[43:0]), | |
2725 | .DMA8_Inc_Head (port0_DMA8_inc_head), | |
2726 | .DMA8_Reset_Done (port0_DMA8_reset_done), | |
2727 | .DMA8_Mark_Bit (port0_DMA8_mark_bit), | |
2728 | .DMA8_Inc_Pkt_Cnt (port0_DMA8_inc_pkt_cnt), | |
2729 | .SetGetNextDescDMA8 (port0_SetGetNextDescDMA8), | |
2730 | .DMA9_Active (dmc_txc_dma9_active), | |
2731 | .DMA9_EofList (dmc_txc_dma9_eoflist), | |
2732 | .DMA9_Error (dmc_txc_dma9_error), | |
2733 | .DMA9_CacheReady (dmc_txc_dma9_cacheready), | |
2734 | .DMA9_Partial (dmc_txc_dma9_partial), | |
2735 | .DMA9_Reset_Scheduled (dmc_txc_dma9_reset_scheduled), | |
2736 | .DMA9_GotNxtDesc (dmc_txc_dma9_gotnxtdesc), | |
2737 | .DMA9_Mark (dmc_txc_dma9_descriptor[62]), | |
2738 | .DMA9_SOP (dmc_txc_dma9_descriptor[63]), | |
2739 | .DMA9_Func_Num (dmc_txc_dma9_func_num), | |
2740 | .DMA9_DescList (dmc_txc_dma9_descriptor[61:58]), | |
2741 | .DMA9_Length (dmc_txc_dma9_descriptor[56:44]), | |
2742 | .DMA9_PageHandle (dmc_txc_dma9_page_handle), | |
2743 | .DMA9_Address (dmc_txc_dma9_descriptor[43:0]), | |
2744 | .DMA9_Inc_Head (port0_DMA9_inc_head), | |
2745 | .DMA9_Reset_Done (port0_DMA9_reset_done), | |
2746 | .DMA9_Mark_Bit (port0_DMA9_mark_bit), | |
2747 | .DMA9_Inc_Pkt_Cnt (port0_DMA9_inc_pkt_cnt), | |
2748 | .SetGetNextDescDMA9 (port0_SetGetNextDescDMA9), | |
2749 | .DMA10_Active (dmc_txc_dma10_active), | |
2750 | .DMA10_EofList (dmc_txc_dma10_eoflist), | |
2751 | .DMA10_Error (dmc_txc_dma10_error), | |
2752 | .DMA10_CacheReady (dmc_txc_dma10_cacheready), | |
2753 | .DMA10_Partial (dmc_txc_dma10_partial), | |
2754 | .DMA10_Reset_Scheduled (dmc_txc_dma10_reset_scheduled), | |
2755 | .DMA10_GotNxtDesc (dmc_txc_dma10_gotnxtdesc), | |
2756 | .DMA10_Mark (dmc_txc_dma10_descriptor[62]), | |
2757 | .DMA10_SOP (dmc_txc_dma10_descriptor[63]), | |
2758 | .DMA10_Func_Num (dmc_txc_dma10_func_num), | |
2759 | .DMA10_DescList (dmc_txc_dma10_descriptor[61:58]), | |
2760 | .DMA10_Length (dmc_txc_dma10_descriptor[56:44]), | |
2761 | .DMA10_PageHandle (dmc_txc_dma10_page_handle), | |
2762 | .DMA10_Address (dmc_txc_dma10_descriptor[43:0]), | |
2763 | .DMA10_Inc_Head (port0_DMA10_inc_head), | |
2764 | .DMA10_Reset_Done (port0_DMA10_reset_done), | |
2765 | .DMA10_Mark_Bit (port0_DMA10_mark_bit), | |
2766 | .DMA10_Inc_Pkt_Cnt (port0_DMA10_inc_pkt_cnt), | |
2767 | .SetGetNextDescDMA10 (port0_SetGetNextDescDMA10), | |
2768 | .DMA11_Active (dmc_txc_dma11_active), | |
2769 | .DMA11_EofList (dmc_txc_dma11_eoflist), | |
2770 | .DMA11_Error (dmc_txc_dma11_error), | |
2771 | .DMA11_CacheReady (dmc_txc_dma11_cacheready), | |
2772 | .DMA11_Partial (dmc_txc_dma11_partial), | |
2773 | .DMA11_Reset_Scheduled (dmc_txc_dma11_reset_scheduled), | |
2774 | .DMA11_GotNxtDesc (dmc_txc_dma11_gotnxtdesc), | |
2775 | .DMA11_Mark (dmc_txc_dma11_descriptor[62]), | |
2776 | .DMA11_SOP (dmc_txc_dma11_descriptor[63]), | |
2777 | .DMA11_Func_Num (dmc_txc_dma11_func_num), | |
2778 | .DMA11_DescList (dmc_txc_dma11_descriptor[61:58]), | |
2779 | .DMA11_Length (dmc_txc_dma11_descriptor[56:44]), | |
2780 | .DMA11_PageHandle (dmc_txc_dma11_page_handle), | |
2781 | .DMA11_Address (dmc_txc_dma11_descriptor[43:0]), | |
2782 | .DMA11_Inc_Head (port0_DMA11_inc_head), | |
2783 | .DMA11_Reset_Done (port0_DMA11_reset_done), | |
2784 | .DMA11_Mark_Bit (port0_DMA11_mark_bit), | |
2785 | .DMA11_Inc_Pkt_Cnt (port0_DMA11_inc_pkt_cnt), | |
2786 | .SetGetNextDescDMA11 (port0_SetGetNextDescDMA11), | |
2787 | .DMA12_Active (dmc_txc_dma12_active), | |
2788 | .DMA12_EofList (dmc_txc_dma12_eoflist), | |
2789 | .DMA12_Error (dmc_txc_dma12_error), | |
2790 | .DMA12_CacheReady (dmc_txc_dma12_cacheready), | |
2791 | .DMA12_Partial (dmc_txc_dma12_partial), | |
2792 | .DMA12_Reset_Scheduled (dmc_txc_dma12_reset_scheduled), | |
2793 | .DMA12_GotNxtDesc (dmc_txc_dma12_gotnxtdesc), | |
2794 | .DMA12_Mark (dmc_txc_dma12_descriptor[62]), | |
2795 | .DMA12_SOP (dmc_txc_dma12_descriptor[63]), | |
2796 | .DMA12_Func_Num (dmc_txc_dma12_func_num), | |
2797 | .DMA12_DescList (dmc_txc_dma12_descriptor[61:58]), | |
2798 | .DMA12_Length (dmc_txc_dma12_descriptor[56:44]), | |
2799 | .DMA12_PageHandle (dmc_txc_dma12_page_handle), | |
2800 | .DMA12_Address (dmc_txc_dma12_descriptor[43:0]), | |
2801 | .DMA12_Inc_Head (port0_DMA12_inc_head), | |
2802 | .DMA12_Reset_Done (port0_DMA12_reset_done), | |
2803 | .DMA12_Mark_Bit (port0_DMA12_mark_bit), | |
2804 | .DMA12_Inc_Pkt_Cnt (port0_DMA12_inc_pkt_cnt), | |
2805 | .SetGetNextDescDMA12 (port0_SetGetNextDescDMA12), | |
2806 | .DMA13_Active (dmc_txc_dma13_active), | |
2807 | .DMA13_EofList (dmc_txc_dma13_eoflist), | |
2808 | .DMA13_Error (dmc_txc_dma13_error), | |
2809 | .DMA13_CacheReady (dmc_txc_dma13_cacheready), | |
2810 | .DMA13_Partial (dmc_txc_dma13_partial), | |
2811 | .DMA13_Reset_Scheduled (dmc_txc_dma13_reset_scheduled), | |
2812 | .DMA13_GotNxtDesc (dmc_txc_dma13_gotnxtdesc), | |
2813 | .DMA13_Mark (dmc_txc_dma13_descriptor[62]), | |
2814 | .DMA13_SOP (dmc_txc_dma13_descriptor[63]), | |
2815 | .DMA13_Func_Num (dmc_txc_dma13_func_num), | |
2816 | .DMA13_DescList (dmc_txc_dma13_descriptor[61:58]), | |
2817 | .DMA13_Length (dmc_txc_dma13_descriptor[56:44]), | |
2818 | .DMA13_PageHandle (dmc_txc_dma13_page_handle), | |
2819 | .DMA13_Address (dmc_txc_dma13_descriptor[43:0]), | |
2820 | .DMA13_Inc_Head (port0_DMA13_inc_head), | |
2821 | .DMA13_Reset_Done (port0_DMA13_reset_done), | |
2822 | .DMA13_Mark_Bit (port0_DMA13_mark_bit), | |
2823 | .DMA13_Inc_Pkt_Cnt (port0_DMA13_inc_pkt_cnt), | |
2824 | .SetGetNextDescDMA13 (port0_SetGetNextDescDMA13), | |
2825 | .DMA14_Active (dmc_txc_dma14_active), | |
2826 | .DMA14_EofList (dmc_txc_dma14_eoflist), | |
2827 | .DMA14_Error (dmc_txc_dma14_error), | |
2828 | .DMA14_CacheReady (dmc_txc_dma14_cacheready), | |
2829 | .DMA14_Partial (dmc_txc_dma14_partial), | |
2830 | .DMA14_Reset_Scheduled (dmc_txc_dma14_reset_scheduled), | |
2831 | .DMA14_GotNxtDesc (dmc_txc_dma14_gotnxtdesc), | |
2832 | .DMA14_Mark (dmc_txc_dma14_descriptor[62]), | |
2833 | .DMA14_SOP (dmc_txc_dma14_descriptor[63]), | |
2834 | .DMA14_Func_Num (dmc_txc_dma14_func_num), | |
2835 | .DMA14_DescList (dmc_txc_dma14_descriptor[61:58]), | |
2836 | .DMA14_Length (dmc_txc_dma14_descriptor[56:44]), | |
2837 | .DMA14_PageHandle (dmc_txc_dma14_page_handle), | |
2838 | .DMA14_Address (dmc_txc_dma14_descriptor[43:0]), | |
2839 | .DMA14_Inc_Head (port0_DMA14_inc_head), | |
2840 | .DMA14_Reset_Done (port0_DMA14_reset_done), | |
2841 | .DMA14_Mark_Bit (port0_DMA14_mark_bit), | |
2842 | .DMA14_Inc_Pkt_Cnt (port0_DMA14_inc_pkt_cnt), | |
2843 | .SetGetNextDescDMA14 (port0_SetGetNextDescDMA14), | |
2844 | .DMA15_Active (dmc_txc_dma15_active), | |
2845 | .DMA15_EofList (dmc_txc_dma15_eoflist), | |
2846 | .DMA15_Error (dmc_txc_dma15_error), | |
2847 | .DMA15_CacheReady (dmc_txc_dma15_cacheready), | |
2848 | .DMA15_Partial (dmc_txc_dma15_partial), | |
2849 | .DMA15_Reset_Scheduled (dmc_txc_dma15_reset_scheduled), | |
2850 | .DMA15_GotNxtDesc (dmc_txc_dma15_gotnxtdesc), | |
2851 | .DMA15_Mark (dmc_txc_dma15_descriptor[62]), | |
2852 | .DMA15_SOP (dmc_txc_dma15_descriptor[63]), | |
2853 | .DMA15_Func_Num (dmc_txc_dma15_func_num), | |
2854 | .DMA15_DescList (dmc_txc_dma15_descriptor[61:58]), | |
2855 | .DMA15_Length (dmc_txc_dma15_descriptor[56:44]), | |
2856 | .DMA15_PageHandle (dmc_txc_dma15_page_handle), | |
2857 | .DMA15_Address (dmc_txc_dma15_descriptor[43:0]), | |
2858 | .DMA15_Inc_Head (port0_DMA15_inc_head), | |
2859 | .DMA15_Reset_Done (port0_DMA15_reset_done), | |
2860 | .DMA15_Mark_Bit (port0_DMA15_mark_bit), | |
2861 | .DMA15_Inc_Pkt_Cnt (port0_DMA15_inc_pkt_cnt), | |
2862 | .SetGetNextDescDMA15 (port0_SetGetNextDescDMA15), | |
2863 | .DMA16_Active (dmc_txc_dma16_active), | |
2864 | .DMA16_EofList (dmc_txc_dma16_eoflist), | |
2865 | .DMA16_Error (dmc_txc_dma16_error), | |
2866 | .DMA16_CacheReady (dmc_txc_dma16_cacheready), | |
2867 | .DMA16_Partial (dmc_txc_dma16_partial), | |
2868 | .DMA16_Reset_Scheduled (dmc_txc_dma16_reset_scheduled), | |
2869 | .DMA16_GotNxtDesc (dmc_txc_dma16_gotnxtdesc), | |
2870 | .DMA16_Mark (dmc_txc_dma16_descriptor[62]), | |
2871 | .DMA16_SOP (dmc_txc_dma16_descriptor[63]), | |
2872 | .DMA16_Func_Num (dmc_txc_dma16_func_num), | |
2873 | .DMA16_DescList (dmc_txc_dma16_descriptor[61:58]), | |
2874 | .DMA16_Length (dmc_txc_dma16_descriptor[56:44]), | |
2875 | .DMA16_PageHandle (dmc_txc_dma16_page_handle), | |
2876 | .DMA16_Address (dmc_txc_dma16_descriptor[43:0]), | |
2877 | .DMA16_Inc_Head (port0_DMA16_inc_head), | |
2878 | .DMA16_Reset_Done (port0_DMA16_reset_done), | |
2879 | .DMA16_Mark_Bit (port0_DMA16_mark_bit), | |
2880 | .DMA16_Inc_Pkt_Cnt (port0_DMA16_inc_pkt_cnt), | |
2881 | .SetGetNextDescDMA16 (port0_SetGetNextDescDMA16), | |
2882 | .DMA17_Active (dmc_txc_dma17_active), | |
2883 | .DMA17_EofList (dmc_txc_dma17_eoflist), | |
2884 | .DMA17_Error (dmc_txc_dma17_error), | |
2885 | .DMA17_CacheReady (dmc_txc_dma17_cacheready), | |
2886 | .DMA17_Partial (dmc_txc_dma17_partial), | |
2887 | .DMA17_Reset_Scheduled (dmc_txc_dma17_reset_scheduled), | |
2888 | .DMA17_GotNxtDesc (dmc_txc_dma17_gotnxtdesc), | |
2889 | .DMA17_Mark (dmc_txc_dma17_descriptor[62]), | |
2890 | .DMA17_SOP (dmc_txc_dma17_descriptor[63]), | |
2891 | .DMA17_Func_Num (dmc_txc_dma17_func_num), | |
2892 | .DMA17_DescList (dmc_txc_dma17_descriptor[61:58]), | |
2893 | .DMA17_Length (dmc_txc_dma17_descriptor[56:44]), | |
2894 | .DMA17_PageHandle (dmc_txc_dma17_page_handle), | |
2895 | .DMA17_Address (dmc_txc_dma17_descriptor[43:0]), | |
2896 | .DMA17_Inc_Head (port0_DMA17_inc_head), | |
2897 | .DMA17_Reset_Done (port0_DMA17_reset_done), | |
2898 | .DMA17_Mark_Bit (port0_DMA17_mark_bit), | |
2899 | .DMA17_Inc_Pkt_Cnt (port0_DMA17_inc_pkt_cnt), | |
2900 | .SetGetNextDescDMA17 (port0_SetGetNextDescDMA17), | |
2901 | .DMA18_Active (dmc_txc_dma18_active), | |
2902 | .DMA18_EofList (dmc_txc_dma18_eoflist), | |
2903 | .DMA18_Error (dmc_txc_dma18_error), | |
2904 | .DMA18_CacheReady (dmc_txc_dma18_cacheready), | |
2905 | .DMA18_Partial (dmc_txc_dma18_partial), | |
2906 | .DMA18_Reset_Scheduled (dmc_txc_dma18_reset_scheduled), | |
2907 | .DMA18_GotNxtDesc (dmc_txc_dma18_gotnxtdesc), | |
2908 | .DMA18_Mark (dmc_txc_dma18_descriptor[62]), | |
2909 | .DMA18_SOP (dmc_txc_dma18_descriptor[63]), | |
2910 | .DMA18_Func_Num (dmc_txc_dma18_func_num), | |
2911 | .DMA18_DescList (dmc_txc_dma18_descriptor[61:58]), | |
2912 | .DMA18_Length (dmc_txc_dma18_descriptor[56:44]), | |
2913 | .DMA18_PageHandle (dmc_txc_dma18_page_handle), | |
2914 | .DMA18_Address (dmc_txc_dma18_descriptor[43:0]), | |
2915 | .DMA18_Inc_Head (port0_DMA18_inc_head), | |
2916 | .DMA18_Reset_Done (port0_DMA18_reset_done), | |
2917 | .DMA18_Mark_Bit (port0_DMA18_mark_bit), | |
2918 | .DMA18_Inc_Pkt_Cnt (port0_DMA18_inc_pkt_cnt), | |
2919 | .SetGetNextDescDMA18 (port0_SetGetNextDescDMA18), | |
2920 | .DMA19_Active (dmc_txc_dma19_active), | |
2921 | .DMA19_EofList (dmc_txc_dma19_eoflist), | |
2922 | .DMA19_Error (dmc_txc_dma19_error), | |
2923 | .DMA19_CacheReady (dmc_txc_dma19_cacheready), | |
2924 | .DMA19_Partial (dmc_txc_dma19_partial), | |
2925 | .DMA19_Reset_Scheduled (dmc_txc_dma19_reset_scheduled), | |
2926 | .DMA19_GotNxtDesc (dmc_txc_dma19_gotnxtdesc), | |
2927 | .DMA19_Mark (dmc_txc_dma19_descriptor[62]), | |
2928 | .DMA19_SOP (dmc_txc_dma19_descriptor[63]), | |
2929 | .DMA19_Func_Num (dmc_txc_dma19_func_num), | |
2930 | .DMA19_DescList (dmc_txc_dma19_descriptor[61:58]), | |
2931 | .DMA19_Length (dmc_txc_dma19_descriptor[56:44]), | |
2932 | .DMA19_PageHandle (dmc_txc_dma19_page_handle), | |
2933 | .DMA19_Address (dmc_txc_dma19_descriptor[43:0]), | |
2934 | .DMA19_Inc_Head (port0_DMA19_inc_head), | |
2935 | .DMA19_Reset_Done (port0_DMA19_reset_done), | |
2936 | .DMA19_Mark_Bit (port0_DMA19_mark_bit), | |
2937 | .DMA19_Inc_Pkt_Cnt (port0_DMA19_inc_pkt_cnt), | |
2938 | .SetGetNextDescDMA19 (port0_SetGetNextDescDMA19), | |
2939 | .DMA20_Active (dmc_txc_dma20_active), | |
2940 | .DMA20_EofList (dmc_txc_dma20_eoflist), | |
2941 | .DMA20_Error (dmc_txc_dma20_error), | |
2942 | .DMA20_CacheReady (dmc_txc_dma20_cacheready), | |
2943 | .DMA20_Partial (dmc_txc_dma20_partial), | |
2944 | .DMA20_Reset_Scheduled (dmc_txc_dma20_reset_scheduled), | |
2945 | .DMA20_GotNxtDesc (dmc_txc_dma20_gotnxtdesc), | |
2946 | .DMA20_Mark (dmc_txc_dma20_descriptor[62]), | |
2947 | .DMA20_SOP (dmc_txc_dma20_descriptor[63]), | |
2948 | .DMA20_Func_Num (dmc_txc_dma20_func_num), | |
2949 | .DMA20_DescList (dmc_txc_dma20_descriptor[61:58]), | |
2950 | .DMA20_Length (dmc_txc_dma20_descriptor[56:44]), | |
2951 | .DMA20_PageHandle (dmc_txc_dma20_page_handle), | |
2952 | .DMA20_Address (dmc_txc_dma20_descriptor[43:0]), | |
2953 | .DMA20_Inc_Head (port0_DMA20_inc_head), | |
2954 | .DMA20_Reset_Done (port0_DMA20_reset_done), | |
2955 | .DMA20_Mark_Bit (port0_DMA20_mark_bit), | |
2956 | .DMA20_Inc_Pkt_Cnt (port0_DMA20_inc_pkt_cnt), | |
2957 | .SetGetNextDescDMA20 (port0_SetGetNextDescDMA20), | |
2958 | .DMA21_Active (dmc_txc_dma21_active), | |
2959 | .DMA21_EofList (dmc_txc_dma21_eoflist), | |
2960 | .DMA21_Error (dmc_txc_dma21_error), | |
2961 | .DMA21_CacheReady (dmc_txc_dma21_cacheready), | |
2962 | .DMA21_Partial (dmc_txc_dma21_partial), | |
2963 | .DMA21_Reset_Scheduled (dmc_txc_dma21_reset_scheduled), | |
2964 | .DMA21_GotNxtDesc (dmc_txc_dma21_gotnxtdesc), | |
2965 | .DMA21_Mark (dmc_txc_dma21_descriptor[62]), | |
2966 | .DMA21_SOP (dmc_txc_dma21_descriptor[63]), | |
2967 | .DMA21_Func_Num (dmc_txc_dma21_func_num), | |
2968 | .DMA21_DescList (dmc_txc_dma21_descriptor[61:58]), | |
2969 | .DMA21_Length (dmc_txc_dma21_descriptor[56:44]), | |
2970 | .DMA21_PageHandle (dmc_txc_dma21_page_handle), | |
2971 | .DMA21_Address (dmc_txc_dma21_descriptor[43:0]), | |
2972 | .DMA21_Inc_Head (port0_DMA21_inc_head), | |
2973 | .DMA21_Reset_Done (port0_DMA21_reset_done), | |
2974 | .DMA21_Mark_Bit (port0_DMA21_mark_bit), | |
2975 | .DMA21_Inc_Pkt_Cnt (port0_DMA21_inc_pkt_cnt), | |
2976 | .SetGetNextDescDMA21 (port0_SetGetNextDescDMA21), | |
2977 | .DMA22_Active (dmc_txc_dma22_active), | |
2978 | .DMA22_EofList (dmc_txc_dma22_eoflist), | |
2979 | .DMA22_Error (dmc_txc_dma22_error), | |
2980 | .DMA22_CacheReady (dmc_txc_dma22_cacheready), | |
2981 | .DMA22_Partial (dmc_txc_dma22_partial), | |
2982 | .DMA22_Reset_Scheduled (dmc_txc_dma22_reset_scheduled), | |
2983 | .DMA22_GotNxtDesc (dmc_txc_dma22_gotnxtdesc), | |
2984 | .DMA22_Mark (dmc_txc_dma22_descriptor[62]), | |
2985 | .DMA22_SOP (dmc_txc_dma22_descriptor[63]), | |
2986 | .DMA22_Func_Num (dmc_txc_dma22_func_num), | |
2987 | .DMA22_DescList (dmc_txc_dma22_descriptor[61:58]), | |
2988 | .DMA22_Length (dmc_txc_dma22_descriptor[56:44]), | |
2989 | .DMA22_PageHandle (dmc_txc_dma22_page_handle), | |
2990 | .DMA22_Address (dmc_txc_dma22_descriptor[43:0]), | |
2991 | .DMA22_Inc_Head (port0_DMA22_inc_head), | |
2992 | .DMA22_Reset_Done (port0_DMA22_reset_done), | |
2993 | .DMA22_Mark_Bit (port0_DMA22_mark_bit), | |
2994 | .DMA22_Inc_Pkt_Cnt (port0_DMA22_inc_pkt_cnt), | |
2995 | .SetGetNextDescDMA22 (port0_SetGetNextDescDMA22), | |
2996 | .DMA23_Active (dmc_txc_dma23_active), | |
2997 | .DMA23_EofList (dmc_txc_dma23_eoflist), | |
2998 | .DMA23_Error (dmc_txc_dma23_error), | |
2999 | .DMA23_CacheReady (dmc_txc_dma23_cacheready), | |
3000 | .DMA23_Partial (dmc_txc_dma23_partial), | |
3001 | .DMA23_Reset_Scheduled (dmc_txc_dma23_reset_scheduled), | |
3002 | .DMA23_GotNxtDesc (dmc_txc_dma23_gotnxtdesc), | |
3003 | .DMA23_Mark (dmc_txc_dma23_descriptor[62]), | |
3004 | .DMA23_SOP (dmc_txc_dma23_descriptor[63]), | |
3005 | .DMA23_Func_Num (dmc_txc_dma23_func_num), | |
3006 | .DMA23_DescList (dmc_txc_dma23_descriptor[61:58]), | |
3007 | .DMA23_Length (dmc_txc_dma23_descriptor[56:44]), | |
3008 | .DMA23_PageHandle (dmc_txc_dma23_page_handle), | |
3009 | .DMA23_Address (dmc_txc_dma23_descriptor[43:0]), | |
3010 | .DMA23_Inc_Head (port0_DMA23_inc_head), | |
3011 | .DMA23_Reset_Done (port0_DMA23_reset_done), | |
3012 | .DMA23_Mark_Bit (port0_DMA23_mark_bit), | |
3013 | .DMA23_Inc_Pkt_Cnt (port0_DMA23_inc_pkt_cnt), | |
3014 | .SetGetNextDescDMA23 (port0_SetGetNextDescDMA23), | |
3015 | ||
3016 | .DMA0_NewMaxBurst (dma0_NewMaxBurst), | |
3017 | .DMA1_NewMaxBurst (dma1_NewMaxBurst), | |
3018 | .DMA2_NewMaxBurst (dma2_NewMaxBurst), | |
3019 | .DMA3_NewMaxBurst (dma3_NewMaxBurst), | |
3020 | .DMA4_NewMaxBurst (dma4_NewMaxBurst), | |
3021 | .DMA5_NewMaxBurst (dma5_NewMaxBurst), | |
3022 | .DMA6_NewMaxBurst (dma6_NewMaxBurst), | |
3023 | .DMA7_NewMaxBurst (dma7_NewMaxBurst), | |
3024 | .DMA8_NewMaxBurst (dma8_NewMaxBurst), | |
3025 | .DMA9_NewMaxBurst (dma9_NewMaxBurst), | |
3026 | .DMA10_NewMaxBurst (dma10_NewMaxBurst), | |
3027 | .DMA11_NewMaxBurst (dma11_NewMaxBurst), | |
3028 | .DMA12_NewMaxBurst (dma12_NewMaxBurst), | |
3029 | .DMA13_NewMaxBurst (dma13_NewMaxBurst), | |
3030 | .DMA14_NewMaxBurst (dma14_NewMaxBurst), | |
3031 | .DMA15_NewMaxBurst (dma15_NewMaxBurst), | |
3032 | .DMA16_NewMaxBurst (dma16_NewMaxBurst), | |
3033 | .DMA17_NewMaxBurst (dma17_NewMaxBurst), | |
3034 | .DMA18_NewMaxBurst (dma18_NewMaxBurst), | |
3035 | .DMA19_NewMaxBurst (dma19_NewMaxBurst), | |
3036 | .DMA20_NewMaxBurst (dma20_NewMaxBurst), | |
3037 | .DMA21_NewMaxBurst (dma21_NewMaxBurst), | |
3038 | .DMA22_NewMaxBurst (dma22_NewMaxBurst), | |
3039 | .DMA23_NewMaxBurst (dma23_NewMaxBurst), | |
3040 | .DMA0_MaxBurst (dma0_MaxBurst), | |
3041 | .DMA1_MaxBurst (dma1_MaxBurst), | |
3042 | .DMA2_MaxBurst (dma2_MaxBurst), | |
3043 | .DMA3_MaxBurst (dma3_MaxBurst), | |
3044 | .DMA4_MaxBurst (dma4_MaxBurst), | |
3045 | .DMA5_MaxBurst (dma5_MaxBurst), | |
3046 | .DMA6_MaxBurst (dma6_MaxBurst), | |
3047 | .DMA7_MaxBurst (dma7_MaxBurst), | |
3048 | .DMA8_MaxBurst (dma8_MaxBurst), | |
3049 | .DMA9_MaxBurst (dma9_MaxBurst), | |
3050 | .DMA10_MaxBurst (dma10_MaxBurst), | |
3051 | .DMA11_MaxBurst (dma11_MaxBurst), | |
3052 | .DMA12_MaxBurst (dma12_MaxBurst), | |
3053 | .DMA13_MaxBurst (dma13_MaxBurst), | |
3054 | .DMA14_MaxBurst (dma14_MaxBurst), | |
3055 | .DMA15_MaxBurst (dma15_MaxBurst), | |
3056 | .DMA16_MaxBurst (dma16_MaxBurst), | |
3057 | .DMA17_MaxBurst (dma17_MaxBurst), | |
3058 | .DMA18_MaxBurst (dma18_MaxBurst), | |
3059 | .DMA19_MaxBurst (dma19_MaxBurst), | |
3060 | .DMA20_MaxBurst (dma20_MaxBurst), | |
3061 | .DMA21_MaxBurst (dma21_MaxBurst), | |
3062 | .DMA22_MaxBurst (dma22_MaxBurst), | |
3063 | .DMA23_MaxBurst (dma23_MaxBurst), | |
3064 | .MaxReorderNumber (port0_MaxReorderNumber), | |
3065 | .Port_DMA_List (port0_DMA_List), | |
3066 | .ClrMaxBurst (port0_clrMaxBurst), | |
3067 | .UpdateDMA (port0_UpdateDMA), | |
3068 | .UpdateDMALength (port0_UpdateDMALength), | |
3069 | .UpdateDMANumber (port0_UpdateDMANumber), | |
3070 | ||
3071 | .DMC_TXC_Req_Ack (arb1_txc_req_accept), | |
3072 | .DMC_TXC_Req_TransID (arb1_txc_req_transid), | |
3073 | ||
3074 | .Port_Selected (port_Selected[0]), | |
3075 | .Port_Request (port0_Request), | |
3076 | .Port_Request_Func_Num (port0_Request_Func_Num), | |
3077 | .Port_Request_DMA_Num (port0_Request_DMA_Num), | |
3078 | .Port_Request_Length (port0_Request_Length), | |
3079 | .Port_Request_Address (port0_Request_Address), | |
3080 | ||
3081 | .DMC_TXC_Resp_Rdy (dMC_TXC_Resp_Rdy), | |
3082 | .DMC_TXC_Resp_Complete (dMC_TXC_Resp_Complete), | |
3083 | .DMC_TXC_Trans_Complete (dMC_TXC_Trans_Complete), | |
3084 | .DMC_TXC_Resp_Data_Valid (dMC_TXC_Resp_Data_Valid), | |
3085 | .DMC_TXC_Resp_Client (dMC_TXC_Resp_Client), | |
3086 | .DMC_TXC_Resp_Port_Num (dMC_TXC_Resp_Port_Num), | |
3087 | .DMC_TXC_Resp_Cmd_Status (dMC_TXC_Resp_Cmd_Status), | |
3088 | .DMC_TXC_Resp_Data_Status (dMC_TXC_Resp_Data_Status), | |
3089 | .DMC_TXC_Resp_DMA_Num (dMC_TXC_Resp_DMA_Num), | |
3090 | .DMC_TXC_Resp_TransID (dMC_TXC_Resp_TransID), | |
3091 | .DMC_TXC_Resp_Cmd (dMC_TXC_Resp_Cmd), | |
3092 | .DMC_TXC_Resp_Data_Length (dMC_TXC_Resp_Data_Length), | |
3093 | .DMC_TXC_Resp_ByteEnables (dMC_TXC_Resp_ByteEnables), | |
3094 | .DMC_TXC_Resp_Address (dMC_TXC_Resp_Address), | |
3095 | .DMC_TXC_Resp_Data (dMC_TXC_Resp_Data), | |
3096 | .TXC_DMC_Resp_Accept (port0_TXC_DMC_Resp_Accept), | |
3097 | ||
3098 | .ReOrderFifoDataValid (port0_ReOrderFifoDataValid), | |
3099 | .ReOrderUnCorrectError (port0_ReOrder_UnCorrectError), | |
3100 | .ReOrderEccControl (port0_ReOrderEccControl), | |
3101 | .PacketAssyEngineDataIn (port0_PacketAssyEngineDataIn), | |
3102 | .ReOrderCorruptECCSingle (port0_ReOrderCorruptECCSingle), | |
3103 | .ReOrderCorruptECCDouble (port0_ReOrderCorruptECCDouble), | |
3104 | .ReOrderFifoWrite (port0_ReOrderFifoWrite), | |
3105 | .ReOrderFifoReadStrobe (port0_ReOrderFifoRead), | |
3106 | .ReOrderWritePtr (port0_ReOrderWritePtr), | |
3107 | .ReOrderReadPtr (port0_ReOrderReadPtr), | |
3108 | .ReOrderEngineDataOut (port0_ReOrderEngineDataOut), | |
3109 | ||
3110 | .StoreForwardUnCorrectError (port0_StoreForward_UnCorrectError), | |
3111 | .StoreForwardEccControl (port0_StoreForwardEccControl), | |
3112 | .MacXferEngineDataIn (port0_MacXferEngineDataIn), | |
3113 | .StoreForward_CorruptECCSingle (port0_StoreForwardCorruptECCSingle), | |
3114 | .StoreForward_CorruptECCDouble (port0_StoreForwardCorruptECCDouble), | |
3115 | .StoreForwardFifoWrite (port0_StoreForwardFifoWrite), | |
3116 | .StoreForwardFifoReadStrobe (port0_StoreForwardFifoRead), | |
3117 | .StoreForwardWritePtr (port0_StoreForwardWritePtr), | |
3118 | .StoreForwardReadPtr (port0_StoreForwardReadPtr), | |
3119 | .PacketAssyEngineDataOut (port0_PacketAssyEngineDataOut), | |
3120 | ||
3121 | .LatchActiveDMA (port0_LatchActiveDMA), | |
3122 | .ContextActiveList (port0_ContextActiveList), | |
3123 | ||
3124 | .Anchor_State (port0_Anchor_State), | |
3125 | .ReOrder_State (port0_ReOrder_State), | |
3126 | .Pointer_State (port0_Pointer_State), | |
3127 | .PacketAssy_State (port0_PacketAssy_State), | |
3128 | .DRR_ArbState (port0_DRR_ArbState), | |
3129 | .Mac_Xfer_State (port0_Mac_Xfer_State), | |
3130 | .DataPortReq_State (port0_DataPortReq_State), | |
3131 | .Sum_prt_state (port0_Sum_prt_state) | |
3132 | ); | |
3133 | ||
3134 | ||
3135 | niu_txc_ecc_engine port0_niu_txc_ecc_engine ( | |
3136 | .SysClk (niu_clk), | |
3137 | .Reset_L (reset_l), | |
3138 | .ReOrder_ClearEccError (port0_ReOrder_ClearEccError), | |
3139 | .WrReOrderEccState (port0_WrReOrderEccState), | |
3140 | .WrReOrderEccData0 (port0_WrReOrderEccData0), | |
3141 | .WrReOrderEccData1 (port0_WrReOrderEccData1), | |
3142 | .WrReOrderEccData2 (port0_WrReOrderEccData2), | |
3143 | .WrReOrderEccData3 (port0_WrReOrderEccData3), | |
3144 | .WrReOrderEccData4 (port0_WrReOrderEccData4), | |
3145 | .StoreForward_ClearEccError (port0_StoreForward_ClearEccError), | |
3146 | .WrStoreForwardEccState (port0_WrStoreForwardEccState), | |
3147 | .WrStoreForwardEccData0 (port0_WrStoreForwardEccData0), | |
3148 | .WrStoreForwardEccData1 (port0_WrStoreForwardEccData1), | |
3149 | .WrStoreForwardEccData2 (port0_WrStoreForwardEccData2), | |
3150 | .WrStoreForwardEccData3 (port0_WrStoreForwardEccData3), | |
3151 | .WrStoreForwardEccData4 (port0_WrStoreForwardEccData4), | |
3152 | .PioDataIn (port0_PioDataIn), | |
3153 | .ReOrder_ECC_State (port0_ReOrder_ECC_State), | |
3154 | .ReOrder_EccData (port0_ReOrder_EccData), | |
3155 | .StoreForward_ECC_State (port0_StoreForward_ECC_State), | |
3156 | .StoreForward_EccData (port0_StoreForward_EccData), | |
3157 | .ReOrder_CorruptECCSingle (port0_ReOrderCorruptECCSingle), | |
3158 | .ReOrder_CorruptECCDouble (port0_ReOrderCorruptECCDouble), | |
3159 | .ReOrder_FifoRead (port0_ReOrderFifoRead), | |
3160 | .ReOrder_ReadPtr (port0_ReOrderReadPtr), | |
3161 | .ReOrder_FifoDataOut (port0_ReOrderFifoDataOut), | |
3162 | .ReOrder_FifoDataValid (port0_ReOrderFifoDataValid), | |
3163 | .ReOrder_UnCorrectError (port0_ReOrder_UnCorrectError), | |
3164 | .ReOrder_PreECCData (port0_ReOrderEngineDataOut), | |
3165 | .ReOrder_PostECCData (port0_ReOrderFifoDataIn), | |
3166 | .ReOrder_CorrectedData (port0_PacketAssyEngineDataIn), | |
3167 | .StoreForward_CorruptECCSingle (port0_StoreForwardCorruptECCSingle), | |
3168 | .StoreForward_CorruptECCDouble (port0_StoreForwardCorruptECCDouble), | |
3169 | .StoreForward_FifoRead (port0_StoreForwardFifoRead), | |
3170 | .StoreForward_ReadPtr (port0_StoreForwardReadPtr), | |
3171 | .StoreForward_FifoDataOut (port0_StoreForwardFifoDataOut), | |
3172 | .StoreForward_UnCorrectError (port0_StoreForward_UnCorrectError), | |
3173 | .StoreForward_PreECCData (port0_PacketAssyEngineDataOut), | |
3174 | .StoreForward_PostECCData (port0_StoreForwardFifoDataIn), | |
3175 | .StoreForward_CorrectedData (port0_MacXferEngineDataIn) | |
3176 | ); | |
3177 | ||
3178 | ||
3179 | `ifdef NEPTUNE | |
3180 | niu_ram_1024_152 port0_RO_RAM ( | |
3181 | .clk (niu_clk), | |
3182 | .wt_enable (port0_ReOrderFifoWrite), | |
3183 | .cs_rd (port0_ReOrderFifoRead), | |
3184 | .addr_rd (port0_ReOrderReadPtr), | |
3185 | .addr_wt (port0_ReOrderWritePtr), | |
3186 | .data_inp (port0_ReOrderFifoDataIn), | |
3187 | .data_out (port0_ReOrderFifoDataOut) | |
3188 | ); | |
3189 | ||
3190 | niu_ram_640_152 port0_SF_RAM ( | |
3191 | .clk (niu_clk), | |
3192 | .wt_enable (port0_StoreForwardFifoWrite), | |
3193 | .cs_rd (port0_StoreForwardFifoRead), | |
3194 | .addr_rd (port0_StoreForwardReadPtr), | |
3195 | .addr_wt (port0_StoreForwardWritePtr), | |
3196 | .data_inp (port0_StoreForwardFifoDataIn), | |
3197 | .data_out (port0_StoreForwardFifoDataOut) | |
3198 | ); | |
3199 | `else | |
3200 | ||
3201 | niu_mb1 niu_txe0_1024_152_membist ( | |
3202 | .rst_l (reset_l), | |
3203 | .tcu_mbist_user_mode (tcu_mbist_user_mode), | |
3204 | .niu_mb1_xmit_store_rd_en (rtx_txc_txe0_mb1_xmit_store_rd_en), | |
3205 | .niu_mb1_xmit_store_wr_en (rtx_txc_txe0_mb1_xmit_store_wr_en), | |
3206 | .niu_mb1_xmit_realign_rd_en (rtx_txc_txe0_mb1_xmit_realign_rd_en), | |
3207 | .niu_mb1_xmit_realign_wr_en (rtx_txc_txe0_mb1_xmit_realign_wr_en), | |
3208 | .niu_mb1_addr (rtx_txc_txe0_mb1_addr), | |
3209 | .niu_mb1_wdata (rtx_txc_txe0_mb1_wdata), | |
3210 | .niu_mb1_run (rtx_txc_txe0_mb1_run), | |
3211 | .niu_mb1_xmit_store_data_out (port0_StoreForwardFifoDataOut), | |
3212 | .niu_mb1_xmit_realign_data_out (port0_ReOrderFifoDataOut), | |
3213 | .tcu_mbist_bisi_en (tcu_mbist_bisi_en), | |
3214 | .tcu_niu_mbist_start_1 (tcu_rtx_txc_txe0_mbist_start), | |
3215 | .niu_tcu_mbist_fail_1 (rtx_txc_txe0_tcu_mbist_fail), | |
3216 | .niu_tcu_mbist_done_1 (rtx_txc_txe0_tcu_mbist_done), | |
3217 | .l1clk (niu_clk), | |
3218 | .mb1_scan_out (rtx_txc_txe0_mbist_scan_out), | |
3219 | .mb1_scan_in (rtx_txc_txe0_mbist_scan_in), | |
3220 | .mb1_dmo_dout (rtx_txc_txe0_dmo_dout), | |
3221 | .tcu_aclk (tcu_aclk), | |
3222 | .tcu_bclk (tcu_bclk) | |
3223 | ); | |
3224 | ||
3225 | wire [151:0] concate_rtx_txc_txe0_mb1_wdata; | |
3226 | ||
3227 | assign concate_rtx_txc_txe0_mb1_wdata | |
3228 | = {rtx_txc_txe0_mb1_wdata, rtx_txc_txe0_mb1_wdata, | |
3229 | rtx_txc_txe0_mb1_wdata, rtx_txc_txe0_mb1_wdata, | |
3230 | rtx_txc_txe0_mb1_wdata, rtx_txc_txe0_mb1_wdata, | |
3231 | rtx_txc_txe0_mb1_wdata, rtx_txc_txe0_mb1_wdata, | |
3232 | rtx_txc_txe0_mb1_wdata, rtx_txc_txe0_mb1_wdata, | |
3233 | rtx_txc_txe0_mb1_wdata, rtx_txc_txe0_mb1_wdata, | |
3234 | rtx_txc_txe0_mb1_wdata, rtx_txc_txe0_mb1_wdata, | |
3235 | rtx_txc_txe0_mb1_wdata, rtx_txc_txe0_mb1_wdata, | |
3236 | rtx_txc_txe0_mb1_wdata, rtx_txc_txe0_mb1_wdata, | |
3237 | rtx_txc_txe0_mb1_wdata | |
3238 | }; | |
3239 | ||
3240 | niu_ram_1024_152 port0_RO_RAM ( | |
3241 | .clk (iol2clk), | |
3242 | .reset (sram_reset), | |
3243 | .tcu_aclk (tcu_aclk), | |
3244 | .tcu_bclk (tcu_bclk), | |
3245 | .tcu_se_scancollar_in (tcu_se_scancollar_in), | |
3246 | .tcu_se_scancollar_out (tcu_se_scancollar_out), | |
3247 | .tcu_scan_en (tcu_scan_en), | |
3248 | .tcu_array_wr_inhibit (tcu_array_wr_inhibit), | |
3249 | .scan_in (1'b0), | |
3250 | .scan_out (), | |
3251 | .hdr_sram_rvalue (hdr_sram_rvalue_txc0_re), | |
3252 | .hdr_sram_rid (hdr_sram_rid_txc0_re), | |
3253 | .hdr_sram_wr_en (hdr_sram_wr_en_txc0_re), | |
3254 | .hdr_sram_red_clr (hdr_sram_red_clr_txc0_re), | |
3255 | .sram_hdr_read_data (sram_hdr_read_data_txc0_re), | |
3256 | ||
3257 | .mbi_wdata (concate_rtx_txc_txe0_mb1_wdata), | |
3258 | .mbi_rd_adr (rtx_txc_txe0_mb1_addr), | |
3259 | .mbi_wr_adr (rtx_txc_txe0_mb1_addr), | |
3260 | .mbi_wr_en (rtx_txc_txe0_mb1_xmit_realign_wr_en), | |
3261 | .mbi_rd_en (rtx_txc_txe0_mb1_xmit_realign_rd_en), | |
3262 | .mbi_run (rtx_txc_txe0_mb1_run), | |
3263 | .l2clk_2x (l2clk_2x), | |
3264 | .wt_enable (port0_ReOrderFifoWrite), | |
3265 | .cs_rd (port0_ReOrderFifoRead), | |
3266 | .addr_rd (port0_ReOrderReadPtr), | |
3267 | .addr_wt (port0_ReOrderWritePtr), | |
3268 | .data_inp (port0_ReOrderFifoDataIn), | |
3269 | .data_out (port0_ReOrderFifoDataOut) | |
3270 | ); | |
3271 | ||
3272 | niu_ram_1024_152 port0_SF_RAM ( | |
3273 | .clk (iol2clk), | |
3274 | .reset (sram_reset), | |
3275 | .tcu_aclk (tcu_aclk), | |
3276 | .tcu_bclk (tcu_bclk), | |
3277 | .tcu_se_scancollar_in (tcu_se_scancollar_in), | |
3278 | .tcu_se_scancollar_out (tcu_se_scancollar_out), | |
3279 | .tcu_scan_en (tcu_scan_en), | |
3280 | .tcu_array_wr_inhibit (tcu_array_wr_inhibit), | |
3281 | .scan_in (1'b0), | |
3282 | .scan_out (), | |
3283 | .hdr_sram_rvalue (hdr_sram_rvalue_txc0_st), | |
3284 | .hdr_sram_rid (hdr_sram_rid_txc0_st), | |
3285 | .hdr_sram_wr_en (hdr_sram_wr_en_txc0_st), | |
3286 | .hdr_sram_red_clr (hdr_sram_red_clr_txc0_st), | |
3287 | .sram_hdr_read_data (sram_hdr_read_data_txc0_st), | |
3288 | ||
3289 | .mbi_wdata (concate_rtx_txc_txe0_mb1_wdata), | |
3290 | .mbi_rd_adr (rtx_txc_txe0_mb1_addr), | |
3291 | .mbi_wr_adr (rtx_txc_txe0_mb1_addr), | |
3292 | .mbi_wr_en (rtx_txc_txe0_mb1_xmit_store_wr_en), | |
3293 | .mbi_rd_en (rtx_txc_txe0_mb1_xmit_store_rd_en), | |
3294 | .mbi_run (rtx_txc_txe0_mb1_run), | |
3295 | .l2clk_2x (l2clk_2x), | |
3296 | .wt_enable (port0_StoreForwardFifoWrite), | |
3297 | .cs_rd (port0_StoreForwardFifoRead), | |
3298 | .addr_rd (port0_StoreForwardReadPtr), | |
3299 | .addr_wt (port0_StoreForwardWritePtr), | |
3300 | .data_inp (port0_StoreForwardFifoDataIn), | |
3301 | .data_out (port0_StoreForwardFifoDataOut) | |
3302 | ); | |
3303 | `endif | |
3304 | ||
3305 | ||
3306 | niu_txc_packetEngine #(REORDER_SIZE_10G,REORDER_PTR_10G) niu_txc_packetEngine1 ( | |
3307 | .SysClk (niu_clk), | |
3308 | .Reset_L (reset_l), | |
3309 | .PacketAssyDead (port1_PacketAssyDead), | |
3310 | .ReOrder_Error (port1_ReOrder_Error), | |
3311 | .Txc_Enabled (txc_Enabled), | |
3312 | .PortIndentifier (`PORT_ONE), | |
3313 | .EnableGMACMode (1'b0), | |
3314 | .MAC_Enabled (port1_Enabled), | |
3315 | .FlushEngine (flushEngine), | |
3316 | ||
3317 | .MAC_Req (port1_mac_req), | |
3318 | .MAC_Ack (txc_mac_ack1), | |
3319 | .MAC_Tag (txc_mac_tag1), | |
3320 | .MAC_Status (txc_mac_stat1), | |
3321 | .MAC_Abort (txc_mac_abort1), | |
3322 | .MAC_Data (txc_mac_data1), | |
3323 | ||
3324 | .TidsInUse (port1_TidsInUse), | |
3325 | .DuplicateTid (port1_DuplicateTid), | |
3326 | .UnInitializedTID (port1_UnInitializedTID), | |
3327 | .TimedoutTids (port1_TimedoutTids), | |
3328 | .ReOrderStateLogic (port1_ReOrderStateLogic), | |
3329 | .ReOrderStateControl (port1_ReOrderStateControl), | |
3330 | .ReOrderStateData0 (port1_ReOrderStateData0), | |
3331 | .ReOrderStateData1 (port1_ReOrderStateData1), | |
3332 | .ReOrderStateData2 (port1_ReOrderStateData2), | |
3333 | .ReOrderStateData3 (port1_ReOrderStateData3), | |
3334 | .WrTidsInUse (port1_WrTidsInUse), | |
3335 | .WrDuplicateTid (port1_WrDuplicateTid), | |
3336 | .WrUnInitializedTID (port1_WrUnInitializedTID), | |
3337 | .WrTimedoutTids (port1_WrTimedoutTids), | |
3338 | .WrReOrderStateLogic (port1_WrReOrderStateLogic), | |
3339 | .WrReOrderStateControl (port1_WrReOrderStateControl), | |
3340 | .WrReOrderStateData0 (port1_WrReOrderStateData0), | |
3341 | .WrReOrderStateData1 (port1_WrReOrderStateData1), | |
3342 | .WrReOrderStateData2 (port1_WrReOrderStateData2), | |
3343 | .WrReOrderStateData3 (port1_WrReOrderStateData3), | |
3344 | .PioDataIn (port1_PioDataIn), | |
3345 | ||
3346 | .ClearStatistics (port1_ClearStatistics), | |
3347 | .WrPacketStuffed (port1_WrPacketStuffed), | |
3348 | .WrPacketXmitted (port1_WrPacketXmitted), | |
3349 | .WrPacketRequested (port1_WrPacketRequested), | |
3350 | .GatherRequestCount (port1_GatherRequestCount), | |
3351 | .PacketRequestCount (port1_PacketRequestCount), | |
3352 | .PktErrAbortCount (port1_PktErrAbortCount), | |
3353 | .ReOrdersStuffed (port1_ReOrdersStuffed), | |
3354 | .PacketsStuffed (port1_PacketsStuffed), | |
3355 | .PacketsTransmitted (port1_PacketsTransmitted), | |
3356 | .BytesTransmitted (port1_BytesTransmitted), | |
3357 | ||
3358 | .Pkt_Size_Err (txc_dmc_p1_pkt_size_err), | |
3359 | `ifdef NEPTUNE | |
3360 | .DMA_Pkt_Size_Err (txc_dmc_p1_dma_pkt_size_err), | |
3361 | `else | |
3362 | .DMA_Pkt_Size_Err ({dummy_txc_dmc_p1_dma_pkt_size_err, | |
3363 | txc_dmc_p1_dma_pkt_size_err}), | |
3364 | `endif | |
3365 | .Pkt_Size_Err_Addr (txc_dmc_p1_pkt_size_err_addr), | |
3366 | ||
3367 | .Nack_Pkt_Rd (port1_Nack_Pkt_Rd), | |
3368 | .DMA_Nack_Pkt_Rd (port1_DMA_Nack_Pkt_Rd), | |
3369 | .Nack_Pkt_Rd_Addr (port1_Nack_Pkt_Rd_Addr), | |
3370 | ||
3371 | .DMA0_Active (dmc_txc_dma0_active), | |
3372 | .DMA0_EofList (dmc_txc_dma0_eoflist), | |
3373 | .DMA0_Error (dmc_txc_dma0_error), | |
3374 | .DMA0_CacheReady (dmc_txc_dma0_cacheready), | |
3375 | .DMA0_Partial (dmc_txc_dma0_partial), | |
3376 | .DMA0_Reset_Scheduled (dmc_txc_dma0_reset_scheduled), | |
3377 | .DMA0_GotNxtDesc (dmc_txc_dma0_gotnxtdesc), | |
3378 | .DMA0_Mark (dmc_txc_dma0_descriptor[62]), | |
3379 | .DMA0_SOP (dmc_txc_dma0_descriptor[63]), | |
3380 | .DMA0_Func_Num (dmc_txc_dma0_func_num), | |
3381 | .DMA0_DescList (dmc_txc_dma0_descriptor[61:58]), | |
3382 | .DMA0_Length (dmc_txc_dma0_descriptor[56:44]), | |
3383 | .DMA0_PageHandle (dmc_txc_dma0_page_handle), | |
3384 | .DMA0_Address (dmc_txc_dma0_descriptor[43:0]), | |
3385 | .DMA0_Inc_Head (port1_DMA0_inc_head), | |
3386 | .DMA0_Reset_Done (port1_DMA0_reset_done), | |
3387 | .DMA0_Mark_Bit (port1_DMA0_mark_bit), | |
3388 | .DMA0_Inc_Pkt_Cnt (port1_DMA0_inc_pkt_cnt), | |
3389 | .SetGetNextDescDMA0 (port1_SetGetNextDescDMA0), | |
3390 | .DMA1_Active (dmc_txc_dma1_active), | |
3391 | .DMA1_EofList (dmc_txc_dma1_eoflist), | |
3392 | .DMA1_Error (dmc_txc_dma1_error), | |
3393 | .DMA1_CacheReady (dmc_txc_dma1_cacheready), | |
3394 | .DMA1_Partial (dmc_txc_dma1_partial), | |
3395 | .DMA1_Reset_Scheduled (dmc_txc_dma1_reset_scheduled), | |
3396 | .DMA1_GotNxtDesc (dmc_txc_dma1_gotnxtdesc), | |
3397 | .DMA1_Mark (dmc_txc_dma1_descriptor[62]), | |
3398 | .DMA1_SOP (dmc_txc_dma1_descriptor[63]), | |
3399 | .DMA1_Func_Num (dmc_txc_dma1_func_num), | |
3400 | .DMA1_DescList (dmc_txc_dma1_descriptor[61:58]), | |
3401 | .DMA1_Length (dmc_txc_dma1_descriptor[56:44]), | |
3402 | .DMA1_PageHandle (dmc_txc_dma1_page_handle), | |
3403 | .DMA1_Address (dmc_txc_dma1_descriptor[43:0]), | |
3404 | .DMA1_Inc_Head (port1_DMA1_inc_head), | |
3405 | .DMA1_Reset_Done (port1_DMA1_reset_done), | |
3406 | .DMA1_Mark_Bit (port1_DMA1_mark_bit), | |
3407 | .DMA1_Inc_Pkt_Cnt (port1_DMA1_inc_pkt_cnt), | |
3408 | .SetGetNextDescDMA1 (port1_SetGetNextDescDMA1), | |
3409 | .DMA2_Active (dmc_txc_dma2_active), | |
3410 | .DMA2_EofList (dmc_txc_dma2_eoflist), | |
3411 | .DMA2_Error (dmc_txc_dma2_error), | |
3412 | .DMA2_CacheReady (dmc_txc_dma2_cacheready), | |
3413 | .DMA2_Partial (dmc_txc_dma2_partial), | |
3414 | .DMA2_Reset_Scheduled (dmc_txc_dma2_reset_scheduled), | |
3415 | .DMA2_GotNxtDesc (dmc_txc_dma2_gotnxtdesc), | |
3416 | .DMA2_Mark (dmc_txc_dma2_descriptor[62]), | |
3417 | .DMA2_SOP (dmc_txc_dma2_descriptor[63]), | |
3418 | .DMA2_Func_Num (dmc_txc_dma2_func_num), | |
3419 | .DMA2_DescList (dmc_txc_dma2_descriptor[61:58]), | |
3420 | .DMA2_Length (dmc_txc_dma2_descriptor[56:44]), | |
3421 | .DMA2_PageHandle (dmc_txc_dma2_page_handle), | |
3422 | .DMA2_Address (dmc_txc_dma2_descriptor[43:0]), | |
3423 | .DMA2_Inc_Head (port1_DMA2_inc_head), | |
3424 | .DMA2_Reset_Done (port1_DMA2_reset_done), | |
3425 | .DMA2_Mark_Bit (port1_DMA2_mark_bit), | |
3426 | .DMA2_Inc_Pkt_Cnt (port1_DMA2_inc_pkt_cnt), | |
3427 | .SetGetNextDescDMA2 (port1_SetGetNextDescDMA2), | |
3428 | .DMA3_Active (dmc_txc_dma3_active), | |
3429 | .DMA3_EofList (dmc_txc_dma3_eoflist), | |
3430 | .DMA3_Error (dmc_txc_dma3_error), | |
3431 | .DMA3_CacheReady (dmc_txc_dma3_cacheready), | |
3432 | .DMA3_Partial (dmc_txc_dma3_partial), | |
3433 | .DMA3_Reset_Scheduled (dmc_txc_dma3_reset_scheduled), | |
3434 | .DMA3_GotNxtDesc (dmc_txc_dma3_gotnxtdesc), | |
3435 | .DMA3_Mark (dmc_txc_dma3_descriptor[62]), | |
3436 | .DMA3_SOP (dmc_txc_dma3_descriptor[63]), | |
3437 | .DMA3_Func_Num (dmc_txc_dma3_func_num), | |
3438 | .DMA3_DescList (dmc_txc_dma3_descriptor[61:58]), | |
3439 | .DMA3_Length (dmc_txc_dma3_descriptor[56:44]), | |
3440 | .DMA3_PageHandle (dmc_txc_dma3_page_handle), | |
3441 | .DMA3_Address (dmc_txc_dma3_descriptor[43:0]), | |
3442 | .DMA3_Inc_Head (port1_DMA3_inc_head), | |
3443 | .DMA3_Reset_Done (port1_DMA3_reset_done), | |
3444 | .DMA3_Mark_Bit (port1_DMA3_mark_bit), | |
3445 | .DMA3_Inc_Pkt_Cnt (port1_DMA3_inc_pkt_cnt), | |
3446 | .SetGetNextDescDMA3 (port1_SetGetNextDescDMA3), | |
3447 | .DMA4_Active (dmc_txc_dma4_active), | |
3448 | .DMA4_EofList (dmc_txc_dma4_eoflist), | |
3449 | .DMA4_Error (dmc_txc_dma4_error), | |
3450 | .DMA4_CacheReady (dmc_txc_dma4_cacheready), | |
3451 | .DMA4_Partial (dmc_txc_dma4_partial), | |
3452 | .DMA4_Reset_Scheduled (dmc_txc_dma4_reset_scheduled), | |
3453 | .DMA4_GotNxtDesc (dmc_txc_dma4_gotnxtdesc), | |
3454 | .DMA4_Mark (dmc_txc_dma4_descriptor[62]), | |
3455 | .DMA4_SOP (dmc_txc_dma4_descriptor[63]), | |
3456 | .DMA4_Func_Num (dmc_txc_dma4_func_num), | |
3457 | .DMA4_DescList (dmc_txc_dma4_descriptor[61:58]), | |
3458 | .DMA4_Length (dmc_txc_dma4_descriptor[56:44]), | |
3459 | .DMA4_PageHandle (dmc_txc_dma4_page_handle), | |
3460 | .DMA4_Address (dmc_txc_dma4_descriptor[43:0]), | |
3461 | .DMA4_Inc_Head (port1_DMA4_inc_head), | |
3462 | .DMA4_Reset_Done (port1_DMA4_reset_done), | |
3463 | .DMA4_Mark_Bit (port1_DMA4_mark_bit), | |
3464 | .DMA4_Inc_Pkt_Cnt (port1_DMA4_inc_pkt_cnt), | |
3465 | .SetGetNextDescDMA4 (port1_SetGetNextDescDMA4), | |
3466 | .DMA5_Active (dmc_txc_dma5_active), | |
3467 | .DMA5_EofList (dmc_txc_dma5_eoflist), | |
3468 | .DMA5_Error (dmc_txc_dma5_error), | |
3469 | .DMA5_CacheReady (dmc_txc_dma5_cacheready), | |
3470 | .DMA5_Partial (dmc_txc_dma5_partial), | |
3471 | .DMA5_Reset_Scheduled (dmc_txc_dma5_reset_scheduled), | |
3472 | .DMA5_GotNxtDesc (dmc_txc_dma5_gotnxtdesc), | |
3473 | .DMA5_Mark (dmc_txc_dma5_descriptor[62]), | |
3474 | .DMA5_SOP (dmc_txc_dma5_descriptor[63]), | |
3475 | .DMA5_Func_Num (dmc_txc_dma5_func_num), | |
3476 | .DMA5_DescList (dmc_txc_dma5_descriptor[61:58]), | |
3477 | .DMA5_Length (dmc_txc_dma5_descriptor[56:44]), | |
3478 | .DMA5_PageHandle (dmc_txc_dma5_page_handle), | |
3479 | .DMA5_Address (dmc_txc_dma5_descriptor[43:0]), | |
3480 | .DMA5_Inc_Head (port1_DMA5_inc_head), | |
3481 | .DMA5_Reset_Done (port1_DMA5_reset_done), | |
3482 | .DMA5_Mark_Bit (port1_DMA5_mark_bit), | |
3483 | .DMA5_Inc_Pkt_Cnt (port1_DMA5_inc_pkt_cnt), | |
3484 | .SetGetNextDescDMA5 (port1_SetGetNextDescDMA5), | |
3485 | .DMA6_Active (dmc_txc_dma6_active), | |
3486 | .DMA6_EofList (dmc_txc_dma6_eoflist), | |
3487 | .DMA6_Error (dmc_txc_dma6_error), | |
3488 | .DMA6_CacheReady (dmc_txc_dma6_cacheready), | |
3489 | .DMA6_Partial (dmc_txc_dma6_partial), | |
3490 | .DMA6_Reset_Scheduled (dmc_txc_dma6_reset_scheduled), | |
3491 | .DMA6_GotNxtDesc (dmc_txc_dma6_gotnxtdesc), | |
3492 | .DMA6_Mark (dmc_txc_dma6_descriptor[62]), | |
3493 | .DMA6_SOP (dmc_txc_dma6_descriptor[63]), | |
3494 | .DMA6_Func_Num (dmc_txc_dma6_func_num), | |
3495 | .DMA6_DescList (dmc_txc_dma6_descriptor[61:58]), | |
3496 | .DMA6_Length (dmc_txc_dma6_descriptor[56:44]), | |
3497 | .DMA6_PageHandle (dmc_txc_dma6_page_handle), | |
3498 | .DMA6_Address (dmc_txc_dma6_descriptor[43:0]), | |
3499 | .DMA6_Inc_Head (port1_DMA6_inc_head), | |
3500 | .DMA6_Reset_Done (port1_DMA6_reset_done), | |
3501 | .DMA6_Mark_Bit (port1_DMA6_mark_bit), | |
3502 | .DMA6_Inc_Pkt_Cnt (port1_DMA6_inc_pkt_cnt), | |
3503 | .SetGetNextDescDMA6 (port1_SetGetNextDescDMA6), | |
3504 | .DMA7_Active (dmc_txc_dma7_active), | |
3505 | .DMA7_EofList (dmc_txc_dma7_eoflist), | |
3506 | .DMA7_Error (dmc_txc_dma7_error), | |
3507 | .DMA7_CacheReady (dmc_txc_dma7_cacheready), | |
3508 | .DMA7_Partial (dmc_txc_dma7_partial), | |
3509 | .DMA7_Reset_Scheduled (dmc_txc_dma7_reset_scheduled), | |
3510 | .DMA7_GotNxtDesc (dmc_txc_dma7_gotnxtdesc), | |
3511 | .DMA7_Mark (dmc_txc_dma7_descriptor[62]), | |
3512 | .DMA7_SOP (dmc_txc_dma7_descriptor[63]), | |
3513 | .DMA7_Func_Num (dmc_txc_dma7_func_num), | |
3514 | .DMA7_DescList (dmc_txc_dma7_descriptor[61:58]), | |
3515 | .DMA7_Length (dmc_txc_dma7_descriptor[56:44]), | |
3516 | .DMA7_PageHandle (dmc_txc_dma7_page_handle), | |
3517 | .DMA7_Address (dmc_txc_dma7_descriptor[43:0]), | |
3518 | .DMA7_Inc_Head (port1_DMA7_inc_head), | |
3519 | .DMA7_Reset_Done (port1_DMA7_reset_done), | |
3520 | .DMA7_Mark_Bit (port1_DMA7_mark_bit), | |
3521 | .DMA7_Inc_Pkt_Cnt (port1_DMA7_inc_pkt_cnt), | |
3522 | .SetGetNextDescDMA7 (port1_SetGetNextDescDMA7), | |
3523 | .DMA8_Active (dmc_txc_dma8_active), | |
3524 | .DMA8_EofList (dmc_txc_dma8_eoflist), | |
3525 | .DMA8_Error (dmc_txc_dma8_error), | |
3526 | .DMA8_CacheReady (dmc_txc_dma8_cacheready), | |
3527 | .DMA8_Partial (dmc_txc_dma8_partial), | |
3528 | .DMA8_Reset_Scheduled (dmc_txc_dma8_reset_scheduled), | |
3529 | .DMA8_GotNxtDesc (dmc_txc_dma8_gotnxtdesc), | |
3530 | .DMA8_Mark (dmc_txc_dma8_descriptor[62]), | |
3531 | .DMA8_SOP (dmc_txc_dma8_descriptor[63]), | |
3532 | .DMA8_Func_Num (dmc_txc_dma8_func_num), | |
3533 | .DMA8_DescList (dmc_txc_dma8_descriptor[61:58]), | |
3534 | .DMA8_Length (dmc_txc_dma8_descriptor[56:44]), | |
3535 | .DMA8_PageHandle (dmc_txc_dma8_page_handle), | |
3536 | .DMA8_Address (dmc_txc_dma8_descriptor[43:0]), | |
3537 | .DMA8_Inc_Head (port1_DMA8_inc_head), | |
3538 | .DMA8_Reset_Done (port1_DMA8_reset_done), | |
3539 | .DMA8_Mark_Bit (port1_DMA8_mark_bit), | |
3540 | .DMA8_Inc_Pkt_Cnt (port1_DMA8_inc_pkt_cnt), | |
3541 | .SetGetNextDescDMA8 (port1_SetGetNextDescDMA8), | |
3542 | .DMA9_Active (dmc_txc_dma9_active), | |
3543 | .DMA9_EofList (dmc_txc_dma9_eoflist), | |
3544 | .DMA9_Error (dmc_txc_dma9_error), | |
3545 | .DMA9_CacheReady (dmc_txc_dma9_cacheready), | |
3546 | .DMA9_Partial (dmc_txc_dma9_partial), | |
3547 | .DMA9_Reset_Scheduled (dmc_txc_dma9_reset_scheduled), | |
3548 | .DMA9_GotNxtDesc (dmc_txc_dma9_gotnxtdesc), | |
3549 | .DMA9_Mark (dmc_txc_dma9_descriptor[62]), | |
3550 | .DMA9_SOP (dmc_txc_dma9_descriptor[63]), | |
3551 | .DMA9_Func_Num (dmc_txc_dma9_func_num), | |
3552 | .DMA9_DescList (dmc_txc_dma9_descriptor[61:58]), | |
3553 | .DMA9_Length (dmc_txc_dma9_descriptor[56:44]), | |
3554 | .DMA9_PageHandle (dmc_txc_dma9_page_handle), | |
3555 | .DMA9_Address (dmc_txc_dma9_descriptor[43:0]), | |
3556 | .DMA9_Inc_Head (port1_DMA9_inc_head), | |
3557 | .DMA9_Reset_Done (port1_DMA9_reset_done), | |
3558 | .DMA9_Mark_Bit (port1_DMA9_mark_bit), | |
3559 | .DMA9_Inc_Pkt_Cnt (port1_DMA9_inc_pkt_cnt), | |
3560 | .SetGetNextDescDMA9 (port1_SetGetNextDescDMA9), | |
3561 | .DMA10_Active (dmc_txc_dma10_active), | |
3562 | .DMA10_EofList (dmc_txc_dma10_eoflist), | |
3563 | .DMA10_Error (dmc_txc_dma10_error), | |
3564 | .DMA10_CacheReady (dmc_txc_dma10_cacheready), | |
3565 | .DMA10_Partial (dmc_txc_dma10_partial), | |
3566 | .DMA10_Reset_Scheduled (dmc_txc_dma10_reset_scheduled), | |
3567 | .DMA10_GotNxtDesc (dmc_txc_dma10_gotnxtdesc), | |
3568 | .DMA10_Mark (dmc_txc_dma10_descriptor[62]), | |
3569 | .DMA10_SOP (dmc_txc_dma10_descriptor[63]), | |
3570 | .DMA10_Func_Num (dmc_txc_dma10_func_num), | |
3571 | .DMA10_DescList (dmc_txc_dma10_descriptor[61:58]), | |
3572 | .DMA10_Length (dmc_txc_dma10_descriptor[56:44]), | |
3573 | .DMA10_PageHandle (dmc_txc_dma10_page_handle), | |
3574 | .DMA10_Address (dmc_txc_dma10_descriptor[43:0]), | |
3575 | .DMA10_Inc_Head (port1_DMA10_inc_head), | |
3576 | .DMA10_Reset_Done (port1_DMA10_reset_done), | |
3577 | .DMA10_Mark_Bit (port1_DMA10_mark_bit), | |
3578 | .DMA10_Inc_Pkt_Cnt (port1_DMA10_inc_pkt_cnt), | |
3579 | .SetGetNextDescDMA10 (port1_SetGetNextDescDMA10), | |
3580 | .DMA11_Active (dmc_txc_dma11_active), | |
3581 | .DMA11_EofList (dmc_txc_dma11_eoflist), | |
3582 | .DMA11_Error (dmc_txc_dma11_error), | |
3583 | .DMA11_CacheReady (dmc_txc_dma11_cacheready), | |
3584 | .DMA11_Partial (dmc_txc_dma11_partial), | |
3585 | .DMA11_Reset_Scheduled (dmc_txc_dma11_reset_scheduled), | |
3586 | .DMA11_GotNxtDesc (dmc_txc_dma11_gotnxtdesc), | |
3587 | .DMA11_Mark (dmc_txc_dma11_descriptor[62]), | |
3588 | .DMA11_SOP (dmc_txc_dma11_descriptor[63]), | |
3589 | .DMA11_Func_Num (dmc_txc_dma11_func_num), | |
3590 | .DMA11_DescList (dmc_txc_dma11_descriptor[61:58]), | |
3591 | .DMA11_Length (dmc_txc_dma11_descriptor[56:44]), | |
3592 | .DMA11_PageHandle (dmc_txc_dma11_page_handle), | |
3593 | .DMA11_Address (dmc_txc_dma11_descriptor[43:0]), | |
3594 | .DMA11_Inc_Head (port1_DMA11_inc_head), | |
3595 | .DMA11_Reset_Done (port1_DMA11_reset_done), | |
3596 | .DMA11_Mark_Bit (port1_DMA11_mark_bit), | |
3597 | .DMA11_Inc_Pkt_Cnt (port1_DMA11_inc_pkt_cnt), | |
3598 | .SetGetNextDescDMA11 (port1_SetGetNextDescDMA11), | |
3599 | .DMA12_Active (dmc_txc_dma12_active), | |
3600 | .DMA12_EofList (dmc_txc_dma12_eoflist), | |
3601 | .DMA12_Error (dmc_txc_dma12_error), | |
3602 | .DMA12_CacheReady (dmc_txc_dma12_cacheready), | |
3603 | .DMA12_Partial (dmc_txc_dma12_partial), | |
3604 | .DMA12_Reset_Scheduled (dmc_txc_dma12_reset_scheduled), | |
3605 | .DMA12_GotNxtDesc (dmc_txc_dma12_gotnxtdesc), | |
3606 | .DMA12_Mark (dmc_txc_dma12_descriptor[62]), | |
3607 | .DMA12_SOP (dmc_txc_dma12_descriptor[63]), | |
3608 | .DMA12_Func_Num (dmc_txc_dma12_func_num), | |
3609 | .DMA12_DescList (dmc_txc_dma12_descriptor[61:58]), | |
3610 | .DMA12_Length (dmc_txc_dma12_descriptor[56:44]), | |
3611 | .DMA12_PageHandle (dmc_txc_dma12_page_handle), | |
3612 | .DMA12_Address (dmc_txc_dma12_descriptor[43:0]), | |
3613 | .DMA12_Inc_Head (port1_DMA12_inc_head), | |
3614 | .DMA12_Reset_Done (port1_DMA12_reset_done), | |
3615 | .DMA12_Mark_Bit (port1_DMA12_mark_bit), | |
3616 | .DMA12_Inc_Pkt_Cnt (port1_DMA12_inc_pkt_cnt), | |
3617 | .SetGetNextDescDMA12 (port1_SetGetNextDescDMA12), | |
3618 | .DMA13_Active (dmc_txc_dma13_active), | |
3619 | .DMA13_EofList (dmc_txc_dma13_eoflist), | |
3620 | .DMA13_Error (dmc_txc_dma13_error), | |
3621 | .DMA13_CacheReady (dmc_txc_dma13_cacheready), | |
3622 | .DMA13_Partial (dmc_txc_dma13_partial), | |
3623 | .DMA13_Reset_Scheduled (dmc_txc_dma13_reset_scheduled), | |
3624 | .DMA13_GotNxtDesc (dmc_txc_dma13_gotnxtdesc), | |
3625 | .DMA13_Mark (dmc_txc_dma13_descriptor[62]), | |
3626 | .DMA13_SOP (dmc_txc_dma13_descriptor[63]), | |
3627 | .DMA13_Func_Num (dmc_txc_dma13_func_num), | |
3628 | .DMA13_DescList (dmc_txc_dma13_descriptor[61:58]), | |
3629 | .DMA13_Length (dmc_txc_dma13_descriptor[56:44]), | |
3630 | .DMA13_PageHandle (dmc_txc_dma13_page_handle), | |
3631 | .DMA13_Address (dmc_txc_dma13_descriptor[43:0]), | |
3632 | .DMA13_Inc_Head (port1_DMA13_inc_head), | |
3633 | .DMA13_Reset_Done (port1_DMA13_reset_done), | |
3634 | .DMA13_Mark_Bit (port1_DMA13_mark_bit), | |
3635 | .DMA13_Inc_Pkt_Cnt (port1_DMA13_inc_pkt_cnt), | |
3636 | .SetGetNextDescDMA13 (port1_SetGetNextDescDMA13), | |
3637 | .DMA14_Active (dmc_txc_dma14_active), | |
3638 | .DMA14_EofList (dmc_txc_dma14_eoflist), | |
3639 | .DMA14_Error (dmc_txc_dma14_error), | |
3640 | .DMA14_CacheReady (dmc_txc_dma14_cacheready), | |
3641 | .DMA14_Partial (dmc_txc_dma14_partial), | |
3642 | .DMA14_Reset_Scheduled (dmc_txc_dma14_reset_scheduled), | |
3643 | .DMA14_GotNxtDesc (dmc_txc_dma14_gotnxtdesc), | |
3644 | .DMA14_Mark (dmc_txc_dma14_descriptor[62]), | |
3645 | .DMA14_SOP (dmc_txc_dma14_descriptor[63]), | |
3646 | .DMA14_Func_Num (dmc_txc_dma14_func_num), | |
3647 | .DMA14_DescList (dmc_txc_dma14_descriptor[61:58]), | |
3648 | .DMA14_Length (dmc_txc_dma14_descriptor[56:44]), | |
3649 | .DMA14_PageHandle (dmc_txc_dma14_page_handle), | |
3650 | .DMA14_Address (dmc_txc_dma14_descriptor[43:0]), | |
3651 | .DMA14_Inc_Head (port1_DMA14_inc_head), | |
3652 | .DMA14_Reset_Done (port1_DMA14_reset_done), | |
3653 | .DMA14_Mark_Bit (port1_DMA14_mark_bit), | |
3654 | .DMA14_Inc_Pkt_Cnt (port1_DMA14_inc_pkt_cnt), | |
3655 | .SetGetNextDescDMA14 (port1_SetGetNextDescDMA14), | |
3656 | .DMA15_Active (dmc_txc_dma15_active), | |
3657 | .DMA15_EofList (dmc_txc_dma15_eoflist), | |
3658 | .DMA15_Error (dmc_txc_dma15_error), | |
3659 | .DMA15_CacheReady (dmc_txc_dma15_cacheready), | |
3660 | .DMA15_Partial (dmc_txc_dma15_partial), | |
3661 | .DMA15_Reset_Scheduled (dmc_txc_dma15_reset_scheduled), | |
3662 | .DMA15_GotNxtDesc (dmc_txc_dma15_gotnxtdesc), | |
3663 | .DMA15_Mark (dmc_txc_dma15_descriptor[62]), | |
3664 | .DMA15_SOP (dmc_txc_dma15_descriptor[63]), | |
3665 | .DMA15_Func_Num (dmc_txc_dma15_func_num), | |
3666 | .DMA15_DescList (dmc_txc_dma15_descriptor[61:58]), | |
3667 | .DMA15_Length (dmc_txc_dma15_descriptor[56:44]), | |
3668 | .DMA15_PageHandle (dmc_txc_dma15_page_handle), | |
3669 | .DMA15_Address (dmc_txc_dma15_descriptor[43:0]), | |
3670 | .DMA15_Inc_Head (port1_DMA15_inc_head), | |
3671 | .DMA15_Reset_Done (port1_DMA15_reset_done), | |
3672 | .DMA15_Mark_Bit (port1_DMA15_mark_bit), | |
3673 | .DMA15_Inc_Pkt_Cnt (port1_DMA15_inc_pkt_cnt), | |
3674 | .SetGetNextDescDMA15 (port1_SetGetNextDescDMA15), | |
3675 | .DMA16_Active (dmc_txc_dma16_active), | |
3676 | .DMA16_EofList (dmc_txc_dma16_eoflist), | |
3677 | .DMA16_Error (dmc_txc_dma16_error), | |
3678 | .DMA16_CacheReady (dmc_txc_dma16_cacheready), | |
3679 | .DMA16_Partial (dmc_txc_dma16_partial), | |
3680 | .DMA16_Reset_Scheduled (dmc_txc_dma16_reset_scheduled), | |
3681 | .DMA16_GotNxtDesc (dmc_txc_dma16_gotnxtdesc), | |
3682 | .DMA16_Mark (dmc_txc_dma16_descriptor[62]), | |
3683 | .DMA16_SOP (dmc_txc_dma16_descriptor[63]), | |
3684 | .DMA16_Func_Num (dmc_txc_dma16_func_num), | |
3685 | .DMA16_DescList (dmc_txc_dma16_descriptor[61:58]), | |
3686 | .DMA16_Length (dmc_txc_dma16_descriptor[56:44]), | |
3687 | .DMA16_PageHandle (dmc_txc_dma16_page_handle), | |
3688 | .DMA16_Address (dmc_txc_dma16_descriptor[43:0]), | |
3689 | .DMA16_Inc_Head (port1_DMA16_inc_head), | |
3690 | .DMA16_Reset_Done (port1_DMA16_reset_done), | |
3691 | .DMA16_Mark_Bit (port1_DMA16_mark_bit), | |
3692 | .DMA16_Inc_Pkt_Cnt (port1_DMA16_inc_pkt_cnt), | |
3693 | .SetGetNextDescDMA16 (port1_SetGetNextDescDMA16), | |
3694 | .DMA17_Active (dmc_txc_dma17_active), | |
3695 | .DMA17_EofList (dmc_txc_dma17_eoflist), | |
3696 | .DMA17_Error (dmc_txc_dma17_error), | |
3697 | .DMA17_CacheReady (dmc_txc_dma17_cacheready), | |
3698 | .DMA17_Partial (dmc_txc_dma17_partial), | |
3699 | .DMA17_Reset_Scheduled (dmc_txc_dma17_reset_scheduled), | |
3700 | .DMA17_GotNxtDesc (dmc_txc_dma17_gotnxtdesc), | |
3701 | .DMA17_Mark (dmc_txc_dma17_descriptor[62]), | |
3702 | .DMA17_SOP (dmc_txc_dma17_descriptor[63]), | |
3703 | .DMA17_Func_Num (dmc_txc_dma17_func_num), | |
3704 | .DMA17_DescList (dmc_txc_dma17_descriptor[61:58]), | |
3705 | .DMA17_Length (dmc_txc_dma17_descriptor[56:44]), | |
3706 | .DMA17_PageHandle (dmc_txc_dma17_page_handle), | |
3707 | .DMA17_Address (dmc_txc_dma17_descriptor[43:0]), | |
3708 | .DMA17_Inc_Head (port1_DMA17_inc_head), | |
3709 | .DMA17_Reset_Done (port1_DMA17_reset_done), | |
3710 | .DMA17_Mark_Bit (port1_DMA17_mark_bit), | |
3711 | .DMA17_Inc_Pkt_Cnt (port1_DMA17_inc_pkt_cnt), | |
3712 | .SetGetNextDescDMA17 (port1_SetGetNextDescDMA17), | |
3713 | .DMA18_Active (dmc_txc_dma18_active), | |
3714 | .DMA18_EofList (dmc_txc_dma18_eoflist), | |
3715 | .DMA18_Error (dmc_txc_dma18_error), | |
3716 | .DMA18_CacheReady (dmc_txc_dma18_cacheready), | |
3717 | .DMA18_Partial (dmc_txc_dma18_partial), | |
3718 | .DMA18_Reset_Scheduled (dmc_txc_dma18_reset_scheduled), | |
3719 | .DMA18_GotNxtDesc (dmc_txc_dma18_gotnxtdesc), | |
3720 | .DMA18_Mark (dmc_txc_dma18_descriptor[62]), | |
3721 | .DMA18_SOP (dmc_txc_dma18_descriptor[63]), | |
3722 | .DMA18_Func_Num (dmc_txc_dma18_func_num), | |
3723 | .DMA18_DescList (dmc_txc_dma18_descriptor[61:58]), | |
3724 | .DMA18_Length (dmc_txc_dma18_descriptor[56:44]), | |
3725 | .DMA18_PageHandle (dmc_txc_dma18_page_handle), | |
3726 | .DMA18_Address (dmc_txc_dma18_descriptor[43:0]), | |
3727 | .DMA18_Inc_Head (port1_DMA18_inc_head), | |
3728 | .DMA18_Reset_Done (port1_DMA18_reset_done), | |
3729 | .DMA18_Mark_Bit (port1_DMA18_mark_bit), | |
3730 | .DMA18_Inc_Pkt_Cnt (port1_DMA18_inc_pkt_cnt), | |
3731 | .SetGetNextDescDMA18 (port1_SetGetNextDescDMA18), | |
3732 | .DMA19_Active (dmc_txc_dma19_active), | |
3733 | .DMA19_EofList (dmc_txc_dma19_eoflist), | |
3734 | .DMA19_Error (dmc_txc_dma19_error), | |
3735 | .DMA19_CacheReady (dmc_txc_dma19_cacheready), | |
3736 | .DMA19_Partial (dmc_txc_dma19_partial), | |
3737 | .DMA19_Reset_Scheduled (dmc_txc_dma19_reset_scheduled), | |
3738 | .DMA19_GotNxtDesc (dmc_txc_dma19_gotnxtdesc), | |
3739 | .DMA19_Mark (dmc_txc_dma19_descriptor[62]), | |
3740 | .DMA19_SOP (dmc_txc_dma19_descriptor[63]), | |
3741 | .DMA19_Func_Num (dmc_txc_dma19_func_num), | |
3742 | .DMA19_DescList (dmc_txc_dma19_descriptor[61:58]), | |
3743 | .DMA19_Length (dmc_txc_dma19_descriptor[56:44]), | |
3744 | .DMA19_PageHandle (dmc_txc_dma19_page_handle), | |
3745 | .DMA19_Address (dmc_txc_dma19_descriptor[43:0]), | |
3746 | .DMA19_Inc_Head (port1_DMA19_inc_head), | |
3747 | .DMA19_Reset_Done (port1_DMA19_reset_done), | |
3748 | .DMA19_Mark_Bit (port1_DMA19_mark_bit), | |
3749 | .DMA19_Inc_Pkt_Cnt (port1_DMA19_inc_pkt_cnt), | |
3750 | .SetGetNextDescDMA19 (port1_SetGetNextDescDMA19), | |
3751 | .DMA20_Active (dmc_txc_dma20_active), | |
3752 | .DMA20_EofList (dmc_txc_dma20_eoflist), | |
3753 | .DMA20_Error (dmc_txc_dma20_error), | |
3754 | .DMA20_CacheReady (dmc_txc_dma20_cacheready), | |
3755 | .DMA20_Partial (dmc_txc_dma20_partial), | |
3756 | .DMA20_Reset_Scheduled (dmc_txc_dma20_reset_scheduled), | |
3757 | .DMA20_GotNxtDesc (dmc_txc_dma20_gotnxtdesc), | |
3758 | .DMA20_Mark (dmc_txc_dma20_descriptor[62]), | |
3759 | .DMA20_SOP (dmc_txc_dma20_descriptor[63]), | |
3760 | .DMA20_Func_Num (dmc_txc_dma20_func_num), | |
3761 | .DMA20_DescList (dmc_txc_dma20_descriptor[61:58]), | |
3762 | .DMA20_Length (dmc_txc_dma20_descriptor[56:44]), | |
3763 | .DMA20_PageHandle (dmc_txc_dma20_page_handle), | |
3764 | .DMA20_Address (dmc_txc_dma20_descriptor[43:0]), | |
3765 | .DMA20_Inc_Head (port1_DMA20_inc_head), | |
3766 | .DMA20_Reset_Done (port1_DMA20_reset_done), | |
3767 | .DMA20_Mark_Bit (port1_DMA20_mark_bit), | |
3768 | .DMA20_Inc_Pkt_Cnt (port1_DMA20_inc_pkt_cnt), | |
3769 | .SetGetNextDescDMA20 (port1_SetGetNextDescDMA20), | |
3770 | .DMA21_Active (dmc_txc_dma21_active), | |
3771 | .DMA21_EofList (dmc_txc_dma21_eoflist), | |
3772 | .DMA21_Error (dmc_txc_dma21_error), | |
3773 | .DMA21_CacheReady (dmc_txc_dma21_cacheready), | |
3774 | .DMA21_Partial (dmc_txc_dma21_partial), | |
3775 | .DMA21_Reset_Scheduled (dmc_txc_dma21_reset_scheduled), | |
3776 | .DMA21_GotNxtDesc (dmc_txc_dma21_gotnxtdesc), | |
3777 | .DMA21_Mark (dmc_txc_dma21_descriptor[62]), | |
3778 | .DMA21_SOP (dmc_txc_dma21_descriptor[63]), | |
3779 | .DMA21_Func_Num (dmc_txc_dma21_func_num), | |
3780 | .DMA21_DescList (dmc_txc_dma21_descriptor[61:58]), | |
3781 | .DMA21_Length (dmc_txc_dma21_descriptor[56:44]), | |
3782 | .DMA21_PageHandle (dmc_txc_dma21_page_handle), | |
3783 | .DMA21_Address (dmc_txc_dma21_descriptor[43:0]), | |
3784 | .DMA21_Inc_Head (port1_DMA21_inc_head), | |
3785 | .DMA21_Reset_Done (port1_DMA21_reset_done), | |
3786 | .DMA21_Mark_Bit (port1_DMA21_mark_bit), | |
3787 | .DMA21_Inc_Pkt_Cnt (port1_DMA21_inc_pkt_cnt), | |
3788 | .SetGetNextDescDMA21 (port1_SetGetNextDescDMA21), | |
3789 | .DMA22_Active (dmc_txc_dma22_active), | |
3790 | .DMA22_EofList (dmc_txc_dma22_eoflist), | |
3791 | .DMA22_Error (dmc_txc_dma22_error), | |
3792 | .DMA22_CacheReady (dmc_txc_dma22_cacheready), | |
3793 | .DMA22_Partial (dmc_txc_dma22_partial), | |
3794 | .DMA22_Reset_Scheduled (dmc_txc_dma22_reset_scheduled), | |
3795 | .DMA22_GotNxtDesc (dmc_txc_dma22_gotnxtdesc), | |
3796 | .DMA22_Mark (dmc_txc_dma22_descriptor[62]), | |
3797 | .DMA22_SOP (dmc_txc_dma22_descriptor[63]), | |
3798 | .DMA22_Func_Num (dmc_txc_dma22_func_num), | |
3799 | .DMA22_DescList (dmc_txc_dma22_descriptor[61:58]), | |
3800 | .DMA22_Length (dmc_txc_dma22_descriptor[56:44]), | |
3801 | .DMA22_PageHandle (dmc_txc_dma22_page_handle), | |
3802 | .DMA22_Address (dmc_txc_dma22_descriptor[43:0]), | |
3803 | .DMA22_Inc_Head (port1_DMA22_inc_head), | |
3804 | .DMA22_Reset_Done (port1_DMA22_reset_done), | |
3805 | .DMA22_Mark_Bit (port1_DMA22_mark_bit), | |
3806 | .DMA22_Inc_Pkt_Cnt (port1_DMA22_inc_pkt_cnt), | |
3807 | .SetGetNextDescDMA22 (port1_SetGetNextDescDMA22), | |
3808 | .DMA23_Active (dmc_txc_dma23_active), | |
3809 | .DMA23_EofList (dmc_txc_dma23_eoflist), | |
3810 | .DMA23_Error (dmc_txc_dma23_error), | |
3811 | .DMA23_CacheReady (dmc_txc_dma23_cacheready), | |
3812 | .DMA23_Partial (dmc_txc_dma23_partial), | |
3813 | .DMA23_Reset_Scheduled (dmc_txc_dma23_reset_scheduled), | |
3814 | .DMA23_GotNxtDesc (dmc_txc_dma23_gotnxtdesc), | |
3815 | .DMA23_Mark (dmc_txc_dma23_descriptor[62]), | |
3816 | .DMA23_SOP (dmc_txc_dma23_descriptor[63]), | |
3817 | .DMA23_Func_Num (dmc_txc_dma23_func_num), | |
3818 | .DMA23_DescList (dmc_txc_dma23_descriptor[61:58]), | |
3819 | .DMA23_Length (dmc_txc_dma23_descriptor[56:44]), | |
3820 | .DMA23_PageHandle (dmc_txc_dma23_page_handle), | |
3821 | .DMA23_Address (dmc_txc_dma23_descriptor[43:0]), | |
3822 | .DMA23_Inc_Head (port1_DMA23_inc_head), | |
3823 | .DMA23_Reset_Done (port1_DMA23_reset_done), | |
3824 | .DMA23_Mark_Bit (port1_DMA23_mark_bit), | |
3825 | .DMA23_Inc_Pkt_Cnt (port1_DMA23_inc_pkt_cnt), | |
3826 | .SetGetNextDescDMA23 (port1_SetGetNextDescDMA23), | |
3827 | ||
3828 | .DMA0_NewMaxBurst (dma0_NewMaxBurst), | |
3829 | .DMA1_NewMaxBurst (dma1_NewMaxBurst), | |
3830 | .DMA2_NewMaxBurst (dma2_NewMaxBurst), | |
3831 | .DMA3_NewMaxBurst (dma3_NewMaxBurst), | |
3832 | .DMA4_NewMaxBurst (dma4_NewMaxBurst), | |
3833 | .DMA5_NewMaxBurst (dma5_NewMaxBurst), | |
3834 | .DMA6_NewMaxBurst (dma6_NewMaxBurst), | |
3835 | .DMA7_NewMaxBurst (dma7_NewMaxBurst), | |
3836 | .DMA8_NewMaxBurst (dma8_NewMaxBurst), | |
3837 | .DMA9_NewMaxBurst (dma9_NewMaxBurst), | |
3838 | .DMA10_NewMaxBurst (dma10_NewMaxBurst), | |
3839 | .DMA11_NewMaxBurst (dma11_NewMaxBurst), | |
3840 | .DMA12_NewMaxBurst (dma12_NewMaxBurst), | |
3841 | .DMA13_NewMaxBurst (dma13_NewMaxBurst), | |
3842 | .DMA14_NewMaxBurst (dma14_NewMaxBurst), | |
3843 | .DMA15_NewMaxBurst (dma15_NewMaxBurst), | |
3844 | .DMA16_NewMaxBurst (dma16_NewMaxBurst), | |
3845 | .DMA17_NewMaxBurst (dma17_NewMaxBurst), | |
3846 | .DMA18_NewMaxBurst (dma18_NewMaxBurst), | |
3847 | .DMA19_NewMaxBurst (dma19_NewMaxBurst), | |
3848 | .DMA20_NewMaxBurst (dma20_NewMaxBurst), | |
3849 | .DMA21_NewMaxBurst (dma21_NewMaxBurst), | |
3850 | .DMA22_NewMaxBurst (dma22_NewMaxBurst), | |
3851 | .DMA23_NewMaxBurst (dma23_NewMaxBurst), | |
3852 | .DMA0_MaxBurst (dma0_MaxBurst), | |
3853 | .DMA1_MaxBurst (dma1_MaxBurst), | |
3854 | .DMA2_MaxBurst (dma2_MaxBurst), | |
3855 | .DMA3_MaxBurst (dma3_MaxBurst), | |
3856 | .DMA4_MaxBurst (dma4_MaxBurst), | |
3857 | .DMA5_MaxBurst (dma5_MaxBurst), | |
3858 | .DMA6_MaxBurst (dma6_MaxBurst), | |
3859 | .DMA7_MaxBurst (dma7_MaxBurst), | |
3860 | .DMA8_MaxBurst (dma8_MaxBurst), | |
3861 | .DMA9_MaxBurst (dma9_MaxBurst), | |
3862 | .DMA10_MaxBurst (dma10_MaxBurst), | |
3863 | .DMA11_MaxBurst (dma11_MaxBurst), | |
3864 | .DMA12_MaxBurst (dma12_MaxBurst), | |
3865 | .DMA13_MaxBurst (dma13_MaxBurst), | |
3866 | .DMA14_MaxBurst (dma14_MaxBurst), | |
3867 | .DMA15_MaxBurst (dma15_MaxBurst), | |
3868 | .DMA16_MaxBurst (dma16_MaxBurst), | |
3869 | .DMA17_MaxBurst (dma17_MaxBurst), | |
3870 | .DMA18_MaxBurst (dma18_MaxBurst), | |
3871 | .DMA19_MaxBurst (dma19_MaxBurst), | |
3872 | .DMA20_MaxBurst (dma20_MaxBurst), | |
3873 | .DMA21_MaxBurst (dma21_MaxBurst), | |
3874 | .DMA22_MaxBurst (dma22_MaxBurst), | |
3875 | .DMA23_MaxBurst (dma23_MaxBurst), | |
3876 | .MaxReorderNumber (port1_MaxReorderNumber), | |
3877 | .Port_DMA_List (port1_DMA_List), | |
3878 | .ClrMaxBurst (port1_clrMaxBurst), | |
3879 | .UpdateDMA (port1_UpdateDMA), | |
3880 | .UpdateDMALength (port1_UpdateDMALength), | |
3881 | .UpdateDMANumber (port1_UpdateDMANumber), | |
3882 | ||
3883 | .DMC_TXC_Req_Ack (arb1_txc_req_accept), | |
3884 | .DMC_TXC_Req_TransID (arb1_txc_req_transid), | |
3885 | ||
3886 | .Port_Selected (port_Selected[1]), | |
3887 | .Port_Request (port1_Request), | |
3888 | .Port_Request_Func_Num (port1_Request_Func_Num), | |
3889 | .Port_Request_DMA_Num (port1_Request_DMA_Num), | |
3890 | .Port_Request_Length (port1_Request_Length), | |
3891 | .Port_Request_Address (port1_Request_Address), | |
3892 | ||
3893 | .DMC_TXC_Resp_Rdy (dMC_TXC_Resp_Rdy), | |
3894 | .DMC_TXC_Resp_Complete (dMC_TXC_Resp_Complete), | |
3895 | .DMC_TXC_Trans_Complete (dMC_TXC_Trans_Complete), | |
3896 | .DMC_TXC_Resp_Data_Valid (dMC_TXC_Resp_Data_Valid), | |
3897 | .DMC_TXC_Resp_Client (dMC_TXC_Resp_Client), | |
3898 | .DMC_TXC_Resp_Port_Num (dMC_TXC_Resp_Port_Num), | |
3899 | .DMC_TXC_Resp_Cmd_Status (dMC_TXC_Resp_Cmd_Status), | |
3900 | .DMC_TXC_Resp_Data_Status (dMC_TXC_Resp_Data_Status), | |
3901 | .DMC_TXC_Resp_DMA_Num (dMC_TXC_Resp_DMA_Num), | |
3902 | .DMC_TXC_Resp_TransID (dMC_TXC_Resp_TransID), | |
3903 | .DMC_TXC_Resp_Cmd (dMC_TXC_Resp_Cmd), | |
3904 | .DMC_TXC_Resp_Data_Length (dMC_TXC_Resp_Data_Length), | |
3905 | .DMC_TXC_Resp_ByteEnables (dMC_TXC_Resp_ByteEnables), | |
3906 | .DMC_TXC_Resp_Address (dMC_TXC_Resp_Address), | |
3907 | .DMC_TXC_Resp_Data (dMC_TXC_Resp_Data), | |
3908 | .TXC_DMC_Resp_Accept (port1_TXC_DMC_Resp_Accept), | |
3909 | ||
3910 | .ReOrderFifoDataValid (port1_ReOrderFifoDataValid), | |
3911 | .ReOrderUnCorrectError (port1_ReOrder_UnCorrectError), | |
3912 | .ReOrderEccControl (port1_ReOrderEccControl), | |
3913 | .PacketAssyEngineDataIn (port1_PacketAssyEngineDataIn), | |
3914 | .ReOrderCorruptECCSingle (port1_ReOrderCorruptECCSingle), | |
3915 | .ReOrderCorruptECCDouble (port1_ReOrderCorruptECCDouble), | |
3916 | .ReOrderFifoWrite (port1_ReOrderFifoWrite), | |
3917 | .ReOrderFifoReadStrobe (port1_ReOrderFifoRead), | |
3918 | .ReOrderWritePtr (port1_ReOrderWritePtr), | |
3919 | .ReOrderReadPtr (port1_ReOrderReadPtr), | |
3920 | .ReOrderEngineDataOut (port1_ReOrderEngineDataOut), | |
3921 | ||
3922 | .StoreForwardUnCorrectError (port1_StoreForward_UnCorrectError), | |
3923 | .StoreForwardEccControl (port1_StoreForwardEccControl), | |
3924 | .MacXferEngineDataIn (port1_MacXferEngineDataIn), | |
3925 | .StoreForward_CorruptECCSingle (port1_StoreForwardCorruptECCSingle), | |
3926 | .StoreForward_CorruptECCDouble (port1_StoreForwardCorruptECCDouble), | |
3927 | .StoreForwardFifoWrite (port1_StoreForwardFifoWrite), | |
3928 | .StoreForwardFifoReadStrobe (port1_StoreForwardFifoRead), | |
3929 | .StoreForwardWritePtr (port1_StoreForwardWritePtr), | |
3930 | .StoreForwardReadPtr (port1_StoreForwardReadPtr), | |
3931 | .PacketAssyEngineDataOut (port1_PacketAssyEngineDataOut), | |
3932 | ||
3933 | .LatchActiveDMA (port1_LatchActiveDMA), | |
3934 | .ContextActiveList (port1_ContextActiveList), | |
3935 | ||
3936 | .Anchor_State (port1_Anchor_State), | |
3937 | .ReOrder_State (port1_ReOrder_State), | |
3938 | .Pointer_State (port1_Pointer_State), | |
3939 | .PacketAssy_State (port1_PacketAssy_State), | |
3940 | .DRR_ArbState (port1_DRR_ArbState), | |
3941 | .Mac_Xfer_State (port1_Mac_Xfer_State), | |
3942 | .DataPortReq_State (port1_DataPortReq_State), | |
3943 | .Sum_prt_state (port1_Sum_prt_state) | |
3944 | ); | |
3945 | ||
3946 | ||
3947 | niu_txc_ecc_engine port1_niu_txc_ecc_engine ( | |
3948 | .SysClk (niu_clk), | |
3949 | .Reset_L (reset_l), | |
3950 | .ReOrder_ClearEccError (port1_ReOrder_ClearEccError), | |
3951 | .WrReOrderEccState (port1_WrReOrderEccState), | |
3952 | .WrReOrderEccData0 (port1_WrReOrderEccData0), | |
3953 | .WrReOrderEccData1 (port1_WrReOrderEccData1), | |
3954 | .WrReOrderEccData2 (port1_WrReOrderEccData2), | |
3955 | .WrReOrderEccData3 (port1_WrReOrderEccData3), | |
3956 | .WrReOrderEccData4 (port1_WrReOrderEccData4), | |
3957 | .StoreForward_ClearEccError (port1_StoreForward_ClearEccError), | |
3958 | .WrStoreForwardEccState (port1_WrStoreForwardEccState), | |
3959 | .WrStoreForwardEccData0 (port1_WrStoreForwardEccData0), | |
3960 | .WrStoreForwardEccData1 (port1_WrStoreForwardEccData1), | |
3961 | .WrStoreForwardEccData2 (port1_WrStoreForwardEccData2), | |
3962 | .WrStoreForwardEccData3 (port1_WrStoreForwardEccData3), | |
3963 | .WrStoreForwardEccData4 (port1_WrStoreForwardEccData4), | |
3964 | .PioDataIn (port1_PioDataIn), | |
3965 | .ReOrder_ECC_State (port1_ReOrder_ECC_State), | |
3966 | .ReOrder_EccData (port1_ReOrder_EccData), | |
3967 | .StoreForward_ECC_State (port1_StoreForward_ECC_State), | |
3968 | .StoreForward_EccData (port1_StoreForward_EccData), | |
3969 | .ReOrder_CorruptECCSingle (port1_ReOrderCorruptECCSingle), | |
3970 | .ReOrder_CorruptECCDouble (port1_ReOrderCorruptECCDouble), | |
3971 | .ReOrder_FifoRead (port1_ReOrderFifoRead), | |
3972 | .ReOrder_ReadPtr (port1_ReOrderReadPtr), | |
3973 | .ReOrder_FifoDataOut (port1_ReOrderFifoDataOut), | |
3974 | .ReOrder_FifoDataValid (port1_ReOrderFifoDataValid), | |
3975 | .ReOrder_UnCorrectError (port1_ReOrder_UnCorrectError), | |
3976 | .ReOrder_PreECCData (port1_ReOrderEngineDataOut), | |
3977 | .ReOrder_PostECCData (port1_ReOrderFifoDataIn), | |
3978 | .ReOrder_CorrectedData (port1_PacketAssyEngineDataIn), | |
3979 | .StoreForward_CorruptECCSingle (port1_StoreForwardCorruptECCSingle), | |
3980 | .StoreForward_CorruptECCDouble (port1_StoreForwardCorruptECCDouble), | |
3981 | .StoreForward_FifoRead (port1_StoreForwardFifoRead), | |
3982 | .StoreForward_ReadPtr (port1_StoreForwardReadPtr), | |
3983 | .StoreForward_FifoDataOut (port1_StoreForwardFifoDataOut), | |
3984 | .StoreForward_UnCorrectError (port1_StoreForward_UnCorrectError), | |
3985 | .StoreForward_PreECCData (port1_PacketAssyEngineDataOut), | |
3986 | .StoreForward_PostECCData (port1_StoreForwardFifoDataIn), | |
3987 | .StoreForward_CorrectedData (port1_MacXferEngineDataIn) | |
3988 | ); | |
3989 | ||
3990 | ||
3991 | `ifdef NEPTUNE | |
3992 | niu_ram_1024_152 port1_RO_RAM ( | |
3993 | .clk (niu_clk), | |
3994 | .wt_enable (port1_ReOrderFifoWrite), | |
3995 | .cs_rd (port1_ReOrderFifoRead), | |
3996 | .addr_rd (port1_ReOrderReadPtr), | |
3997 | .addr_wt (port1_ReOrderWritePtr), | |
3998 | .data_inp (port1_ReOrderFifoDataIn), | |
3999 | .data_out (port1_ReOrderFifoDataOut) | |
4000 | ); | |
4001 | ||
4002 | niu_ram_640_152 port1_SF_RAM ( | |
4003 | .clk (niu_clk), | |
4004 | .wt_enable (port1_StoreForwardFifoWrite), | |
4005 | .cs_rd (port1_StoreForwardFifoRead), | |
4006 | .addr_rd (port1_StoreForwardReadPtr), | |
4007 | .addr_wt (port1_StoreForwardWritePtr), | |
4008 | .data_inp (port1_StoreForwardFifoDataIn), | |
4009 | .data_out (port1_StoreForwardFifoDataOut) | |
4010 | ); | |
4011 | `else | |
4012 | ||
4013 | niu_mb1 niu_txe1_1024_152_membist ( | |
4014 | .rst_l (reset_l), | |
4015 | .tcu_mbist_user_mode (tcu_mbist_user_mode), | |
4016 | .niu_mb1_xmit_store_rd_en (rtx_txc_txe1_mb1_xmit_store_rd_en), | |
4017 | .niu_mb1_xmit_store_wr_en (rtx_txc_txe1_mb1_xmit_store_wr_en), | |
4018 | .niu_mb1_xmit_realign_rd_en (rtx_txc_txe1_mb1_xmit_realign_rd_en), | |
4019 | .niu_mb1_xmit_realign_wr_en (rtx_txc_txe1_mb1_xmit_realign_wr_en), | |
4020 | .niu_mb1_addr (rtx_txc_txe1_mb1_addr), | |
4021 | .niu_mb1_wdata (rtx_txc_txe1_mb1_wdata), | |
4022 | .niu_mb1_run (rtx_txc_txe1_mb1_run), | |
4023 | .niu_mb1_xmit_store_data_out (port1_StoreForwardFifoDataOut), | |
4024 | .niu_mb1_xmit_realign_data_out (port1_ReOrderFifoDataOut), | |
4025 | .tcu_mbist_bisi_en (tcu_mbist_bisi_en), | |
4026 | .tcu_niu_mbist_start_1 (tcu_rtx_txc_txe1_mbist_start), | |
4027 | .niu_tcu_mbist_fail_1 (rtx_txc_txe1_tcu_mbist_fail), | |
4028 | .niu_tcu_mbist_done_1 (rtx_txc_txe1_tcu_mbist_done), | |
4029 | .l1clk (niu_clk), | |
4030 | .mb1_scan_out (rtx_txc_txe1_mbist_scan_out), | |
4031 | .mb1_scan_in (rtx_txc_txe1_mbist_scan_in), | |
4032 | .mb1_dmo_dout (rtx_txc_txe1_dmo_dout), | |
4033 | .tcu_aclk (tcu_aclk), | |
4034 | .tcu_bclk (tcu_bclk) | |
4035 | ); | |
4036 | ||
4037 | wire [151:0] concate_rtx_txc_txe1_mb1_wdata; | |
4038 | ||
4039 | assign concate_rtx_txc_txe1_mb1_wdata | |
4040 | = {rtx_txc_txe1_mb1_wdata, rtx_txc_txe1_mb1_wdata, | |
4041 | rtx_txc_txe1_mb1_wdata, rtx_txc_txe1_mb1_wdata, | |
4042 | rtx_txc_txe1_mb1_wdata, rtx_txc_txe1_mb1_wdata, | |
4043 | rtx_txc_txe1_mb1_wdata, rtx_txc_txe1_mb1_wdata, | |
4044 | rtx_txc_txe1_mb1_wdata, rtx_txc_txe1_mb1_wdata, | |
4045 | rtx_txc_txe1_mb1_wdata, rtx_txc_txe1_mb1_wdata, | |
4046 | rtx_txc_txe1_mb1_wdata, rtx_txc_txe1_mb1_wdata, | |
4047 | rtx_txc_txe1_mb1_wdata, rtx_txc_txe1_mb1_wdata, | |
4048 | rtx_txc_txe1_mb1_wdata, rtx_txc_txe1_mb1_wdata, | |
4049 | rtx_txc_txe1_mb1_wdata | |
4050 | }; | |
4051 | ||
4052 | niu_ram_1024_152 port1_RO_RAM ( | |
4053 | .clk (iol2clk), | |
4054 | .reset (sram_reset), | |
4055 | .tcu_aclk (tcu_aclk), | |
4056 | .tcu_bclk (tcu_bclk), | |
4057 | .tcu_se_scancollar_in (tcu_se_scancollar_in), | |
4058 | .tcu_se_scancollar_out (tcu_se_scancollar_out), | |
4059 | .tcu_scan_en (tcu_scan_en), | |
4060 | .tcu_array_wr_inhibit (tcu_array_wr_inhibit), | |
4061 | .scan_in (1'b0), | |
4062 | .scan_out (), | |
4063 | .hdr_sram_rvalue (hdr_sram_rvalue_txc1_re), | |
4064 | .hdr_sram_rid (hdr_sram_rid_txc1_re), | |
4065 | .hdr_sram_wr_en (hdr_sram_wr_en_txc1_re), | |
4066 | .hdr_sram_red_clr (hdr_sram_red_clr_txc1_re), | |
4067 | .sram_hdr_read_data (sram_hdr_read_data_txc1_re), | |
4068 | .mbi_wdata (concate_rtx_txc_txe1_mb1_wdata), | |
4069 | .mbi_rd_adr (rtx_txc_txe1_mb1_addr), | |
4070 | .mbi_wr_adr (rtx_txc_txe1_mb1_addr), | |
4071 | .mbi_wr_en (rtx_txc_txe1_mb1_xmit_realign_wr_en), | |
4072 | .mbi_rd_en (rtx_txc_txe1_mb1_xmit_realign_rd_en), | |
4073 | .mbi_run (rtx_txc_txe1_mb1_run), | |
4074 | .l2clk_2x (l2clk_2x), | |
4075 | .wt_enable (port1_ReOrderFifoWrite), | |
4076 | .cs_rd (port1_ReOrderFifoRead), | |
4077 | .addr_rd (port1_ReOrderReadPtr), | |
4078 | .addr_wt (port1_ReOrderWritePtr), | |
4079 | .data_inp (port1_ReOrderFifoDataIn), | |
4080 | .data_out (port1_ReOrderFifoDataOut) | |
4081 | ); | |
4082 | ||
4083 | niu_ram_1024_152 port1_SF_RAM ( | |
4084 | .clk (iol2clk), | |
4085 | .reset (sram_reset), | |
4086 | .tcu_aclk (tcu_aclk), | |
4087 | .tcu_bclk (tcu_bclk), | |
4088 | .tcu_se_scancollar_in (tcu_se_scancollar_in), | |
4089 | .tcu_se_scancollar_out (tcu_se_scancollar_out), | |
4090 | .tcu_scan_en (tcu_scan_en), | |
4091 | .tcu_array_wr_inhibit (tcu_array_wr_inhibit), | |
4092 | .scan_in (1'b0), | |
4093 | .scan_out (), | |
4094 | .hdr_sram_rvalue (hdr_sram_rvalue_txc1_st), | |
4095 | .hdr_sram_rid (hdr_sram_rid_txc1_st), | |
4096 | .hdr_sram_wr_en (hdr_sram_wr_en_txc1_st), | |
4097 | .hdr_sram_red_clr (hdr_sram_red_clr_txc1_st), | |
4098 | .sram_hdr_read_data (sram_hdr_read_data_txc1_st), | |
4099 | .mbi_wdata (concate_rtx_txc_txe1_mb1_wdata), | |
4100 | .mbi_rd_adr (rtx_txc_txe1_mb1_addr), | |
4101 | .mbi_wr_adr (rtx_txc_txe1_mb1_addr), | |
4102 | .mbi_wr_en (rtx_txc_txe1_mb1_xmit_store_wr_en), | |
4103 | .mbi_rd_en (rtx_txc_txe1_mb1_xmit_store_rd_en), | |
4104 | .mbi_run (rtx_txc_txe1_mb1_run), | |
4105 | .l2clk_2x (l2clk_2x), | |
4106 | .wt_enable (port1_StoreForwardFifoWrite), | |
4107 | .cs_rd (port1_StoreForwardFifoRead), | |
4108 | .addr_rd (port1_StoreForwardReadPtr), | |
4109 | .addr_wt (port1_StoreForwardWritePtr), | |
4110 | .data_inp (port1_StoreForwardFifoDataIn), | |
4111 | .data_out (port1_StoreForwardFifoDataOut) | |
4112 | ); | |
4113 | `endif | |
4114 | ||
4115 | ||
4116 | `ifdef NEPTUNE | |
4117 | ||
4118 | niu_txc_packetEngine #(REORDER_SIZE_1G, REORDER_PTR_1G) niu_txc_packetEngine2 ( | |
4119 | .SysClk (niu_clk), | |
4120 | .Reset_L (reset_l), | |
4121 | .PacketAssyDead (port2_PacketAssyDead), | |
4122 | .ReOrder_Error (port2_ReOrder_Error), | |
4123 | .Txc_Enabled (txc_Enabled), | |
4124 | .PortIndentifier (`PORT_TWO), | |
4125 | .EnableGMACMode (1'b1), | |
4126 | .MAC_Enabled (port2_Enabled), | |
4127 | .FlushEngine (flushEngine), | |
4128 | ||
4129 | .MAC_Req (port2_mac_req), | |
4130 | .MAC_Ack (txc_mac_ack2), | |
4131 | .MAC_Tag (txc_mac_tag2), | |
4132 | .MAC_Status (), | |
4133 | .MAC_Abort (), | |
4134 | .MAC_Data (txc_mac_data2), | |
4135 | ||
4136 | .TidsInUse (port2_TidsInUse), | |
4137 | .DuplicateTid (port2_DuplicateTid), | |
4138 | .UnInitializedTID (port2_UnInitializedTID), | |
4139 | .TimedoutTids (port2_TimedoutTids), | |
4140 | .ReOrderStateLogic (port2_ReOrderStateLogic), | |
4141 | .ReOrderStateControl (port2_ReOrderStateControl), | |
4142 | .ReOrderStateData0 (port2_ReOrderStateData0), | |
4143 | .ReOrderStateData1 (port2_ReOrderStateData1), | |
4144 | .ReOrderStateData2 (port2_ReOrderStateData2), | |
4145 | .ReOrderStateData3 (port2_ReOrderStateData3), | |
4146 | .WrTidsInUse (port2_WrTidsInUse), | |
4147 | .WrDuplicateTid (port2_WrDuplicateTid), | |
4148 | .WrUnInitializedTID (port2_WrUnInitializedTID), | |
4149 | .WrTimedoutTids (port2_WrTimedoutTids), | |
4150 | .WrReOrderStateLogic (port2_WrReOrderStateLogic), | |
4151 | .WrReOrderStateControl (port2_WrReOrderStateControl), | |
4152 | .WrReOrderStateData0 (port2_WrReOrderStateData0), | |
4153 | .WrReOrderStateData1 (port2_WrReOrderStateData1), | |
4154 | .WrReOrderStateData2 (port2_WrReOrderStateData2), | |
4155 | .WrReOrderStateData3 (port2_WrReOrderStateData3), | |
4156 | .PioDataIn (port2_PioDataIn), | |
4157 | ||
4158 | .ClearStatistics (port2_ClearStatistics), | |
4159 | .WrPacketStuffed (port2_WrPacketStuffed), | |
4160 | .WrPacketXmitted (port2_WrPacketXmitted), | |
4161 | .WrPacketRequested (port2_WrPacketRequested), | |
4162 | .GatherRequestCount (port2_GatherRequestCount), | |
4163 | .PacketRequestCount (port2_PacketRequestCount), | |
4164 | .PktErrAbortCount (port2_PktErrAbortCount), | |
4165 | .ReOrdersStuffed (port2_ReOrdersStuffed), | |
4166 | .PacketsStuffed (port2_PacketsStuffed), | |
4167 | .PacketsTransmitted (port2_PacketsTransmitted), | |
4168 | .BytesTransmitted (port2_BytesTransmitted), | |
4169 | ||
4170 | .Pkt_Size_Err (txc_dmc_p2_pkt_size_err), | |
4171 | .DMA_Pkt_Size_Err (txc_dmc_p2_dma_pkt_size_err), | |
4172 | .Pkt_Size_Err_Addr (txc_dmc_p2_pkt_size_err_addr), | |
4173 | ||
4174 | .Nack_Pkt_Rd (port2_Nack_Pkt_Rd), | |
4175 | .DMA_Nack_Pkt_Rd (port2_DMA_Nack_Pkt_Rd), | |
4176 | .Nack_Pkt_Rd_Addr (port2_Nack_Pkt_Rd_Addr), | |
4177 | ||
4178 | .DMA0_Active (dmc_txc_dma0_active), | |
4179 | .DMA0_EofList (dmc_txc_dma0_eoflist), | |
4180 | .DMA0_Error (dmc_txc_dma0_error), | |
4181 | .DMA0_CacheReady (dmc_txc_dma0_cacheready), | |
4182 | .DMA0_Partial (dmc_txc_dma0_partial), | |
4183 | .DMA0_Reset_Scheduled (dmc_txc_dma0_reset_scheduled), | |
4184 | .DMA0_GotNxtDesc (dmc_txc_dma0_gotnxtdesc), | |
4185 | .DMA0_Mark (dmc_txc_dma0_descriptor[62]), | |
4186 | .DMA0_SOP (dmc_txc_dma0_descriptor[63]), | |
4187 | .DMA0_Func_Num (dmc_txc_dma0_func_num), | |
4188 | .DMA0_DescList (dmc_txc_dma0_descriptor[61:58]), | |
4189 | .DMA0_Length (dmc_txc_dma0_descriptor[56:44]), | |
4190 | .DMA0_PageHandle (dmc_txc_dma0_page_handle), | |
4191 | .DMA0_Address (dmc_txc_dma0_descriptor[43:0]), | |
4192 | .DMA0_Inc_Head (port2_DMA0_inc_head), | |
4193 | .DMA0_Reset_Done (port2_DMA0_reset_done), | |
4194 | .DMA0_Mark_Bit (port2_DMA0_mark_bit), | |
4195 | .DMA0_Inc_Pkt_Cnt (port2_DMA0_inc_pkt_cnt), | |
4196 | .SetGetNextDescDMA0 (port2_SetGetNextDescDMA0), | |
4197 | .DMA1_Active (dmc_txc_dma1_active), | |
4198 | .DMA1_EofList (dmc_txc_dma1_eoflist), | |
4199 | .DMA1_Error (dmc_txc_dma1_error), | |
4200 | .DMA1_CacheReady (dmc_txc_dma1_cacheready), | |
4201 | .DMA1_Partial (dmc_txc_dma1_partial), | |
4202 | .DMA1_Reset_Scheduled (dmc_txc_dma1_reset_scheduled), | |
4203 | .DMA1_GotNxtDesc (dmc_txc_dma1_gotnxtdesc), | |
4204 | .DMA1_Mark (dmc_txc_dma1_descriptor[62]), | |
4205 | .DMA1_SOP (dmc_txc_dma1_descriptor[63]), | |
4206 | .DMA1_Func_Num (dmc_txc_dma1_func_num), | |
4207 | .DMA1_DescList (dmc_txc_dma1_descriptor[61:58]), | |
4208 | .DMA1_Length (dmc_txc_dma1_descriptor[56:44]), | |
4209 | .DMA1_PageHandle (dmc_txc_dma1_page_handle), | |
4210 | .DMA1_Address (dmc_txc_dma1_descriptor[43:0]), | |
4211 | .DMA1_Inc_Head (port2_DMA1_inc_head), | |
4212 | .DMA1_Reset_Done (port2_DMA1_reset_done), | |
4213 | .DMA1_Mark_Bit (port2_DMA1_mark_bit), | |
4214 | .DMA1_Inc_Pkt_Cnt (port2_DMA1_inc_pkt_cnt), | |
4215 | .SetGetNextDescDMA1 (port2_SetGetNextDescDMA1), | |
4216 | .DMA2_Active (dmc_txc_dma2_active), | |
4217 | .DMA2_EofList (dmc_txc_dma2_eoflist), | |
4218 | .DMA2_Error (dmc_txc_dma2_error), | |
4219 | .DMA2_CacheReady (dmc_txc_dma2_cacheready), | |
4220 | .DMA2_Partial (dmc_txc_dma2_partial), | |
4221 | .DMA2_Reset_Scheduled (dmc_txc_dma2_reset_scheduled), | |
4222 | .DMA2_GotNxtDesc (dmc_txc_dma2_gotnxtdesc), | |
4223 | .DMA2_Mark (dmc_txc_dma2_descriptor[62]), | |
4224 | .DMA2_SOP (dmc_txc_dma2_descriptor[63]), | |
4225 | .DMA2_Func_Num (dmc_txc_dma2_func_num), | |
4226 | .DMA2_DescList (dmc_txc_dma2_descriptor[61:58]), | |
4227 | .DMA2_Length (dmc_txc_dma2_descriptor[56:44]), | |
4228 | .DMA2_PageHandle (dmc_txc_dma2_page_handle), | |
4229 | .DMA2_Address (dmc_txc_dma2_descriptor[43:0]), | |
4230 | .DMA2_Inc_Head (port2_DMA2_inc_head), | |
4231 | .DMA2_Reset_Done (port2_DMA2_reset_done), | |
4232 | .DMA2_Mark_Bit (port2_DMA2_mark_bit), | |
4233 | .DMA2_Inc_Pkt_Cnt (port2_DMA2_inc_pkt_cnt), | |
4234 | .SetGetNextDescDMA2 (port2_SetGetNextDescDMA2), | |
4235 | .DMA3_Active (dmc_txc_dma3_active), | |
4236 | .DMA3_EofList (dmc_txc_dma3_eoflist), | |
4237 | .DMA3_Error (dmc_txc_dma3_error), | |
4238 | .DMA3_CacheReady (dmc_txc_dma3_cacheready), | |
4239 | .DMA3_Partial (dmc_txc_dma3_partial), | |
4240 | .DMA3_Reset_Scheduled (dmc_txc_dma3_reset_scheduled), | |
4241 | .DMA3_GotNxtDesc (dmc_txc_dma3_gotnxtdesc), | |
4242 | .DMA3_Mark (dmc_txc_dma3_descriptor[62]), | |
4243 | .DMA3_SOP (dmc_txc_dma3_descriptor[63]), | |
4244 | .DMA3_Func_Num (dmc_txc_dma3_func_num), | |
4245 | .DMA3_DescList (dmc_txc_dma3_descriptor[61:58]), | |
4246 | .DMA3_Length (dmc_txc_dma3_descriptor[56:44]), | |
4247 | .DMA3_PageHandle (dmc_txc_dma3_page_handle), | |
4248 | .DMA3_Address (dmc_txc_dma3_descriptor[43:0]), | |
4249 | .DMA3_Inc_Head (port2_DMA3_inc_head), | |
4250 | .DMA3_Reset_Done (port2_DMA3_reset_done), | |
4251 | .DMA3_Mark_Bit (port2_DMA3_mark_bit), | |
4252 | .DMA3_Inc_Pkt_Cnt (port2_DMA3_inc_pkt_cnt), | |
4253 | .SetGetNextDescDMA3 (port2_SetGetNextDescDMA3), | |
4254 | .DMA4_Active (dmc_txc_dma4_active), | |
4255 | .DMA4_EofList (dmc_txc_dma4_eoflist), | |
4256 | .DMA4_Error (dmc_txc_dma4_error), | |
4257 | .DMA4_CacheReady (dmc_txc_dma4_cacheready), | |
4258 | .DMA4_Partial (dmc_txc_dma4_partial), | |
4259 | .DMA4_Reset_Scheduled (dmc_txc_dma4_reset_scheduled), | |
4260 | .DMA4_GotNxtDesc (dmc_txc_dma4_gotnxtdesc), | |
4261 | .DMA4_Mark (dmc_txc_dma4_descriptor[62]), | |
4262 | .DMA4_SOP (dmc_txc_dma4_descriptor[63]), | |
4263 | .DMA4_Func_Num (dmc_txc_dma4_func_num), | |
4264 | .DMA4_DescList (dmc_txc_dma4_descriptor[61:58]), | |
4265 | .DMA4_Length (dmc_txc_dma4_descriptor[56:44]), | |
4266 | .DMA4_PageHandle (dmc_txc_dma4_page_handle), | |
4267 | .DMA4_Address (dmc_txc_dma4_descriptor[43:0]), | |
4268 | .DMA4_Inc_Head (port2_DMA4_inc_head), | |
4269 | .DMA4_Reset_Done (port2_DMA4_reset_done), | |
4270 | .DMA4_Mark_Bit (port2_DMA4_mark_bit), | |
4271 | .DMA4_Inc_Pkt_Cnt (port2_DMA4_inc_pkt_cnt), | |
4272 | .SetGetNextDescDMA4 (port2_SetGetNextDescDMA4), | |
4273 | .DMA5_Active (dmc_txc_dma5_active), | |
4274 | .DMA5_EofList (dmc_txc_dma5_eoflist), | |
4275 | .DMA5_Error (dmc_txc_dma5_error), | |
4276 | .DMA5_CacheReady (dmc_txc_dma5_cacheready), | |
4277 | .DMA5_Partial (dmc_txc_dma5_partial), | |
4278 | .DMA5_Reset_Scheduled (dmc_txc_dma5_reset_scheduled), | |
4279 | .DMA5_GotNxtDesc (dmc_txc_dma5_gotnxtdesc), | |
4280 | .DMA5_Mark (dmc_txc_dma5_descriptor[62]), | |
4281 | .DMA5_SOP (dmc_txc_dma5_descriptor[63]), | |
4282 | .DMA5_Func_Num (dmc_txc_dma5_func_num), | |
4283 | .DMA5_DescList (dmc_txc_dma5_descriptor[61:58]), | |
4284 | .DMA5_Length (dmc_txc_dma5_descriptor[56:44]), | |
4285 | .DMA5_PageHandle (dmc_txc_dma5_page_handle), | |
4286 | .DMA5_Address (dmc_txc_dma5_descriptor[43:0]), | |
4287 | .DMA5_Inc_Head (port2_DMA5_inc_head), | |
4288 | .DMA5_Reset_Done (port2_DMA5_reset_done), | |
4289 | .DMA5_Mark_Bit (port2_DMA5_mark_bit), | |
4290 | .DMA5_Inc_Pkt_Cnt (port2_DMA5_inc_pkt_cnt), | |
4291 | .SetGetNextDescDMA5 (port2_SetGetNextDescDMA5), | |
4292 | .DMA6_Active (dmc_txc_dma6_active), | |
4293 | .DMA6_EofList (dmc_txc_dma6_eoflist), | |
4294 | .DMA6_Error (dmc_txc_dma6_error), | |
4295 | .DMA6_CacheReady (dmc_txc_dma6_cacheready), | |
4296 | .DMA6_Partial (dmc_txc_dma6_partial), | |
4297 | .DMA6_Reset_Scheduled (dmc_txc_dma6_reset_scheduled), | |
4298 | .DMA6_GotNxtDesc (dmc_txc_dma6_gotnxtdesc), | |
4299 | .DMA6_Mark (dmc_txc_dma6_descriptor[62]), | |
4300 | .DMA6_SOP (dmc_txc_dma6_descriptor[63]), | |
4301 | .DMA6_Func_Num (dmc_txc_dma6_func_num), | |
4302 | .DMA6_DescList (dmc_txc_dma6_descriptor[61:58]), | |
4303 | .DMA6_Length (dmc_txc_dma6_descriptor[56:44]), | |
4304 | .DMA6_PageHandle (dmc_txc_dma6_page_handle), | |
4305 | .DMA6_Address (dmc_txc_dma6_descriptor[43:0]), | |
4306 | .DMA6_Inc_Head (port2_DMA6_inc_head), | |
4307 | .DMA6_Reset_Done (port2_DMA6_reset_done), | |
4308 | .DMA6_Mark_Bit (port2_DMA6_mark_bit), | |
4309 | .DMA6_Inc_Pkt_Cnt (port2_DMA6_inc_pkt_cnt), | |
4310 | .SetGetNextDescDMA6 (port2_SetGetNextDescDMA6), | |
4311 | .DMA7_Active (dmc_txc_dma7_active), | |
4312 | .DMA7_EofList (dmc_txc_dma7_eoflist), | |
4313 | .DMA7_Error (dmc_txc_dma7_error), | |
4314 | .DMA7_CacheReady (dmc_txc_dma7_cacheready), | |
4315 | .DMA7_Partial (dmc_txc_dma7_partial), | |
4316 | .DMA7_Reset_Scheduled (dmc_txc_dma7_reset_scheduled), | |
4317 | .DMA7_GotNxtDesc (dmc_txc_dma7_gotnxtdesc), | |
4318 | .DMA7_Mark (dmc_txc_dma7_descriptor[62]), | |
4319 | .DMA7_SOP (dmc_txc_dma7_descriptor[63]), | |
4320 | .DMA7_Func_Num (dmc_txc_dma7_func_num), | |
4321 | .DMA7_DescList (dmc_txc_dma7_descriptor[61:58]), | |
4322 | .DMA7_Length (dmc_txc_dma7_descriptor[56:44]), | |
4323 | .DMA7_PageHandle (dmc_txc_dma7_page_handle), | |
4324 | .DMA7_Address (dmc_txc_dma7_descriptor[43:0]), | |
4325 | .DMA7_Inc_Head (port2_DMA7_inc_head), | |
4326 | .DMA7_Reset_Done (port2_DMA7_reset_done), | |
4327 | .DMA7_Mark_Bit (port2_DMA7_mark_bit), | |
4328 | .DMA7_Inc_Pkt_Cnt (port2_DMA7_inc_pkt_cnt), | |
4329 | .SetGetNextDescDMA7 (port2_SetGetNextDescDMA7), | |
4330 | .DMA8_Active (dmc_txc_dma8_active), | |
4331 | .DMA8_EofList (dmc_txc_dma8_eoflist), | |
4332 | .DMA8_Error (dmc_txc_dma8_error), | |
4333 | .DMA8_CacheReady (dmc_txc_dma8_cacheready), | |
4334 | .DMA8_Partial (dmc_txc_dma8_partial), | |
4335 | .DMA8_Reset_Scheduled (dmc_txc_dma8_reset_scheduled), | |
4336 | .DMA8_GotNxtDesc (dmc_txc_dma8_gotnxtdesc), | |
4337 | .DMA8_Mark (dmc_txc_dma8_descriptor[62]), | |
4338 | .DMA8_SOP (dmc_txc_dma8_descriptor[63]), | |
4339 | .DMA8_Func_Num (dmc_txc_dma8_func_num), | |
4340 | .DMA8_DescList (dmc_txc_dma8_descriptor[61:58]), | |
4341 | .DMA8_Length (dmc_txc_dma8_descriptor[56:44]), | |
4342 | .DMA8_PageHandle (dmc_txc_dma8_page_handle), | |
4343 | .DMA8_Address (dmc_txc_dma8_descriptor[43:0]), | |
4344 | .DMA8_Inc_Head (port2_DMA8_inc_head), | |
4345 | .DMA8_Reset_Done (port2_DMA8_reset_done), | |
4346 | .DMA8_Mark_Bit (port2_DMA8_mark_bit), | |
4347 | .DMA8_Inc_Pkt_Cnt (port2_DMA8_inc_pkt_cnt), | |
4348 | .SetGetNextDescDMA8 (port2_SetGetNextDescDMA8), | |
4349 | .DMA9_Active (dmc_txc_dma9_active), | |
4350 | .DMA9_EofList (dmc_txc_dma9_eoflist), | |
4351 | .DMA9_Error (dmc_txc_dma9_error), | |
4352 | .DMA9_CacheReady (dmc_txc_dma9_cacheready), | |
4353 | .DMA9_Partial (dmc_txc_dma9_partial), | |
4354 | .DMA9_Reset_Scheduled (dmc_txc_dma9_reset_scheduled), | |
4355 | .DMA9_GotNxtDesc (dmc_txc_dma9_gotnxtdesc), | |
4356 | .DMA9_Mark (dmc_txc_dma9_descriptor[62]), | |
4357 | .DMA9_SOP (dmc_txc_dma9_descriptor[63]), | |
4358 | .DMA9_Func_Num (dmc_txc_dma9_func_num), | |
4359 | .DMA9_DescList (dmc_txc_dma9_descriptor[61:58]), | |
4360 | .DMA9_Length (dmc_txc_dma9_descriptor[56:44]), | |
4361 | .DMA9_PageHandle (dmc_txc_dma9_page_handle), | |
4362 | .DMA9_Address (dmc_txc_dma9_descriptor[43:0]), | |
4363 | .DMA9_Inc_Head (port2_DMA9_inc_head), | |
4364 | .DMA9_Reset_Done (port2_DMA9_reset_done), | |
4365 | .DMA9_Mark_Bit (port2_DMA9_mark_bit), | |
4366 | .DMA9_Inc_Pkt_Cnt (port2_DMA9_inc_pkt_cnt), | |
4367 | .SetGetNextDescDMA9 (port2_SetGetNextDescDMA9), | |
4368 | .DMA10_Active (dmc_txc_dma10_active), | |
4369 | .DMA10_EofList (dmc_txc_dma10_eoflist), | |
4370 | .DMA10_Error (dmc_txc_dma10_error), | |
4371 | .DMA10_CacheReady (dmc_txc_dma10_cacheready), | |
4372 | .DMA10_Partial (dmc_txc_dma10_partial), | |
4373 | .DMA10_Reset_Scheduled (dmc_txc_dma10_reset_scheduled), | |
4374 | .DMA10_GotNxtDesc (dmc_txc_dma10_gotnxtdesc), | |
4375 | .DMA10_Mark (dmc_txc_dma10_descriptor[62]), | |
4376 | .DMA10_SOP (dmc_txc_dma10_descriptor[63]), | |
4377 | .DMA10_Func_Num (dmc_txc_dma10_func_num), | |
4378 | .DMA10_DescList (dmc_txc_dma10_descriptor[61:58]), | |
4379 | .DMA10_Length (dmc_txc_dma10_descriptor[56:44]), | |
4380 | .DMA10_PageHandle (dmc_txc_dma10_page_handle), | |
4381 | .DMA10_Address (dmc_txc_dma10_descriptor[43:0]), | |
4382 | .DMA10_Inc_Head (port2_DMA10_inc_head), | |
4383 | .DMA10_Reset_Done (port2_DMA10_reset_done), | |
4384 | .DMA10_Mark_Bit (port2_DMA10_mark_bit), | |
4385 | .DMA10_Inc_Pkt_Cnt (port2_DMA10_inc_pkt_cnt), | |
4386 | .SetGetNextDescDMA10 (port2_SetGetNextDescDMA10), | |
4387 | .DMA11_Active (dmc_txc_dma11_active), | |
4388 | .DMA11_EofList (dmc_txc_dma11_eoflist), | |
4389 | .DMA11_Error (dmc_txc_dma11_error), | |
4390 | .DMA11_CacheReady (dmc_txc_dma11_cacheready), | |
4391 | .DMA11_Partial (dmc_txc_dma11_partial), | |
4392 | .DMA11_Reset_Scheduled (dmc_txc_dma11_reset_scheduled), | |
4393 | .DMA11_GotNxtDesc (dmc_txc_dma11_gotnxtdesc), | |
4394 | .DMA11_Mark (dmc_txc_dma11_descriptor[62]), | |
4395 | .DMA11_SOP (dmc_txc_dma11_descriptor[63]), | |
4396 | .DMA11_Func_Num (dmc_txc_dma11_func_num), | |
4397 | .DMA11_DescList (dmc_txc_dma11_descriptor[61:58]), | |
4398 | .DMA11_Length (dmc_txc_dma11_descriptor[56:44]), | |
4399 | .DMA11_PageHandle (dmc_txc_dma11_page_handle), | |
4400 | .DMA11_Address (dmc_txc_dma11_descriptor[43:0]), | |
4401 | .DMA11_Inc_Head (port2_DMA11_inc_head), | |
4402 | .DMA11_Reset_Done (port2_DMA11_reset_done), | |
4403 | .DMA11_Mark_Bit (port2_DMA11_mark_bit), | |
4404 | .DMA11_Inc_Pkt_Cnt (port2_DMA11_inc_pkt_cnt), | |
4405 | .SetGetNextDescDMA11 (port2_SetGetNextDescDMA11), | |
4406 | .DMA12_Active (dmc_txc_dma12_active), | |
4407 | .DMA12_EofList (dmc_txc_dma12_eoflist), | |
4408 | .DMA12_Error (dmc_txc_dma12_error), | |
4409 | .DMA12_CacheReady (dmc_txc_dma12_cacheready), | |
4410 | .DMA12_Partial (dmc_txc_dma12_partial), | |
4411 | .DMA12_Reset_Scheduled (dmc_txc_dma12_reset_scheduled), | |
4412 | .DMA12_GotNxtDesc (dmc_txc_dma12_gotnxtdesc), | |
4413 | .DMA12_Mark (dmc_txc_dma12_descriptor[62]), | |
4414 | .DMA12_SOP (dmc_txc_dma12_descriptor[63]), | |
4415 | .DMA12_Func_Num (dmc_txc_dma12_func_num), | |
4416 | .DMA12_DescList (dmc_txc_dma12_descriptor[61:58]), | |
4417 | .DMA12_Length (dmc_txc_dma12_descriptor[56:44]), | |
4418 | .DMA12_PageHandle (dmc_txc_dma12_page_handle), | |
4419 | .DMA12_Address (dmc_txc_dma12_descriptor[43:0]), | |
4420 | .DMA12_Inc_Head (port2_DMA12_inc_head), | |
4421 | .DMA12_Reset_Done (port2_DMA12_reset_done), | |
4422 | .DMA12_Mark_Bit (port2_DMA12_mark_bit), | |
4423 | .DMA12_Inc_Pkt_Cnt (port2_DMA12_inc_pkt_cnt), | |
4424 | .SetGetNextDescDMA12 (port2_SetGetNextDescDMA12), | |
4425 | .DMA13_Active (dmc_txc_dma13_active), | |
4426 | .DMA13_EofList (dmc_txc_dma13_eoflist), | |
4427 | .DMA13_Error (dmc_txc_dma13_error), | |
4428 | .DMA13_CacheReady (dmc_txc_dma13_cacheready), | |
4429 | .DMA13_Partial (dmc_txc_dma13_partial), | |
4430 | .DMA13_Reset_Scheduled (dmc_txc_dma13_reset_scheduled), | |
4431 | .DMA13_GotNxtDesc (dmc_txc_dma13_gotnxtdesc), | |
4432 | .DMA13_Mark (dmc_txc_dma13_descriptor[62]), | |
4433 | .DMA13_SOP (dmc_txc_dma13_descriptor[63]), | |
4434 | .DMA13_Func_Num (dmc_txc_dma13_func_num), | |
4435 | .DMA13_DescList (dmc_txc_dma13_descriptor[61:58]), | |
4436 | .DMA13_Length (dmc_txc_dma13_descriptor[56:44]), | |
4437 | .DMA13_PageHandle (dmc_txc_dma13_page_handle), | |
4438 | .DMA13_Address (dmc_txc_dma13_descriptor[43:0]), | |
4439 | .DMA13_Inc_Head (port2_DMA13_inc_head), | |
4440 | .DMA13_Reset_Done (port2_DMA13_reset_done), | |
4441 | .DMA13_Mark_Bit (port2_DMA13_mark_bit), | |
4442 | .DMA13_Inc_Pkt_Cnt (port2_DMA13_inc_pkt_cnt), | |
4443 | .SetGetNextDescDMA13 (port2_SetGetNextDescDMA13), | |
4444 | .DMA14_Active (dmc_txc_dma14_active), | |
4445 | .DMA14_EofList (dmc_txc_dma14_eoflist), | |
4446 | .DMA14_Error (dmc_txc_dma14_error), | |
4447 | .DMA14_CacheReady (dmc_txc_dma14_cacheready), | |
4448 | .DMA14_Partial (dmc_txc_dma14_partial), | |
4449 | .DMA14_Reset_Scheduled (dmc_txc_dma14_reset_scheduled), | |
4450 | .DMA14_GotNxtDesc (dmc_txc_dma14_gotnxtdesc), | |
4451 | .DMA14_Mark (dmc_txc_dma14_descriptor[62]), | |
4452 | .DMA14_SOP (dmc_txc_dma14_descriptor[63]), | |
4453 | .DMA14_Func_Num (dmc_txc_dma14_func_num), | |
4454 | .DMA14_DescList (dmc_txc_dma14_descriptor[61:58]), | |
4455 | .DMA14_Length (dmc_txc_dma14_descriptor[56:44]), | |
4456 | .DMA14_PageHandle (dmc_txc_dma14_page_handle), | |
4457 | .DMA14_Address (dmc_txc_dma14_descriptor[43:0]), | |
4458 | .DMA14_Inc_Head (port2_DMA14_inc_head), | |
4459 | .DMA14_Reset_Done (port2_DMA14_reset_done), | |
4460 | .DMA14_Mark_Bit (port2_DMA14_mark_bit), | |
4461 | .DMA14_Inc_Pkt_Cnt (port2_DMA14_inc_pkt_cnt), | |
4462 | .SetGetNextDescDMA14 (port2_SetGetNextDescDMA14), | |
4463 | .DMA15_Active (dmc_txc_dma15_active), | |
4464 | .DMA15_EofList (dmc_txc_dma15_eoflist), | |
4465 | .DMA15_Error (dmc_txc_dma15_error), | |
4466 | .DMA15_CacheReady (dmc_txc_dma15_cacheready), | |
4467 | .DMA15_Partial (dmc_txc_dma15_partial), | |
4468 | .DMA15_Reset_Scheduled (dmc_txc_dma15_reset_scheduled), | |
4469 | .DMA15_GotNxtDesc (dmc_txc_dma15_gotnxtdesc), | |
4470 | .DMA15_Mark (dmc_txc_dma15_descriptor[62]), | |
4471 | .DMA15_SOP (dmc_txc_dma15_descriptor[63]), | |
4472 | .DMA15_Func_Num (dmc_txc_dma15_func_num), | |
4473 | .DMA15_DescList (dmc_txc_dma15_descriptor[61:58]), | |
4474 | .DMA15_Length (dmc_txc_dma15_descriptor[56:44]), | |
4475 | .DMA15_PageHandle (dmc_txc_dma15_page_handle), | |
4476 | .DMA15_Address (dmc_txc_dma15_descriptor[43:0]), | |
4477 | .DMA15_Inc_Head (port2_DMA15_inc_head), | |
4478 | .DMA15_Reset_Done (port2_DMA15_reset_done), | |
4479 | .DMA15_Mark_Bit (port2_DMA15_mark_bit), | |
4480 | .DMA15_Inc_Pkt_Cnt (port2_DMA15_inc_pkt_cnt), | |
4481 | .SetGetNextDescDMA15 (port2_SetGetNextDescDMA15), | |
4482 | .DMA16_Active (dmc_txc_dma16_active), | |
4483 | .DMA16_EofList (dmc_txc_dma16_eoflist), | |
4484 | .DMA16_Error (dmc_txc_dma16_error), | |
4485 | .DMA16_CacheReady (dmc_txc_dma16_cacheready), | |
4486 | .DMA16_Partial (dmc_txc_dma16_partial), | |
4487 | .DMA16_Reset_Scheduled (dmc_txc_dma16_reset_scheduled), | |
4488 | .DMA16_GotNxtDesc (dmc_txc_dma16_gotnxtdesc), | |
4489 | .DMA16_Mark (dmc_txc_dma16_descriptor[62]), | |
4490 | .DMA16_SOP (dmc_txc_dma16_descriptor[63]), | |
4491 | .DMA16_Func_Num (dmc_txc_dma16_func_num), | |
4492 | .DMA16_DescList (dmc_txc_dma16_descriptor[61:58]), | |
4493 | .DMA16_Length (dmc_txc_dma16_descriptor[56:44]), | |
4494 | .DMA16_PageHandle (dmc_txc_dma16_page_handle), | |
4495 | .DMA16_Address (dmc_txc_dma16_descriptor[43:0]), | |
4496 | .DMA16_Inc_Head (port2_DMA16_inc_head), | |
4497 | .DMA16_Reset_Done (port2_DMA16_reset_done), | |
4498 | .DMA16_Mark_Bit (port2_DMA16_mark_bit), | |
4499 | .DMA16_Inc_Pkt_Cnt (port2_DMA16_inc_pkt_cnt), | |
4500 | .SetGetNextDescDMA16 (port2_SetGetNextDescDMA16), | |
4501 | .DMA17_Active (dmc_txc_dma17_active), | |
4502 | .DMA17_EofList (dmc_txc_dma17_eoflist), | |
4503 | .DMA17_Error (dmc_txc_dma17_error), | |
4504 | .DMA17_CacheReady (dmc_txc_dma17_cacheready), | |
4505 | .DMA17_Partial (dmc_txc_dma17_partial), | |
4506 | .DMA17_Reset_Scheduled (dmc_txc_dma17_reset_scheduled), | |
4507 | .DMA17_GotNxtDesc (dmc_txc_dma17_gotnxtdesc), | |
4508 | .DMA17_Mark (dmc_txc_dma17_descriptor[62]), | |
4509 | .DMA17_SOP (dmc_txc_dma17_descriptor[63]), | |
4510 | .DMA17_Func_Num (dmc_txc_dma17_func_num), | |
4511 | .DMA17_DescList (dmc_txc_dma17_descriptor[61:58]), | |
4512 | .DMA17_Length (dmc_txc_dma17_descriptor[56:44]), | |
4513 | .DMA17_PageHandle (dmc_txc_dma17_page_handle), | |
4514 | .DMA17_Address (dmc_txc_dma17_descriptor[43:0]), | |
4515 | .DMA17_Inc_Head (port2_DMA17_inc_head), | |
4516 | .DMA17_Reset_Done (port2_DMA17_reset_done), | |
4517 | .DMA17_Mark_Bit (port2_DMA17_mark_bit), | |
4518 | .DMA17_Inc_Pkt_Cnt (port2_DMA17_inc_pkt_cnt), | |
4519 | .SetGetNextDescDMA17 (port2_SetGetNextDescDMA17), | |
4520 | .DMA18_Active (dmc_txc_dma18_active), | |
4521 | .DMA18_EofList (dmc_txc_dma18_eoflist), | |
4522 | .DMA18_Error (dmc_txc_dma18_error), | |
4523 | .DMA18_CacheReady (dmc_txc_dma18_cacheready), | |
4524 | .DMA18_Partial (dmc_txc_dma18_partial), | |
4525 | .DMA18_Reset_Scheduled (dmc_txc_dma18_reset_scheduled), | |
4526 | .DMA18_GotNxtDesc (dmc_txc_dma18_gotnxtdesc), | |
4527 | .DMA18_Mark (dmc_txc_dma18_descriptor[62]), | |
4528 | .DMA18_SOP (dmc_txc_dma18_descriptor[63]), | |
4529 | .DMA18_Func_Num (dmc_txc_dma18_func_num), | |
4530 | .DMA18_DescList (dmc_txc_dma18_descriptor[61:58]), | |
4531 | .DMA18_Length (dmc_txc_dma18_descriptor[56:44]), | |
4532 | .DMA18_PageHandle (dmc_txc_dma18_page_handle), | |
4533 | .DMA18_Address (dmc_txc_dma18_descriptor[43:0]), | |
4534 | .DMA18_Inc_Head (port2_DMA18_inc_head), | |
4535 | .DMA18_Reset_Done (port2_DMA18_reset_done), | |
4536 | .DMA18_Mark_Bit (port2_DMA18_mark_bit), | |
4537 | .DMA18_Inc_Pkt_Cnt (port2_DMA18_inc_pkt_cnt), | |
4538 | .SetGetNextDescDMA18 (port2_SetGetNextDescDMA18), | |
4539 | .DMA19_Active (dmc_txc_dma19_active), | |
4540 | .DMA19_EofList (dmc_txc_dma19_eoflist), | |
4541 | .DMA19_Error (dmc_txc_dma19_error), | |
4542 | .DMA19_CacheReady (dmc_txc_dma19_cacheready), | |
4543 | .DMA19_Partial (dmc_txc_dma19_partial), | |
4544 | .DMA19_Reset_Scheduled (dmc_txc_dma19_reset_scheduled), | |
4545 | .DMA19_GotNxtDesc (dmc_txc_dma19_gotnxtdesc), | |
4546 | .DMA19_Mark (dmc_txc_dma19_descriptor[62]), | |
4547 | .DMA19_SOP (dmc_txc_dma19_descriptor[63]), | |
4548 | .DMA19_Func_Num (dmc_txc_dma19_func_num), | |
4549 | .DMA19_DescList (dmc_txc_dma19_descriptor[61:58]), | |
4550 | .DMA19_Length (dmc_txc_dma19_descriptor[56:44]), | |
4551 | .DMA19_PageHandle (dmc_txc_dma19_page_handle), | |
4552 | .DMA19_Address (dmc_txc_dma19_descriptor[43:0]), | |
4553 | .DMA19_Inc_Head (port2_DMA19_inc_head), | |
4554 | .DMA19_Reset_Done (port2_DMA19_reset_done), | |
4555 | .DMA19_Mark_Bit (port2_DMA19_mark_bit), | |
4556 | .DMA19_Inc_Pkt_Cnt (port2_DMA19_inc_pkt_cnt), | |
4557 | .SetGetNextDescDMA19 (port2_SetGetNextDescDMA19), | |
4558 | .DMA20_Active (dmc_txc_dma20_active), | |
4559 | .DMA20_EofList (dmc_txc_dma20_eoflist), | |
4560 | .DMA20_Error (dmc_txc_dma20_error), | |
4561 | .DMA20_CacheReady (dmc_txc_dma20_cacheready), | |
4562 | .DMA20_Partial (dmc_txc_dma20_partial), | |
4563 | .DMA20_Reset_Scheduled (dmc_txc_dma20_reset_scheduled), | |
4564 | .DMA20_GotNxtDesc (dmc_txc_dma20_gotnxtdesc), | |
4565 | .DMA20_Mark (dmc_txc_dma20_descriptor[62]), | |
4566 | .DMA20_SOP (dmc_txc_dma20_descriptor[63]), | |
4567 | .DMA20_Func_Num (dmc_txc_dma20_func_num), | |
4568 | .DMA20_DescList (dmc_txc_dma20_descriptor[61:58]), | |
4569 | .DMA20_Length (dmc_txc_dma20_descriptor[56:44]), | |
4570 | .DMA20_PageHandle (dmc_txc_dma20_page_handle), | |
4571 | .DMA20_Address (dmc_txc_dma20_descriptor[43:0]), | |
4572 | .DMA20_Inc_Head (port2_DMA20_inc_head), | |
4573 | .DMA20_Reset_Done (port2_DMA20_reset_done), | |
4574 | .DMA20_Mark_Bit (port2_DMA20_mark_bit), | |
4575 | .DMA20_Inc_Pkt_Cnt (port2_DMA20_inc_pkt_cnt), | |
4576 | .SetGetNextDescDMA20 (port2_SetGetNextDescDMA20), | |
4577 | .DMA21_Active (dmc_txc_dma21_active), | |
4578 | .DMA21_EofList (dmc_txc_dma21_eoflist), | |
4579 | .DMA21_Error (dmc_txc_dma21_error), | |
4580 | .DMA21_CacheReady (dmc_txc_dma21_cacheready), | |
4581 | .DMA21_Partial (dmc_txc_dma21_partial), | |
4582 | .DMA21_Reset_Scheduled (dmc_txc_dma21_reset_scheduled), | |
4583 | .DMA21_GotNxtDesc (dmc_txc_dma21_gotnxtdesc), | |
4584 | .DMA21_Mark (dmc_txc_dma21_descriptor[62]), | |
4585 | .DMA21_SOP (dmc_txc_dma21_descriptor[63]), | |
4586 | .DMA21_Func_Num (dmc_txc_dma21_func_num), | |
4587 | .DMA21_DescList (dmc_txc_dma21_descriptor[61:58]), | |
4588 | .DMA21_Length (dmc_txc_dma21_descriptor[56:44]), | |
4589 | .DMA21_PageHandle (dmc_txc_dma21_page_handle), | |
4590 | .DMA21_Address (dmc_txc_dma21_descriptor[43:0]), | |
4591 | .DMA21_Inc_Head (port2_DMA21_inc_head), | |
4592 | .DMA21_Reset_Done (port2_DMA21_reset_done), | |
4593 | .DMA21_Mark_Bit (port2_DMA21_mark_bit), | |
4594 | .DMA21_Inc_Pkt_Cnt (port2_DMA21_inc_pkt_cnt), | |
4595 | .SetGetNextDescDMA21 (port2_SetGetNextDescDMA21), | |
4596 | .DMA22_Active (dmc_txc_dma22_active), | |
4597 | .DMA22_EofList (dmc_txc_dma22_eoflist), | |
4598 | .DMA22_Error (dmc_txc_dma22_error), | |
4599 | .DMA22_CacheReady (dmc_txc_dma22_cacheready), | |
4600 | .DMA22_Partial (dmc_txc_dma22_partial), | |
4601 | .DMA22_Reset_Scheduled (dmc_txc_dma22_reset_scheduled), | |
4602 | .DMA22_GotNxtDesc (dmc_txc_dma22_gotnxtdesc), | |
4603 | .DMA22_Mark (dmc_txc_dma22_descriptor[62]), | |
4604 | .DMA22_SOP (dmc_txc_dma22_descriptor[63]), | |
4605 | .DMA22_Func_Num (dmc_txc_dma22_func_num), | |
4606 | .DMA22_DescList (dmc_txc_dma22_descriptor[61:58]), | |
4607 | .DMA22_Length (dmc_txc_dma22_descriptor[56:44]), | |
4608 | .DMA22_PageHandle (dmc_txc_dma22_page_handle), | |
4609 | .DMA22_Address (dmc_txc_dma22_descriptor[43:0]), | |
4610 | .DMA22_Inc_Head (port2_DMA22_inc_head), | |
4611 | .DMA22_Reset_Done (port2_DMA22_reset_done), | |
4612 | .DMA22_Mark_Bit (port2_DMA22_mark_bit), | |
4613 | .DMA22_Inc_Pkt_Cnt (port2_DMA22_inc_pkt_cnt), | |
4614 | .SetGetNextDescDMA22 (port2_SetGetNextDescDMA22), | |
4615 | .DMA23_Active (dmc_txc_dma23_active), | |
4616 | .DMA23_EofList (dmc_txc_dma23_eoflist), | |
4617 | .DMA23_Error (dmc_txc_dma23_error), | |
4618 | .DMA23_CacheReady (dmc_txc_dma23_cacheready), | |
4619 | .DMA23_Partial (dmc_txc_dma23_partial), | |
4620 | .DMA23_Reset_Scheduled (dmc_txc_dma23_reset_scheduled), | |
4621 | .DMA23_GotNxtDesc (dmc_txc_dma23_gotnxtdesc), | |
4622 | .DMA23_Mark (dmc_txc_dma23_descriptor[62]), | |
4623 | .DMA23_SOP (dmc_txc_dma23_descriptor[63]), | |
4624 | .DMA23_Func_Num (dmc_txc_dma23_func_num), | |
4625 | .DMA23_DescList (dmc_txc_dma23_descriptor[61:58]), | |
4626 | .DMA23_Length (dmc_txc_dma23_descriptor[56:44]), | |
4627 | .DMA23_PageHandle (dmc_txc_dma23_page_handle), | |
4628 | .DMA23_Address (dmc_txc_dma23_descriptor[43:0]), | |
4629 | .DMA23_Inc_Head (port2_DMA23_inc_head), | |
4630 | .DMA23_Reset_Done (port2_DMA23_reset_done), | |
4631 | .DMA23_Mark_Bit (port2_DMA23_mark_bit), | |
4632 | .DMA23_Inc_Pkt_Cnt (port2_DMA23_inc_pkt_cnt), | |
4633 | .SetGetNextDescDMA23 (port2_SetGetNextDescDMA23), | |
4634 | ||
4635 | .DMA0_NewMaxBurst (dma0_NewMaxBurst), | |
4636 | .DMA1_NewMaxBurst (dma1_NewMaxBurst), | |
4637 | .DMA2_NewMaxBurst (dma2_NewMaxBurst), | |
4638 | .DMA3_NewMaxBurst (dma3_NewMaxBurst), | |
4639 | .DMA4_NewMaxBurst (dma4_NewMaxBurst), | |
4640 | .DMA5_NewMaxBurst (dma5_NewMaxBurst), | |
4641 | .DMA6_NewMaxBurst (dma6_NewMaxBurst), | |
4642 | .DMA7_NewMaxBurst (dma7_NewMaxBurst), | |
4643 | .DMA8_NewMaxBurst (dma8_NewMaxBurst), | |
4644 | .DMA9_NewMaxBurst (dma9_NewMaxBurst), | |
4645 | .DMA10_NewMaxBurst (dma10_NewMaxBurst), | |
4646 | .DMA11_NewMaxBurst (dma11_NewMaxBurst), | |
4647 | .DMA12_NewMaxBurst (dma12_NewMaxBurst), | |
4648 | .DMA13_NewMaxBurst (dma13_NewMaxBurst), | |
4649 | .DMA14_NewMaxBurst (dma14_NewMaxBurst), | |
4650 | .DMA15_NewMaxBurst (dma15_NewMaxBurst), | |
4651 | .DMA16_NewMaxBurst (dma16_NewMaxBurst), | |
4652 | .DMA17_NewMaxBurst (dma17_NewMaxBurst), | |
4653 | .DMA18_NewMaxBurst (dma18_NewMaxBurst), | |
4654 | .DMA19_NewMaxBurst (dma19_NewMaxBurst), | |
4655 | .DMA20_NewMaxBurst (dma20_NewMaxBurst), | |
4656 | .DMA21_NewMaxBurst (dma21_NewMaxBurst), | |
4657 | .DMA22_NewMaxBurst (dma22_NewMaxBurst), | |
4658 | .DMA23_NewMaxBurst (dma23_NewMaxBurst), | |
4659 | .DMA0_MaxBurst (dma0_MaxBurst), | |
4660 | .DMA1_MaxBurst (dma1_MaxBurst), | |
4661 | .DMA2_MaxBurst (dma2_MaxBurst), | |
4662 | .DMA3_MaxBurst (dma3_MaxBurst), | |
4663 | .DMA4_MaxBurst (dma4_MaxBurst), | |
4664 | .DMA5_MaxBurst (dma5_MaxBurst), | |
4665 | .DMA6_MaxBurst (dma6_MaxBurst), | |
4666 | .DMA7_MaxBurst (dma7_MaxBurst), | |
4667 | .DMA8_MaxBurst (dma8_MaxBurst), | |
4668 | .DMA9_MaxBurst (dma9_MaxBurst), | |
4669 | .DMA10_MaxBurst (dma10_MaxBurst), | |
4670 | .DMA11_MaxBurst (dma11_MaxBurst), | |
4671 | .DMA12_MaxBurst (dma12_MaxBurst), | |
4672 | .DMA13_MaxBurst (dma13_MaxBurst), | |
4673 | .DMA14_MaxBurst (dma14_MaxBurst), | |
4674 | .DMA15_MaxBurst (dma15_MaxBurst), | |
4675 | .DMA16_MaxBurst (dma16_MaxBurst), | |
4676 | .DMA17_MaxBurst (dma17_MaxBurst), | |
4677 | .DMA18_MaxBurst (dma18_MaxBurst), | |
4678 | .DMA19_MaxBurst (dma19_MaxBurst), | |
4679 | .DMA20_MaxBurst (dma20_MaxBurst), | |
4680 | .DMA21_MaxBurst (dma21_MaxBurst), | |
4681 | .DMA22_MaxBurst (dma22_MaxBurst), | |
4682 | .DMA23_MaxBurst (dma23_MaxBurst), | |
4683 | .MaxReorderNumber (port2_MaxReorderNumber), | |
4684 | .Port_DMA_List (port2_DMA_List), | |
4685 | .ClrMaxBurst (port2_clrMaxBurst), | |
4686 | .UpdateDMA (port2_UpdateDMA), | |
4687 | .UpdateDMALength (port2_UpdateDMALength), | |
4688 | .UpdateDMANumber (port2_UpdateDMANumber), | |
4689 | ||
4690 | .DMC_TXC_Req_Ack (arb1_txc_req_accept), | |
4691 | .DMC_TXC_Req_TransID (arb1_txc_req_transid), | |
4692 | ||
4693 | .Port_Selected (port_Selected[2]), | |
4694 | .Port_Request (port2_Request), | |
4695 | .Port_Request_Func_Num (port2_Request_Func_Num), | |
4696 | .Port_Request_DMA_Num (port2_Request_DMA_Num), | |
4697 | .Port_Request_Length (port2_Request_Length), | |
4698 | .Port_Request_Address (port2_Request_Address), | |
4699 | ||
4700 | .DMC_TXC_Resp_Rdy (dMC_TXC_Resp_Rdy), | |
4701 | .DMC_TXC_Resp_Complete (dMC_TXC_Resp_Complete), | |
4702 | .DMC_TXC_Trans_Complete (dMC_TXC_Trans_Complete), | |
4703 | .DMC_TXC_Resp_Data_Valid (dMC_TXC_Resp_Data_Valid), | |
4704 | .DMC_TXC_Resp_Client (dMC_TXC_Resp_Client), | |
4705 | .DMC_TXC_Resp_Port_Num (dMC_TXC_Resp_Port_Num), | |
4706 | .DMC_TXC_Resp_Cmd_Status (dMC_TXC_Resp_Cmd_Status), | |
4707 | .DMC_TXC_Resp_Data_Status (dMC_TXC_Resp_Data_Status), | |
4708 | .DMC_TXC_Resp_DMA_Num (dMC_TXC_Resp_DMA_Num), | |
4709 | .DMC_TXC_Resp_TransID (dMC_TXC_Resp_TransID), | |
4710 | .DMC_TXC_Resp_Cmd (dMC_TXC_Resp_Cmd), | |
4711 | .DMC_TXC_Resp_Data_Length (dMC_TXC_Resp_Data_Length), | |
4712 | .DMC_TXC_Resp_ByteEnables (dMC_TXC_Resp_ByteEnables), | |
4713 | .DMC_TXC_Resp_Address (dMC_TXC_Resp_Address), | |
4714 | .DMC_TXC_Resp_Data (dMC_TXC_Resp_Data), | |
4715 | .TXC_DMC_Resp_Accept (port2_TXC_DMC_Resp_Accept), | |
4716 | ||
4717 | .ReOrderFifoDataValid (port2_ReOrderFifoDataValid), | |
4718 | .ReOrderUnCorrectError (port2_ReOrder_UnCorrectError), | |
4719 | .ReOrderEccControl (port2_ReOrderEccControl), | |
4720 | .PacketAssyEngineDataIn (port2_PacketAssyEngineDataIn), | |
4721 | .ReOrderCorruptECCSingle (port2_ReOrderCorruptECCSingle), | |
4722 | .ReOrderCorruptECCDouble (port2_ReOrderCorruptECCDouble), | |
4723 | .ReOrderFifoWrite (port2_ReOrderFifoWrite), | |
4724 | .ReOrderFifoReadStrobe (port2_ReOrderFifoRead), | |
4725 | .ReOrderWritePtr (port2_ReOrderWritePtr), | |
4726 | .ReOrderReadPtr (port2_ReOrderReadPtr), | |
4727 | .ReOrderEngineDataOut (port2_ReOrderEngineDataOut), | |
4728 | ||
4729 | .StoreForwardUnCorrectError (port2_StoreForward_UnCorrectError), | |
4730 | .StoreForwardEccControl (port2_StoreForwardEccControl), | |
4731 | .MacXferEngineDataIn (port2_MacXferEngineDataIn), | |
4732 | .StoreForward_CorruptECCSingle (port2_StoreForwardCorruptECCSingle), | |
4733 | .StoreForward_CorruptECCDouble (port2_StoreForwardCorruptECCDouble), | |
4734 | .StoreForwardFifoWrite (port2_StoreForwardFifoWrite), | |
4735 | .StoreForwardFifoReadStrobe (port2_StoreForwardFifoRead), | |
4736 | .StoreForwardWritePtr (port2_StoreForwardWritePtr), | |
4737 | .StoreForwardReadPtr (port2_StoreForwardReadPtr), | |
4738 | .PacketAssyEngineDataOut (port2_PacketAssyEngineDataOut), | |
4739 | ||
4740 | .LatchActiveDMA (port2_LatchActiveDMA), | |
4741 | .ContextActiveList (port2_ContextActiveList), | |
4742 | ||
4743 | .Anchor_State (port2_Anchor_State), | |
4744 | .ReOrder_State (port2_ReOrder_State), | |
4745 | .Pointer_State (port2_Pointer_State), | |
4746 | .PacketAssy_State (port2_PacketAssy_State), | |
4747 | .DRR_ArbState (port2_DRR_ArbState), | |
4748 | .Mac_Xfer_State (port2_Mac_Xfer_State), | |
4749 | .DataPortReq_State (port2_DataPortReq_State), | |
4750 | .Sum_prt_state (port2_Sum_prt_state) | |
4751 | ); | |
4752 | ||
4753 | ||
4754 | niu_txc_ecc_engine port2_niu_txc_ecc_engine ( | |
4755 | .SysClk (niu_clk), | |
4756 | .Reset_L (reset_l), | |
4757 | .ReOrder_ClearEccError (port2_ReOrder_ClearEccError), | |
4758 | .WrReOrderEccState (port2_WrReOrderEccState), | |
4759 | .WrReOrderEccData0 (port2_WrReOrderEccData0), | |
4760 | .WrReOrderEccData1 (port2_WrReOrderEccData1), | |
4761 | .WrReOrderEccData2 (port2_WrReOrderEccData2), | |
4762 | .WrReOrderEccData3 (port2_WrReOrderEccData3), | |
4763 | .WrReOrderEccData4 (port2_WrReOrderEccData4), | |
4764 | .StoreForward_ClearEccError (port2_StoreForward_ClearEccError), | |
4765 | .WrStoreForwardEccState (port2_WrStoreForwardEccState), | |
4766 | .WrStoreForwardEccData0 (port2_WrStoreForwardEccData0), | |
4767 | .WrStoreForwardEccData1 (port2_WrStoreForwardEccData1), | |
4768 | .WrStoreForwardEccData2 (port2_WrStoreForwardEccData2), | |
4769 | .WrStoreForwardEccData3 (port2_WrStoreForwardEccData3), | |
4770 | .WrStoreForwardEccData4 (port2_WrStoreForwardEccData4), | |
4771 | .PioDataIn (port2_PioDataIn), | |
4772 | .ReOrder_ECC_State (port2_ReOrder_ECC_State), | |
4773 | .ReOrder_EccData (port2_ReOrder_EccData), | |
4774 | .StoreForward_ECC_State (port2_StoreForward_ECC_State), | |
4775 | .StoreForward_EccData (port2_StoreForward_EccData), | |
4776 | .ReOrder_CorruptECCSingle (port2_ReOrderCorruptECCSingle), | |
4777 | .ReOrder_CorruptECCDouble (port2_ReOrderCorruptECCDouble), | |
4778 | .ReOrder_FifoRead (port2_ReOrderFifoRead), | |
4779 | .ReOrder_ReadPtr (port2_ReOrderReadPtr), | |
4780 | .ReOrder_FifoDataOut (port2_ReOrderFifoDataOut), | |
4781 | .ReOrder_FifoDataValid (port2_ReOrderFifoDataValid), | |
4782 | .ReOrder_UnCorrectError (port2_ReOrder_UnCorrectError), | |
4783 | .ReOrder_PreECCData (port2_ReOrderEngineDataOut), | |
4784 | .ReOrder_PostECCData (port2_ReOrderFifoDataIn), | |
4785 | .ReOrder_CorrectedData (port2_PacketAssyEngineDataIn), | |
4786 | .StoreForward_CorruptECCSingle (port2_StoreForwardCorruptECCSingle), | |
4787 | .StoreForward_CorruptECCDouble (port2_StoreForwardCorruptECCDouble), | |
4788 | .StoreForward_FifoRead (port2_StoreForwardFifoRead), | |
4789 | .StoreForward_ReadPtr (port2_StoreForwardReadPtr), | |
4790 | .StoreForward_FifoDataOut (port2_StoreForwardFifoDataOut), | |
4791 | .StoreForward_UnCorrectError (port2_StoreForward_UnCorrectError), | |
4792 | .StoreForward_PreECCData (port2_PacketAssyEngineDataOut), | |
4793 | .StoreForward_PostECCData (port2_StoreForwardFifoDataIn), | |
4794 | .StoreForward_CorrectedData (port2_MacXferEngineDataIn) | |
4795 | ); | |
4796 | ||
4797 | ||
4798 | niu_ram_1024_152 port2_RO_RAM ( | |
4799 | .clk (niu_clk), | |
4800 | .wt_enable (port2_ReOrderFifoWrite), | |
4801 | .cs_rd (port2_ReOrderFifoRead), | |
4802 | .addr_rd (port2_ReOrderReadPtr), | |
4803 | .addr_wt (port2_ReOrderWritePtr), | |
4804 | .data_inp (port2_ReOrderFifoDataIn), | |
4805 | .data_out (port2_ReOrderFifoDataOut) | |
4806 | ); | |
4807 | ||
4808 | ||
4809 | niu_ram_640_152 port2_SF_RAM ( | |
4810 | .clk (niu_clk), | |
4811 | .wt_enable (port2_StoreForwardFifoWrite), | |
4812 | .cs_rd (port2_StoreForwardFifoRead), | |
4813 | .addr_rd (port2_StoreForwardReadPtr), | |
4814 | .addr_wt (port2_StoreForwardWritePtr), | |
4815 | .data_inp (port2_StoreForwardFifoDataIn), | |
4816 | .data_out (port2_StoreForwardFifoDataOut) | |
4817 | ); | |
4818 | ||
4819 | ||
4820 | niu_txc_packetEngine #(REORDER_SIZE_1G, REORDER_PTR_1G) niu_txc_packetEngine3 ( | |
4821 | .SysClk (niu_clk), | |
4822 | .Reset_L (reset_l), | |
4823 | .PacketAssyDead (port3_PacketAssyDead), | |
4824 | .ReOrder_Error (port3_ReOrder_Error), | |
4825 | .Txc_Enabled (txc_Enabled), | |
4826 | .PortIndentifier (`PORT_THREE), | |
4827 | .EnableGMACMode (1'b1), | |
4828 | .MAC_Enabled (port3_Enabled), | |
4829 | .FlushEngine (flushEngine), | |
4830 | ||
4831 | .MAC_Req (port3_mac_req), | |
4832 | .MAC_Ack (txc_mac_ack3), | |
4833 | .MAC_Tag (txc_mac_tag3), | |
4834 | .MAC_Status (), | |
4835 | .MAC_Abort (), | |
4836 | .MAC_Data (txc_mac_data3), | |
4837 | ||
4838 | .TidsInUse (port3_TidsInUse), | |
4839 | .DuplicateTid (port3_DuplicateTid), | |
4840 | .UnInitializedTID (port3_UnInitializedTID), | |
4841 | .TimedoutTids (port3_TimedoutTids), | |
4842 | .ReOrderStateLogic (port3_ReOrderStateLogic), | |
4843 | .ReOrderStateControl (port3_ReOrderStateControl), | |
4844 | .ReOrderStateData0 (port3_ReOrderStateData0), | |
4845 | .ReOrderStateData1 (port3_ReOrderStateData1), | |
4846 | .ReOrderStateData2 (port3_ReOrderStateData2), | |
4847 | .ReOrderStateData3 (port3_ReOrderStateData3), | |
4848 | .WrTidsInUse (port3_WrTidsInUse), | |
4849 | .WrDuplicateTid (port3_WrDuplicateTid), | |
4850 | .WrUnInitializedTID (port3_WrUnInitializedTID), | |
4851 | .WrTimedoutTids (port3_WrTimedoutTids), | |
4852 | .WrReOrderStateLogic (port3_WrReOrderStateLogic), | |
4853 | .WrReOrderStateControl (port3_WrReOrderStateControl), | |
4854 | .WrReOrderStateData0 (port3_WrReOrderStateData0), | |
4855 | .WrReOrderStateData1 (port3_WrReOrderStateData1), | |
4856 | .WrReOrderStateData2 (port3_WrReOrderStateData2), | |
4857 | .WrReOrderStateData3 (port3_WrReOrderStateData3), | |
4858 | .PioDataIn (port3_PioDataIn), | |
4859 | ||
4860 | .ClearStatistics (port3_ClearStatistics), | |
4861 | .WrPacketStuffed (port3_WrPacketStuffed), | |
4862 | .WrPacketXmitted (port3_WrPacketXmitted), | |
4863 | .WrPacketRequested (port3_WrPacketRequested), | |
4864 | .GatherRequestCount (port3_GatherRequestCount), | |
4865 | .PacketRequestCount (port3_PacketRequestCount), | |
4866 | .PktErrAbortCount (port3_PktErrAbortCount), | |
4867 | .ReOrdersStuffed (port3_ReOrdersStuffed), | |
4868 | .PacketsStuffed (port3_PacketsStuffed), | |
4869 | .PacketsTransmitted (port3_PacketsTransmitted), | |
4870 | .BytesTransmitted (port3_BytesTransmitted), | |
4871 | ||
4872 | .Pkt_Size_Err (txc_dmc_p3_pkt_size_err), | |
4873 | .DMA_Pkt_Size_Err (txc_dmc_p3_dma_pkt_size_err), | |
4874 | .Pkt_Size_Err_Addr (txc_dmc_p3_pkt_size_err_addr), | |
4875 | ||
4876 | .Nack_Pkt_Rd (port3_Nack_Pkt_Rd), | |
4877 | .DMA_Nack_Pkt_Rd (port3_DMA_Nack_Pkt_Rd), | |
4878 | .Nack_Pkt_Rd_Addr (port3_Nack_Pkt_Rd_Addr), | |
4879 | ||
4880 | .DMA0_Active (dmc_txc_dma0_active), | |
4881 | .DMA0_EofList (dmc_txc_dma0_eoflist), | |
4882 | .DMA0_Error (dmc_txc_dma0_error), | |
4883 | .DMA0_CacheReady (dmc_txc_dma0_cacheready), | |
4884 | .DMA0_Partial (dmc_txc_dma0_partial), | |
4885 | .DMA0_Reset_Scheduled (dmc_txc_dma0_reset_scheduled), | |
4886 | .DMA0_GotNxtDesc (dmc_txc_dma0_gotnxtdesc), | |
4887 | .DMA0_Mark (dmc_txc_dma0_descriptor[62]), | |
4888 | .DMA0_SOP (dmc_txc_dma0_descriptor[63]), | |
4889 | .DMA0_Func_Num (dmc_txc_dma0_func_num), | |
4890 | .DMA0_DescList (dmc_txc_dma0_descriptor[61:58]), | |
4891 | .DMA0_Length (dmc_txc_dma0_descriptor[56:44]), | |
4892 | .DMA0_PageHandle (dmc_txc_dma0_page_handle), | |
4893 | .DMA0_Address (dmc_txc_dma0_descriptor[43:0]), | |
4894 | .DMA0_Inc_Head (port3_DMA0_inc_head), | |
4895 | .DMA0_Reset_Done (port3_DMA0_reset_done), | |
4896 | .DMA0_Mark_Bit (port3_DMA0_mark_bit), | |
4897 | .DMA0_Inc_Pkt_Cnt (port3_DMA0_inc_pkt_cnt), | |
4898 | .SetGetNextDescDMA0 (port3_SetGetNextDescDMA0), | |
4899 | .DMA1_Active (dmc_txc_dma1_active), | |
4900 | .DMA1_EofList (dmc_txc_dma1_eoflist), | |
4901 | .DMA1_Error (dmc_txc_dma1_error), | |
4902 | .DMA1_CacheReady (dmc_txc_dma1_cacheready), | |
4903 | .DMA1_Partial (dmc_txc_dma1_partial), | |
4904 | .DMA1_Reset_Scheduled (dmc_txc_dma1_reset_scheduled), | |
4905 | .DMA1_GotNxtDesc (dmc_txc_dma1_gotnxtdesc), | |
4906 | .DMA1_Mark (dmc_txc_dma1_descriptor[62]), | |
4907 | .DMA1_SOP (dmc_txc_dma1_descriptor[63]), | |
4908 | .DMA1_Func_Num (dmc_txc_dma1_func_num), | |
4909 | .DMA1_DescList (dmc_txc_dma1_descriptor[61:58]), | |
4910 | .DMA1_Length (dmc_txc_dma1_descriptor[56:44]), | |
4911 | .DMA1_PageHandle (dmc_txc_dma1_page_handle), | |
4912 | .DMA1_Address (dmc_txc_dma1_descriptor[43:0]), | |
4913 | .DMA1_Inc_Head (port3_DMA1_inc_head), | |
4914 | .DMA1_Reset_Done (port3_DMA1_reset_done), | |
4915 | .DMA1_Mark_Bit (port3_DMA1_mark_bit), | |
4916 | .DMA1_Inc_Pkt_Cnt (port3_DMA1_inc_pkt_cnt), | |
4917 | .SetGetNextDescDMA1 (port3_SetGetNextDescDMA1), | |
4918 | .DMA2_Active (dmc_txc_dma2_active), | |
4919 | .DMA2_EofList (dmc_txc_dma2_eoflist), | |
4920 | .DMA2_Error (dmc_txc_dma2_error), | |
4921 | .DMA2_CacheReady (dmc_txc_dma2_cacheready), | |
4922 | .DMA2_Partial (dmc_txc_dma2_partial), | |
4923 | .DMA2_Reset_Scheduled (dmc_txc_dma2_reset_scheduled), | |
4924 | .DMA2_GotNxtDesc (dmc_txc_dma2_gotnxtdesc), | |
4925 | .DMA2_Mark (dmc_txc_dma2_descriptor[62]), | |
4926 | .DMA2_SOP (dmc_txc_dma2_descriptor[63]), | |
4927 | .DMA2_Func_Num (dmc_txc_dma2_func_num), | |
4928 | .DMA2_DescList (dmc_txc_dma2_descriptor[61:58]), | |
4929 | .DMA2_Length (dmc_txc_dma2_descriptor[56:44]), | |
4930 | .DMA2_PageHandle (dmc_txc_dma2_page_handle), | |
4931 | .DMA2_Address (dmc_txc_dma2_descriptor[43:0]), | |
4932 | .DMA2_Inc_Head (port3_DMA2_inc_head), | |
4933 | .DMA2_Reset_Done (port3_DMA2_reset_done), | |
4934 | .DMA2_Mark_Bit (port3_DMA2_mark_bit), | |
4935 | .DMA2_Inc_Pkt_Cnt (port3_DMA2_inc_pkt_cnt), | |
4936 | .SetGetNextDescDMA2 (port3_SetGetNextDescDMA2), | |
4937 | .DMA3_Active (dmc_txc_dma3_active), | |
4938 | .DMA3_EofList (dmc_txc_dma3_eoflist), | |
4939 | .DMA3_Error (dmc_txc_dma3_error), | |
4940 | .DMA3_CacheReady (dmc_txc_dma3_cacheready), | |
4941 | .DMA3_Partial (dmc_txc_dma3_partial), | |
4942 | .DMA3_Reset_Scheduled (dmc_txc_dma3_reset_scheduled), | |
4943 | .DMA3_GotNxtDesc (dmc_txc_dma3_gotnxtdesc), | |
4944 | .DMA3_Mark (dmc_txc_dma3_descriptor[62]), | |
4945 | .DMA3_SOP (dmc_txc_dma3_descriptor[63]), | |
4946 | .DMA3_Func_Num (dmc_txc_dma3_func_num), | |
4947 | .DMA3_DescList (dmc_txc_dma3_descriptor[61:58]), | |
4948 | .DMA3_Length (dmc_txc_dma3_descriptor[56:44]), | |
4949 | .DMA3_PageHandle (dmc_txc_dma3_page_handle), | |
4950 | .DMA3_Address (dmc_txc_dma3_descriptor[43:0]), | |
4951 | .DMA3_Inc_Head (port3_DMA3_inc_head), | |
4952 | .DMA3_Reset_Done (port3_DMA3_reset_done), | |
4953 | .DMA3_Mark_Bit (port3_DMA3_mark_bit), | |
4954 | .DMA3_Inc_Pkt_Cnt (port3_DMA3_inc_pkt_cnt), | |
4955 | .SetGetNextDescDMA3 (port3_SetGetNextDescDMA3), | |
4956 | .DMA4_Active (dmc_txc_dma4_active), | |
4957 | .DMA4_EofList (dmc_txc_dma4_eoflist), | |
4958 | .DMA4_Error (dmc_txc_dma4_error), | |
4959 | .DMA4_CacheReady (dmc_txc_dma4_cacheready), | |
4960 | .DMA4_Partial (dmc_txc_dma4_partial), | |
4961 | .DMA4_Reset_Scheduled (dmc_txc_dma4_reset_scheduled), | |
4962 | .DMA4_GotNxtDesc (dmc_txc_dma4_gotnxtdesc), | |
4963 | .DMA4_Mark (dmc_txc_dma4_descriptor[62]), | |
4964 | .DMA4_SOP (dmc_txc_dma4_descriptor[63]), | |
4965 | .DMA4_Func_Num (dmc_txc_dma4_func_num), | |
4966 | .DMA4_DescList (dmc_txc_dma4_descriptor[61:58]), | |
4967 | .DMA4_Length (dmc_txc_dma4_descriptor[56:44]), | |
4968 | .DMA4_PageHandle (dmc_txc_dma4_page_handle), | |
4969 | .DMA4_Address (dmc_txc_dma4_descriptor[43:0]), | |
4970 | .DMA4_Inc_Head (port3_DMA4_inc_head), | |
4971 | .DMA4_Reset_Done (port3_DMA4_reset_done), | |
4972 | .DMA4_Mark_Bit (port3_DMA4_mark_bit), | |
4973 | .DMA4_Inc_Pkt_Cnt (port3_DMA4_inc_pkt_cnt), | |
4974 | .SetGetNextDescDMA4 (port3_SetGetNextDescDMA4), | |
4975 | .DMA5_Active (dmc_txc_dma5_active), | |
4976 | .DMA5_EofList (dmc_txc_dma5_eoflist), | |
4977 | .DMA5_Error (dmc_txc_dma5_error), | |
4978 | .DMA5_CacheReady (dmc_txc_dma5_cacheready), | |
4979 | .DMA5_Partial (dmc_txc_dma5_partial), | |
4980 | .DMA5_Reset_Scheduled (dmc_txc_dma5_reset_scheduled), | |
4981 | .DMA5_GotNxtDesc (dmc_txc_dma5_gotnxtdesc), | |
4982 | .DMA5_Mark (dmc_txc_dma5_descriptor[62]), | |
4983 | .DMA5_SOP (dmc_txc_dma5_descriptor[63]), | |
4984 | .DMA5_Func_Num (dmc_txc_dma5_func_num), | |
4985 | .DMA5_DescList (dmc_txc_dma5_descriptor[61:58]), | |
4986 | .DMA5_Length (dmc_txc_dma5_descriptor[56:44]), | |
4987 | .DMA5_PageHandle (dmc_txc_dma5_page_handle), | |
4988 | .DMA5_Address (dmc_txc_dma5_descriptor[43:0]), | |
4989 | .DMA5_Inc_Head (port3_DMA5_inc_head), | |
4990 | .DMA5_Reset_Done (port3_DMA5_reset_done), | |
4991 | .DMA5_Mark_Bit (port3_DMA5_mark_bit), | |
4992 | .DMA5_Inc_Pkt_Cnt (port3_DMA5_inc_pkt_cnt), | |
4993 | .SetGetNextDescDMA5 (port3_SetGetNextDescDMA5), | |
4994 | .DMA6_Active (dmc_txc_dma6_active), | |
4995 | .DMA6_EofList (dmc_txc_dma6_eoflist), | |
4996 | .DMA6_Error (dmc_txc_dma6_error), | |
4997 | .DMA6_CacheReady (dmc_txc_dma6_cacheready), | |
4998 | .DMA6_Partial (dmc_txc_dma6_partial), | |
4999 | .DMA6_Reset_Scheduled (dmc_txc_dma6_reset_scheduled), | |
5000 | .DMA6_GotNxtDesc (dmc_txc_dma6_gotnxtdesc), | |
5001 | .DMA6_Mark (dmc_txc_dma6_descriptor[62]), | |
5002 | .DMA6_SOP (dmc_txc_dma6_descriptor[63]), | |
5003 | .DMA6_Func_Num (dmc_txc_dma6_func_num), | |
5004 | .DMA6_DescList (dmc_txc_dma6_descriptor[61:58]), | |
5005 | .DMA6_Length (dmc_txc_dma6_descriptor[56:44]), | |
5006 | .DMA6_PageHandle (dmc_txc_dma6_page_handle), | |
5007 | .DMA6_Address (dmc_txc_dma6_descriptor[43:0]), | |
5008 | .DMA6_Inc_Head (port3_DMA6_inc_head), | |
5009 | .DMA6_Reset_Done (port3_DMA6_reset_done), | |
5010 | .DMA6_Mark_Bit (port3_DMA6_mark_bit), | |
5011 | .DMA6_Inc_Pkt_Cnt (port3_DMA6_inc_pkt_cnt), | |
5012 | .SetGetNextDescDMA6 (port3_SetGetNextDescDMA6), | |
5013 | .DMA7_Active (dmc_txc_dma7_active), | |
5014 | .DMA7_EofList (dmc_txc_dma7_eoflist), | |
5015 | .DMA7_Error (dmc_txc_dma7_error), | |
5016 | .DMA7_CacheReady (dmc_txc_dma7_cacheready), | |
5017 | .DMA7_Partial (dmc_txc_dma7_partial), | |
5018 | .DMA7_Reset_Scheduled (dmc_txc_dma7_reset_scheduled), | |
5019 | .DMA7_GotNxtDesc (dmc_txc_dma7_gotnxtdesc), | |
5020 | .DMA7_Mark (dmc_txc_dma7_descriptor[62]), | |
5021 | .DMA7_SOP (dmc_txc_dma7_descriptor[63]), | |
5022 | .DMA7_Func_Num (dmc_txc_dma7_func_num), | |
5023 | .DMA7_DescList (dmc_txc_dma7_descriptor[61:58]), | |
5024 | .DMA7_Length (dmc_txc_dma7_descriptor[56:44]), | |
5025 | .DMA7_PageHandle (dmc_txc_dma7_page_handle), | |
5026 | .DMA7_Address (dmc_txc_dma7_descriptor[43:0]), | |
5027 | .DMA7_Inc_Head (port3_DMA7_inc_head), | |
5028 | .DMA7_Reset_Done (port3_DMA7_reset_done), | |
5029 | .DMA7_Mark_Bit (port3_DMA7_mark_bit), | |
5030 | .DMA7_Inc_Pkt_Cnt (port3_DMA7_inc_pkt_cnt), | |
5031 | .SetGetNextDescDMA7 (port3_SetGetNextDescDMA7), | |
5032 | .DMA8_Active (dmc_txc_dma8_active), | |
5033 | .DMA8_EofList (dmc_txc_dma8_eoflist), | |
5034 | .DMA8_Error (dmc_txc_dma8_error), | |
5035 | .DMA8_CacheReady (dmc_txc_dma8_cacheready), | |
5036 | .DMA8_Partial (dmc_txc_dma8_partial), | |
5037 | .DMA8_Reset_Scheduled (dmc_txc_dma8_reset_scheduled), | |
5038 | .DMA8_GotNxtDesc (dmc_txc_dma8_gotnxtdesc), | |
5039 | .DMA8_Mark (dmc_txc_dma8_descriptor[62]), | |
5040 | .DMA8_SOP (dmc_txc_dma8_descriptor[63]), | |
5041 | .DMA8_Func_Num (dmc_txc_dma8_func_num), | |
5042 | .DMA8_DescList (dmc_txc_dma8_descriptor[61:58]), | |
5043 | .DMA8_Length (dmc_txc_dma8_descriptor[56:44]), | |
5044 | .DMA8_PageHandle (dmc_txc_dma8_page_handle), | |
5045 | .DMA8_Address (dmc_txc_dma8_descriptor[43:0]), | |
5046 | .DMA8_Inc_Head (port3_DMA8_inc_head), | |
5047 | .DMA8_Reset_Done (port3_DMA8_reset_done), | |
5048 | .DMA8_Mark_Bit (port3_DMA8_mark_bit), | |
5049 | .DMA8_Inc_Pkt_Cnt (port3_DMA8_inc_pkt_cnt), | |
5050 | .SetGetNextDescDMA8 (port3_SetGetNextDescDMA8), | |
5051 | .DMA9_Active (dmc_txc_dma9_active), | |
5052 | .DMA9_EofList (dmc_txc_dma9_eoflist), | |
5053 | .DMA9_Error (dmc_txc_dma9_error), | |
5054 | .DMA9_CacheReady (dmc_txc_dma9_cacheready), | |
5055 | .DMA9_Partial (dmc_txc_dma9_partial), | |
5056 | .DMA9_Reset_Scheduled (dmc_txc_dma9_reset_scheduled), | |
5057 | .DMA9_GotNxtDesc (dmc_txc_dma9_gotnxtdesc), | |
5058 | .DMA9_Mark (dmc_txc_dma9_descriptor[62]), | |
5059 | .DMA9_SOP (dmc_txc_dma9_descriptor[63]), | |
5060 | .DMA9_Func_Num (dmc_txc_dma9_func_num), | |
5061 | .DMA9_DescList (dmc_txc_dma9_descriptor[61:58]), | |
5062 | .DMA9_Length (dmc_txc_dma9_descriptor[56:44]), | |
5063 | .DMA9_PageHandle (dmc_txc_dma9_page_handle), | |
5064 | .DMA9_Address (dmc_txc_dma9_descriptor[43:0]), | |
5065 | .DMA9_Inc_Head (port3_DMA9_inc_head), | |
5066 | .DMA9_Reset_Done (port3_DMA9_reset_done), | |
5067 | .DMA9_Mark_Bit (port3_DMA9_mark_bit), | |
5068 | .DMA9_Inc_Pkt_Cnt (port3_DMA9_inc_pkt_cnt), | |
5069 | .SetGetNextDescDMA9 (port3_SetGetNextDescDMA9), | |
5070 | .DMA10_Active (dmc_txc_dma10_active), | |
5071 | .DMA10_EofList (dmc_txc_dma10_eoflist), | |
5072 | .DMA10_Error (dmc_txc_dma10_error), | |
5073 | .DMA10_CacheReady (dmc_txc_dma10_cacheready), | |
5074 | .DMA10_Partial (dmc_txc_dma10_partial), | |
5075 | .DMA10_Reset_Scheduled (dmc_txc_dma10_reset_scheduled), | |
5076 | .DMA10_GotNxtDesc (dmc_txc_dma10_gotnxtdesc), | |
5077 | .DMA10_Mark (dmc_txc_dma10_descriptor[62]), | |
5078 | .DMA10_SOP (dmc_txc_dma10_descriptor[63]), | |
5079 | .DMA10_Func_Num (dmc_txc_dma10_func_num), | |
5080 | .DMA10_DescList (dmc_txc_dma10_descriptor[61:58]), | |
5081 | .DMA10_Length (dmc_txc_dma10_descriptor[56:44]), | |
5082 | .DMA10_PageHandle (dmc_txc_dma10_page_handle), | |
5083 | .DMA10_Address (dmc_txc_dma10_descriptor[43:0]), | |
5084 | .DMA10_Inc_Head (port3_DMA10_inc_head), | |
5085 | .DMA10_Reset_Done (port3_DMA10_reset_done), | |
5086 | .DMA10_Mark_Bit (port3_DMA10_mark_bit), | |
5087 | .DMA10_Inc_Pkt_Cnt (port3_DMA10_inc_pkt_cnt), | |
5088 | .SetGetNextDescDMA10 (port3_SetGetNextDescDMA10), | |
5089 | .DMA11_Active (dmc_txc_dma11_active), | |
5090 | .DMA11_EofList (dmc_txc_dma11_eoflist), | |
5091 | .DMA11_Error (dmc_txc_dma11_error), | |
5092 | .DMA11_CacheReady (dmc_txc_dma11_cacheready), | |
5093 | .DMA11_Partial (dmc_txc_dma11_partial), | |
5094 | .DMA11_Reset_Scheduled (dmc_txc_dma11_reset_scheduled), | |
5095 | .DMA11_GotNxtDesc (dmc_txc_dma11_gotnxtdesc), | |
5096 | .DMA11_Mark (dmc_txc_dma11_descriptor[62]), | |
5097 | .DMA11_SOP (dmc_txc_dma11_descriptor[63]), | |
5098 | .DMA11_Func_Num (dmc_txc_dma11_func_num), | |
5099 | .DMA11_DescList (dmc_txc_dma11_descriptor[61:58]), | |
5100 | .DMA11_Length (dmc_txc_dma11_descriptor[56:44]), | |
5101 | .DMA11_PageHandle (dmc_txc_dma11_page_handle), | |
5102 | .DMA11_Address (dmc_txc_dma11_descriptor[43:0]), | |
5103 | .DMA11_Inc_Head (port3_DMA11_inc_head), | |
5104 | .DMA11_Reset_Done (port3_DMA11_reset_done), | |
5105 | .DMA11_Mark_Bit (port3_DMA11_mark_bit), | |
5106 | .DMA11_Inc_Pkt_Cnt (port3_DMA11_inc_pkt_cnt), | |
5107 | .SetGetNextDescDMA11 (port3_SetGetNextDescDMA11), | |
5108 | .DMA12_Active (dmc_txc_dma12_active), | |
5109 | .DMA12_EofList (dmc_txc_dma12_eoflist), | |
5110 | .DMA12_Error (dmc_txc_dma12_error), | |
5111 | .DMA12_CacheReady (dmc_txc_dma12_cacheready), | |
5112 | .DMA12_Partial (dmc_txc_dma12_partial), | |
5113 | .DMA12_Reset_Scheduled (dmc_txc_dma12_reset_scheduled), | |
5114 | .DMA12_GotNxtDesc (dmc_txc_dma12_gotnxtdesc), | |
5115 | .DMA12_Mark (dmc_txc_dma12_descriptor[62]), | |
5116 | .DMA12_SOP (dmc_txc_dma12_descriptor[63]), | |
5117 | .DMA12_Func_Num (dmc_txc_dma12_func_num), | |
5118 | .DMA12_DescList (dmc_txc_dma12_descriptor[61:58]), | |
5119 | .DMA12_Length (dmc_txc_dma12_descriptor[56:44]), | |
5120 | .DMA12_PageHandle (dmc_txc_dma12_page_handle), | |
5121 | .DMA12_Address (dmc_txc_dma12_descriptor[43:0]), | |
5122 | .DMA12_Inc_Head (port3_DMA12_inc_head), | |
5123 | .DMA12_Reset_Done (port3_DMA12_reset_done), | |
5124 | .DMA12_Mark_Bit (port3_DMA12_mark_bit), | |
5125 | .DMA12_Inc_Pkt_Cnt (port3_DMA12_inc_pkt_cnt), | |
5126 | .SetGetNextDescDMA12 (port3_SetGetNextDescDMA12), | |
5127 | .DMA13_Active (dmc_txc_dma13_active), | |
5128 | .DMA13_EofList (dmc_txc_dma13_eoflist), | |
5129 | .DMA13_Error (dmc_txc_dma13_error), | |
5130 | .DMA13_CacheReady (dmc_txc_dma13_cacheready), | |
5131 | .DMA13_Partial (dmc_txc_dma13_partial), | |
5132 | .DMA13_Reset_Scheduled (dmc_txc_dma13_reset_scheduled), | |
5133 | .DMA13_GotNxtDesc (dmc_txc_dma13_gotnxtdesc), | |
5134 | .DMA13_Mark (dmc_txc_dma13_descriptor[62]), | |
5135 | .DMA13_SOP (dmc_txc_dma13_descriptor[63]), | |
5136 | .DMA13_Func_Num (dmc_txc_dma13_func_num), | |
5137 | .DMA13_DescList (dmc_txc_dma13_descriptor[61:58]), | |
5138 | .DMA13_Length (dmc_txc_dma13_descriptor[56:44]), | |
5139 | .DMA13_PageHandle (dmc_txc_dma13_page_handle), | |
5140 | .DMA13_Address (dmc_txc_dma13_descriptor[43:0]), | |
5141 | .DMA13_Inc_Head (port3_DMA13_inc_head), | |
5142 | .DMA13_Reset_Done (port3_DMA13_reset_done), | |
5143 | .DMA13_Mark_Bit (port3_DMA13_mark_bit), | |
5144 | .DMA13_Inc_Pkt_Cnt (port3_DMA13_inc_pkt_cnt), | |
5145 | .SetGetNextDescDMA13 (port3_SetGetNextDescDMA13), | |
5146 | .DMA14_Active (dmc_txc_dma14_active), | |
5147 | .DMA14_EofList (dmc_txc_dma14_eoflist), | |
5148 | .DMA14_Error (dmc_txc_dma14_error), | |
5149 | .DMA14_CacheReady (dmc_txc_dma14_cacheready), | |
5150 | .DMA14_Partial (dmc_txc_dma14_partial), | |
5151 | .DMA14_Reset_Scheduled (dmc_txc_dma14_reset_scheduled), | |
5152 | .DMA14_GotNxtDesc (dmc_txc_dma14_gotnxtdesc), | |
5153 | .DMA14_Mark (dmc_txc_dma14_descriptor[62]), | |
5154 | .DMA14_SOP (dmc_txc_dma14_descriptor[63]), | |
5155 | .DMA14_Func_Num (dmc_txc_dma14_func_num), | |
5156 | .DMA14_DescList (dmc_txc_dma14_descriptor[61:58]), | |
5157 | .DMA14_Length (dmc_txc_dma14_descriptor[56:44]), | |
5158 | .DMA14_PageHandle (dmc_txc_dma14_page_handle), | |
5159 | .DMA14_Address (dmc_txc_dma14_descriptor[43:0]), | |
5160 | .DMA14_Inc_Head (port3_DMA14_inc_head), | |
5161 | .DMA14_Reset_Done (port3_DMA14_reset_done), | |
5162 | .DMA14_Mark_Bit (port3_DMA14_mark_bit), | |
5163 | .DMA14_Inc_Pkt_Cnt (port3_DMA14_inc_pkt_cnt), | |
5164 | .SetGetNextDescDMA14 (port3_SetGetNextDescDMA14), | |
5165 | .DMA15_Active (dmc_txc_dma15_active), | |
5166 | .DMA15_EofList (dmc_txc_dma15_eoflist), | |
5167 | .DMA15_Error (dmc_txc_dma15_error), | |
5168 | .DMA15_CacheReady (dmc_txc_dma15_cacheready), | |
5169 | .DMA15_Partial (dmc_txc_dma15_partial), | |
5170 | .DMA15_Reset_Scheduled (dmc_txc_dma15_reset_scheduled), | |
5171 | .DMA15_GotNxtDesc (dmc_txc_dma15_gotnxtdesc), | |
5172 | .DMA15_Mark (dmc_txc_dma15_descriptor[62]), | |
5173 | .DMA15_SOP (dmc_txc_dma15_descriptor[63]), | |
5174 | .DMA15_Func_Num (dmc_txc_dma15_func_num), | |
5175 | .DMA15_DescList (dmc_txc_dma15_descriptor[61:58]), | |
5176 | .DMA15_Length (dmc_txc_dma15_descriptor[56:44]), | |
5177 | .DMA15_PageHandle (dmc_txc_dma15_page_handle), | |
5178 | .DMA15_Address (dmc_txc_dma15_descriptor[43:0]), | |
5179 | .DMA15_Inc_Head (port3_DMA15_inc_head), | |
5180 | .DMA15_Reset_Done (port3_DMA15_reset_done), | |
5181 | .DMA15_Mark_Bit (port3_DMA15_mark_bit), | |
5182 | .DMA15_Inc_Pkt_Cnt (port3_DMA15_inc_pkt_cnt), | |
5183 | .SetGetNextDescDMA15 (port3_SetGetNextDescDMA15), | |
5184 | .DMA16_Active (dmc_txc_dma16_active), | |
5185 | .DMA16_EofList (dmc_txc_dma16_eoflist), | |
5186 | .DMA16_Error (dmc_txc_dma16_error), | |
5187 | .DMA16_CacheReady (dmc_txc_dma16_cacheready), | |
5188 | .DMA16_Partial (dmc_txc_dma16_partial), | |
5189 | .DMA16_Reset_Scheduled (dmc_txc_dma16_reset_scheduled), | |
5190 | .DMA16_GotNxtDesc (dmc_txc_dma16_gotnxtdesc), | |
5191 | .DMA16_Mark (dmc_txc_dma16_descriptor[62]), | |
5192 | .DMA16_SOP (dmc_txc_dma16_descriptor[63]), | |
5193 | .DMA16_Func_Num (dmc_txc_dma16_func_num), | |
5194 | .DMA16_DescList (dmc_txc_dma16_descriptor[61:58]), | |
5195 | .DMA16_Length (dmc_txc_dma16_descriptor[56:44]), | |
5196 | .DMA16_PageHandle (dmc_txc_dma16_page_handle), | |
5197 | .DMA16_Address (dmc_txc_dma16_descriptor[43:0]), | |
5198 | .DMA16_Inc_Head (port3_DMA16_inc_head), | |
5199 | .DMA16_Reset_Done (port3_DMA16_reset_done), | |
5200 | .DMA16_Mark_Bit (port3_DMA16_mark_bit), | |
5201 | .DMA16_Inc_Pkt_Cnt (port3_DMA16_inc_pkt_cnt), | |
5202 | .SetGetNextDescDMA16 (port3_SetGetNextDescDMA16), | |
5203 | .DMA17_Active (dmc_txc_dma17_active), | |
5204 | .DMA17_EofList (dmc_txc_dma17_eoflist), | |
5205 | .DMA17_Error (dmc_txc_dma17_error), | |
5206 | .DMA17_CacheReady (dmc_txc_dma17_cacheready), | |
5207 | .DMA17_Partial (dmc_txc_dma17_partial), | |
5208 | .DMA17_Reset_Scheduled (dmc_txc_dma17_reset_scheduled), | |
5209 | .DMA17_GotNxtDesc (dmc_txc_dma17_gotnxtdesc), | |
5210 | .DMA17_Mark (dmc_txc_dma17_descriptor[62]), | |
5211 | .DMA17_SOP (dmc_txc_dma17_descriptor[63]), | |
5212 | .DMA17_Func_Num (dmc_txc_dma17_func_num), | |
5213 | .DMA17_DescList (dmc_txc_dma17_descriptor[61:58]), | |
5214 | .DMA17_Length (dmc_txc_dma17_descriptor[56:44]), | |
5215 | .DMA17_PageHandle (dmc_txc_dma17_page_handle), | |
5216 | .DMA17_Address (dmc_txc_dma17_descriptor[43:0]), | |
5217 | .DMA17_Inc_Head (port3_DMA17_inc_head), | |
5218 | .DMA17_Reset_Done (port3_DMA17_reset_done), | |
5219 | .DMA17_Mark_Bit (port3_DMA17_mark_bit), | |
5220 | .DMA17_Inc_Pkt_Cnt (port3_DMA17_inc_pkt_cnt), | |
5221 | .SetGetNextDescDMA17 (port3_SetGetNextDescDMA17), | |
5222 | .DMA18_Active (dmc_txc_dma18_active), | |
5223 | .DMA18_EofList (dmc_txc_dma18_eoflist), | |
5224 | .DMA18_Error (dmc_txc_dma18_error), | |
5225 | .DMA18_CacheReady (dmc_txc_dma18_cacheready), | |
5226 | .DMA18_Partial (dmc_txc_dma18_partial), | |
5227 | .DMA18_Reset_Scheduled (dmc_txc_dma18_reset_scheduled), | |
5228 | .DMA18_GotNxtDesc (dmc_txc_dma18_gotnxtdesc), | |
5229 | .DMA18_Mark (dmc_txc_dma18_descriptor[62]), | |
5230 | .DMA18_SOP (dmc_txc_dma18_descriptor[63]), | |
5231 | .DMA18_Func_Num (dmc_txc_dma18_func_num), | |
5232 | .DMA18_DescList (dmc_txc_dma18_descriptor[61:58]), | |
5233 | .DMA18_Length (dmc_txc_dma18_descriptor[56:44]), | |
5234 | .DMA18_PageHandle (dmc_txc_dma18_page_handle), | |
5235 | .DMA18_Address (dmc_txc_dma18_descriptor[43:0]), | |
5236 | .DMA18_Inc_Head (port3_DMA18_inc_head), | |
5237 | .DMA18_Reset_Done (port3_DMA18_reset_done), | |
5238 | .DMA18_Mark_Bit (port3_DMA18_mark_bit), | |
5239 | .DMA18_Inc_Pkt_Cnt (port3_DMA18_inc_pkt_cnt), | |
5240 | .SetGetNextDescDMA18 (port3_SetGetNextDescDMA18), | |
5241 | .DMA19_Active (dmc_txc_dma19_active), | |
5242 | .DMA19_EofList (dmc_txc_dma19_eoflist), | |
5243 | .DMA19_Error (dmc_txc_dma19_error), | |
5244 | .DMA19_CacheReady (dmc_txc_dma19_cacheready), | |
5245 | .DMA19_Partial (dmc_txc_dma19_partial), | |
5246 | .DMA19_Reset_Scheduled (dmc_txc_dma19_reset_scheduled), | |
5247 | .DMA19_GotNxtDesc (dmc_txc_dma19_gotnxtdesc), | |
5248 | .DMA19_Mark (dmc_txc_dma19_descriptor[62]), | |
5249 | .DMA19_SOP (dmc_txc_dma19_descriptor[63]), | |
5250 | .DMA19_Func_Num (dmc_txc_dma19_func_num), | |
5251 | .DMA19_DescList (dmc_txc_dma19_descriptor[61:58]), | |
5252 | .DMA19_Length (dmc_txc_dma19_descriptor[56:44]), | |
5253 | .DMA19_PageHandle (dmc_txc_dma19_page_handle), | |
5254 | .DMA19_Address (dmc_txc_dma19_descriptor[43:0]), | |
5255 | .DMA19_Inc_Head (port3_DMA19_inc_head), | |
5256 | .DMA19_Reset_Done (port3_DMA19_reset_done), | |
5257 | .DMA19_Mark_Bit (port3_DMA19_mark_bit), | |
5258 | .DMA19_Inc_Pkt_Cnt (port3_DMA19_inc_pkt_cnt), | |
5259 | .SetGetNextDescDMA19 (port3_SetGetNextDescDMA19), | |
5260 | .DMA20_Active (dmc_txc_dma20_active), | |
5261 | .DMA20_EofList (dmc_txc_dma20_eoflist), | |
5262 | .DMA20_Error (dmc_txc_dma20_error), | |
5263 | .DMA20_CacheReady (dmc_txc_dma20_cacheready), | |
5264 | .DMA20_Partial (dmc_txc_dma20_partial), | |
5265 | .DMA20_Reset_Scheduled (dmc_txc_dma20_reset_scheduled), | |
5266 | .DMA20_GotNxtDesc (dmc_txc_dma20_gotnxtdesc), | |
5267 | .DMA20_Mark (dmc_txc_dma20_descriptor[62]), | |
5268 | .DMA20_SOP (dmc_txc_dma20_descriptor[63]), | |
5269 | .DMA20_Func_Num (dmc_txc_dma20_func_num), | |
5270 | .DMA20_DescList (dmc_txc_dma20_descriptor[61:58]), | |
5271 | .DMA20_Length (dmc_txc_dma20_descriptor[56:44]), | |
5272 | .DMA20_PageHandle (dmc_txc_dma20_page_handle), | |
5273 | .DMA20_Address (dmc_txc_dma20_descriptor[43:0]), | |
5274 | .DMA20_Inc_Head (port3_DMA20_inc_head), | |
5275 | .DMA20_Reset_Done (port3_DMA20_reset_done), | |
5276 | .DMA20_Mark_Bit (port3_DMA20_mark_bit), | |
5277 | .DMA20_Inc_Pkt_Cnt (port3_DMA20_inc_pkt_cnt), | |
5278 | .SetGetNextDescDMA20 (port3_SetGetNextDescDMA20), | |
5279 | .DMA21_Active (dmc_txc_dma21_active), | |
5280 | .DMA21_EofList (dmc_txc_dma21_eoflist), | |
5281 | .DMA21_Error (dmc_txc_dma21_error), | |
5282 | .DMA21_CacheReady (dmc_txc_dma21_cacheready), | |
5283 | .DMA21_Partial (dmc_txc_dma21_partial), | |
5284 | .DMA21_Reset_Scheduled (dmc_txc_dma21_reset_scheduled), | |
5285 | .DMA21_GotNxtDesc (dmc_txc_dma21_gotnxtdesc), | |
5286 | .DMA21_Mark (dmc_txc_dma21_descriptor[62]), | |
5287 | .DMA21_SOP (dmc_txc_dma21_descriptor[63]), | |
5288 | .DMA21_Func_Num (dmc_txc_dma21_func_num), | |
5289 | .DMA21_DescList (dmc_txc_dma21_descriptor[61:58]), | |
5290 | .DMA21_Length (dmc_txc_dma21_descriptor[56:44]), | |
5291 | .DMA21_PageHandle (dmc_txc_dma21_page_handle), | |
5292 | .DMA21_Address (dmc_txc_dma21_descriptor[43:0]), | |
5293 | .DMA21_Inc_Head (port3_DMA21_inc_head), | |
5294 | .DMA21_Reset_Done (port3_DMA21_reset_done), | |
5295 | .DMA21_Mark_Bit (port3_DMA21_mark_bit), | |
5296 | .DMA21_Inc_Pkt_Cnt (port3_DMA21_inc_pkt_cnt), | |
5297 | .SetGetNextDescDMA21 (port3_SetGetNextDescDMA21), | |
5298 | .DMA22_Active (dmc_txc_dma22_active), | |
5299 | .DMA22_EofList (dmc_txc_dma22_eoflist), | |
5300 | .DMA22_Error (dmc_txc_dma22_error), | |
5301 | .DMA22_CacheReady (dmc_txc_dma22_cacheready), | |
5302 | .DMA22_Partial (dmc_txc_dma22_partial), | |
5303 | .DMA22_Reset_Scheduled (dmc_txc_dma22_reset_scheduled), | |
5304 | .DMA22_GotNxtDesc (dmc_txc_dma22_gotnxtdesc), | |
5305 | .DMA22_Mark (dmc_txc_dma22_descriptor[62]), | |
5306 | .DMA22_SOP (dmc_txc_dma22_descriptor[63]), | |
5307 | .DMA22_Func_Num (dmc_txc_dma22_func_num), | |
5308 | .DMA22_DescList (dmc_txc_dma22_descriptor[61:58]), | |
5309 | .DMA22_Length (dmc_txc_dma22_descriptor[56:44]), | |
5310 | .DMA22_PageHandle (dmc_txc_dma22_page_handle), | |
5311 | .DMA22_Address (dmc_txc_dma22_descriptor[43:0]), | |
5312 | .DMA22_Inc_Head (port3_DMA22_inc_head), | |
5313 | .DMA22_Reset_Done (port3_DMA22_reset_done), | |
5314 | .DMA22_Mark_Bit (port3_DMA22_mark_bit), | |
5315 | .DMA22_Inc_Pkt_Cnt (port3_DMA22_inc_pkt_cnt), | |
5316 | .SetGetNextDescDMA22 (port3_SetGetNextDescDMA22), | |
5317 | .DMA23_Active (dmc_txc_dma23_active), | |
5318 | .DMA23_EofList (dmc_txc_dma23_eoflist), | |
5319 | .DMA23_Error (dmc_txc_dma23_error), | |
5320 | .DMA23_CacheReady (dmc_txc_dma23_cacheready), | |
5321 | .DMA23_Partial (dmc_txc_dma23_partial), | |
5322 | .DMA23_Reset_Scheduled (dmc_txc_dma23_reset_scheduled), | |
5323 | .DMA23_GotNxtDesc (dmc_txc_dma23_gotnxtdesc), | |
5324 | .DMA23_Mark (dmc_txc_dma23_descriptor[62]), | |
5325 | .DMA23_SOP (dmc_txc_dma23_descriptor[63]), | |
5326 | .DMA23_Func_Num (dmc_txc_dma23_func_num), | |
5327 | .DMA23_DescList (dmc_txc_dma23_descriptor[61:58]), | |
5328 | .DMA23_Length (dmc_txc_dma23_descriptor[56:44]), | |
5329 | .DMA23_PageHandle (dmc_txc_dma23_page_handle), | |
5330 | .DMA23_Address (dmc_txc_dma23_descriptor[43:0]), | |
5331 | .DMA23_Inc_Head (port3_DMA23_inc_head), | |
5332 | .DMA23_Reset_Done (port3_DMA23_reset_done), | |
5333 | .DMA23_Mark_Bit (port3_DMA23_mark_bit), | |
5334 | .DMA23_Inc_Pkt_Cnt (port3_DMA23_inc_pkt_cnt), | |
5335 | .SetGetNextDescDMA23 (port3_SetGetNextDescDMA23), | |
5336 | ||
5337 | .DMA0_NewMaxBurst (dma0_NewMaxBurst), | |
5338 | .DMA1_NewMaxBurst (dma1_NewMaxBurst), | |
5339 | .DMA2_NewMaxBurst (dma2_NewMaxBurst), | |
5340 | .DMA3_NewMaxBurst (dma3_NewMaxBurst), | |
5341 | .DMA4_NewMaxBurst (dma4_NewMaxBurst), | |
5342 | .DMA5_NewMaxBurst (dma5_NewMaxBurst), | |
5343 | .DMA6_NewMaxBurst (dma6_NewMaxBurst), | |
5344 | .DMA7_NewMaxBurst (dma7_NewMaxBurst), | |
5345 | .DMA8_NewMaxBurst (dma8_NewMaxBurst), | |
5346 | .DMA9_NewMaxBurst (dma9_NewMaxBurst), | |
5347 | .DMA10_NewMaxBurst (dma10_NewMaxBurst), | |
5348 | .DMA11_NewMaxBurst (dma11_NewMaxBurst), | |
5349 | .DMA12_NewMaxBurst (dma12_NewMaxBurst), | |
5350 | .DMA13_NewMaxBurst (dma13_NewMaxBurst), | |
5351 | .DMA14_NewMaxBurst (dma14_NewMaxBurst), | |
5352 | .DMA15_NewMaxBurst (dma15_NewMaxBurst), | |
5353 | .DMA16_NewMaxBurst (dma16_NewMaxBurst), | |
5354 | .DMA17_NewMaxBurst (dma17_NewMaxBurst), | |
5355 | .DMA18_NewMaxBurst (dma18_NewMaxBurst), | |
5356 | .DMA19_NewMaxBurst (dma19_NewMaxBurst), | |
5357 | .DMA20_NewMaxBurst (dma20_NewMaxBurst), | |
5358 | .DMA21_NewMaxBurst (dma21_NewMaxBurst), | |
5359 | .DMA22_NewMaxBurst (dma22_NewMaxBurst), | |
5360 | .DMA23_NewMaxBurst (dma23_NewMaxBurst), | |
5361 | .DMA0_MaxBurst (dma0_MaxBurst), | |
5362 | .DMA1_MaxBurst (dma1_MaxBurst), | |
5363 | .DMA2_MaxBurst (dma2_MaxBurst), | |
5364 | .DMA3_MaxBurst (dma3_MaxBurst), | |
5365 | .DMA4_MaxBurst (dma4_MaxBurst), | |
5366 | .DMA5_MaxBurst (dma5_MaxBurst), | |
5367 | .DMA6_MaxBurst (dma6_MaxBurst), | |
5368 | .DMA7_MaxBurst (dma7_MaxBurst), | |
5369 | .DMA8_MaxBurst (dma8_MaxBurst), | |
5370 | .DMA9_MaxBurst (dma9_MaxBurst), | |
5371 | .DMA10_MaxBurst (dma10_MaxBurst), | |
5372 | .DMA11_MaxBurst (dma11_MaxBurst), | |
5373 | .DMA12_MaxBurst (dma12_MaxBurst), | |
5374 | .DMA13_MaxBurst (dma13_MaxBurst), | |
5375 | .DMA14_MaxBurst (dma14_MaxBurst), | |
5376 | .DMA15_MaxBurst (dma15_MaxBurst), | |
5377 | .DMA16_MaxBurst (dma16_MaxBurst), | |
5378 | .DMA17_MaxBurst (dma17_MaxBurst), | |
5379 | .DMA18_MaxBurst (dma18_MaxBurst), | |
5380 | .DMA19_MaxBurst (dma19_MaxBurst), | |
5381 | .DMA20_MaxBurst (dma20_MaxBurst), | |
5382 | .DMA21_MaxBurst (dma21_MaxBurst), | |
5383 | .DMA22_MaxBurst (dma22_MaxBurst), | |
5384 | .DMA23_MaxBurst (dma23_MaxBurst), | |
5385 | .MaxReorderNumber (port3_MaxReorderNumber), | |
5386 | .Port_DMA_List (port3_DMA_List), | |
5387 | .ClrMaxBurst (port3_clrMaxBurst), | |
5388 | .UpdateDMA (port3_UpdateDMA), | |
5389 | .UpdateDMALength (port3_UpdateDMALength), | |
5390 | .UpdateDMANumber (port3_UpdateDMANumber), | |
5391 | ||
5392 | .DMC_TXC_Req_Ack (arb1_txc_req_accept), | |
5393 | .DMC_TXC_Req_TransID (arb1_txc_req_transid), | |
5394 | ||
5395 | .Port_Selected (port_Selected[3]), | |
5396 | .Port_Request (port3_Request), | |
5397 | .Port_Request_Func_Num (port3_Request_Func_Num), | |
5398 | .Port_Request_DMA_Num (port3_Request_DMA_Num), | |
5399 | .Port_Request_Length (port3_Request_Length), | |
5400 | .Port_Request_Address (port3_Request_Address), | |
5401 | ||
5402 | .DMC_TXC_Resp_Rdy (dMC_TXC_Resp_Rdy), | |
5403 | .DMC_TXC_Resp_Complete (dMC_TXC_Resp_Complete), | |
5404 | .DMC_TXC_Trans_Complete (dMC_TXC_Trans_Complete), | |
5405 | .DMC_TXC_Resp_Data_Valid (dMC_TXC_Resp_Data_Valid), | |
5406 | .DMC_TXC_Resp_Client (dMC_TXC_Resp_Client), | |
5407 | .DMC_TXC_Resp_Port_Num (dMC_TXC_Resp_Port_Num), | |
5408 | .DMC_TXC_Resp_Cmd_Status (dMC_TXC_Resp_Cmd_Status), | |
5409 | .DMC_TXC_Resp_Data_Status (dMC_TXC_Resp_Data_Status), | |
5410 | .DMC_TXC_Resp_DMA_Num (dMC_TXC_Resp_DMA_Num), | |
5411 | .DMC_TXC_Resp_TransID (dMC_TXC_Resp_TransID), | |
5412 | .DMC_TXC_Resp_Cmd (dMC_TXC_Resp_Cmd), | |
5413 | .DMC_TXC_Resp_Data_Length (dMC_TXC_Resp_Data_Length), | |
5414 | .DMC_TXC_Resp_ByteEnables (dMC_TXC_Resp_ByteEnables), | |
5415 | .DMC_TXC_Resp_Address (dMC_TXC_Resp_Address), | |
5416 | .DMC_TXC_Resp_Data (dMC_TXC_Resp_Data), | |
5417 | .TXC_DMC_Resp_Accept (port3_TXC_DMC_Resp_Accept), | |
5418 | ||
5419 | .ReOrderFifoDataValid (port3_ReOrderFifoDataValid), | |
5420 | .ReOrderUnCorrectError (port3_ReOrder_UnCorrectError), | |
5421 | .ReOrderEccControl (port3_ReOrderEccControl), | |
5422 | .PacketAssyEngineDataIn (port3_PacketAssyEngineDataIn), | |
5423 | .ReOrderCorruptECCSingle (port3_ReOrderCorruptECCSingle), | |
5424 | .ReOrderCorruptECCDouble (port3_ReOrderCorruptECCDouble), | |
5425 | .ReOrderFifoWrite (port3_ReOrderFifoWrite), | |
5426 | .ReOrderFifoReadStrobe (port3_ReOrderFifoRead), | |
5427 | .ReOrderWritePtr (port3_ReOrderWritePtr), | |
5428 | .ReOrderReadPtr (port3_ReOrderReadPtr), | |
5429 | .ReOrderEngineDataOut (port3_ReOrderEngineDataOut), | |
5430 | ||
5431 | .StoreForwardUnCorrectError (port3_StoreForward_UnCorrectError), | |
5432 | .StoreForwardEccControl (port3_StoreForwardEccControl), | |
5433 | .MacXferEngineDataIn (port3_MacXferEngineDataIn), | |
5434 | .StoreForward_CorruptECCSingle (port3_StoreForwardCorruptECCSingle), | |
5435 | .StoreForward_CorruptECCDouble (port3_StoreForwardCorruptECCDouble), | |
5436 | .StoreForwardFifoWrite (port3_StoreForwardFifoWrite), | |
5437 | .StoreForwardFifoReadStrobe (port3_StoreForwardFifoRead), | |
5438 | .StoreForwardWritePtr (port3_StoreForwardWritePtr), | |
5439 | .StoreForwardReadPtr (port3_StoreForwardReadPtr), | |
5440 | .PacketAssyEngineDataOut (port3_PacketAssyEngineDataOut), | |
5441 | ||
5442 | .LatchActiveDMA (port3_LatchActiveDMA), | |
5443 | .ContextActiveList (port3_ContextActiveList), | |
5444 | ||
5445 | .Anchor_State (port3_Anchor_State), | |
5446 | .ReOrder_State (port3_ReOrder_State), | |
5447 | .Pointer_State (port3_Pointer_State), | |
5448 | .PacketAssy_State (port3_PacketAssy_State), | |
5449 | .DRR_ArbState (port3_DRR_ArbState), | |
5450 | .Mac_Xfer_State (port3_Mac_Xfer_State), | |
5451 | .DataPortReq_State (port3_DataPortReq_State), | |
5452 | .Sum_prt_state (port3_Sum_prt_state) | |
5453 | ); | |
5454 | ||
5455 | ||
5456 | niu_txc_ecc_engine port3_niu_txc_ecc_engine ( | |
5457 | .SysClk (niu_clk), | |
5458 | .Reset_L (reset_l), | |
5459 | .ReOrder_ClearEccError (port3_ReOrder_ClearEccError), | |
5460 | .WrReOrderEccState (port3_WrReOrderEccState), | |
5461 | .WrReOrderEccData0 (port3_WrReOrderEccData0), | |
5462 | .WrReOrderEccData1 (port3_WrReOrderEccData1), | |
5463 | .WrReOrderEccData2 (port3_WrReOrderEccData2), | |
5464 | .WrReOrderEccData3 (port3_WrReOrderEccData3), | |
5465 | .WrReOrderEccData4 (port3_WrReOrderEccData4), | |
5466 | .StoreForward_ClearEccError (port3_StoreForward_ClearEccError), | |
5467 | .WrStoreForwardEccState (port3_WrStoreForwardEccState), | |
5468 | .WrStoreForwardEccData0 (port3_WrStoreForwardEccData0), | |
5469 | .WrStoreForwardEccData1 (port3_WrStoreForwardEccData1), | |
5470 | .WrStoreForwardEccData2 (port3_WrStoreForwardEccData2), | |
5471 | .WrStoreForwardEccData3 (port3_WrStoreForwardEccData3), | |
5472 | .WrStoreForwardEccData4 (port3_WrStoreForwardEccData4), | |
5473 | .PioDataIn (port3_PioDataIn), | |
5474 | .ReOrder_ECC_State (port3_ReOrder_ECC_State), | |
5475 | .ReOrder_EccData (port3_ReOrder_EccData), | |
5476 | .StoreForward_ECC_State (port3_StoreForward_ECC_State), | |
5477 | .StoreForward_EccData (port3_StoreForward_EccData), | |
5478 | .ReOrder_CorruptECCSingle (port3_ReOrderCorruptECCSingle), | |
5479 | .ReOrder_CorruptECCDouble (port3_ReOrderCorruptECCDouble), | |
5480 | .ReOrder_FifoRead (port3_ReOrderFifoRead), | |
5481 | .ReOrder_ReadPtr (port3_ReOrderReadPtr), | |
5482 | .ReOrder_FifoDataOut (port3_ReOrderFifoDataOut), | |
5483 | .ReOrder_FifoDataValid (port3_ReOrderFifoDataValid), | |
5484 | .ReOrder_UnCorrectError (port3_ReOrder_UnCorrectError), | |
5485 | .ReOrder_PreECCData (port3_ReOrderEngineDataOut), | |
5486 | .ReOrder_PostECCData (port3_ReOrderFifoDataIn), | |
5487 | .ReOrder_CorrectedData (port3_PacketAssyEngineDataIn), | |
5488 | .StoreForward_CorruptECCSingle (port3_StoreForwardCorruptECCSingle), | |
5489 | .StoreForward_CorruptECCDouble (port3_StoreForwardCorruptECCDouble), | |
5490 | .StoreForward_FifoRead (port3_StoreForwardFifoRead), | |
5491 | .StoreForward_ReadPtr (port3_StoreForwardReadPtr), | |
5492 | .StoreForward_FifoDataOut (port3_StoreForwardFifoDataOut), | |
5493 | .StoreForward_UnCorrectError (port3_StoreForward_UnCorrectError), | |
5494 | .StoreForward_PreECCData (port3_PacketAssyEngineDataOut), | |
5495 | .StoreForward_PostECCData (port3_StoreForwardFifoDataIn), | |
5496 | .StoreForward_CorrectedData (port3_MacXferEngineDataIn) | |
5497 | ); | |
5498 | ||
5499 | ||
5500 | niu_ram_1024_152 port3_RO_RAM ( | |
5501 | .clk (niu_clk), | |
5502 | .wt_enable (port3_ReOrderFifoWrite), | |
5503 | .cs_rd (port3_ReOrderFifoRead), | |
5504 | .addr_rd (port3_ReOrderReadPtr), | |
5505 | .addr_wt (port3_ReOrderWritePtr), | |
5506 | .data_inp (port3_ReOrderFifoDataIn), | |
5507 | .data_out (port3_ReOrderFifoDataOut) | |
5508 | ); | |
5509 | ||
5510 | ||
5511 | niu_ram_640_152 port3_SF_RAM ( | |
5512 | .clk (niu_clk), | |
5513 | .wt_enable (port3_StoreForwardFifoWrite), | |
5514 | .cs_rd (port3_StoreForwardFifoRead), | |
5515 | .addr_rd (port3_StoreForwardReadPtr), | |
5516 | .addr_wt (port3_StoreForwardWritePtr), | |
5517 | .data_inp (port3_StoreForwardFifoDataIn), | |
5518 | .data_out (port3_StoreForwardFifoDataOut) | |
5519 | ); | |
5520 | ||
5521 | ||
5522 | `endif | |
5523 | ||
5524 | ||
5525 | niu_txc_ControlRegs niu_txc_ControlRegs ( | |
5526 | .SysClk (niu_clk), | |
5527 | .Reset_L (reset_l), | |
5528 | .niu_txc_interrupts (niu_txc_interrupts), | |
5529 | .Slave_32BitMode (pio_clients_32b), | |
5530 | .Slave_Read (pio_clients_rd), | |
5531 | .Slave_Sel (pio_txc_sel), | |
5532 | .Slave_Addr (pio_clients_addr), | |
5533 | .Slave_DataIn (pio_clients_wdata[31:0]), | |
5534 | .Slave_Ack (txc_pio_ack), | |
5535 | .Slave_Err (txc_pio_err), | |
5536 | .Slave_DataOut (txc_pio_rdata), | |
5537 | ||
5538 | .Txc_Enabled (txc_Enabled), | |
5539 | .MAC0_Enabled (port0_Enabled), | |
5540 | .MAC1_Enabled (port1_Enabled), | |
5541 | `ifdef NEPTUNE | |
5542 | .MAC2_Enabled (port2_Enabled), | |
5543 | .MAC3_Enabled (port3_Enabled), | |
5544 | `endif | |
5545 | .FlushEngine (flushEngine), | |
5546 | ||
5547 | .Port0_PacketAssyDead (port0_PacketAssyDead), | |
5548 | .Port0_ReOrder_Error (port0_ReOrder_Error), | |
5549 | ||
5550 | .Port0_ReOrderEccControl (port0_ReOrderEccControl), | |
5551 | .Port0_StoreForwardEccControl (port0_StoreForwardEccControl), | |
5552 | .Port0_ClrMaxBurst (port0_clrMaxBurst), | |
5553 | .Port0_UpdateDMA (port0_UpdateDMA), | |
5554 | .Port0_UpdateDMALength (port0_UpdateDMALength), | |
5555 | .Port0_UpdateDMANumber (port0_UpdateDMANumber), | |
5556 | .Port0_ClearStatistics (port0_ClearStatistics), | |
5557 | .Port0_WrPacketStuffed (port0_WrPacketStuffed), | |
5558 | .Port0_WrPacketXmitted (port0_WrPacketXmitted), | |
5559 | .Port0_WrPacketRequested (port0_WrPacketRequested), | |
5560 | .Port0_GatherRequestCount (port0_GatherRequestCount), | |
5561 | .Port0_PacketRequestCount (port0_PacketRequestCount), | |
5562 | .Port0_PktErrAbortCount (port0_PktErrAbortCount), | |
5563 | .Port0_ReOrdersStuffed (port0_ReOrdersStuffed), | |
5564 | .Port0_PacketsStuffed (port0_PacketsStuffed), | |
5565 | .Port0_PacketsTransmitted (port0_PacketsTransmitted), | |
5566 | .Port0_BytesTransmitted (port0_BytesTransmitted), | |
5567 | .Port0_MaxReorderNumber (port0_MaxReorderNumber), | |
5568 | .Port0_DMA_List (port0_DMA_List), | |
5569 | ||
5570 | .Port0_TidsInUse (port0_TidsInUse), | |
5571 | .Port0_DuplicateTid (port0_DuplicateTid), | |
5572 | .Port0_UnInitializedTID (port0_UnInitializedTID), | |
5573 | .Port0_TimedoutTids (port0_TimedoutTids), | |
5574 | .Port0_ReOrderStateLogic (port0_ReOrderStateLogic), | |
5575 | .Port0_ReOrderStateControl (port0_ReOrderStateControl), | |
5576 | .Port0_ReOrderStateData0 (port0_ReOrderStateData0), | |
5577 | .Port0_ReOrderStateData1 (port0_ReOrderStateData1), | |
5578 | .Port0_ReOrderStateData2 (port0_ReOrderStateData2), | |
5579 | .Port0_ReOrderStateData3 (port0_ReOrderStateData3), | |
5580 | .Port0_WrTidsInUse (port0_WrTidsInUse), | |
5581 | .Port0_WrDuplicateTid (port0_WrDuplicateTid), | |
5582 | .Port0_WrUnInitializedTID (port0_WrUnInitializedTID), | |
5583 | .Port0_WrTimedoutTids (port0_WrTimedoutTids), | |
5584 | .Port0_WrReOrderStateLogic (port0_WrReOrderStateLogic), | |
5585 | .Port0_WrReOrderStateControl (port0_WrReOrderStateControl), | |
5586 | .Port0_WrReOrderStateData0 (port0_WrReOrderStateData0), | |
5587 | .Port0_WrReOrderStateData1 (port0_WrReOrderStateData1), | |
5588 | .Port0_WrReOrderStateData2 (port0_WrReOrderStateData2), | |
5589 | .Port0_WrReOrderStateData3 (port0_WrReOrderStateData3), | |
5590 | .Port0_PioDataIn (port0_PioDataIn), | |
5591 | ||
5592 | .Port0_ReOrder_ECC_State (port0_ReOrder_ECC_State), | |
5593 | .Port0_ReOrder_EccData (port0_ReOrder_EccData), | |
5594 | .Port0_StoreForward_ECC_State (port0_StoreForward_ECC_State), | |
5595 | .Port0_StoreForward_EccData (port0_StoreForward_EccData), | |
5596 | .Port0_ReOrder_ClearEccError (port0_ReOrder_ClearEccError), | |
5597 | .Port0_WrReOrderEccState (port0_WrReOrderEccState), | |
5598 | .Port0_WrReOrderEccData0 (port0_WrReOrderEccData0), | |
5599 | .Port0_WrReOrderEccData1 (port0_WrReOrderEccData1), | |
5600 | .Port0_WrReOrderEccData2 (port0_WrReOrderEccData2), | |
5601 | .Port0_WrReOrderEccData3 (port0_WrReOrderEccData3), | |
5602 | .Port0_WrReOrderEccData4 (port0_WrReOrderEccData4), | |
5603 | .Port0_StoreForward_ClearEccError (port0_StoreForward_ClearEccError), | |
5604 | .Port0_WrStoreForwardEccState (port0_WrStoreForwardEccState), | |
5605 | .Port0_WrStoreForwardEccData0 (port0_WrStoreForwardEccData0), | |
5606 | .Port0_WrStoreForwardEccData1 (port0_WrStoreForwardEccData1), | |
5607 | .Port0_WrStoreForwardEccData2 (port0_WrStoreForwardEccData2), | |
5608 | .Port0_WrStoreForwardEccData3 (port0_WrStoreForwardEccData3), | |
5609 | .Port0_WrStoreForwardEccData4 (port0_WrStoreForwardEccData4), | |
5610 | ||
5611 | .Port1_PacketAssyDead (port1_PacketAssyDead), | |
5612 | .Port1_ReOrder_Error (port1_ReOrder_Error), | |
5613 | ||
5614 | .Port1_ReOrderEccControl (port1_ReOrderEccControl), | |
5615 | .Port1_StoreForwardEccControl (port1_StoreForwardEccControl), | |
5616 | .Port1_ClrMaxBurst (port1_clrMaxBurst), | |
5617 | .Port1_UpdateDMA (port1_UpdateDMA), | |
5618 | .Port1_UpdateDMALength (port1_UpdateDMALength), | |
5619 | .Port1_UpdateDMANumber (port1_UpdateDMANumber), | |
5620 | .Port1_ClearStatistics (port1_ClearStatistics), | |
5621 | .Port1_WrPacketStuffed (port1_WrPacketStuffed), | |
5622 | .Port1_WrPacketXmitted (port1_WrPacketXmitted), | |
5623 | .Port1_WrPacketRequested (port1_WrPacketRequested), | |
5624 | .Port1_GatherRequestCount (port1_GatherRequestCount), | |
5625 | .Port1_PacketRequestCount (port1_PacketRequestCount), | |
5626 | .Port1_PktErrAbortCount (port1_PktErrAbortCount), | |
5627 | .Port1_ReOrdersStuffed (port1_ReOrdersStuffed), | |
5628 | .Port1_PacketsStuffed (port1_PacketsStuffed), | |
5629 | .Port1_PacketsTransmitted (port1_PacketsTransmitted), | |
5630 | .Port1_BytesTransmitted (port1_BytesTransmitted), | |
5631 | .Port1_MaxReorderNumber (port1_MaxReorderNumber), | |
5632 | .Port1_DMA_List (port1_DMA_List), | |
5633 | ||
5634 | .Port1_TidsInUse (port1_TidsInUse), | |
5635 | .Port1_DuplicateTid (port1_DuplicateTid), | |
5636 | .Port1_UnInitializedTID (port1_UnInitializedTID), | |
5637 | .Port1_TimedoutTids (port1_TimedoutTids), | |
5638 | .Port1_ReOrderStateLogic (port1_ReOrderStateLogic), | |
5639 | .Port1_ReOrderStateControl (port1_ReOrderStateControl), | |
5640 | .Port1_ReOrderStateData0 (port1_ReOrderStateData0), | |
5641 | .Port1_ReOrderStateData1 (port1_ReOrderStateData1), | |
5642 | .Port1_ReOrderStateData2 (port1_ReOrderStateData2), | |
5643 | .Port1_ReOrderStateData3 (port1_ReOrderStateData3), | |
5644 | .Port1_WrTidsInUse (port1_WrTidsInUse), | |
5645 | .Port1_WrDuplicateTid (port1_WrDuplicateTid), | |
5646 | .Port1_WrUnInitializedTID (port1_WrUnInitializedTID), | |
5647 | .Port1_WrTimedoutTids (port1_WrTimedoutTids), | |
5648 | .Port1_WrReOrderStateLogic (port1_WrReOrderStateLogic), | |
5649 | .Port1_WrReOrderStateControl (port1_WrReOrderStateControl), | |
5650 | .Port1_WrReOrderStateData0 (port1_WrReOrderStateData0), | |
5651 | .Port1_WrReOrderStateData1 (port1_WrReOrderStateData1), | |
5652 | .Port1_WrReOrderStateData2 (port1_WrReOrderStateData2), | |
5653 | .Port1_WrReOrderStateData3 (port1_WrReOrderStateData3), | |
5654 | .Port1_PioDataIn (port1_PioDataIn), | |
5655 | ||
5656 | .Port1_ReOrder_ECC_State (port1_ReOrder_ECC_State), | |
5657 | .Port1_ReOrder_EccData (port1_ReOrder_EccData), | |
5658 | .Port1_StoreForward_ECC_State (port1_StoreForward_ECC_State), | |
5659 | .Port1_StoreForward_EccData (port1_StoreForward_EccData), | |
5660 | .Port1_ReOrder_ClearEccError (port1_ReOrder_ClearEccError), | |
5661 | .Port1_WrReOrderEccState (port1_WrReOrderEccState), | |
5662 | .Port1_WrReOrderEccData0 (port1_WrReOrderEccData0), | |
5663 | .Port1_WrReOrderEccData1 (port1_WrReOrderEccData1), | |
5664 | .Port1_WrReOrderEccData2 (port1_WrReOrderEccData2), | |
5665 | .Port1_WrReOrderEccData3 (port1_WrReOrderEccData3), | |
5666 | .Port1_WrReOrderEccData4 (port1_WrReOrderEccData4), | |
5667 | .Port1_StoreForward_ClearEccError (port1_StoreForward_ClearEccError), | |
5668 | .Port1_WrStoreForwardEccState (port1_WrStoreForwardEccState), | |
5669 | .Port1_WrStoreForwardEccData0 (port1_WrStoreForwardEccData0), | |
5670 | .Port1_WrStoreForwardEccData1 (port1_WrStoreForwardEccData1), | |
5671 | .Port1_WrStoreForwardEccData2 (port1_WrStoreForwardEccData2), | |
5672 | .Port1_WrStoreForwardEccData3 (port1_WrStoreForwardEccData3), | |
5673 | .Port1_WrStoreForwardEccData4 (port1_WrStoreForwardEccData4), | |
5674 | ||
5675 | `ifdef NEPTUNE | |
5676 | .Port2_PacketAssyDead (port2_PacketAssyDead), | |
5677 | .Port2_ReOrder_Error (port2_ReOrder_Error), | |
5678 | ||
5679 | .Port2_ReOrderEccControl (port2_ReOrderEccControl), | |
5680 | .Port2_StoreForwardEccControl (port2_StoreForwardEccControl), | |
5681 | .Port2_ClrMaxBurst (port2_clrMaxBurst), | |
5682 | .Port2_UpdateDMA (port2_UpdateDMA), | |
5683 | .Port2_UpdateDMALength (port2_UpdateDMALength), | |
5684 | .Port2_UpdateDMANumber (port2_UpdateDMANumber), | |
5685 | .Port2_ClearStatistics (port2_ClearStatistics), | |
5686 | .Port2_WrPacketStuffed (port2_WrPacketStuffed), | |
5687 | .Port2_WrPacketXmitted (port2_WrPacketXmitted), | |
5688 | .Port2_WrPacketRequested (port2_WrPacketRequested), | |
5689 | .Port2_GatherRequestCount (port2_GatherRequestCount), | |
5690 | .Port2_PacketRequestCount (port2_PacketRequestCount), | |
5691 | .Port2_PktErrAbortCount (port2_PktErrAbortCount), | |
5692 | .Port2_ReOrdersStuffed (port2_ReOrdersStuffed), | |
5693 | .Port2_PacketsStuffed (port2_PacketsStuffed), | |
5694 | .Port2_PacketsTransmitted (port2_PacketsTransmitted), | |
5695 | .Port2_BytesTransmitted (port2_BytesTransmitted), | |
5696 | .Port2_MaxReorderNumber (port2_MaxReorderNumber), | |
5697 | .Port2_DMA_List (port2_DMA_List), | |
5698 | ||
5699 | .Port2_TidsInUse (port2_TidsInUse), | |
5700 | .Port2_DuplicateTid (port2_DuplicateTid), | |
5701 | .Port2_UnInitializedTID (port2_UnInitializedTID), | |
5702 | .Port2_TimedoutTids (port2_TimedoutTids), | |
5703 | .Port2_ReOrderStateLogic (port2_ReOrderStateLogic), | |
5704 | .Port2_ReOrderStateControl (port2_ReOrderStateControl), | |
5705 | .Port2_ReOrderStateData0 (port2_ReOrderStateData0), | |
5706 | .Port2_ReOrderStateData1 (port2_ReOrderStateData1), | |
5707 | .Port2_ReOrderStateData2 (port2_ReOrderStateData2), | |
5708 | .Port2_ReOrderStateData3 (port2_ReOrderStateData3), | |
5709 | .Port2_WrTidsInUse (port2_WrTidsInUse), | |
5710 | .Port2_WrDuplicateTid (port2_WrDuplicateTid), | |
5711 | .Port2_WrUnInitializedTID (port2_WrUnInitializedTID), | |
5712 | .Port2_WrTimedoutTids (port2_WrTimedoutTids), | |
5713 | .Port2_WrReOrderStateLogic (port2_WrReOrderStateLogic), | |
5714 | .Port2_WrReOrderStateControl (port2_WrReOrderStateControl), | |
5715 | .Port2_WrReOrderStateData0 (port2_WrReOrderStateData0), | |
5716 | .Port2_WrReOrderStateData1 (port2_WrReOrderStateData1), | |
5717 | .Port2_WrReOrderStateData2 (port2_WrReOrderStateData2), | |
5718 | .Port2_WrReOrderStateData3 (port2_WrReOrderStateData3), | |
5719 | .Port2_PioDataIn (port2_PioDataIn), | |
5720 | ||
5721 | .Port2_ReOrder_ECC_State (port2_ReOrder_ECC_State), | |
5722 | .Port2_ReOrder_EccData (port2_ReOrder_EccData), | |
5723 | .Port2_StoreForward_ECC_State (port2_StoreForward_ECC_State), | |
5724 | .Port2_StoreForward_EccData (port2_StoreForward_EccData), | |
5725 | .Port2_ReOrder_ClearEccError (port2_ReOrder_ClearEccError), | |
5726 | .Port2_WrReOrderEccState (port2_WrReOrderEccState), | |
5727 | .Port2_WrReOrderEccData0 (port2_WrReOrderEccData0), | |
5728 | .Port2_WrReOrderEccData1 (port2_WrReOrderEccData1), | |
5729 | .Port2_WrReOrderEccData2 (port2_WrReOrderEccData2), | |
5730 | .Port2_WrReOrderEccData3 (port2_WrReOrderEccData3), | |
5731 | .Port2_WrReOrderEccData4 (port2_WrReOrderEccData4), | |
5732 | .Port2_StoreForward_ClearEccError (port2_StoreForward_ClearEccError), | |
5733 | .Port2_WrStoreForwardEccState (port2_WrStoreForwardEccState), | |
5734 | .Port2_WrStoreForwardEccData0 (port2_WrStoreForwardEccData0), | |
5735 | .Port2_WrStoreForwardEccData1 (port2_WrStoreForwardEccData1), | |
5736 | .Port2_WrStoreForwardEccData2 (port2_WrStoreForwardEccData2), | |
5737 | .Port2_WrStoreForwardEccData3 (port2_WrStoreForwardEccData3), | |
5738 | .Port2_WrStoreForwardEccData4 (port2_WrStoreForwardEccData4), | |
5739 | ||
5740 | .Port3_PacketAssyDead (port3_PacketAssyDead), | |
5741 | .Port3_ReOrder_Error (port3_ReOrder_Error), | |
5742 | ||
5743 | .Port3_ReOrderEccControl (port3_ReOrderEccControl), | |
5744 | .Port3_StoreForwardEccControl (port3_StoreForwardEccControl), | |
5745 | .Port3_ClrMaxBurst (port3_clrMaxBurst), | |
5746 | .Port3_UpdateDMA (port3_UpdateDMA), | |
5747 | .Port3_UpdateDMALength (port3_UpdateDMALength), | |
5748 | .Port3_UpdateDMANumber (port3_UpdateDMANumber), | |
5749 | .Port3_ClearStatistics (port3_ClearStatistics), | |
5750 | .Port3_WrPacketStuffed (port3_WrPacketStuffed), | |
5751 | .Port3_WrPacketXmitted (port3_WrPacketXmitted), | |
5752 | .Port3_WrPacketRequested (port3_WrPacketRequested), | |
5753 | .Port3_GatherRequestCount (port3_GatherRequestCount), | |
5754 | .Port3_PacketRequestCount (port3_PacketRequestCount), | |
5755 | .Port3_PktErrAbortCount (port3_PktErrAbortCount), | |
5756 | .Port3_ReOrdersStuffed (port3_ReOrdersStuffed), | |
5757 | .Port3_PacketsStuffed (port3_PacketsStuffed), | |
5758 | .Port3_PacketsTransmitted (port3_PacketsTransmitted), | |
5759 | .Port3_BytesTransmitted (port3_BytesTransmitted), | |
5760 | .Port3_MaxReorderNumber (port3_MaxReorderNumber), | |
5761 | .Port3_DMA_List (port3_DMA_List), | |
5762 | ||
5763 | .Port3_TidsInUse (port3_TidsInUse), | |
5764 | .Port3_DuplicateTid (port3_DuplicateTid), | |
5765 | .Port3_UnInitializedTID (port3_UnInitializedTID), | |
5766 | .Port3_TimedoutTids (port3_TimedoutTids), | |
5767 | .Port3_ReOrderStateLogic (port3_ReOrderStateLogic), | |
5768 | .Port3_ReOrderStateControl (port3_ReOrderStateControl), | |
5769 | .Port3_ReOrderStateData0 (port3_ReOrderStateData0), | |
5770 | .Port3_ReOrderStateData1 (port3_ReOrderStateData1), | |
5771 | .Port3_ReOrderStateData2 (port3_ReOrderStateData2), | |
5772 | .Port3_ReOrderStateData3 (port3_ReOrderStateData3), | |
5773 | .Port3_WrTidsInUse (port3_WrTidsInUse), | |
5774 | .Port3_WrDuplicateTid (port3_WrDuplicateTid), | |
5775 | .Port3_WrUnInitializedTID (port3_WrUnInitializedTID), | |
5776 | .Port3_WrTimedoutTids (port3_WrTimedoutTids), | |
5777 | .Port3_WrReOrderStateLogic (port3_WrReOrderStateLogic), | |
5778 | .Port3_WrReOrderStateControl (port3_WrReOrderStateControl), | |
5779 | .Port3_WrReOrderStateData0 (port3_WrReOrderStateData0), | |
5780 | .Port3_WrReOrderStateData1 (port3_WrReOrderStateData1), | |
5781 | .Port3_WrReOrderStateData2 (port3_WrReOrderStateData2), | |
5782 | .Port3_WrReOrderStateData3 (port3_WrReOrderStateData3), | |
5783 | .Port3_PioDataIn (port3_PioDataIn), | |
5784 | ||
5785 | .Port3_ReOrder_ECC_State (port3_ReOrder_ECC_State), | |
5786 | .Port3_ReOrder_EccData (port3_ReOrder_EccData), | |
5787 | .Port3_StoreForward_ECC_State (port3_StoreForward_ECC_State), | |
5788 | .Port3_StoreForward_EccData (port3_StoreForward_EccData), | |
5789 | .Port3_ReOrder_ClearEccError (port3_ReOrder_ClearEccError), | |
5790 | .Port3_WrReOrderEccState (port3_WrReOrderEccState), | |
5791 | .Port3_WrReOrderEccData0 (port3_WrReOrderEccData0), | |
5792 | .Port3_WrReOrderEccData1 (port3_WrReOrderEccData1), | |
5793 | .Port3_WrReOrderEccData2 (port3_WrReOrderEccData2), | |
5794 | .Port3_WrReOrderEccData3 (port3_WrReOrderEccData3), | |
5795 | .Port3_WrReOrderEccData4 (port3_WrReOrderEccData4), | |
5796 | .Port3_StoreForward_ClearEccError (port3_StoreForward_ClearEccError), | |
5797 | .Port3_WrStoreForwardEccState (port3_WrStoreForwardEccState), | |
5798 | .Port3_WrStoreForwardEccData0 (port3_WrStoreForwardEccData0), | |
5799 | .Port3_WrStoreForwardEccData1 (port3_WrStoreForwardEccData1), | |
5800 | .Port3_WrStoreForwardEccData2 (port3_WrStoreForwardEccData2), | |
5801 | .Port3_WrStoreForwardEccData3 (port3_WrStoreForwardEccData3), | |
5802 | .Port3_WrStoreForwardEccData4 (port3_WrStoreForwardEccData4), | |
5803 | `endif | |
5804 | .DMA0_NewMaxBurst (dma0_NewMaxBurst), | |
5805 | .DMA0_MaxBurst (dma0_MaxBurst), | |
5806 | .DMA1_NewMaxBurst (dma1_NewMaxBurst), | |
5807 | .DMA1_MaxBurst (dma1_MaxBurst), | |
5808 | .DMA2_NewMaxBurst (dma2_NewMaxBurst), | |
5809 | .DMA2_MaxBurst (dma2_MaxBurst), | |
5810 | .DMA3_NewMaxBurst (dma3_NewMaxBurst), | |
5811 | .DMA3_MaxBurst (dma3_MaxBurst), | |
5812 | .DMA4_NewMaxBurst (dma4_NewMaxBurst), | |
5813 | .DMA4_MaxBurst (dma4_MaxBurst), | |
5814 | .DMA5_NewMaxBurst (dma5_NewMaxBurst), | |
5815 | .DMA5_MaxBurst (dma5_MaxBurst), | |
5816 | .DMA6_NewMaxBurst (dma6_NewMaxBurst), | |
5817 | .DMA6_MaxBurst (dma6_MaxBurst), | |
5818 | .DMA7_NewMaxBurst (dma7_NewMaxBurst), | |
5819 | .DMA7_MaxBurst (dma7_MaxBurst), | |
5820 | .DMA8_NewMaxBurst (dma8_NewMaxBurst), | |
5821 | .DMA8_MaxBurst (dma8_MaxBurst), | |
5822 | .DMA9_NewMaxBurst (dma9_NewMaxBurst), | |
5823 | .DMA9_MaxBurst (dma9_MaxBurst), | |
5824 | .DMA10_NewMaxBurst (dma10_NewMaxBurst), | |
5825 | .DMA10_MaxBurst (dma10_MaxBurst), | |
5826 | .DMA11_NewMaxBurst (dma11_NewMaxBurst), | |
5827 | .DMA11_MaxBurst (dma11_MaxBurst), | |
5828 | .DMA12_NewMaxBurst (dma12_NewMaxBurst), | |
5829 | .DMA12_MaxBurst (dma12_MaxBurst), | |
5830 | .DMA13_NewMaxBurst (dma13_NewMaxBurst), | |
5831 | .DMA13_MaxBurst (dma13_MaxBurst), | |
5832 | .DMA14_NewMaxBurst (dma14_NewMaxBurst), | |
5833 | .DMA14_MaxBurst (dma14_MaxBurst), | |
5834 | .DMA15_NewMaxBurst (dma15_NewMaxBurst), | |
5835 | .DMA15_MaxBurst (dma15_MaxBurst), | |
5836 | .DMA16_NewMaxBurst (dma16_NewMaxBurst), | |
5837 | .DMA16_MaxBurst (dma16_MaxBurst), | |
5838 | .DMA17_NewMaxBurst (dma17_NewMaxBurst), | |
5839 | .DMA17_MaxBurst (dma17_MaxBurst), | |
5840 | .DMA18_NewMaxBurst (dma18_NewMaxBurst), | |
5841 | .DMA18_MaxBurst (dma18_MaxBurst), | |
5842 | .DMA19_NewMaxBurst (dma19_NewMaxBurst), | |
5843 | .DMA19_MaxBurst (dma19_MaxBurst), | |
5844 | .DMA20_NewMaxBurst (dma20_NewMaxBurst), | |
5845 | .DMA20_MaxBurst (dma20_MaxBurst), | |
5846 | .DMA21_NewMaxBurst (dma21_NewMaxBurst), | |
5847 | .DMA21_MaxBurst (dma21_MaxBurst), | |
5848 | .DMA22_NewMaxBurst (dma22_NewMaxBurst), | |
5849 | .DMA22_MaxBurst (dma22_MaxBurst), | |
5850 | .DMA23_NewMaxBurst (dma23_NewMaxBurst), | |
5851 | .DMA23_MaxBurst (dma23_MaxBurst), | |
5852 | ||
5853 | .Debug_Select (debug_select), | |
5854 | .TrainingVector (trainingVector) | |
5855 | ); | |
5856 | ||
5857 | ||
5858 | niu_txc_debug niu_txc_debug ( | |
5859 | .SysClk (niu_clk), | |
5860 | .Reset_L (reset_l), | |
5861 | .Debug_Select (debug_select), | |
5862 | .TrainingVector (trainingVector), | |
5863 | .PortSelect_State (portSelect_State), | |
5864 | .DataFetch_State (dataFetch_State), | |
5865 | .Port0_LatchActiveDMA (port0_LatchActiveDMA), | |
5866 | .Port0_Anchor_State (port0_Anchor_State), | |
5867 | .Port0_ReOrder_State (port0_ReOrder_State), | |
5868 | .Port0_Pointer_State (port0_Pointer_State), | |
5869 | .Port0_PacketAssy_State (port0_PacketAssy_State), | |
5870 | .Port0_DRR_ArbState (port0_DRR_ArbState), | |
5871 | .Port0_Mac_Xfer_State (port0_Mac_Xfer_State), | |
5872 | .Port0_DataPortReq_State (port0_DataPortReq_State), | |
5873 | .Port0_ContextActiveList (port0_ContextActiveList), | |
5874 | .Port0_Sum_prt_state (port0_Sum_prt_state), | |
5875 | .Port1_LatchActiveDMA (port1_LatchActiveDMA), | |
5876 | .Port1_Anchor_State (port1_Anchor_State), | |
5877 | .Port1_ReOrder_State (port1_ReOrder_State), | |
5878 | .Port1_Pointer_State (port1_Pointer_State), | |
5879 | .Port1_PacketAssy_State (port1_PacketAssy_State), | |
5880 | .Port1_DRR_ArbState (port1_DRR_ArbState), | |
5881 | .Port1_Mac_Xfer_State (port1_Mac_Xfer_State), | |
5882 | .Port1_DataPortReq_State (port1_DataPortReq_State), | |
5883 | .Port1_ContextActiveList (port1_ContextActiveList), | |
5884 | .Port1_Sum_prt_state (port1_Sum_prt_state), | |
5885 | `ifdef NEPTUNE | |
5886 | .Port2_LatchActiveDMA (port2_LatchActiveDMA), | |
5887 | .Port2_Anchor_State (port2_Anchor_State), | |
5888 | .Port2_ReOrder_State (port2_ReOrder_State), | |
5889 | .Port2_Pointer_State (port2_Pointer_State), | |
5890 | .Port2_PacketAssy_State (port2_PacketAssy_State), | |
5891 | .Port2_DRR_ArbState (port2_DRR_ArbState), | |
5892 | .Port2_Mac_Xfer_State (port2_Mac_Xfer_State), | |
5893 | .Port2_DataPortReq_State (port2_DataPortReq_State), | |
5894 | .Port2_ContextActiveList (port2_ContextActiveList), | |
5895 | .Port2_Sum_prt_state (port2_Sum_prt_state), | |
5896 | .Port3_LatchActiveDMA (port3_LatchActiveDMA), | |
5897 | .Port3_Anchor_State (port3_Anchor_State), | |
5898 | .Port3_ReOrder_State (port3_ReOrder_State), | |
5899 | .Port3_Pointer_State (port3_Pointer_State), | |
5900 | .Port3_PacketAssy_State (port3_PacketAssy_State), | |
5901 | .Port3_DRR_ArbState (port3_DRR_ArbState), | |
5902 | .Port3_Mac_Xfer_State (port3_Mac_Xfer_State), | |
5903 | .Port3_DataPortReq_State (port3_DataPortReq_State), | |
5904 | .Port3_ContextActiveList (port3_ContextActiveList), | |
5905 | .Port3_Sum_prt_state (port3_Sum_prt_state), | |
5906 | `else | |
5907 | .Port2_LatchActiveDMA (1'b0), | |
5908 | .Port2_Anchor_State (4'h0), | |
5909 | .Port2_ReOrder_State (4'h0), | |
5910 | .Port2_Pointer_State (4'h0), | |
5911 | .Port2_PacketAssy_State (4'h0), | |
5912 | .Port2_DRR_ArbState (4'h0), | |
5913 | .Port2_Mac_Xfer_State (4'h0), | |
5914 | .Port2_DataPortReq_State (4'h0), | |
5915 | .Port2_ContextActiveList (24'h0), | |
5916 | .Port2_Sum_prt_state (32'h0), | |
5917 | .Port3_LatchActiveDMA (1'b0), | |
5918 | .Port3_Anchor_State (4'h0), | |
5919 | .Port3_ReOrder_State (4'h0), | |
5920 | .Port3_Pointer_State (4'h0), | |
5921 | .Port3_PacketAssy_State (4'h0), | |
5922 | .Port3_DRR_ArbState (4'h0), | |
5923 | .Port3_Mac_Xfer_State (4'h0), | |
5924 | .Port3_DataPortReq_State (4'h0), | |
5925 | .Port3_ContextActiveList (24'h0), | |
5926 | .Port3_Sum_prt_state (32'h0), | |
5927 | `endif | |
5928 | .Txc_Debug_Port (txc_debug_port) | |
5929 | ); | |
5930 | ||
5931 | ||
5932 | niu_txc_tdmc_ifc niu_txc_tdmc_ifc ( | |
5933 | .SysClk (niu_clk), | |
5934 | .Reset_L (reset_l), | |
5935 | ||
5936 | .Port0_Nack_Pkt_Rd (port0_Nack_Pkt_Rd), | |
5937 | .Port0_DMA_Nack_Pkt_Rd (port0_DMA_Nack_Pkt_Rd), | |
5938 | .Port0_Nack_Pkt_Rd_Addr (port0_Nack_Pkt_Rd_Addr), | |
5939 | .Port0_DMA0_inc_head (port0_DMA0_inc_head), | |
5940 | .Port0_DMA0_reset_done (port0_DMA0_reset_done), | |
5941 | .Port0_DMA0_mark_bit (port0_DMA0_mark_bit), | |
5942 | .Port0_DMA0_inc_pkt_cnt (port0_DMA0_inc_pkt_cnt), | |
5943 | .Port0_SetGetNextDescDMA0 (port0_SetGetNextDescDMA0), | |
5944 | .Port0_DMA1_inc_head (port0_DMA1_inc_head), | |
5945 | .Port0_DMA1_reset_done (port0_DMA1_reset_done), | |
5946 | .Port0_DMA1_mark_bit (port0_DMA1_mark_bit), | |
5947 | .Port0_DMA1_inc_pkt_cnt (port0_DMA1_inc_pkt_cnt), | |
5948 | .Port0_SetGetNextDescDMA1 (port0_SetGetNextDescDMA1), | |
5949 | .Port0_DMA2_inc_head (port0_DMA2_inc_head), | |
5950 | .Port0_DMA2_reset_done (port0_DMA2_reset_done), | |
5951 | .Port0_DMA2_mark_bit (port0_DMA2_mark_bit), | |
5952 | .Port0_DMA2_inc_pkt_cnt (port0_DMA2_inc_pkt_cnt), | |
5953 | .Port0_SetGetNextDescDMA2 (port0_SetGetNextDescDMA2), | |
5954 | .Port0_DMA3_inc_head (port0_DMA3_inc_head), | |
5955 | .Port0_DMA3_reset_done (port0_DMA3_reset_done), | |
5956 | .Port0_DMA3_mark_bit (port0_DMA3_mark_bit), | |
5957 | .Port0_DMA3_inc_pkt_cnt (port0_DMA3_inc_pkt_cnt), | |
5958 | .Port0_SetGetNextDescDMA3 (port0_SetGetNextDescDMA3), | |
5959 | .Port0_DMA4_inc_head (port0_DMA4_inc_head), | |
5960 | .Port0_DMA4_reset_done (port0_DMA4_reset_done), | |
5961 | .Port0_DMA4_mark_bit (port0_DMA4_mark_bit), | |
5962 | .Port0_DMA4_inc_pkt_cnt (port0_DMA4_inc_pkt_cnt), | |
5963 | .Port0_SetGetNextDescDMA4 (port0_SetGetNextDescDMA4), | |
5964 | .Port0_DMA5_inc_head (port0_DMA5_inc_head), | |
5965 | .Port0_DMA5_reset_done (port0_DMA5_reset_done), | |
5966 | .Port0_DMA5_mark_bit (port0_DMA5_mark_bit), | |
5967 | .Port0_DMA5_inc_pkt_cnt (port0_DMA5_inc_pkt_cnt), | |
5968 | .Port0_SetGetNextDescDMA5 (port0_SetGetNextDescDMA5), | |
5969 | .Port0_DMA6_inc_head (port0_DMA6_inc_head), | |
5970 | .Port0_DMA6_reset_done (port0_DMA6_reset_done), | |
5971 | .Port0_DMA6_mark_bit (port0_DMA6_mark_bit), | |
5972 | .Port0_DMA6_inc_pkt_cnt (port0_DMA6_inc_pkt_cnt), | |
5973 | .Port0_SetGetNextDescDMA6 (port0_SetGetNextDescDMA6), | |
5974 | .Port0_DMA7_inc_head (port0_DMA7_inc_head), | |
5975 | .Port0_DMA7_reset_done (port0_DMA7_reset_done), | |
5976 | .Port0_DMA7_mark_bit (port0_DMA7_mark_bit), | |
5977 | .Port0_DMA7_inc_pkt_cnt (port0_DMA7_inc_pkt_cnt), | |
5978 | .Port0_SetGetNextDescDMA7 (port0_SetGetNextDescDMA7), | |
5979 | .Port0_DMA8_inc_head (port0_DMA8_inc_head), | |
5980 | .Port0_DMA8_reset_done (port0_DMA8_reset_done), | |
5981 | .Port0_DMA8_mark_bit (port0_DMA8_mark_bit), | |
5982 | .Port0_DMA8_inc_pkt_cnt (port0_DMA8_inc_pkt_cnt), | |
5983 | .Port0_SetGetNextDescDMA8 (port0_SetGetNextDescDMA8), | |
5984 | .Port0_DMA9_inc_head (port0_DMA9_inc_head), | |
5985 | .Port0_DMA9_reset_done (port0_DMA9_reset_done), | |
5986 | .Port0_DMA9_mark_bit (port0_DMA9_mark_bit), | |
5987 | .Port0_DMA9_inc_pkt_cnt (port0_DMA9_inc_pkt_cnt), | |
5988 | .Port0_SetGetNextDescDMA9 (port0_SetGetNextDescDMA9), | |
5989 | .Port0_DMA10_inc_head (port0_DMA10_inc_head), | |
5990 | .Port0_DMA10_reset_done (port0_DMA10_reset_done), | |
5991 | .Port0_DMA10_mark_bit (port0_DMA10_mark_bit), | |
5992 | .Port0_DMA10_inc_pkt_cnt (port0_DMA10_inc_pkt_cnt), | |
5993 | .Port0_SetGetNextDescDMA10 (port0_SetGetNextDescDMA10), | |
5994 | .Port0_DMA11_inc_head (port0_DMA11_inc_head), | |
5995 | .Port0_DMA11_reset_done (port0_DMA11_reset_done), | |
5996 | .Port0_DMA11_mark_bit (port0_DMA11_mark_bit), | |
5997 | .Port0_DMA11_inc_pkt_cnt (port0_DMA11_inc_pkt_cnt), | |
5998 | .Port0_SetGetNextDescDMA11 (port0_SetGetNextDescDMA11), | |
5999 | .Port0_DMA12_inc_head (port0_DMA12_inc_head), | |
6000 | .Port0_DMA12_reset_done (port0_DMA12_reset_done), | |
6001 | .Port0_DMA12_mark_bit (port0_DMA12_mark_bit), | |
6002 | .Port0_DMA12_inc_pkt_cnt (port0_DMA12_inc_pkt_cnt), | |
6003 | .Port0_SetGetNextDescDMA12 (port0_SetGetNextDescDMA12), | |
6004 | .Port0_DMA13_inc_head (port0_DMA13_inc_head), | |
6005 | .Port0_DMA13_reset_done (port0_DMA13_reset_done), | |
6006 | .Port0_DMA13_mark_bit (port0_DMA13_mark_bit), | |
6007 | .Port0_DMA13_inc_pkt_cnt (port0_DMA13_inc_pkt_cnt), | |
6008 | .Port0_SetGetNextDescDMA13 (port0_SetGetNextDescDMA13), | |
6009 | .Port0_DMA14_inc_head (port0_DMA14_inc_head), | |
6010 | .Port0_DMA14_reset_done (port0_DMA14_reset_done), | |
6011 | .Port0_DMA14_mark_bit (port0_DMA14_mark_bit), | |
6012 | .Port0_DMA14_inc_pkt_cnt (port0_DMA14_inc_pkt_cnt), | |
6013 | .Port0_SetGetNextDescDMA14 (port0_SetGetNextDescDMA14), | |
6014 | .Port0_DMA15_inc_head (port0_DMA15_inc_head), | |
6015 | .Port0_DMA15_reset_done (port0_DMA15_reset_done), | |
6016 | .Port0_DMA15_mark_bit (port0_DMA15_mark_bit), | |
6017 | .Port0_DMA15_inc_pkt_cnt (port0_DMA15_inc_pkt_cnt), | |
6018 | .Port0_SetGetNextDescDMA15 (port0_SetGetNextDescDMA15), | |
6019 | `ifdef NEPTUNE | |
6020 | .Port0_DMA16_inc_head (port0_DMA16_inc_head), | |
6021 | .Port0_DMA16_reset_done (port0_DMA16_reset_done), | |
6022 | .Port0_DMA16_mark_bit (port0_DMA16_mark_bit), | |
6023 | .Port0_DMA16_inc_pkt_cnt (port0_DMA16_inc_pkt_cnt), | |
6024 | .Port0_SetGetNextDescDMA16 (port0_SetGetNextDescDMA16), | |
6025 | .Port0_DMA17_inc_head (port0_DMA17_inc_head), | |
6026 | .Port0_DMA17_reset_done (port0_DMA17_reset_done), | |
6027 | .Port0_DMA17_mark_bit (port0_DMA17_mark_bit), | |
6028 | .Port0_DMA17_inc_pkt_cnt (port0_DMA17_inc_pkt_cnt), | |
6029 | .Port0_SetGetNextDescDMA17 (port0_SetGetNextDescDMA17), | |
6030 | .Port0_DMA18_inc_head (port0_DMA18_inc_head), | |
6031 | .Port0_DMA18_reset_done (port0_DMA18_reset_done), | |
6032 | .Port0_DMA18_mark_bit (port0_DMA18_mark_bit), | |
6033 | .Port0_DMA18_inc_pkt_cnt (port0_DMA18_inc_pkt_cnt), | |
6034 | .Port0_SetGetNextDescDMA18 (port0_SetGetNextDescDMA18), | |
6035 | .Port0_DMA19_inc_head (port0_DMA19_inc_head), | |
6036 | .Port0_DMA19_reset_done (port0_DMA19_reset_done), | |
6037 | .Port0_DMA19_mark_bit (port0_DMA19_mark_bit), | |
6038 | .Port0_DMA19_inc_pkt_cnt (port0_DMA19_inc_pkt_cnt), | |
6039 | .Port0_SetGetNextDescDMA19 (port0_SetGetNextDescDMA19), | |
6040 | .Port0_DMA20_inc_head (port0_DMA20_inc_head), | |
6041 | .Port0_DMA20_reset_done (port0_DMA20_reset_done), | |
6042 | .Port0_DMA20_mark_bit (port0_DMA20_mark_bit), | |
6043 | .Port0_DMA20_inc_pkt_cnt (port0_DMA20_inc_pkt_cnt), | |
6044 | .Port0_SetGetNextDescDMA20 (port0_SetGetNextDescDMA20), | |
6045 | .Port0_DMA21_inc_head (port0_DMA21_inc_head), | |
6046 | .Port0_DMA21_reset_done (port0_DMA21_reset_done), | |
6047 | .Port0_DMA21_mark_bit (port0_DMA21_mark_bit), | |
6048 | .Port0_DMA21_inc_pkt_cnt (port0_DMA21_inc_pkt_cnt), | |
6049 | .Port0_SetGetNextDescDMA21 (port0_SetGetNextDescDMA21), | |
6050 | .Port0_DMA22_inc_head (port0_DMA22_inc_head), | |
6051 | .Port0_DMA22_reset_done (port0_DMA22_reset_done), | |
6052 | .Port0_DMA22_mark_bit (port0_DMA22_mark_bit), | |
6053 | .Port0_DMA22_inc_pkt_cnt (port0_DMA22_inc_pkt_cnt), | |
6054 | .Port0_SetGetNextDescDMA22 (port0_SetGetNextDescDMA22), | |
6055 | .Port0_DMA23_inc_head (port0_DMA23_inc_head), | |
6056 | .Port0_DMA23_reset_done (port0_DMA23_reset_done), | |
6057 | .Port0_DMA23_mark_bit (port0_DMA23_mark_bit), | |
6058 | .Port0_DMA23_inc_pkt_cnt (port0_DMA23_inc_pkt_cnt), | |
6059 | .Port0_SetGetNextDescDMA23 (port0_SetGetNextDescDMA23), | |
6060 | `else | |
6061 | .Port0_DMA16_inc_head (1'b0), | |
6062 | .Port0_DMA16_reset_done (1'b0), | |
6063 | .Port0_DMA16_mark_bit (1'b0), | |
6064 | .Port0_DMA16_inc_pkt_cnt (1'b0), | |
6065 | .Port0_SetGetNextDescDMA16 (1'b0), | |
6066 | .Port0_DMA17_inc_head (1'b0), | |
6067 | .Port0_DMA17_reset_done (1'b0), | |
6068 | .Port0_DMA17_mark_bit (1'b0), | |
6069 | .Port0_DMA17_inc_pkt_cnt (1'b0), | |
6070 | .Port0_SetGetNextDescDMA17 (1'b0), | |
6071 | .Port0_DMA18_inc_head (1'b0), | |
6072 | .Port0_DMA18_reset_done (1'b0), | |
6073 | .Port0_DMA18_mark_bit (1'b0), | |
6074 | .Port0_DMA18_inc_pkt_cnt (1'b0), | |
6075 | .Port0_SetGetNextDescDMA18 (1'b0), | |
6076 | .Port0_DMA19_inc_head (1'b0), | |
6077 | .Port0_DMA19_reset_done (1'b0), | |
6078 | .Port0_DMA19_mark_bit (1'b0), | |
6079 | .Port0_DMA19_inc_pkt_cnt (1'b0), | |
6080 | .Port0_SetGetNextDescDMA19 (1'b0), | |
6081 | .Port0_DMA20_inc_head (1'b0), | |
6082 | .Port0_DMA20_reset_done (1'b0), | |
6083 | .Port0_DMA20_mark_bit (1'b0), | |
6084 | .Port0_DMA20_inc_pkt_cnt (1'b0), | |
6085 | .Port0_SetGetNextDescDMA20 (1'b0), | |
6086 | .Port0_DMA21_inc_head (1'b0), | |
6087 | .Port0_DMA21_reset_done (1'b0), | |
6088 | .Port0_DMA21_mark_bit (1'b0), | |
6089 | .Port0_DMA21_inc_pkt_cnt (1'b0), | |
6090 | .Port0_SetGetNextDescDMA21 (1'b0), | |
6091 | .Port0_DMA22_inc_head (1'b0), | |
6092 | .Port0_DMA22_reset_done (1'b0), | |
6093 | .Port0_DMA22_mark_bit (1'b0), | |
6094 | .Port0_DMA22_inc_pkt_cnt (1'b0), | |
6095 | .Port0_SetGetNextDescDMA22 (1'b0), | |
6096 | .Port0_DMA23_inc_head (1'b0), | |
6097 | .Port0_DMA23_reset_done (1'b0), | |
6098 | .Port0_DMA23_mark_bit (1'b0), | |
6099 | .Port0_DMA23_inc_pkt_cnt (1'b0), | |
6100 | .Port0_SetGetNextDescDMA23 (1'b0), | |
6101 | `endif | |
6102 | .Port1_Nack_Pkt_Rd (port1_Nack_Pkt_Rd), | |
6103 | .Port1_DMA_Nack_Pkt_Rd (port1_DMA_Nack_Pkt_Rd), | |
6104 | .Port1_Nack_Pkt_Rd_Addr (port1_Nack_Pkt_Rd_Addr), | |
6105 | .Port1_DMA0_inc_head (port1_DMA0_inc_head), | |
6106 | .Port1_DMA0_reset_done (port1_DMA0_reset_done), | |
6107 | .Port1_DMA0_mark_bit (port1_DMA0_mark_bit), | |
6108 | .Port1_DMA0_inc_pkt_cnt (port1_DMA0_inc_pkt_cnt), | |
6109 | .Port1_SetGetNextDescDMA0 (port1_SetGetNextDescDMA0), | |
6110 | .Port1_DMA1_inc_head (port1_DMA1_inc_head), | |
6111 | .Port1_DMA1_reset_done (port1_DMA1_reset_done), | |
6112 | .Port1_DMA1_mark_bit (port1_DMA1_mark_bit), | |
6113 | .Port1_DMA1_inc_pkt_cnt (port1_DMA1_inc_pkt_cnt), | |
6114 | .Port1_SetGetNextDescDMA1 (port1_SetGetNextDescDMA1), | |
6115 | .Port1_DMA2_inc_head (port1_DMA2_inc_head), | |
6116 | .Port1_DMA2_reset_done (port1_DMA2_reset_done), | |
6117 | .Port1_DMA2_mark_bit (port1_DMA2_mark_bit), | |
6118 | .Port1_DMA2_inc_pkt_cnt (port1_DMA2_inc_pkt_cnt), | |
6119 | .Port1_SetGetNextDescDMA2 (port1_SetGetNextDescDMA2), | |
6120 | .Port1_DMA3_inc_head (port1_DMA3_inc_head), | |
6121 | .Port1_DMA3_reset_done (port1_DMA3_reset_done), | |
6122 | .Port1_DMA3_mark_bit (port1_DMA3_mark_bit), | |
6123 | .Port1_DMA3_inc_pkt_cnt (port1_DMA3_inc_pkt_cnt), | |
6124 | .Port1_SetGetNextDescDMA3 (port1_SetGetNextDescDMA3), | |
6125 | .Port1_DMA4_inc_head (port1_DMA4_inc_head), | |
6126 | .Port1_DMA4_reset_done (port1_DMA4_reset_done), | |
6127 | .Port1_DMA4_mark_bit (port1_DMA4_mark_bit), | |
6128 | .Port1_DMA4_inc_pkt_cnt (port1_DMA4_inc_pkt_cnt), | |
6129 | .Port1_SetGetNextDescDMA4 (port1_SetGetNextDescDMA4), | |
6130 | .Port1_DMA5_inc_head (port1_DMA5_inc_head), | |
6131 | .Port1_DMA5_reset_done (port1_DMA5_reset_done), | |
6132 | .Port1_DMA5_mark_bit (port1_DMA5_mark_bit), | |
6133 | .Port1_DMA5_inc_pkt_cnt (port1_DMA5_inc_pkt_cnt), | |
6134 | .Port1_SetGetNextDescDMA5 (port1_SetGetNextDescDMA5), | |
6135 | .Port1_DMA6_inc_head (port1_DMA6_inc_head), | |
6136 | .Port1_DMA6_reset_done (port1_DMA6_reset_done), | |
6137 | .Port1_DMA6_mark_bit (port1_DMA6_mark_bit), | |
6138 | .Port1_DMA6_inc_pkt_cnt (port1_DMA6_inc_pkt_cnt), | |
6139 | .Port1_SetGetNextDescDMA6 (port1_SetGetNextDescDMA6), | |
6140 | .Port1_DMA7_inc_head (port1_DMA7_inc_head), | |
6141 | .Port1_DMA7_reset_done (port1_DMA7_reset_done), | |
6142 | .Port1_DMA7_mark_bit (port1_DMA7_mark_bit), | |
6143 | .Port1_DMA7_inc_pkt_cnt (port1_DMA7_inc_pkt_cnt), | |
6144 | .Port1_SetGetNextDescDMA7 (port1_SetGetNextDescDMA7), | |
6145 | .Port1_DMA8_inc_head (port1_DMA8_inc_head), | |
6146 | .Port1_DMA8_reset_done (port1_DMA8_reset_done), | |
6147 | .Port1_DMA8_mark_bit (port1_DMA8_mark_bit), | |
6148 | .Port1_DMA8_inc_pkt_cnt (port1_DMA8_inc_pkt_cnt), | |
6149 | .Port1_SetGetNextDescDMA8 (port1_SetGetNextDescDMA8), | |
6150 | .Port1_DMA9_inc_head (port1_DMA9_inc_head), | |
6151 | .Port1_DMA9_reset_done (port1_DMA9_reset_done), | |
6152 | .Port1_DMA9_mark_bit (port1_DMA9_mark_bit), | |
6153 | .Port1_DMA9_inc_pkt_cnt (port1_DMA9_inc_pkt_cnt), | |
6154 | .Port1_SetGetNextDescDMA9 (port1_SetGetNextDescDMA9), | |
6155 | .Port1_DMA10_inc_head (port1_DMA10_inc_head), | |
6156 | .Port1_DMA10_reset_done (port1_DMA10_reset_done), | |
6157 | .Port1_DMA10_mark_bit (port1_DMA10_mark_bit), | |
6158 | .Port1_DMA10_inc_pkt_cnt (port1_DMA10_inc_pkt_cnt), | |
6159 | .Port1_SetGetNextDescDMA10 (port1_SetGetNextDescDMA10), | |
6160 | .Port1_DMA11_inc_head (port1_DMA11_inc_head), | |
6161 | .Port1_DMA11_reset_done (port1_DMA11_reset_done), | |
6162 | .Port1_DMA11_mark_bit (port1_DMA11_mark_bit), | |
6163 | .Port1_DMA11_inc_pkt_cnt (port1_DMA11_inc_pkt_cnt), | |
6164 | .Port1_SetGetNextDescDMA11 (port1_SetGetNextDescDMA11), | |
6165 | .Port1_DMA12_inc_head (port1_DMA12_inc_head), | |
6166 | .Port1_DMA12_reset_done (port1_DMA12_reset_done), | |
6167 | .Port1_DMA12_mark_bit (port1_DMA12_mark_bit), | |
6168 | .Port1_DMA12_inc_pkt_cnt (port1_DMA12_inc_pkt_cnt), | |
6169 | .Port1_SetGetNextDescDMA12 (port1_SetGetNextDescDMA12), | |
6170 | .Port1_DMA13_inc_head (port1_DMA13_inc_head), | |
6171 | .Port1_DMA13_reset_done (port1_DMA13_reset_done), | |
6172 | .Port1_DMA13_mark_bit (port1_DMA13_mark_bit), | |
6173 | .Port1_DMA13_inc_pkt_cnt (port1_DMA13_inc_pkt_cnt), | |
6174 | .Port1_SetGetNextDescDMA13 (port1_SetGetNextDescDMA13), | |
6175 | .Port1_DMA14_inc_head (port1_DMA14_inc_head), | |
6176 | .Port1_DMA14_reset_done (port1_DMA14_reset_done), | |
6177 | .Port1_DMA14_mark_bit (port1_DMA14_mark_bit), | |
6178 | .Port1_DMA14_inc_pkt_cnt (port1_DMA14_inc_pkt_cnt), | |
6179 | .Port1_SetGetNextDescDMA14 (port1_SetGetNextDescDMA14), | |
6180 | .Port1_DMA15_inc_head (port1_DMA15_inc_head), | |
6181 | .Port1_DMA15_reset_done (port1_DMA15_reset_done), | |
6182 | .Port1_DMA15_mark_bit (port1_DMA15_mark_bit), | |
6183 | .Port1_DMA15_inc_pkt_cnt (port1_DMA15_inc_pkt_cnt), | |
6184 | .Port1_SetGetNextDescDMA15 (port1_SetGetNextDescDMA15), | |
6185 | `ifdef NEPTUNE | |
6186 | .Port1_DMA16_inc_head (port1_DMA16_inc_head), | |
6187 | .Port1_DMA16_reset_done (port1_DMA16_reset_done), | |
6188 | .Port1_DMA16_mark_bit (port1_DMA16_mark_bit), | |
6189 | .Port1_DMA16_inc_pkt_cnt (port1_DMA16_inc_pkt_cnt), | |
6190 | .Port1_SetGetNextDescDMA16 (port1_SetGetNextDescDMA16), | |
6191 | .Port1_DMA17_inc_head (port1_DMA17_inc_head), | |
6192 | .Port1_DMA17_reset_done (port1_DMA17_reset_done), | |
6193 | .Port1_DMA17_mark_bit (port1_DMA17_mark_bit), | |
6194 | .Port1_DMA17_inc_pkt_cnt (port1_DMA17_inc_pkt_cnt), | |
6195 | .Port1_SetGetNextDescDMA17 (port1_SetGetNextDescDMA17), | |
6196 | .Port1_DMA18_inc_head (port1_DMA18_inc_head), | |
6197 | .Port1_DMA18_reset_done (port1_DMA18_reset_done), | |
6198 | .Port1_DMA18_mark_bit (port1_DMA18_mark_bit), | |
6199 | .Port1_DMA18_inc_pkt_cnt (port1_DMA18_inc_pkt_cnt), | |
6200 | .Port1_SetGetNextDescDMA18 (port1_SetGetNextDescDMA18), | |
6201 | .Port1_DMA19_inc_head (port1_DMA19_inc_head), | |
6202 | .Port1_DMA19_reset_done (port1_DMA19_reset_done), | |
6203 | .Port1_DMA19_mark_bit (port1_DMA19_mark_bit), | |
6204 | .Port1_DMA19_inc_pkt_cnt (port1_DMA19_inc_pkt_cnt), | |
6205 | .Port1_SetGetNextDescDMA19 (port1_SetGetNextDescDMA19), | |
6206 | .Port1_DMA20_inc_head (port1_DMA20_inc_head), | |
6207 | .Port1_DMA20_reset_done (port1_DMA20_reset_done), | |
6208 | .Port1_DMA20_mark_bit (port1_DMA20_mark_bit), | |
6209 | .Port1_DMA20_inc_pkt_cnt (port1_DMA20_inc_pkt_cnt), | |
6210 | .Port1_SetGetNextDescDMA20 (port1_SetGetNextDescDMA20), | |
6211 | .Port1_DMA21_inc_head (port1_DMA21_inc_head), | |
6212 | .Port1_DMA21_reset_done (port1_DMA21_reset_done), | |
6213 | .Port1_DMA21_mark_bit (port1_DMA21_mark_bit), | |
6214 | .Port1_DMA21_inc_pkt_cnt (port1_DMA21_inc_pkt_cnt), | |
6215 | .Port1_SetGetNextDescDMA21 (port1_SetGetNextDescDMA21), | |
6216 | .Port1_DMA22_inc_head (port1_DMA22_inc_head), | |
6217 | .Port1_DMA22_reset_done (port1_DMA22_reset_done), | |
6218 | .Port1_DMA22_mark_bit (port1_DMA22_mark_bit), | |
6219 | .Port1_DMA22_inc_pkt_cnt (port1_DMA22_inc_pkt_cnt), | |
6220 | .Port1_SetGetNextDescDMA22 (port1_SetGetNextDescDMA22), | |
6221 | .Port1_DMA23_inc_head (port1_DMA23_inc_head), | |
6222 | .Port1_DMA23_reset_done (port1_DMA23_reset_done), | |
6223 | .Port1_DMA23_mark_bit (port1_DMA23_mark_bit), | |
6224 | .Port1_DMA23_inc_pkt_cnt (port1_DMA23_inc_pkt_cnt), | |
6225 | .Port1_SetGetNextDescDMA23 (port1_SetGetNextDescDMA23), | |
6226 | `else | |
6227 | .Port1_DMA16_inc_head (1'b0), | |
6228 | .Port1_DMA16_reset_done (1'b0), | |
6229 | .Port1_DMA16_mark_bit (1'b0), | |
6230 | .Port1_DMA16_inc_pkt_cnt (1'b0), | |
6231 | .Port1_SetGetNextDescDMA16 (1'b0), | |
6232 | .Port1_DMA17_inc_head (1'b0), | |
6233 | .Port1_DMA17_reset_done (1'b0), | |
6234 | .Port1_DMA17_mark_bit (1'b0), | |
6235 | .Port1_DMA17_inc_pkt_cnt (1'b0), | |
6236 | .Port1_SetGetNextDescDMA17 (1'b0), | |
6237 | .Port1_DMA18_inc_head (1'b0), | |
6238 | .Port1_DMA18_reset_done (1'b0), | |
6239 | .Port1_DMA18_mark_bit (1'b0), | |
6240 | .Port1_DMA18_inc_pkt_cnt (1'b0), | |
6241 | .Port1_SetGetNextDescDMA18 (1'b0), | |
6242 | .Port1_DMA19_inc_head (1'b0), | |
6243 | .Port1_DMA19_reset_done (1'b0), | |
6244 | .Port1_DMA19_mark_bit (1'b0), | |
6245 | .Port1_DMA19_inc_pkt_cnt (1'b0), | |
6246 | .Port1_SetGetNextDescDMA19 (1'b0), | |
6247 | .Port1_DMA20_inc_head (1'b0), | |
6248 | .Port1_DMA20_reset_done (1'b0), | |
6249 | .Port1_DMA20_mark_bit (1'b0), | |
6250 | .Port1_DMA20_inc_pkt_cnt (1'b0), | |
6251 | .Port1_SetGetNextDescDMA20 (1'b0), | |
6252 | .Port1_DMA21_inc_head (1'b0), | |
6253 | .Port1_DMA21_reset_done (1'b0), | |
6254 | .Port1_DMA21_mark_bit (1'b0), | |
6255 | .Port1_DMA21_inc_pkt_cnt (1'b0), | |
6256 | .Port1_SetGetNextDescDMA21 (1'b0), | |
6257 | .Port1_DMA22_inc_head (1'b0), | |
6258 | .Port1_DMA22_reset_done (1'b0), | |
6259 | .Port1_DMA22_mark_bit (1'b0), | |
6260 | .Port1_DMA22_inc_pkt_cnt (1'b0), | |
6261 | .Port1_SetGetNextDescDMA22 (1'b0), | |
6262 | .Port1_DMA23_inc_head (1'b0), | |
6263 | .Port1_DMA23_reset_done (1'b0), | |
6264 | .Port1_DMA23_mark_bit (1'b0), | |
6265 | .Port1_DMA23_inc_pkt_cnt (1'b0), | |
6266 | .Port1_SetGetNextDescDMA23 (1'b0), | |
6267 | `endif | |
6268 | ||
6269 | `ifdef NEPTUNE | |
6270 | .Port2_Nack_Pkt_Rd (port2_Nack_Pkt_Rd), | |
6271 | .Port2_DMA_Nack_Pkt_Rd (port2_DMA_Nack_Pkt_Rd), | |
6272 | .Port2_Nack_Pkt_Rd_Addr (port2_Nack_Pkt_Rd_Addr), | |
6273 | .Port2_DMA0_inc_head (port2_DMA0_inc_head), | |
6274 | .Port2_DMA0_reset_done (port2_DMA0_reset_done), | |
6275 | .Port2_DMA0_mark_bit (port2_DMA0_mark_bit), | |
6276 | .Port2_DMA0_inc_pkt_cnt (port2_DMA0_inc_pkt_cnt), | |
6277 | .Port2_SetGetNextDescDMA0 (port2_SetGetNextDescDMA0), | |
6278 | .Port2_DMA1_inc_head (port2_DMA1_inc_head), | |
6279 | .Port2_DMA1_reset_done (port2_DMA1_reset_done), | |
6280 | .Port2_DMA1_mark_bit (port2_DMA1_mark_bit), | |
6281 | .Port2_DMA1_inc_pkt_cnt (port2_DMA1_inc_pkt_cnt), | |
6282 | .Port2_SetGetNextDescDMA1 (port2_SetGetNextDescDMA1), | |
6283 | .Port2_DMA2_inc_head (port2_DMA2_inc_head), | |
6284 | .Port2_DMA2_reset_done (port2_DMA2_reset_done), | |
6285 | .Port2_DMA2_mark_bit (port2_DMA2_mark_bit), | |
6286 | .Port2_DMA2_inc_pkt_cnt (port2_DMA2_inc_pkt_cnt), | |
6287 | .Port2_SetGetNextDescDMA2 (port2_SetGetNextDescDMA2), | |
6288 | .Port2_DMA3_inc_head (port2_DMA3_inc_head), | |
6289 | .Port2_DMA3_reset_done (port2_DMA3_reset_done), | |
6290 | .Port2_DMA3_mark_bit (port2_DMA3_mark_bit), | |
6291 | .Port2_DMA3_inc_pkt_cnt (port2_DMA3_inc_pkt_cnt), | |
6292 | .Port2_SetGetNextDescDMA3 (port2_SetGetNextDescDMA3), | |
6293 | .Port2_DMA4_inc_head (port2_DMA4_inc_head), | |
6294 | .Port2_DMA4_reset_done (port2_DMA4_reset_done), | |
6295 | .Port2_DMA4_mark_bit (port2_DMA4_mark_bit), | |
6296 | .Port2_DMA4_inc_pkt_cnt (port2_DMA4_inc_pkt_cnt), | |
6297 | .Port2_SetGetNextDescDMA4 (port2_SetGetNextDescDMA4), | |
6298 | .Port2_DMA5_inc_head (port2_DMA5_inc_head), | |
6299 | .Port2_DMA5_reset_done (port2_DMA5_reset_done), | |
6300 | .Port2_DMA5_mark_bit (port2_DMA5_mark_bit), | |
6301 | .Port2_DMA5_inc_pkt_cnt (port2_DMA5_inc_pkt_cnt), | |
6302 | .Port2_SetGetNextDescDMA5 (port2_SetGetNextDescDMA5), | |
6303 | .Port2_DMA6_inc_head (port2_DMA6_inc_head), | |
6304 | .Port2_DMA6_reset_done (port2_DMA6_reset_done), | |
6305 | .Port2_DMA6_mark_bit (port2_DMA6_mark_bit), | |
6306 | .Port2_DMA6_inc_pkt_cnt (port2_DMA6_inc_pkt_cnt), | |
6307 | .Port2_SetGetNextDescDMA6 (port2_SetGetNextDescDMA6), | |
6308 | .Port2_DMA7_inc_head (port2_DMA7_inc_head), | |
6309 | .Port2_DMA7_reset_done (port2_DMA7_reset_done), | |
6310 | .Port2_DMA7_mark_bit (port2_DMA7_mark_bit), | |
6311 | .Port2_DMA7_inc_pkt_cnt (port2_DMA7_inc_pkt_cnt), | |
6312 | .Port2_SetGetNextDescDMA7 (port2_SetGetNextDescDMA7), | |
6313 | .Port2_DMA8_inc_head (port2_DMA8_inc_head), | |
6314 | .Port2_DMA8_reset_done (port2_DMA8_reset_done), | |
6315 | .Port2_DMA8_mark_bit (port2_DMA8_mark_bit), | |
6316 | .Port2_DMA8_inc_pkt_cnt (port2_DMA8_inc_pkt_cnt), | |
6317 | .Port2_SetGetNextDescDMA8 (port2_SetGetNextDescDMA8), | |
6318 | .Port2_DMA9_inc_head (port2_DMA9_inc_head), | |
6319 | .Port2_DMA9_reset_done (port2_DMA9_reset_done), | |
6320 | .Port2_DMA9_mark_bit (port2_DMA9_mark_bit), | |
6321 | .Port2_DMA9_inc_pkt_cnt (port2_DMA9_inc_pkt_cnt), | |
6322 | .Port2_SetGetNextDescDMA9 (port2_SetGetNextDescDMA9), | |
6323 | .Port2_DMA10_inc_head (port2_DMA10_inc_head), | |
6324 | .Port2_DMA10_reset_done (port2_DMA10_reset_done), | |
6325 | .Port2_DMA10_mark_bit (port2_DMA10_mark_bit), | |
6326 | .Port2_DMA10_inc_pkt_cnt (port2_DMA10_inc_pkt_cnt), | |
6327 | .Port2_SetGetNextDescDMA10 (port2_SetGetNextDescDMA10), | |
6328 | .Port2_DMA11_inc_head (port2_DMA11_inc_head), | |
6329 | .Port2_DMA11_reset_done (port2_DMA11_reset_done), | |
6330 | .Port2_DMA11_mark_bit (port2_DMA11_mark_bit), | |
6331 | .Port2_DMA11_inc_pkt_cnt (port2_DMA11_inc_pkt_cnt), | |
6332 | .Port2_SetGetNextDescDMA11 (port2_SetGetNextDescDMA11), | |
6333 | .Port2_DMA12_inc_head (port2_DMA12_inc_head), | |
6334 | .Port2_DMA12_reset_done (port2_DMA12_reset_done), | |
6335 | .Port2_DMA12_mark_bit (port2_DMA12_mark_bit), | |
6336 | .Port2_DMA12_inc_pkt_cnt (port2_DMA12_inc_pkt_cnt), | |
6337 | .Port2_SetGetNextDescDMA12 (port2_SetGetNextDescDMA12), | |
6338 | .Port2_DMA13_inc_head (port2_DMA13_inc_head), | |
6339 | .Port2_DMA13_reset_done (port2_DMA13_reset_done), | |
6340 | .Port2_DMA13_mark_bit (port2_DMA13_mark_bit), | |
6341 | .Port2_DMA13_inc_pkt_cnt (port2_DMA13_inc_pkt_cnt), | |
6342 | .Port2_SetGetNextDescDMA13 (port2_SetGetNextDescDMA13), | |
6343 | .Port2_DMA14_inc_head (port2_DMA14_inc_head), | |
6344 | .Port2_DMA14_reset_done (port2_DMA14_reset_done), | |
6345 | .Port2_DMA14_mark_bit (port2_DMA14_mark_bit), | |
6346 | .Port2_DMA14_inc_pkt_cnt (port2_DMA14_inc_pkt_cnt), | |
6347 | .Port2_SetGetNextDescDMA14 (port2_SetGetNextDescDMA14), | |
6348 | .Port2_DMA15_inc_head (port2_DMA15_inc_head), | |
6349 | .Port2_DMA15_reset_done (port2_DMA15_reset_done), | |
6350 | .Port2_DMA15_mark_bit (port2_DMA15_mark_bit), | |
6351 | .Port2_DMA15_inc_pkt_cnt (port2_DMA15_inc_pkt_cnt), | |
6352 | .Port2_SetGetNextDescDMA15 (port2_SetGetNextDescDMA15), | |
6353 | .Port2_DMA16_inc_head (port2_DMA16_inc_head), | |
6354 | .Port2_DMA16_reset_done (port2_DMA16_reset_done), | |
6355 | .Port2_DMA16_mark_bit (port2_DMA16_mark_bit), | |
6356 | .Port2_DMA16_inc_pkt_cnt (port2_DMA16_inc_pkt_cnt), | |
6357 | .Port2_SetGetNextDescDMA16 (port2_SetGetNextDescDMA16), | |
6358 | .Port2_DMA17_inc_head (port2_DMA17_inc_head), | |
6359 | .Port2_DMA17_reset_done (port2_DMA17_reset_done), | |
6360 | .Port2_DMA17_mark_bit (port2_DMA17_mark_bit), | |
6361 | .Port2_DMA17_inc_pkt_cnt (port2_DMA17_inc_pkt_cnt), | |
6362 | .Port2_SetGetNextDescDMA17 (port2_SetGetNextDescDMA17), | |
6363 | .Port2_DMA18_inc_head (port2_DMA18_inc_head), | |
6364 | .Port2_DMA18_reset_done (port2_DMA18_reset_done), | |
6365 | .Port2_DMA18_mark_bit (port2_DMA18_mark_bit), | |
6366 | .Port2_DMA18_inc_pkt_cnt (port2_DMA18_inc_pkt_cnt), | |
6367 | .Port2_SetGetNextDescDMA18 (port2_SetGetNextDescDMA18), | |
6368 | .Port2_DMA19_inc_head (port2_DMA19_inc_head), | |
6369 | .Port2_DMA19_reset_done (port2_DMA19_reset_done), | |
6370 | .Port2_DMA19_mark_bit (port2_DMA19_mark_bit), | |
6371 | .Port2_DMA19_inc_pkt_cnt (port2_DMA19_inc_pkt_cnt), | |
6372 | .Port2_SetGetNextDescDMA19 (port2_SetGetNextDescDMA19), | |
6373 | .Port2_DMA20_inc_head (port2_DMA20_inc_head), | |
6374 | .Port2_DMA20_reset_done (port2_DMA20_reset_done), | |
6375 | .Port2_DMA20_mark_bit (port2_DMA20_mark_bit), | |
6376 | .Port2_DMA20_inc_pkt_cnt (port2_DMA20_inc_pkt_cnt), | |
6377 | .Port2_SetGetNextDescDMA20 (port2_SetGetNextDescDMA20), | |
6378 | .Port2_DMA21_inc_head (port2_DMA21_inc_head), | |
6379 | .Port2_DMA21_reset_done (port2_DMA21_reset_done), | |
6380 | .Port2_DMA21_mark_bit (port2_DMA21_mark_bit), | |
6381 | .Port2_DMA21_inc_pkt_cnt (port2_DMA21_inc_pkt_cnt), | |
6382 | .Port2_SetGetNextDescDMA21 (port2_SetGetNextDescDMA21), | |
6383 | .Port2_DMA22_inc_head (port2_DMA22_inc_head), | |
6384 | .Port2_DMA22_reset_done (port2_DMA22_reset_done), | |
6385 | .Port2_DMA22_mark_bit (port2_DMA22_mark_bit), | |
6386 | .Port2_DMA22_inc_pkt_cnt (port2_DMA22_inc_pkt_cnt), | |
6387 | .Port2_SetGetNextDescDMA22 (port2_SetGetNextDescDMA22), | |
6388 | .Port2_DMA23_inc_head (port2_DMA23_inc_head), | |
6389 | .Port2_DMA23_reset_done (port2_DMA23_reset_done), | |
6390 | .Port2_DMA23_mark_bit (port2_DMA23_mark_bit), | |
6391 | .Port2_DMA23_inc_pkt_cnt (port2_DMA23_inc_pkt_cnt), | |
6392 | .Port2_SetGetNextDescDMA23 (port2_SetGetNextDescDMA23), | |
6393 | .Port3_Nack_Pkt_Rd (port3_Nack_Pkt_Rd), | |
6394 | .Port3_DMA_Nack_Pkt_Rd (port3_DMA_Nack_Pkt_Rd), | |
6395 | .Port3_Nack_Pkt_Rd_Addr (port3_Nack_Pkt_Rd_Addr), | |
6396 | .Port3_DMA0_inc_head (port3_DMA0_inc_head), | |
6397 | .Port3_DMA0_reset_done (port3_DMA0_reset_done), | |
6398 | .Port3_DMA0_mark_bit (port3_DMA0_mark_bit), | |
6399 | .Port3_DMA0_inc_pkt_cnt (port3_DMA0_inc_pkt_cnt), | |
6400 | .Port3_SetGetNextDescDMA0 (port3_SetGetNextDescDMA0), | |
6401 | .Port3_DMA1_inc_head (port3_DMA1_inc_head), | |
6402 | .Port3_DMA1_reset_done (port3_DMA1_reset_done), | |
6403 | .Port3_DMA1_mark_bit (port3_DMA1_mark_bit), | |
6404 | .Port3_DMA1_inc_pkt_cnt (port3_DMA1_inc_pkt_cnt), | |
6405 | .Port3_SetGetNextDescDMA1 (port3_SetGetNextDescDMA1), | |
6406 | .Port3_DMA2_inc_head (port3_DMA2_inc_head), | |
6407 | .Port3_DMA2_reset_done (port3_DMA2_reset_done), | |
6408 | .Port3_DMA2_mark_bit (port3_DMA2_mark_bit), | |
6409 | .Port3_DMA2_inc_pkt_cnt (port3_DMA2_inc_pkt_cnt), | |
6410 | .Port3_SetGetNextDescDMA2 (port3_SetGetNextDescDMA2), | |
6411 | .Port3_DMA3_inc_head (port3_DMA3_inc_head), | |
6412 | .Port3_DMA3_reset_done (port3_DMA3_reset_done), | |
6413 | .Port3_DMA3_mark_bit (port3_DMA3_mark_bit), | |
6414 | .Port3_DMA3_inc_pkt_cnt (port3_DMA3_inc_pkt_cnt), | |
6415 | .Port3_SetGetNextDescDMA3 (port3_SetGetNextDescDMA3), | |
6416 | .Port3_DMA4_inc_head (port3_DMA4_inc_head), | |
6417 | .Port3_DMA4_reset_done (port3_DMA4_reset_done), | |
6418 | .Port3_DMA4_mark_bit (port3_DMA4_mark_bit), | |
6419 | .Port3_DMA4_inc_pkt_cnt (port3_DMA4_inc_pkt_cnt), | |
6420 | .Port3_SetGetNextDescDMA4 (port3_SetGetNextDescDMA4), | |
6421 | .Port3_DMA5_inc_head (port3_DMA5_inc_head), | |
6422 | .Port3_DMA5_reset_done (port3_DMA5_reset_done), | |
6423 | .Port3_DMA5_mark_bit (port3_DMA5_mark_bit), | |
6424 | .Port3_DMA5_inc_pkt_cnt (port3_DMA5_inc_pkt_cnt), | |
6425 | .Port3_SetGetNextDescDMA5 (port3_SetGetNextDescDMA5), | |
6426 | .Port3_DMA6_inc_head (port3_DMA6_inc_head), | |
6427 | .Port3_DMA6_reset_done (port3_DMA6_reset_done), | |
6428 | .Port3_DMA6_mark_bit (port3_DMA6_mark_bit), | |
6429 | .Port3_DMA6_inc_pkt_cnt (port3_DMA6_inc_pkt_cnt), | |
6430 | .Port3_SetGetNextDescDMA6 (port3_SetGetNextDescDMA6), | |
6431 | .Port3_DMA7_inc_head (port3_DMA7_inc_head), | |
6432 | .Port3_DMA7_reset_done (port3_DMA7_reset_done), | |
6433 | .Port3_DMA7_mark_bit (port3_DMA7_mark_bit), | |
6434 | .Port3_DMA7_inc_pkt_cnt (port3_DMA7_inc_pkt_cnt), | |
6435 | .Port3_SetGetNextDescDMA7 (port3_SetGetNextDescDMA7), | |
6436 | .Port3_DMA8_inc_head (port3_DMA8_inc_head), | |
6437 | .Port3_DMA8_reset_done (port3_DMA8_reset_done), | |
6438 | .Port3_DMA8_mark_bit (port3_DMA8_mark_bit), | |
6439 | .Port3_DMA8_inc_pkt_cnt (port3_DMA8_inc_pkt_cnt), | |
6440 | .Port3_SetGetNextDescDMA8 (port3_SetGetNextDescDMA8), | |
6441 | .Port3_DMA9_inc_head (port3_DMA9_inc_head), | |
6442 | .Port3_DMA9_reset_done (port3_DMA9_reset_done), | |
6443 | .Port3_DMA9_mark_bit (port3_DMA9_mark_bit), | |
6444 | .Port3_DMA9_inc_pkt_cnt (port3_DMA9_inc_pkt_cnt), | |
6445 | .Port3_SetGetNextDescDMA9 (port3_SetGetNextDescDMA9), | |
6446 | .Port3_DMA10_inc_head (port3_DMA10_inc_head), | |
6447 | .Port3_DMA10_reset_done (port3_DMA10_reset_done), | |
6448 | .Port3_DMA10_mark_bit (port3_DMA10_mark_bit), | |
6449 | .Port3_DMA10_inc_pkt_cnt (port3_DMA10_inc_pkt_cnt), | |
6450 | .Port3_SetGetNextDescDMA10 (port3_SetGetNextDescDMA10), | |
6451 | .Port3_DMA11_inc_head (port3_DMA11_inc_head), | |
6452 | .Port3_DMA11_reset_done (port3_DMA11_reset_done), | |
6453 | .Port3_DMA11_mark_bit (port3_DMA11_mark_bit), | |
6454 | .Port3_DMA11_inc_pkt_cnt (port3_DMA11_inc_pkt_cnt), | |
6455 | .Port3_SetGetNextDescDMA11 (port3_SetGetNextDescDMA11), | |
6456 | .Port3_DMA12_inc_head (port3_DMA12_inc_head), | |
6457 | .Port3_DMA12_reset_done (port3_DMA12_reset_done), | |
6458 | .Port3_DMA12_mark_bit (port3_DMA12_mark_bit), | |
6459 | .Port3_DMA12_inc_pkt_cnt (port3_DMA12_inc_pkt_cnt), | |
6460 | .Port3_SetGetNextDescDMA12 (port3_SetGetNextDescDMA12), | |
6461 | .Port3_DMA13_inc_head (port3_DMA13_inc_head), | |
6462 | .Port3_DMA13_reset_done (port3_DMA13_reset_done), | |
6463 | .Port3_DMA13_mark_bit (port3_DMA13_mark_bit), | |
6464 | .Port3_DMA13_inc_pkt_cnt (port3_DMA13_inc_pkt_cnt), | |
6465 | .Port3_SetGetNextDescDMA13 (port3_SetGetNextDescDMA13), | |
6466 | .Port3_DMA14_inc_head (port3_DMA14_inc_head), | |
6467 | .Port3_DMA14_reset_done (port3_DMA14_reset_done), | |
6468 | .Port3_DMA14_mark_bit (port3_DMA14_mark_bit), | |
6469 | .Port3_DMA14_inc_pkt_cnt (port3_DMA14_inc_pkt_cnt), | |
6470 | .Port3_SetGetNextDescDMA14 (port3_SetGetNextDescDMA14), | |
6471 | .Port3_DMA15_inc_head (port3_DMA15_inc_head), | |
6472 | .Port3_DMA15_reset_done (port3_DMA15_reset_done), | |
6473 | .Port3_DMA15_mark_bit (port3_DMA15_mark_bit), | |
6474 | .Port3_DMA15_inc_pkt_cnt (port3_DMA15_inc_pkt_cnt), | |
6475 | .Port3_SetGetNextDescDMA15 (port3_SetGetNextDescDMA15), | |
6476 | .Port3_DMA16_inc_head (port3_DMA16_inc_head), | |
6477 | .Port3_DMA16_reset_done (port3_DMA16_reset_done), | |
6478 | .Port3_DMA16_mark_bit (port3_DMA16_mark_bit), | |
6479 | .Port3_DMA16_inc_pkt_cnt (port3_DMA16_inc_pkt_cnt), | |
6480 | .Port3_SetGetNextDescDMA16 (port3_SetGetNextDescDMA16), | |
6481 | .Port3_DMA17_inc_head (port3_DMA17_inc_head), | |
6482 | .Port3_DMA17_reset_done (port3_DMA17_reset_done), | |
6483 | .Port3_DMA17_mark_bit (port3_DMA17_mark_bit), | |
6484 | .Port3_DMA17_inc_pkt_cnt (port3_DMA17_inc_pkt_cnt), | |
6485 | .Port3_SetGetNextDescDMA17 (port3_SetGetNextDescDMA17), | |
6486 | .Port3_DMA18_inc_head (port3_DMA18_inc_head), | |
6487 | .Port3_DMA18_reset_done (port3_DMA18_reset_done), | |
6488 | .Port3_DMA18_mark_bit (port3_DMA18_mark_bit), | |
6489 | .Port3_DMA18_inc_pkt_cnt (port3_DMA18_inc_pkt_cnt), | |
6490 | .Port3_SetGetNextDescDMA18 (port3_SetGetNextDescDMA18), | |
6491 | .Port3_DMA19_inc_head (port3_DMA19_inc_head), | |
6492 | .Port3_DMA19_reset_done (port3_DMA19_reset_done), | |
6493 | .Port3_DMA19_mark_bit (port3_DMA19_mark_bit), | |
6494 | .Port3_DMA19_inc_pkt_cnt (port3_DMA19_inc_pkt_cnt), | |
6495 | .Port3_SetGetNextDescDMA19 (port3_SetGetNextDescDMA19), | |
6496 | .Port3_DMA20_inc_head (port3_DMA20_inc_head), | |
6497 | .Port3_DMA20_reset_done (port3_DMA20_reset_done), | |
6498 | .Port3_DMA20_mark_bit (port3_DMA20_mark_bit), | |
6499 | .Port3_DMA20_inc_pkt_cnt (port3_DMA20_inc_pkt_cnt), | |
6500 | .Port3_SetGetNextDescDMA20 (port3_SetGetNextDescDMA20), | |
6501 | .Port3_DMA21_inc_head (port3_DMA21_inc_head), | |
6502 | .Port3_DMA21_reset_done (port3_DMA21_reset_done), | |
6503 | .Port3_DMA21_mark_bit (port3_DMA21_mark_bit), | |
6504 | .Port3_DMA21_inc_pkt_cnt (port3_DMA21_inc_pkt_cnt), | |
6505 | .Port3_SetGetNextDescDMA21 (port3_SetGetNextDescDMA21), | |
6506 | .Port3_DMA22_inc_head (port3_DMA22_inc_head), | |
6507 | .Port3_DMA22_reset_done (port3_DMA22_reset_done), | |
6508 | .Port3_DMA22_mark_bit (port3_DMA22_mark_bit), | |
6509 | .Port3_DMA22_inc_pkt_cnt (port3_DMA22_inc_pkt_cnt), | |
6510 | .Port3_SetGetNextDescDMA22 (port3_SetGetNextDescDMA22), | |
6511 | .Port3_DMA23_inc_head (port3_DMA23_inc_head), | |
6512 | .Port3_DMA23_reset_done (port3_DMA23_reset_done), | |
6513 | .Port3_DMA23_mark_bit (port3_DMA23_mark_bit), | |
6514 | .Port3_DMA23_inc_pkt_cnt (port3_DMA23_inc_pkt_cnt), | |
6515 | .Port3_SetGetNextDescDMA23 (port3_SetGetNextDescDMA23), | |
6516 | `else | |
6517 | .Port2_Nack_Pkt_Rd (1'b0), | |
6518 | .Port2_DMA_Nack_Pkt_Rd (24'h0), | |
6519 | .Port2_Nack_Pkt_Rd_Addr (44'h0), | |
6520 | .Port2_DMA0_inc_head (1'b0), | |
6521 | .Port2_DMA0_reset_done (1'b0), | |
6522 | .Port2_DMA0_mark_bit (1'b0), | |
6523 | .Port2_DMA0_inc_pkt_cnt (1'b0), | |
6524 | .Port2_SetGetNextDescDMA0 (1'b0), | |
6525 | .Port2_DMA1_inc_head (1'b0), | |
6526 | .Port2_DMA1_reset_done (1'b0), | |
6527 | .Port2_DMA1_mark_bit (1'b0), | |
6528 | .Port2_DMA1_inc_pkt_cnt (1'b0), | |
6529 | .Port2_SetGetNextDescDMA1 (1'b0), | |
6530 | .Port2_DMA2_inc_head (1'b0), | |
6531 | .Port2_DMA2_reset_done (1'b0), | |
6532 | .Port2_DMA2_mark_bit (1'b0), | |
6533 | .Port2_DMA2_inc_pkt_cnt (1'b0), | |
6534 | .Port2_SetGetNextDescDMA2 (1'b0), | |
6535 | .Port2_DMA3_inc_head (1'b0), | |
6536 | .Port2_DMA3_reset_done (1'b0), | |
6537 | .Port2_DMA3_mark_bit (1'b0), | |
6538 | .Port2_DMA3_inc_pkt_cnt (1'b0), | |
6539 | .Port2_SetGetNextDescDMA3 (1'b0), | |
6540 | .Port2_DMA4_inc_head (1'b0), | |
6541 | .Port2_DMA4_reset_done (1'b0), | |
6542 | .Port2_DMA4_mark_bit (1'b0), | |
6543 | .Port2_DMA4_inc_pkt_cnt (1'b0), | |
6544 | .Port2_SetGetNextDescDMA4 (1'b0), | |
6545 | .Port2_DMA5_inc_head (1'b0), | |
6546 | .Port2_DMA5_reset_done (1'b0), | |
6547 | .Port2_DMA5_mark_bit (1'b0), | |
6548 | .Port2_DMA5_inc_pkt_cnt (1'b0), | |
6549 | .Port2_SetGetNextDescDMA5 (1'b0), | |
6550 | .Port2_DMA6_inc_head (1'b0), | |
6551 | .Port2_DMA6_reset_done (1'b0), | |
6552 | .Port2_DMA6_mark_bit (1'b0), | |
6553 | .Port2_DMA6_inc_pkt_cnt (1'b0), | |
6554 | .Port2_SetGetNextDescDMA6 (1'b0), | |
6555 | .Port2_DMA7_inc_head (1'b0), | |
6556 | .Port2_DMA7_reset_done (1'b0), | |
6557 | .Port2_DMA7_mark_bit (1'b0), | |
6558 | .Port2_DMA7_inc_pkt_cnt (1'b0), | |
6559 | .Port2_SetGetNextDescDMA7 (1'b0), | |
6560 | .Port2_DMA8_inc_head (1'b0), | |
6561 | .Port2_DMA8_reset_done (1'b0), | |
6562 | .Port2_DMA8_mark_bit (1'b0), | |
6563 | .Port2_DMA8_inc_pkt_cnt (1'b0), | |
6564 | .Port2_SetGetNextDescDMA8 (1'b0), | |
6565 | .Port2_DMA9_inc_head (1'b0), | |
6566 | .Port2_DMA9_reset_done (1'b0), | |
6567 | .Port2_DMA9_mark_bit (1'b0), | |
6568 | .Port2_DMA9_inc_pkt_cnt (1'b0), | |
6569 | .Port2_SetGetNextDescDMA9 (1'b0), | |
6570 | .Port2_DMA10_inc_head (1'b0), | |
6571 | .Port2_DMA10_reset_done (1'b0), | |
6572 | .Port2_DMA10_mark_bit (1'b0), | |
6573 | .Port2_DMA10_inc_pkt_cnt (1'b0), | |
6574 | .Port2_SetGetNextDescDMA10 (1'b0), | |
6575 | .Port2_DMA11_inc_head (1'b0), | |
6576 | .Port2_DMA11_reset_done (1'b0), | |
6577 | .Port2_DMA11_mark_bit (1'b0), | |
6578 | .Port2_DMA11_inc_pkt_cnt (1'b0), | |
6579 | .Port2_SetGetNextDescDMA11 (1'b0), | |
6580 | .Port2_DMA12_inc_head (1'b0), | |
6581 | .Port2_DMA12_reset_done (1'b0), | |
6582 | .Port2_DMA12_mark_bit (1'b0), | |
6583 | .Port2_DMA12_inc_pkt_cnt (1'b0), | |
6584 | .Port2_SetGetNextDescDMA12 (1'b0), | |
6585 | .Port2_DMA13_inc_head (1'b0), | |
6586 | .Port2_DMA13_reset_done (1'b0), | |
6587 | .Port2_DMA13_mark_bit (1'b0), | |
6588 | .Port2_DMA13_inc_pkt_cnt (1'b0), | |
6589 | .Port2_SetGetNextDescDMA13 (1'b0), | |
6590 | .Port2_DMA14_inc_head (1'b0), | |
6591 | .Port2_DMA14_reset_done (1'b0), | |
6592 | .Port2_DMA14_mark_bit (1'b0), | |
6593 | .Port2_DMA14_inc_pkt_cnt (1'b0), | |
6594 | .Port2_SetGetNextDescDMA14 (1'b0), | |
6595 | .Port2_DMA15_inc_head (1'b0), | |
6596 | .Port2_DMA15_reset_done (1'b0), | |
6597 | .Port2_DMA15_mark_bit (1'b0), | |
6598 | .Port2_DMA15_inc_pkt_cnt (1'b0), | |
6599 | .Port2_SetGetNextDescDMA15 (1'b0), | |
6600 | .Port2_DMA16_inc_head (1'b0), | |
6601 | .Port2_DMA16_reset_done (1'b0), | |
6602 | .Port2_DMA16_mark_bit (1'b0), | |
6603 | .Port2_DMA16_inc_pkt_cnt (1'b0), | |
6604 | .Port2_SetGetNextDescDMA16 (1'b0), | |
6605 | .Port2_DMA17_inc_head (1'b0), | |
6606 | .Port2_DMA17_reset_done (1'b0), | |
6607 | .Port2_DMA17_mark_bit (1'b0), | |
6608 | .Port2_DMA17_inc_pkt_cnt (1'b0), | |
6609 | .Port2_SetGetNextDescDMA17 (1'b0), | |
6610 | .Port2_DMA18_inc_head (1'b0), | |
6611 | .Port2_DMA18_reset_done (1'b0), | |
6612 | .Port2_DMA18_mark_bit (1'b0), | |
6613 | .Port2_DMA18_inc_pkt_cnt (1'b0), | |
6614 | .Port2_SetGetNextDescDMA18 (1'b0), | |
6615 | .Port2_DMA19_inc_head (1'b0), | |
6616 | .Port2_DMA19_reset_done (1'b0), | |
6617 | .Port2_DMA19_mark_bit (1'b0), | |
6618 | .Port2_DMA19_inc_pkt_cnt (1'b0), | |
6619 | .Port2_SetGetNextDescDMA19 (1'b0), | |
6620 | .Port2_DMA20_inc_head (1'b0), | |
6621 | .Port2_DMA20_reset_done (1'b0), | |
6622 | .Port2_DMA20_mark_bit (1'b0), | |
6623 | .Port2_DMA20_inc_pkt_cnt (1'b0), | |
6624 | .Port2_SetGetNextDescDMA20 (1'b0), | |
6625 | .Port2_DMA21_inc_head (1'b0), | |
6626 | .Port2_DMA21_reset_done (1'b0), | |
6627 | .Port2_DMA21_mark_bit (1'b0), | |
6628 | .Port2_DMA21_inc_pkt_cnt (1'b0), | |
6629 | .Port2_SetGetNextDescDMA21 (1'b0), | |
6630 | .Port2_DMA22_inc_head (1'b0), | |
6631 | .Port2_DMA22_reset_done (1'b0), | |
6632 | .Port2_DMA22_mark_bit (1'b0), | |
6633 | .Port2_DMA22_inc_pkt_cnt (1'b0), | |
6634 | .Port2_SetGetNextDescDMA22 (1'b0), | |
6635 | .Port2_DMA23_inc_head (1'b0), | |
6636 | .Port2_DMA23_reset_done (1'b0), | |
6637 | .Port2_DMA23_mark_bit (1'b0), | |
6638 | .Port2_DMA23_inc_pkt_cnt (1'b0), | |
6639 | .Port2_SetGetNextDescDMA23 (1'b0), | |
6640 | ||
6641 | .Port3_Nack_Pkt_Rd (1'b0), | |
6642 | .Port3_DMA_Nack_Pkt_Rd (24'h0), | |
6643 | .Port3_Nack_Pkt_Rd_Addr (44'h0), | |
6644 | .Port3_DMA0_inc_head (1'b0), | |
6645 | .Port3_DMA0_reset_done (1'b0), | |
6646 | .Port3_DMA0_mark_bit (1'b0), | |
6647 | .Port3_DMA0_inc_pkt_cnt (1'b0), | |
6648 | .Port3_SetGetNextDescDMA0 (1'b0), | |
6649 | .Port3_DMA1_inc_head (1'b0), | |
6650 | .Port3_DMA1_reset_done (1'b0), | |
6651 | .Port3_DMA1_mark_bit (1'b0), | |
6652 | .Port3_DMA1_inc_pkt_cnt (1'b0), | |
6653 | .Port3_SetGetNextDescDMA1 (1'b0), | |
6654 | .Port3_DMA2_inc_head (1'b0), | |
6655 | .Port3_DMA2_reset_done (1'b0), | |
6656 | .Port3_DMA2_mark_bit (1'b0), | |
6657 | .Port3_DMA2_inc_pkt_cnt (1'b0), | |
6658 | .Port3_SetGetNextDescDMA2 (1'b0), | |
6659 | .Port3_DMA3_inc_head (1'b0), | |
6660 | .Port3_DMA3_reset_done (1'b0), | |
6661 | .Port3_DMA3_mark_bit (1'b0), | |
6662 | .Port3_DMA3_inc_pkt_cnt (1'b0), | |
6663 | .Port3_SetGetNextDescDMA3 (1'b0), | |
6664 | .Port3_DMA4_inc_head (1'b0), | |
6665 | .Port3_DMA4_reset_done (1'b0), | |
6666 | .Port3_DMA4_mark_bit (1'b0), | |
6667 | .Port3_DMA4_inc_pkt_cnt (1'b0), | |
6668 | .Port3_SetGetNextDescDMA4 (1'b0), | |
6669 | .Port3_DMA5_inc_head (1'b0), | |
6670 | .Port3_DMA5_reset_done (1'b0), | |
6671 | .Port3_DMA5_mark_bit (1'b0), | |
6672 | .Port3_DMA5_inc_pkt_cnt (1'b0), | |
6673 | .Port3_SetGetNextDescDMA5 (1'b0), | |
6674 | .Port3_DMA6_inc_head (1'b0), | |
6675 | .Port3_DMA6_reset_done (1'b0), | |
6676 | .Port3_DMA6_mark_bit (1'b0), | |
6677 | .Port3_DMA6_inc_pkt_cnt (1'b0), | |
6678 | .Port3_SetGetNextDescDMA6 (1'b0), | |
6679 | .Port3_DMA7_inc_head (1'b0), | |
6680 | .Port3_DMA7_reset_done (1'b0), | |
6681 | .Port3_DMA7_mark_bit (1'b0), | |
6682 | .Port3_DMA7_inc_pkt_cnt (1'b0), | |
6683 | .Port3_SetGetNextDescDMA7 (1'b0), | |
6684 | .Port3_DMA8_inc_head (1'b0), | |
6685 | .Port3_DMA8_reset_done (1'b0), | |
6686 | .Port3_DMA8_mark_bit (1'b0), | |
6687 | .Port3_DMA8_inc_pkt_cnt (1'b0), | |
6688 | .Port3_SetGetNextDescDMA8 (1'b0), | |
6689 | .Port3_DMA9_inc_head (1'b0), | |
6690 | .Port3_DMA9_reset_done (1'b0), | |
6691 | .Port3_DMA9_mark_bit (1'b0), | |
6692 | .Port3_DMA9_inc_pkt_cnt (1'b0), | |
6693 | .Port3_SetGetNextDescDMA9 (1'b0), | |
6694 | .Port3_DMA10_inc_head (1'b0), | |
6695 | .Port3_DMA10_reset_done (1'b0), | |
6696 | .Port3_DMA10_mark_bit (1'b0), | |
6697 | .Port3_DMA10_inc_pkt_cnt (1'b0), | |
6698 | .Port3_SetGetNextDescDMA10 (1'b0), | |
6699 | .Port3_DMA11_inc_head (1'b0), | |
6700 | .Port3_DMA11_reset_done (1'b0), | |
6701 | .Port3_DMA11_mark_bit (1'b0), | |
6702 | .Port3_DMA11_inc_pkt_cnt (1'b0), | |
6703 | .Port3_SetGetNextDescDMA11 (1'b0), | |
6704 | .Port3_DMA12_inc_head (1'b0), | |
6705 | .Port3_DMA12_reset_done (1'b0), | |
6706 | .Port3_DMA12_mark_bit (1'b0), | |
6707 | .Port3_DMA12_inc_pkt_cnt (1'b0), | |
6708 | .Port3_SetGetNextDescDMA12 (1'b0), | |
6709 | .Port3_DMA13_inc_head (1'b0), | |
6710 | .Port3_DMA13_reset_done (1'b0), | |
6711 | .Port3_DMA13_mark_bit (1'b0), | |
6712 | .Port3_DMA13_inc_pkt_cnt (1'b0), | |
6713 | .Port3_SetGetNextDescDMA13 (1'b0), | |
6714 | .Port3_DMA14_inc_head (1'b0), | |
6715 | .Port3_DMA14_reset_done (1'b0), | |
6716 | .Port3_DMA14_mark_bit (1'b0), | |
6717 | .Port3_DMA14_inc_pkt_cnt (1'b0), | |
6718 | .Port3_SetGetNextDescDMA14 (1'b0), | |
6719 | .Port3_DMA15_inc_head (1'b0), | |
6720 | .Port3_DMA15_reset_done (1'b0), | |
6721 | .Port3_DMA15_mark_bit (1'b0), | |
6722 | .Port3_DMA15_inc_pkt_cnt (1'b0), | |
6723 | .Port3_SetGetNextDescDMA15 (1'b0), | |
6724 | .Port3_DMA16_inc_head (1'b0), | |
6725 | .Port3_DMA16_reset_done (1'b0), | |
6726 | .Port3_DMA16_mark_bit (1'b0), | |
6727 | .Port3_DMA16_inc_pkt_cnt (1'b0), | |
6728 | .Port3_SetGetNextDescDMA16 (1'b0), | |
6729 | .Port3_DMA17_inc_head (1'b0), | |
6730 | .Port3_DMA17_reset_done (1'b0), | |
6731 | .Port3_DMA17_mark_bit (1'b0), | |
6732 | .Port3_DMA17_inc_pkt_cnt (1'b0), | |
6733 | .Port3_SetGetNextDescDMA17 (1'b0), | |
6734 | .Port3_DMA18_inc_head (1'b0), | |
6735 | .Port3_DMA18_reset_done (1'b0), | |
6736 | .Port3_DMA18_mark_bit (1'b0), | |
6737 | .Port3_DMA18_inc_pkt_cnt (1'b0), | |
6738 | .Port3_SetGetNextDescDMA18 (1'b0), | |
6739 | .Port3_DMA19_inc_head (1'b0), | |
6740 | .Port3_DMA19_reset_done (1'b0), | |
6741 | .Port3_DMA19_mark_bit (1'b0), | |
6742 | .Port3_DMA19_inc_pkt_cnt (1'b0), | |
6743 | .Port3_SetGetNextDescDMA19 (1'b0), | |
6744 | .Port3_DMA20_inc_head (1'b0), | |
6745 | .Port3_DMA20_reset_done (1'b0), | |
6746 | .Port3_DMA20_mark_bit (1'b0), | |
6747 | .Port3_DMA20_inc_pkt_cnt (1'b0), | |
6748 | .Port3_SetGetNextDescDMA20 (1'b0), | |
6749 | .Port3_DMA21_inc_head (1'b0), | |
6750 | .Port3_DMA21_reset_done (1'b0), | |
6751 | .Port3_DMA21_mark_bit (1'b0), | |
6752 | .Port3_DMA21_inc_pkt_cnt (1'b0), | |
6753 | .Port3_SetGetNextDescDMA21 (1'b0), | |
6754 | .Port3_DMA22_inc_head (1'b0), | |
6755 | .Port3_DMA22_reset_done (1'b0), | |
6756 | .Port3_DMA22_mark_bit (1'b0), | |
6757 | .Port3_DMA22_inc_pkt_cnt (1'b0), | |
6758 | .Port3_SetGetNextDescDMA22 (1'b0), | |
6759 | .Port3_DMA23_inc_head (1'b0), | |
6760 | .Port3_DMA23_reset_done (1'b0), | |
6761 | .Port3_DMA23_mark_bit (1'b0), | |
6762 | .Port3_DMA23_inc_pkt_cnt (1'b0), | |
6763 | .Port3_SetGetNextDescDMA23 (1'b0), | |
6764 | `endif | |
6765 | `ifdef NEPTUNE | |
6766 | .TXC_DMC_DMA_Nack_Pkt_Rd (txc_dmc_dma_nack_pkt_rd), | |
6767 | `else | |
6768 | .TXC_DMC_DMA_Nack_Pkt_Rd ({dummy_txc_dmc_dma_nack_pkt_rd, | |
6769 | txc_dmc_dma_nack_pkt_rd}), | |
6770 | `endif | |
6771 | .TXC_DMC_Nack_Pkt_Rd (txc_dmc_nack_pkt_rd), | |
6772 | .TXC_DMC_Nack_Pkt_Rd_Addr (txc_dmc_nack_pkt_rd_addr), | |
6773 | .DMC_TXC_DMA0_GotNxtDesc (dmc_txc_dma0_gotnxtdesc), | |
6774 | .TXC_DMC_DMA0_GetNxtDesc (txc_dmc_dma0_getnxtdesc), | |
6775 | .TXC_DMC_DMA0_inc_head (txc_dmc_dma0_inc_head), | |
6776 | .TXC_DMC_DMA0_reset_done (txc_dmc_dma0_reset_done), | |
6777 | .TXC_DMC_DMA0_mark_bit (txc_dmc_dma0_mark_bit), | |
6778 | .TXC_DMC_DMA0_inc_pkt_cnt (txc_dmc_dma0_inc_pkt_cnt), | |
6779 | .DMC_TXC_DMA1_GotNxtDesc (dmc_txc_dma1_gotnxtdesc), | |
6780 | .TXC_DMC_DMA1_GetNxtDesc (txc_dmc_dma1_getnxtdesc), | |
6781 | .TXC_DMC_DMA1_inc_head (txc_dmc_dma1_inc_head), | |
6782 | .TXC_DMC_DMA1_reset_done (txc_dmc_dma1_reset_done), | |
6783 | .TXC_DMC_DMA1_mark_bit (txc_dmc_dma1_mark_bit), | |
6784 | .TXC_DMC_DMA1_inc_pkt_cnt (txc_dmc_dma1_inc_pkt_cnt), | |
6785 | .DMC_TXC_DMA2_GotNxtDesc (dmc_txc_dma2_gotnxtdesc), | |
6786 | .TXC_DMC_DMA2_GetNxtDesc (txc_dmc_dma2_getnxtdesc), | |
6787 | .TXC_DMC_DMA2_inc_head (txc_dmc_dma2_inc_head), | |
6788 | .TXC_DMC_DMA2_reset_done (txc_dmc_dma2_reset_done), | |
6789 | .TXC_DMC_DMA2_mark_bit (txc_dmc_dma2_mark_bit), | |
6790 | .TXC_DMC_DMA2_inc_pkt_cnt (txc_dmc_dma2_inc_pkt_cnt), | |
6791 | .DMC_TXC_DMA3_GotNxtDesc (dmc_txc_dma3_gotnxtdesc), | |
6792 | .TXC_DMC_DMA3_GetNxtDesc (txc_dmc_dma3_getnxtdesc), | |
6793 | .TXC_DMC_DMA3_inc_head (txc_dmc_dma3_inc_head), | |
6794 | .TXC_DMC_DMA3_reset_done (txc_dmc_dma3_reset_done), | |
6795 | .TXC_DMC_DMA3_mark_bit (txc_dmc_dma3_mark_bit), | |
6796 | .TXC_DMC_DMA3_inc_pkt_cnt (txc_dmc_dma3_inc_pkt_cnt), | |
6797 | .DMC_TXC_DMA4_GotNxtDesc (dmc_txc_dma4_gotnxtdesc), | |
6798 | .TXC_DMC_DMA4_GetNxtDesc (txc_dmc_dma4_getnxtdesc), | |
6799 | .TXC_DMC_DMA4_inc_head (txc_dmc_dma4_inc_head), | |
6800 | .TXC_DMC_DMA4_reset_done (txc_dmc_dma4_reset_done), | |
6801 | .TXC_DMC_DMA4_mark_bit (txc_dmc_dma4_mark_bit), | |
6802 | .TXC_DMC_DMA4_inc_pkt_cnt (txc_dmc_dma4_inc_pkt_cnt), | |
6803 | .DMC_TXC_DMA5_GotNxtDesc (dmc_txc_dma5_gotnxtdesc), | |
6804 | .TXC_DMC_DMA5_GetNxtDesc (txc_dmc_dma5_getnxtdesc), | |
6805 | .TXC_DMC_DMA5_inc_head (txc_dmc_dma5_inc_head), | |
6806 | .TXC_DMC_DMA5_reset_done (txc_dmc_dma5_reset_done), | |
6807 | .TXC_DMC_DMA5_mark_bit (txc_dmc_dma5_mark_bit), | |
6808 | .TXC_DMC_DMA5_inc_pkt_cnt (txc_dmc_dma5_inc_pkt_cnt), | |
6809 | .DMC_TXC_DMA6_GotNxtDesc (dmc_txc_dma6_gotnxtdesc), | |
6810 | .TXC_DMC_DMA6_GetNxtDesc (txc_dmc_dma6_getnxtdesc), | |
6811 | .TXC_DMC_DMA6_inc_head (txc_dmc_dma6_inc_head), | |
6812 | .TXC_DMC_DMA6_reset_done (txc_dmc_dma6_reset_done), | |
6813 | .TXC_DMC_DMA6_mark_bit (txc_dmc_dma6_mark_bit), | |
6814 | .TXC_DMC_DMA6_inc_pkt_cnt (txc_dmc_dma6_inc_pkt_cnt), | |
6815 | .DMC_TXC_DMA7_GotNxtDesc (dmc_txc_dma7_gotnxtdesc), | |
6816 | .TXC_DMC_DMA7_GetNxtDesc (txc_dmc_dma7_getnxtdesc), | |
6817 | .TXC_DMC_DMA7_inc_head (txc_dmc_dma7_inc_head), | |
6818 | .TXC_DMC_DMA7_reset_done (txc_dmc_dma7_reset_done), | |
6819 | .TXC_DMC_DMA7_mark_bit (txc_dmc_dma7_mark_bit), | |
6820 | .TXC_DMC_DMA7_inc_pkt_cnt (txc_dmc_dma7_inc_pkt_cnt), | |
6821 | .DMC_TXC_DMA8_GotNxtDesc (dmc_txc_dma8_gotnxtdesc), | |
6822 | .TXC_DMC_DMA8_GetNxtDesc (txc_dmc_dma8_getnxtdesc), | |
6823 | .TXC_DMC_DMA8_inc_head (txc_dmc_dma8_inc_head), | |
6824 | .TXC_DMC_DMA8_reset_done (txc_dmc_dma8_reset_done), | |
6825 | .TXC_DMC_DMA8_mark_bit (txc_dmc_dma8_mark_bit), | |
6826 | .TXC_DMC_DMA8_inc_pkt_cnt (txc_dmc_dma8_inc_pkt_cnt), | |
6827 | .DMC_TXC_DMA9_GotNxtDesc (dmc_txc_dma9_gotnxtdesc), | |
6828 | .TXC_DMC_DMA9_GetNxtDesc (txc_dmc_dma9_getnxtdesc), | |
6829 | .TXC_DMC_DMA9_inc_head (txc_dmc_dma9_inc_head), | |
6830 | .TXC_DMC_DMA9_reset_done (txc_dmc_dma9_reset_done), | |
6831 | .TXC_DMC_DMA9_mark_bit (txc_dmc_dma9_mark_bit), | |
6832 | .TXC_DMC_DMA9_inc_pkt_cnt (txc_dmc_dma9_inc_pkt_cnt), | |
6833 | .DMC_TXC_DMA10_GotNxtDesc (dmc_txc_dma10_gotnxtdesc), | |
6834 | .TXC_DMC_DMA10_GetNxtDesc (txc_dmc_dma10_getnxtdesc), | |
6835 | .TXC_DMC_DMA10_inc_head (txc_dmc_dma10_inc_head), | |
6836 | .TXC_DMC_DMA10_reset_done (txc_dmc_dma10_reset_done), | |
6837 | .TXC_DMC_DMA10_mark_bit (txc_dmc_dma10_mark_bit), | |
6838 | .TXC_DMC_DMA10_inc_pkt_cnt (txc_dmc_dma10_inc_pkt_cnt), | |
6839 | .DMC_TXC_DMA11_GotNxtDesc (dmc_txc_dma11_gotnxtdesc), | |
6840 | .TXC_DMC_DMA11_GetNxtDesc (txc_dmc_dma11_getnxtdesc), | |
6841 | .TXC_DMC_DMA11_inc_head (txc_dmc_dma11_inc_head), | |
6842 | .TXC_DMC_DMA11_reset_done (txc_dmc_dma11_reset_done), | |
6843 | .TXC_DMC_DMA11_mark_bit (txc_dmc_dma11_mark_bit), | |
6844 | .TXC_DMC_DMA11_inc_pkt_cnt (txc_dmc_dma11_inc_pkt_cnt), | |
6845 | .DMC_TXC_DMA12_GotNxtDesc (dmc_txc_dma12_gotnxtdesc), | |
6846 | .TXC_DMC_DMA12_GetNxtDesc (txc_dmc_dma12_getnxtdesc), | |
6847 | .TXC_DMC_DMA12_inc_head (txc_dmc_dma12_inc_head), | |
6848 | .TXC_DMC_DMA12_reset_done (txc_dmc_dma12_reset_done), | |
6849 | .TXC_DMC_DMA12_mark_bit (txc_dmc_dma12_mark_bit), | |
6850 | .TXC_DMC_DMA12_inc_pkt_cnt (txc_dmc_dma12_inc_pkt_cnt), | |
6851 | .DMC_TXC_DMA13_GotNxtDesc (dmc_txc_dma13_gotnxtdesc), | |
6852 | .TXC_DMC_DMA13_GetNxtDesc (txc_dmc_dma13_getnxtdesc), | |
6853 | .TXC_DMC_DMA13_inc_head (txc_dmc_dma13_inc_head), | |
6854 | .TXC_DMC_DMA13_reset_done (txc_dmc_dma13_reset_done), | |
6855 | .TXC_DMC_DMA13_mark_bit (txc_dmc_dma13_mark_bit), | |
6856 | .TXC_DMC_DMA13_inc_pkt_cnt (txc_dmc_dma13_inc_pkt_cnt), | |
6857 | .DMC_TXC_DMA14_GotNxtDesc (dmc_txc_dma14_gotnxtdesc), | |
6858 | .TXC_DMC_DMA14_GetNxtDesc (txc_dmc_dma14_getnxtdesc), | |
6859 | .TXC_DMC_DMA14_inc_head (txc_dmc_dma14_inc_head), | |
6860 | .TXC_DMC_DMA14_reset_done (txc_dmc_dma14_reset_done), | |
6861 | .TXC_DMC_DMA14_mark_bit (txc_dmc_dma14_mark_bit), | |
6862 | .TXC_DMC_DMA14_inc_pkt_cnt (txc_dmc_dma14_inc_pkt_cnt), | |
6863 | .DMC_TXC_DMA15_GotNxtDesc (dmc_txc_dma15_gotnxtdesc), | |
6864 | .TXC_DMC_DMA15_GetNxtDesc (txc_dmc_dma15_getnxtdesc), | |
6865 | .TXC_DMC_DMA15_inc_head (txc_dmc_dma15_inc_head), | |
6866 | .TXC_DMC_DMA15_reset_done (txc_dmc_dma15_reset_done), | |
6867 | .TXC_DMC_DMA15_mark_bit (txc_dmc_dma15_mark_bit), | |
6868 | .TXC_DMC_DMA15_inc_pkt_cnt (txc_dmc_dma15_inc_pkt_cnt), | |
6869 | .DMC_TXC_DMA16_GotNxtDesc (dmc_txc_dma16_gotnxtdesc), | |
6870 | .TXC_DMC_DMA16_GetNxtDesc (txc_dmc_dma16_getnxtdesc), | |
6871 | .TXC_DMC_DMA16_inc_head (txc_dmc_dma16_inc_head), | |
6872 | .TXC_DMC_DMA16_reset_done (txc_dmc_dma16_reset_done), | |
6873 | .TXC_DMC_DMA16_mark_bit (txc_dmc_dma16_mark_bit), | |
6874 | .TXC_DMC_DMA16_inc_pkt_cnt (txc_dmc_dma16_inc_pkt_cnt), | |
6875 | .DMC_TXC_DMA17_GotNxtDesc (dmc_txc_dma17_gotnxtdesc), | |
6876 | .TXC_DMC_DMA17_GetNxtDesc (txc_dmc_dma17_getnxtdesc), | |
6877 | .TXC_DMC_DMA17_inc_head (txc_dmc_dma17_inc_head), | |
6878 | .TXC_DMC_DMA17_reset_done (txc_dmc_dma17_reset_done), | |
6879 | .TXC_DMC_DMA17_mark_bit (txc_dmc_dma17_mark_bit), | |
6880 | .TXC_DMC_DMA17_inc_pkt_cnt (txc_dmc_dma17_inc_pkt_cnt), | |
6881 | .DMC_TXC_DMA18_GotNxtDesc (dmc_txc_dma18_gotnxtdesc), | |
6882 | .TXC_DMC_DMA18_GetNxtDesc (txc_dmc_dma18_getnxtdesc), | |
6883 | .TXC_DMC_DMA18_inc_head (txc_dmc_dma18_inc_head), | |
6884 | .TXC_DMC_DMA18_reset_done (txc_dmc_dma18_reset_done), | |
6885 | .TXC_DMC_DMA18_mark_bit (txc_dmc_dma18_mark_bit), | |
6886 | .TXC_DMC_DMA18_inc_pkt_cnt (txc_dmc_dma18_inc_pkt_cnt), | |
6887 | .DMC_TXC_DMA19_GotNxtDesc (dmc_txc_dma19_gotnxtdesc), | |
6888 | .TXC_DMC_DMA19_GetNxtDesc (txc_dmc_dma19_getnxtdesc), | |
6889 | .TXC_DMC_DMA19_inc_head (txc_dmc_dma19_inc_head), | |
6890 | .TXC_DMC_DMA19_reset_done (txc_dmc_dma19_reset_done), | |
6891 | .TXC_DMC_DMA19_mark_bit (txc_dmc_dma19_mark_bit), | |
6892 | .TXC_DMC_DMA19_inc_pkt_cnt (txc_dmc_dma19_inc_pkt_cnt), | |
6893 | .DMC_TXC_DMA20_GotNxtDesc (dmc_txc_dma20_gotnxtdesc), | |
6894 | .TXC_DMC_DMA20_GetNxtDesc (txc_dmc_dma20_getnxtdesc), | |
6895 | .TXC_DMC_DMA20_inc_head (txc_dmc_dma20_inc_head), | |
6896 | .TXC_DMC_DMA20_reset_done (txc_dmc_dma20_reset_done), | |
6897 | .TXC_DMC_DMA20_mark_bit (txc_dmc_dma20_mark_bit), | |
6898 | .TXC_DMC_DMA20_inc_pkt_cnt (txc_dmc_dma20_inc_pkt_cnt), | |
6899 | .DMC_TXC_DMA21_GotNxtDesc (dmc_txc_dma21_gotnxtdesc), | |
6900 | .TXC_DMC_DMA21_GetNxtDesc (txc_dmc_dma21_getnxtdesc), | |
6901 | .TXC_DMC_DMA21_inc_head (txc_dmc_dma21_inc_head), | |
6902 | .TXC_DMC_DMA21_reset_done (txc_dmc_dma21_reset_done), | |
6903 | .TXC_DMC_DMA21_mark_bit (txc_dmc_dma21_mark_bit), | |
6904 | .TXC_DMC_DMA21_inc_pkt_cnt (txc_dmc_dma21_inc_pkt_cnt), | |
6905 | .DMC_TXC_DMA22_GotNxtDesc (dmc_txc_dma22_gotnxtdesc), | |
6906 | .TXC_DMC_DMA22_GetNxtDesc (txc_dmc_dma22_getnxtdesc), | |
6907 | .TXC_DMC_DMA22_inc_head (txc_dmc_dma22_inc_head), | |
6908 | .TXC_DMC_DMA22_reset_done (txc_dmc_dma22_reset_done), | |
6909 | .TXC_DMC_DMA22_mark_bit (txc_dmc_dma22_mark_bit), | |
6910 | .TXC_DMC_DMA22_inc_pkt_cnt (txc_dmc_dma22_inc_pkt_cnt), | |
6911 | .DMC_TXC_DMA23_GotNxtDesc (dmc_txc_dma23_gotnxtdesc), | |
6912 | .TXC_DMC_DMA23_GetNxtDesc (txc_dmc_dma23_getnxtdesc), | |
6913 | .TXC_DMC_DMA23_inc_head (txc_dmc_dma23_inc_head), | |
6914 | .TXC_DMC_DMA23_reset_done (txc_dmc_dma23_reset_done), | |
6915 | .TXC_DMC_DMA23_mark_bit (txc_dmc_dma23_mark_bit), | |
6916 | .TXC_DMC_DMA23_inc_pkt_cnt (txc_dmc_dma23_inc_pkt_cnt) | |
6917 | ); | |
6918 | ||
6919 | `ifdef NEPTUNE | |
6920 | ||
6921 | niu_txc_spare niu_txc_spare0 ( | |
6922 | .clk (niu_clk), | |
6923 | .rst (niu_reset_l) | |
6924 | ); | |
6925 | ||
6926 | niu_txc_spare niu_txc_spare1 ( | |
6927 | .clk (niu_clk), | |
6928 | .rst (niu_reset_l) | |
6929 | ); | |
6930 | ||
6931 | niu_txc_spare niu_txc_spare2 ( | |
6932 | .clk (niu_clk), | |
6933 | .rst (niu_reset_l) | |
6934 | ); | |
6935 | ||
6936 | niu_txc_spare niu_txc_spare3 ( | |
6937 | .clk (niu_clk), | |
6938 | .rst (niu_reset_l) | |
6939 | ); | |
6940 | ||
6941 | niu_txc_spare niu_txc_spare4 ( | |
6942 | .clk (niu_clk), | |
6943 | .rst (niu_reset_l) | |
6944 | ); | |
6945 | ||
6946 | niu_txc_spare niu_txc_spare5 ( | |
6947 | .clk (niu_clk), | |
6948 | .rst (niu_reset_l) | |
6949 | ); | |
6950 | ||
6951 | niu_txc_spare niu_txc_spare6 ( | |
6952 | .clk (niu_clk), | |
6953 | .rst (niu_reset_l) | |
6954 | ); | |
6955 | ||
6956 | niu_txc_spare niu_txc_spare7 ( | |
6957 | .clk (niu_clk), | |
6958 | .rst (niu_reset_l) | |
6959 | ); | |
6960 | ||
6961 | niu_txc_spare niu_txc_spare8 ( | |
6962 | .clk (niu_clk), | |
6963 | .rst (niu_reset_l) | |
6964 | ); | |
6965 | ||
6966 | niu_txc_spare niu_txc_spare9 ( | |
6967 | .clk (niu_clk), | |
6968 | .rst (niu_reset_l) | |
6969 | ); | |
6970 | ||
6971 | niu_txc_spare niu_txc_spare10 ( | |
6972 | .clk (niu_clk), | |
6973 | .rst (niu_reset_l) | |
6974 | ); | |
6975 | ||
6976 | niu_txc_spare niu_txc_spare11 ( | |
6977 | .clk (niu_clk), | |
6978 | .rst (niu_reset_l) | |
6979 | ); | |
6980 | ||
6981 | niu_txc_spare niu_txc_spare12 ( | |
6982 | .clk (niu_clk), | |
6983 | .rst (niu_reset_l) | |
6984 | ); | |
6985 | ||
6986 | niu_txc_spare niu_txc_spare13 ( | |
6987 | .clk (niu_clk), | |
6988 | .rst (niu_reset_l) | |
6989 | ); | |
6990 | ||
6991 | niu_txc_spare niu_txc_spare14 ( | |
6992 | .clk (niu_clk), | |
6993 | .rst (niu_reset_l) | |
6994 | ); | |
6995 | ||
6996 | niu_txc_spare niu_txc_spare15 ( | |
6997 | .clk (niu_clk), | |
6998 | .rst (niu_reset_l) | |
6999 | ); | |
7000 | ||
7001 | niu_txc_spare niu_txc_spare16 ( | |
7002 | .clk (niu_clk), | |
7003 | .rst (niu_reset_l) | |
7004 | ); | |
7005 | ||
7006 | niu_txc_spare niu_txc_spare17 ( | |
7007 | .clk (niu_clk), | |
7008 | .rst (niu_reset_l) | |
7009 | ); | |
7010 | ||
7011 | niu_txc_spare niu_txc_spare18 ( | |
7012 | .clk (niu_clk), | |
7013 | .rst (niu_reset_l) | |
7014 | ); | |
7015 | ||
7016 | niu_txc_spare niu_txc_spare19 ( | |
7017 | .clk (niu_clk), | |
7018 | .rst (niu_reset_l) | |
7019 | ); | |
7020 | ||
7021 | niu_txc_spare niu_txc_spare20 ( | |
7022 | .clk (niu_clk), | |
7023 | .rst (niu_reset_l) | |
7024 | ); | |
7025 | ||
7026 | niu_txc_spare niu_txc_spare21 ( | |
7027 | .clk (niu_clk), | |
7028 | .rst (niu_reset_l) | |
7029 | ); | |
7030 | ||
7031 | niu_txc_spare niu_txc_spare22 ( | |
7032 | .clk (niu_clk), | |
7033 | .rst (niu_reset_l) | |
7034 | ); | |
7035 | ||
7036 | niu_txc_spare niu_txc_spare23 ( | |
7037 | .clk (niu_clk), | |
7038 | .rst (niu_reset_l) | |
7039 | ); | |
7040 | ||
7041 | niu_txc_spare niu_txc_spare24 ( | |
7042 | .clk (niu_clk), | |
7043 | .rst (niu_reset_l) | |
7044 | ); | |
7045 | ||
7046 | niu_txc_spare niu_txc_spare25 ( | |
7047 | .clk (niu_clk), | |
7048 | .rst (niu_reset_l) | |
7049 | ); | |
7050 | ||
7051 | niu_txc_spare niu_txc_spare26 ( | |
7052 | .clk (niu_clk), | |
7053 | .rst (niu_reset_l) | |
7054 | ); | |
7055 | ||
7056 | niu_txc_spare niu_txc_spare27 ( | |
7057 | .clk (niu_clk), | |
7058 | .rst (niu_reset_l) | |
7059 | ); | |
7060 | ||
7061 | niu_txc_spare niu_txc_spare28 ( | |
7062 | .clk (niu_clk), | |
7063 | .rst (niu_reset_l) | |
7064 | ); | |
7065 | ||
7066 | niu_txc_spare niu_txc_spare29 ( | |
7067 | .clk (niu_clk), | |
7068 | .rst (niu_reset_l) | |
7069 | ); | |
7070 | ||
7071 | niu_txc_spare niu_txc_spare30 ( | |
7072 | .clk (niu_clk), | |
7073 | .rst (niu_reset_l) | |
7074 | ); | |
7075 | ||
7076 | niu_txc_spare niu_txc_spare31 ( | |
7077 | .clk (niu_clk), | |
7078 | .rst (niu_reset_l) | |
7079 | ); | |
7080 | ||
7081 | `endif | |
7082 | ||
7083 | endmodule |