[OpenSPARC-T2-DV] / design / sys / iop / niu / rtl / niu_txc_dataFetch.v

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: niu_txc_dataFetch.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
/*********************************************************************
 *
 *  niu_txc_dataFetch.v
 *
 *  TXC Data Fetch
 *
 *  Orignal Author(s):   Rahoul Puri
 *  Modifier(s):
 *  Project(s):          Neptune
 *
 *  Copyright (c) 2004   Sun Microsystems, Inc.
 *
 *  All Rights Reserved.
 *
 *  This verilog model is the confidential and proprietary property of
 *  Sun Microsystems, Inc., and the possession or use of this model
 *  requires a written license from Sun Microsystems, Inc.
 *
 **********************************************************************/

`include "timescale.v"

module niu_txc_dataFetch (
        SysClk,
        Reset_L, 
        Txc_Enabled, 

        DMC_TXC_Tx_Addr_Md,

        DMC_TXC_Req_Ack,
        TXC_DMC_Req,
        TXC_DMC_Req_Func_Num,
        TXC_DMC_Req_Port_Num,
        TXC_DMC_Req_DMA_Num,
        TXC_DMC_Req_Cmd,
        TXC_DMC_Req_Length,
        TXC_DMC_Req_Address,

        Port_Selected,

        Port0_Request,
        Port0_Request_Func_Num,
        Port0_Request_DMA_Num,
        Port0_Request_Length,
        Port0_Request_Address,

        Port1_Request,
        Port1_Request_Func_Num,
        Port1_Request_DMA_Num,
        Port1_Request_Length,
        Port1_Request_Address,

        Port2_Request,
        Port2_Request_Func_Num,
        Port2_Request_DMA_Num,
        Port2_Request_Length,
        Port2_Request_Address,

        Port3_Request,
        Port3_Request_Func_Num,
        Port3_Request_DMA_Num,
        Port3_Request_Length,
        Port3_Request_Address,

        PortSelect_State,
        DataFetch_State
       );
    
`include "txc_defines.h"

// Global Signals
input          SysClk;
input          Reset_L;
input          Txc_Enabled;

// Tx DMA Cache
input          DMC_TXC_Tx_Addr_Md;

// Tx DMA Request Interface
input          DMC_TXC_Req_Ack;

output         TXC_DMC_Req;
output [1:0]   TXC_DMC_Req_Func_Num;
output [1:0]   TXC_DMC_Req_Port_Num;
output [4:0]   TXC_DMC_Req_DMA_Num;
output [7:0]   TXC_DMC_Req_Cmd;
output [13:0]  TXC_DMC_Req_Length;
output [63:0]  TXC_DMC_Req_Address;

reg            TXC_DMC_Req;
reg    [1:0]   TXC_DMC_Req_Func_Num;
reg    [1:0]   TXC_DMC_Req_Port_Num;
reg    [4:0]   TXC_DMC_Req_DMA_Num;
reg    [7:0]   TXC_DMC_Req_Cmd;
reg    [63:0]  TXC_DMC_Req_Address;

// Global Port Interface
output [3:0]   Port_Selected;

// Port 0 Interface
input          Port0_Request;
input [1:0]    Port0_Request_Func_Num;
input [4:0]    Port0_Request_DMA_Num;
input [12:0]   Port0_Request_Length;
input [63:0]   Port0_Request_Address;

// Port 1 Interface
input          Port1_Request;
input [1:0]    Port1_Request_Func_Num;
input [4:0]    Port1_Request_DMA_Num;
input [12:0]   Port1_Request_Length;
input [63:0]   Port1_Request_Address;

// Port 2 Interface
input          Port2_Request;
input [1:0]    Port2_Request_Func_Num;
input [4:0]    Port2_Request_DMA_Num;
input [12:0]   Port2_Request_Length;
input [63:0]   Port2_Request_Address;

// Port 3 Interface
input          Port3_Request;
input [1:0]    Port3_Request_Func_Num;
input [4:0]    Port3_Request_DMA_Num;
input [12:0]   Port3_Request_Length;
input [63:0]   Port3_Request_Address;

// State Machine
output [3:0]   PortSelect_State;
output [3:0]   DataFetch_State;

reg    [3:0]   PortSelect_State;
reg    [3:0]   DataFetch_State;

/*--------------------------------------------------------------*/
// Wires & Registers
/*--------------------------------------------------------------*/
wire           requestValid;
wire           selectPortZero;
wire           selectPortOne;
wire           selectPortTwo;
wire           selectPortThree;
wire   [3:0]   portRequest;
wire   [3:0]   lastPortGranted;

reg            dMC_TXC_Req_AckD1;
reg            latchArbSelect;
reg            requestDone_n;
reg            requestDone;
reg            tXC_DMC_Req_n;
reg            ldPortGranted;
reg            portSelectValid;
reg    [1:0]   portArbSelect_n;
reg    [1:0]   portArbSelect;
reg    [1:0]   requestFunctionNum;
reg    [3:0]   nextFetchState;
reg    [3:0]   nextPortGrant;
reg    [3:0]   nextPortState;
reg    [3:0]   portGranted;
reg    [3:0]   portsThatHaveBeenGranted;
reg    [4:0]   requestDMAChannel;
reg    [12:0]  requestLength;
reg    [12:0]  txcDmcRequestLength;
reg    [63:0]  requestAddress;

/*--------------------------------------------------------------*/
// Parameters and Defines
/*--------------------------------------------------------------*/
parameter PORT_REQ_IDLE         = 4'h0,
          PORT_ARB_SELECT       = 4'h1,
          WAIT_FOR_PORT_DONE    = 4'h2;

parameter FETCH_IDLE            = 4'h0,
          CHECK_PORTS_STATE     = 4'h1,
          PORT_SELECT           = 4'h2,
          TRANSACTION_REQ       = 4'h3,
          WAIT_FOR_REQ_ACCEPT   = 4'h4,
          WAIT_FOR_NEXT_DESC    = 4'h5,
          WAIT_FOR_REQUEST_DONE = 4'h6;

//VCS coverage off
// synopsys translate_off
reg [192:1] DATA_PORT_STATE;
reg [192:1] DATA_FETCH_STATE;


always @(PortSelect_State)
begin
  case(PortSelect_State)
    PORT_REQ_IDLE :         DATA_PORT_STATE = "PORT_REQ_IDLE";
    PORT_ARB_SELECT:        DATA_PORT_STATE = "PORT_ARB_SELECT";
    WAIT_FOR_PORT_DONE :    DATA_PORT_STATE = "WAIT_FOR_PORT_DONE";
       default :            DATA_PORT_STATE = "UNKNOWN";
  endcase
end

always @(DataFetch_State)
begin
  case(DataFetch_State)
    FETCH_IDLE :            DATA_FETCH_STATE = "FETCH_IDLE";
    CHECK_PORTS_STATE:      DATA_FETCH_STATE = "CHECK_PORTS_STATE";
    PORT_SELECT :           DATA_FETCH_STATE = "PORT_SELECT";
    TRANSACTION_REQ:        DATA_FETCH_STATE = "TRANSACTION_REQ";
    WAIT_FOR_REQ_ACCEPT :   DATA_FETCH_STATE = "WAIT_FOR_REQ_ACCEPT";
    WAIT_FOR_NEXT_DESC :    DATA_FETCH_STATE = "WAIT_FOR_NEXT_DESC";
    WAIT_FOR_REQUEST_DONE : DATA_FETCH_STATE = "WAIT_FOR_REQUEST_DONE";
       default :            DATA_FETCH_STATE = "UNKNOWN";
  endcase
end

// synopsys translate_on
//VCS coverage on

/*--------------------------------------------------------------*/
// Zero In Checks
/*--------------------------------------------------------------*/


/*--------------------------------------------------------------*/
// Assigns
/*--------------------------------------------------------------*/
assign requestValid = (Port3_Request | Port2_Request
                       |
                       Port1_Request | Port0_Request);

/*--------------------------------------------------------------*/
// Ports Select Round Robin Arbiter
/*--------------------------------------------------------------*/
assign portRequest = {Port3_Request, Port2_Request,
                      Port1_Request, Port0_Request};

assign lastPortGranted = portRequest & ~portsThatHaveBeenGranted;

always @(/*AUTOSENSE*/lastPortGranted or portGranted
        )
      casex(lastPortGranted) // Synopsys full_case
          4'b???1:  nextPortGrant = 4'b0001;
          4'b??10:  nextPortGrant = 4'b0010;
          4'b?100:  nextPortGrant = 4'b0100;
          4'b1000:  nextPortGrant = 4'b1000;
               default:   nextPortGrant = portGranted;
      endcase

always @(posedge SysClk)
  if (!Reset_L)           portGranted <= #`SD 4'h0;
  else if (ldPortGranted) portGranted <= #`SD nextPortGrant;

always @(posedge SysClk)
  if (!Reset_L)
    portsThatHaveBeenGranted <= #`SD 4'h0;
  else if (ldPortGranted) 
    portsThatHaveBeenGranted <= #`SD (portsThatHaveBeenGranted | nextPortGrant);
  else if (lastPortGranted == 4'h0) 
    portsThatHaveBeenGranted <= #`SD 4'h0;

always @(posedge SysClk)
  if (!Reset_L)           portSelectValid <= #`SD 1'b0;
  else if (ldPortGranted) portSelectValid <= #`SD 1'b1;
  else if (requestDone)   portSelectValid <= #`SD 1'b0;

assign selectPortZero  = portGranted[0];
assign selectPortOne   = portGranted[1];
assign selectPortTwo   = portGranted[2];
assign selectPortThree = portGranted[3];

assign Port_Selected = portGranted;

/*--------------------------------------------------------------*/
// Round Robin
/*--------------------------------------------------------------*/
always @(portArbSelect or Port3_Request_DMA_Num or Port2_Request_DMA_Num
         or Port1_Request_DMA_Num or Port0_Request_DMA_Num
        )
    case(portArbSelect) // synopsys full_case parallel_case 
     `PORT_ZERO:   requestDMAChannel = Port0_Request_DMA_Num;
     `PORT_ONE:    requestDMAChannel = Port1_Request_DMA_Num;
     `PORT_TWO:    requestDMAChannel = Port2_Request_DMA_Num;
     `PORT_THREE:  requestDMAChannel = Port3_Request_DMA_Num;
           default: requestDMAChannel = 5'hx;
    endcase

always @(portArbSelect or Port3_Request_Func_Num or Port2_Request_Func_Num
         or Port1_Request_Func_Num or Port0_Request_Func_Num
        )
    case(portArbSelect) // synopsys full_case parallel_case 
     `PORT_ZERO:   requestFunctionNum = Port0_Request_Func_Num;
     `PORT_ONE:    requestFunctionNum = Port1_Request_Func_Num;
     `PORT_TWO:    requestFunctionNum = Port2_Request_Func_Num;
     `PORT_THREE:  requestFunctionNum = Port3_Request_Func_Num;
           default: requestFunctionNum = 2'hx;
    endcase

always @(portArbSelect or Port3_Request_Length or Port2_Request_Length
         or Port1_Request_Length or Port0_Request_Length
        )
    case(portArbSelect) // synopsys full_case parallel_case 
     `PORT_ZERO:   requestLength = Port0_Request_Length;
     `PORT_ONE:    requestLength = Port1_Request_Length;
     `PORT_TWO:    requestLength = Port2_Request_Length;
     `PORT_THREE:  requestLength = Port3_Request_Length;
           default: requestLength = 13'hx;
    endcase

always @(portArbSelect or Port3_Request_Address or Port2_Request_Address
         or Port1_Request_Address or Port0_Request_Address
        )
    case(portArbSelect) // synopsys full_case parallel_case 
     `PORT_ZERO:   requestAddress = Port0_Request_Address;
     `PORT_ONE:    requestAddress = Port1_Request_Address;
     `PORT_TWO:    requestAddress = Port2_Request_Address;
     `PORT_THREE:  requestAddress = Port3_Request_Address;
           default: requestAddress = 64'hx;
    endcase

/*--------------------------------------------------------------*/
// Request State Variables
/*--------------------------------------------------------------*/
always @(posedge SysClk)
  if (!Reset_L) dMC_TXC_Req_AckD1 <= #`SD 1'b0;
  else          dMC_TXC_Req_AckD1 <= #`SD DMC_TXC_Req_Ack;

always @(posedge SysClk)
  if (!Reset_L)             TXC_DMC_Req <= #`SD 1'b0;
  else if (tXC_DMC_Req_n)   TXC_DMC_Req <= #`SD 1'b1;
  else if (DMC_TXC_Req_Ack) TXC_DMC_Req <= #`SD 1'b0;

always @(posedge SysClk)
  if (!Reset_L)             TXC_DMC_Req_Cmd <= #`SD 8'h0;
  else if (tXC_DMC_Req_n)
    begin
      if (DMC_TXC_Tx_Addr_Md) TXC_DMC_Req_Cmd <= #`SD `TXC_MEM_READ_BYPASS_32;
      else                    TXC_DMC_Req_Cmd <= #`SD `TXC_MEM_READ_BYPASS_64;
    end

always @(posedge SysClk)
  if (!Reset_L)             TXC_DMC_Req_Func_Num <= #`SD 2'h0;
  else if (tXC_DMC_Req_n)   TXC_DMC_Req_Func_Num <= #`SD requestFunctionNum;

always @(posedge SysClk)
  if (!Reset_L)             TXC_DMC_Req_Port_Num <= #`SD 2'h0;
  else if (tXC_DMC_Req_n)   TXC_DMC_Req_Port_Num <= #`SD portArbSelect;

always @(posedge SysClk)
  if (!Reset_L)             TXC_DMC_Req_DMA_Num <= #`SD 5'h0;
  else if (tXC_DMC_Req_n)   TXC_DMC_Req_DMA_Num <= #`SD requestDMAChannel;

assign TXC_DMC_Req_Length = {1'b0, txcDmcRequestLength};

always @(posedge SysClk)
  if (!Reset_L)             txcDmcRequestLength <= #`SD 13'h0;
  else if (tXC_DMC_Req_n)   txcDmcRequestLength <= #`SD requestLength;

always @(posedge SysClk)
  if (!Reset_L)             TXC_DMC_Req_Address <= #`SD 64'h0;
  else if (tXC_DMC_Req_n)   TXC_DMC_Req_Address <= #`SD requestAddress;

/*--------------------------------------------------------------*/
// Local Variables
/*--------------------------------------------------------------*/

always @(posedge SysClk)
  if (!Reset_L) requestDone <= #`SD 1'b0;
  else          requestDone <= #`SD requestDone_n;

always @(posedge SysClk)
  if (!Reset_L)            portArbSelect <= #`SD 2'b0;
  else if (latchArbSelect) portArbSelect <= #`SD portArbSelect_n;

/*--------------------------------------------------------------*/
// Port Select & Data Fetch State Vector
/*--------------------------------------------------------------*/
always @(posedge SysClk)
  if (!Reset_L) PortSelect_State <= #`SD PORT_REQ_IDLE;
  else          PortSelect_State <= #`SD nextPortState;

always @(posedge SysClk)
  if (!Reset_L) DataFetch_State <= #`SD FETCH_IDLE;
  else          DataFetch_State <= #`SD nextFetchState;

/*--------------------------------------------------------------*/
// Ports Select Round Robin Arbiter
/*--------------------------------------------------------------*/
function [3:0] PortDefaults;
input [3:0] currentState;
  begin
    PortDefaults = currentState;
    ldPortGranted = 1'b0;
  end
endfunction


always @(/*AUTOSENSE*/PortSelect_State or Txc_Enabled
         or requestValid or dMC_TXC_Req_AckD1
        )

      case(PortSelect_State) // synopsys full_case parallel_case
                             /* 0in < case -full -parallel */
        PORT_REQ_IDLE:
          begin
            nextPortState = PortDefaults(PortSelect_State);

            if (Txc_Enabled)
              begin
                if (requestValid)
                  nextPortState = PORT_ARB_SELECT;
              end
          end

        PORT_ARB_SELECT:
          begin
            nextPortState = PortDefaults(PortSelect_State);
            ldPortGranted = 1'b1;
            nextPortState = WAIT_FOR_PORT_DONE;
          end


        WAIT_FOR_PORT_DONE: begin
          begin
            nextPortState = PortDefaults(PortSelect_State);

            if (dMC_TXC_Req_AckD1) 
              nextPortState = PORT_REQ_IDLE;

             end
          end

        endcase


/*--------------------------------------------------------------*/
// Data Fetch State Machine
/*--------------------------------------------------------------*/
function [3:0] FetchDefaults;
input [3:0] currentState;
  begin
    FetchDefaults = currentState;
    portArbSelect_n = 2'b0;
    latchArbSelect = 1'b0;
    tXC_DMC_Req_n = 1'b0;
    requestDone_n = 1'b0;
  end
endfunction


always @(/*AUTOSENSE*/DataFetch_State or Txc_Enabled or requestValid
         or selectPortZero or selectPortOne or selectPortTwo or selectPortThree
         or dMC_TXC_Req_AckD1 or portSelectValid or requestDone
	)

      case(DataFetch_State) // synopsys full_case parallel_case
                            /* 0in < case -full -parallel */
        FETCH_IDLE:
          begin
            nextFetchState = FetchDefaults(DataFetch_State);

            if (Txc_Enabled) 
              begin
                if (requestValid) 
                  nextFetchState = CHECK_PORTS_STATE;
              end
          end

        CHECK_PORTS_STATE:
          begin
            nextFetchState = FetchDefaults(DataFetch_State);

            if (~requestValid) 
              nextFetchState = FETCH_IDLE;
            else if (portSelectValid) 
              nextFetchState = PORT_SELECT;

          end

        PORT_SELECT:
          begin
            nextFetchState = FetchDefaults(DataFetch_State);
            latchArbSelect = 1'b1;

            if (portSelectValid) 
              begin

                if (selectPortZero) 
                  portArbSelect_n = `PORT_ZERO;
                else if (selectPortOne) 
                  portArbSelect_n = `PORT_ONE;
                else if (selectPortTwo) 
                  portArbSelect_n = `PORT_TWO;
                else if (selectPortThree) 
                  portArbSelect_n = `PORT_THREE;

                nextFetchState =  TRANSACTION_REQ;
              end
          end

        TRANSACTION_REQ:
          begin
            nextFetchState = FetchDefaults(DataFetch_State);
            tXC_DMC_Req_n = 1'b1;
            nextFetchState = WAIT_FOR_REQ_ACCEPT;
          end

        WAIT_FOR_REQ_ACCEPT:
          begin
            nextFetchState = FetchDefaults(DataFetch_State);

            if (dMC_TXC_Req_AckD1) 
              begin
                nextFetchState = WAIT_FOR_REQUEST_DONE;
                requestDone_n = 1'b1;
              end
          end

        WAIT_FOR_REQUEST_DONE:
          begin
            nextFetchState = FetchDefaults(DataFetch_State);

            if (requestDone)
              begin
                if (!requestValid) 
                  nextFetchState = FETCH_IDLE;
                else
                  nextFetchState = CHECK_PORTS_STATE;
              end
          end

      endcase

endmodule
Commit	Line	Data
86530b38 AT	1	// ========== Copyright Header Begin ==========================================
	2	//
	3	// OpenSPARC T2 Processor File: niu_txc_dataFetch.v
	4	// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
	5	// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
	6	//
	7	// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
	8	//
	9	// This program is free software; you can redistribute it and/or modify
	10	// it under the terms of the GNU General Public License as published by
	11	// the Free Software Foundation; version 2 of the License.
	12	//
	13	// This program is distributed in the hope that it will be useful,
	14	// but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	// GNU General Public License for more details.
	17	//
	18	// You should have received a copy of the GNU General Public License
	19	// along with this program; if not, write to the Free Software
	20	// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	21	//
	22	// For the avoidance of doubt, and except that if any non-GPL license
	23	// choice is available it will apply instead, Sun elects to use only
	24	// the General Public License version 2 (GPLv2) at this time for any
	25	// software where a choice of GPL license versions is made
	26	// available with the language indicating that GPLv2 or any later version
	27	// may be used, or where a choice of which version of the GPL is applied is
	28	// otherwise unspecified.
	29	//
	30	// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
	31	// CA 95054 USA or visit www.sun.com if you need additional information or
	32	// have any questions.
	33	//
	34	// ========== Copyright Header End ============================================
	35	/*********************************************************************
	36	*
	37	* niu_txc_dataFetch.v
	38	*
	39	* TXC Data Fetch
	40	*
	41	* Orignal Author(s): Rahoul Puri
	42	* Modifier(s):
	43	* Project(s): Neptune
	44	*
	45	* Copyright (c) 2004 Sun Microsystems, Inc.
	46	*
	47	* All Rights Reserved.
	48	*
	49	* This verilog model is the confidential and proprietary property of
	50	* Sun Microsystems, Inc., and the possession or use of this model
	51	* requires a written license from Sun Microsystems, Inc.
	52	*
	53	**********************************************************************/
	54
	55	`include "timescale.v"
	56
	57	module niu_txc_dataFetch (
	58	SysClk,
	59	Reset_L,
	60	Txc_Enabled,
	61
	62	DMC_TXC_Tx_Addr_Md,
	63
	64	DMC_TXC_Req_Ack,
65	TXC_DMC_Req,
66	TXC_DMC_Req_Func_Num,
67	TXC_DMC_Req_Port_Num,
68	TXC_DMC_Req_DMA_Num,
69	TXC_DMC_Req_Cmd,
70	TXC_DMC_Req_Length,
71	TXC_DMC_Req_Address,
72
73	Port_Selected,
74
75	Port0_Request,
76	Port0_Request_Func_Num,
77	Port0_Request_DMA_Num,
78	Port0_Request_Length,
79	Port0_Request_Address,
80
81	Port1_Request,
82	Port1_Request_Func_Num,
83	Port1_Request_DMA_Num,
84	Port1_Request_Length,
85	Port1_Request_Address,
86
87	Port2_Request,
88	Port2_Request_Func_Num,
89	Port2_Request_DMA_Num,
90	Port2_Request_Length,
91	Port2_Request_Address,
92
93	Port3_Request,
94	Port3_Request_Func_Num,
95	Port3_Request_DMA_Num,
96	Port3_Request_Length,
97	Port3_Request_Address,
98
99	PortSelect_State,
100	DataFetch_State
101	);
102
103	`include "txc_defines.h"
104
105	// Global Signals
106	input SysClk;
107	input Reset_L;
108	input Txc_Enabled;
109
110	// Tx DMA Cache
111	input DMC_TXC_Tx_Addr_Md;
112
113	// Tx DMA Request Interface
114	input DMC_TXC_Req_Ack;
115
116	output TXC_DMC_Req;
117	output [1:0] TXC_DMC_Req_Func_Num;
118	output [1:0] TXC_DMC_Req_Port_Num;
119	output [4:0] TXC_DMC_Req_DMA_Num;
120	output [7:0] TXC_DMC_Req_Cmd;
121	output [13:0] TXC_DMC_Req_Length;
122	output [63:0] TXC_DMC_Req_Address;
123
124	reg TXC_DMC_Req;
125	reg [1:0] TXC_DMC_Req_Func_Num;
126	reg [1:0] TXC_DMC_Req_Port_Num;
127	reg [4:0] TXC_DMC_Req_DMA_Num;
128	reg [7:0] TXC_DMC_Req_Cmd;
129	reg [63:0] TXC_DMC_Req_Address;
130
131	// Global Port Interface
132	output [3:0] Port_Selected;
133
134	// Port 0 Interface
135	input Port0_Request;
136	input [1:0] Port0_Request_Func_Num;
137	input [4:0] Port0_Request_DMA_Num;
138	input [12:0] Port0_Request_Length;
139	input [63:0] Port0_Request_Address;
140
141	// Port 1 Interface
142	input Port1_Request;
143	input [1:0] Port1_Request_Func_Num;
144	input [4:0] Port1_Request_DMA_Num;
145	input [12:0] Port1_Request_Length;
146	input [63:0] Port1_Request_Address;
147
148	// Port 2 Interface
149	input Port2_Request;
150	input [1:0] Port2_Request_Func_Num;
151	input [4:0] Port2_Request_DMA_Num;
152	input [12:0] Port2_Request_Length;
153	input [63:0] Port2_Request_Address;
154
155	// Port 3 Interface
156	input Port3_Request;
157	input [1:0] Port3_Request_Func_Num;
158	input [4:0] Port3_Request_DMA_Num;
159	input [12:0] Port3_Request_Length;
160	input [63:0] Port3_Request_Address;
161
162	// State Machine
163	output [3:0] PortSelect_State;
164	output [3:0] DataFetch_State;
165
166	reg [3:0] PortSelect_State;
167	reg [3:0] DataFetch_State;
168
169	/--------------------------------------------------------------/
170	// Wires & Registers
171	/--------------------------------------------------------------/
172	wire requestValid;
173	wire selectPortZero;
174	wire selectPortOne;
175	wire selectPortTwo;
176	wire selectPortThree;
177	wire [3:0] portRequest;
178	wire [3:0] lastPortGranted;
179
180	reg dMC_TXC_Req_AckD1;
181	reg latchArbSelect;
182	reg requestDone_n;
183	reg requestDone;
184	reg tXC_DMC_Req_n;
185	reg ldPortGranted;
186	reg portSelectValid;
187	reg [1:0] portArbSelect_n;
188	reg [1:0] portArbSelect;
189	reg [1:0] requestFunctionNum;
190	reg [3:0] nextFetchState;
191	reg [3:0] nextPortGrant;
192	reg [3:0] nextPortState;
193	reg [3:0] portGranted;
194	reg [3:0] portsThatHaveBeenGranted;
195	reg [4:0] requestDMAChannel;
196	reg [12:0] requestLength;
197	reg [12:0] txcDmcRequestLength;
198	reg [63:0] requestAddress;
199
200	/--------------------------------------------------------------/
201	// Parameters and Defines
202	/--------------------------------------------------------------/
203	parameter PORT_REQ_IDLE = 4'h0,
204	PORT_ARB_SELECT = 4'h1,
205	WAIT_FOR_PORT_DONE = 4'h2;
206
207	parameter FETCH_IDLE = 4'h0,
208	CHECK_PORTS_STATE = 4'h1,
209	PORT_SELECT = 4'h2,
210	TRANSACTION_REQ = 4'h3,
211	WAIT_FOR_REQ_ACCEPT = 4'h4,
212	WAIT_FOR_NEXT_DESC = 4'h5,
213	WAIT_FOR_REQUEST_DONE = 4'h6;
214
215	//VCS coverage off
216	// synopsys translate_off
217	reg [192:1] DATA_PORT_STATE;
218	reg [192:1] DATA_FETCH_STATE;
219
220
221	always @(PortSelect_State)
222	begin
223	case(PortSelect_State)
224	PORT_REQ_IDLE : DATA_PORT_STATE = "PORT_REQ_IDLE";
225	PORT_ARB_SELECT: DATA_PORT_STATE = "PORT_ARB_SELECT";
226	WAIT_FOR_PORT_DONE : DATA_PORT_STATE = "WAIT_FOR_PORT_DONE";
227	default : DATA_PORT_STATE = "UNKNOWN";
228	endcase
229	end
230
231	always @(DataFetch_State)
232	begin
233	case(DataFetch_State)
234	FETCH_IDLE : DATA_FETCH_STATE = "FETCH_IDLE";
235	CHECK_PORTS_STATE: DATA_FETCH_STATE = "CHECK_PORTS_STATE";
236	PORT_SELECT : DATA_FETCH_STATE = "PORT_SELECT";
237	TRANSACTION_REQ: DATA_FETCH_STATE = "TRANSACTION_REQ";
238	WAIT_FOR_REQ_ACCEPT : DATA_FETCH_STATE = "WAIT_FOR_REQ_ACCEPT";
239	WAIT_FOR_NEXT_DESC : DATA_FETCH_STATE = "WAIT_FOR_NEXT_DESC";
240	WAIT_FOR_REQUEST_DONE : DATA_FETCH_STATE = "WAIT_FOR_REQUEST_DONE";
241	default : DATA_FETCH_STATE = "UNKNOWN";
242	endcase
243	end
244
245	// synopsys translate_on
246	//VCS coverage on
247
248	/--------------------------------------------------------------/
249	// Zero In Checks
250	/--------------------------------------------------------------/
251
252
253	/--------------------------------------------------------------/
254	// Assigns
255	/--------------------------------------------------------------/
256	assign requestValid = (Port3_Request \| Port2_Request
257	\|
258	Port1_Request \| Port0_Request);
259
260	/--------------------------------------------------------------/
261	// Ports Select Round Robin Arbiter
262	/--------------------------------------------------------------/
263	assign portRequest = {Port3_Request, Port2_Request,
264	Port1_Request, Port0_Request};
265
266	assign lastPortGranted = portRequest & ~portsThatHaveBeenGranted;
267
268	always @(/AUTOSENSE/lastPortGranted or portGranted
269	)
270	casex(lastPortGranted) // Synopsys full_case
271	4'b???1: nextPortGrant = 4'b0001;
272	4'b??10: nextPortGrant = 4'b0010;
273	4'b?100: nextPortGrant = 4'b0100;
274	4'b1000: nextPortGrant = 4'b1000;
275	default: nextPortGrant = portGranted;
276	endcase
277
278	always @(posedge SysClk)
279	if (!Reset_L) portGranted <= #`SD 4'h0;
280	else if (ldPortGranted) portGranted <= #`SD nextPortGrant;
281
282	always @(posedge SysClk)
283	if (!Reset_L)
284	portsThatHaveBeenGranted <= #`SD 4'h0;
285	else if (ldPortGranted)
286	portsThatHaveBeenGranted <= #`SD (portsThatHaveBeenGranted \| nextPortGrant);
287	else if (lastPortGranted == 4'h0)
288	portsThatHaveBeenGranted <= #`SD 4'h0;
289
290	always @(posedge SysClk)
291	if (!Reset_L) portSelectValid <= #`SD 1'b0;
292	else if (ldPortGranted) portSelectValid <= #`SD 1'b1;
293	else if (requestDone) portSelectValid <= #`SD 1'b0;
294
295	assign selectPortZero = portGranted[0];
296	assign selectPortOne = portGranted[1];
297	assign selectPortTwo = portGranted[2];
298	assign selectPortThree = portGranted[3];
299
300	assign Port_Selected = portGranted;
301
302	/--------------------------------------------------------------/
303	// Round Robin
304	/--------------------------------------------------------------/
305	always @(portArbSelect or Port3_Request_DMA_Num or Port2_Request_DMA_Num
306	or Port1_Request_DMA_Num or Port0_Request_DMA_Num
307	)
308	case(portArbSelect) // synopsys full_case parallel_case
309	`PORT_ZERO: requestDMAChannel = Port0_Request_DMA_Num;
310	`PORT_ONE: requestDMAChannel = Port1_Request_DMA_Num;
311	`PORT_TWO: requestDMAChannel = Port2_Request_DMA_Num;
312	`PORT_THREE: requestDMAChannel = Port3_Request_DMA_Num;
313	default: requestDMAChannel = 5'hx;
314	endcase
315
316	always @(portArbSelect or Port3_Request_Func_Num or Port2_Request_Func_Num
317	or Port1_Request_Func_Num or Port0_Request_Func_Num
318	)
319	case(portArbSelect) // synopsys full_case parallel_case
320	`PORT_ZERO: requestFunctionNum = Port0_Request_Func_Num;
321	`PORT_ONE: requestFunctionNum = Port1_Request_Func_Num;
322	`PORT_TWO: requestFunctionNum = Port2_Request_Func_Num;
323	`PORT_THREE: requestFunctionNum = Port3_Request_Func_Num;
324	default: requestFunctionNum = 2'hx;
325	endcase
326
327	always @(portArbSelect or Port3_Request_Length or Port2_Request_Length
328	or Port1_Request_Length or Port0_Request_Length
329	)
330	case(portArbSelect) // synopsys full_case parallel_case
331	`PORT_ZERO: requestLength = Port0_Request_Length;
332	`PORT_ONE: requestLength = Port1_Request_Length;
333	`PORT_TWO: requestLength = Port2_Request_Length;
334	`PORT_THREE: requestLength = Port3_Request_Length;
335	default: requestLength = 13'hx;
336	endcase
337
338	always @(portArbSelect or Port3_Request_Address or Port2_Request_Address
339	or Port1_Request_Address or Port0_Request_Address
340	)
341	case(portArbSelect) // synopsys full_case parallel_case
342	`PORT_ZERO: requestAddress = Port0_Request_Address;
343	`PORT_ONE: requestAddress = Port1_Request_Address;
344	`PORT_TWO: requestAddress = Port2_Request_Address;
345	`PORT_THREE: requestAddress = Port3_Request_Address;
346	default: requestAddress = 64'hx;
347	endcase
348
349	/--------------------------------------------------------------/
350	// Request State Variables
351	/--------------------------------------------------------------/
352	always @(posedge SysClk)
353	if (!Reset_L) dMC_TXC_Req_AckD1 <= #`SD 1'b0;
354	else dMC_TXC_Req_AckD1 <= #`SD DMC_TXC_Req_Ack;
355
356	always @(posedge SysClk)
357	if (!Reset_L) TXC_DMC_Req <= #`SD 1'b0;
358	else if (tXC_DMC_Req_n) TXC_DMC_Req <= #`SD 1'b1;
359	else if (DMC_TXC_Req_Ack) TXC_DMC_Req <= #`SD 1'b0;
360
361	always @(posedge SysClk)
362	if (!Reset_L) TXC_DMC_Req_Cmd <= #`SD 8'h0;
363	else if (tXC_DMC_Req_n)
364	begin
365	if (DMC_TXC_Tx_Addr_Md) TXC_DMC_Req_Cmd <= #`SD `TXC_MEM_READ_BYPASS_32;
366	else TXC_DMC_Req_Cmd <= #`SD `TXC_MEM_READ_BYPASS_64;
367	end
368
369	always @(posedge SysClk)
370	if (!Reset_L) TXC_DMC_Req_Func_Num <= #`SD 2'h0;
371	else if (tXC_DMC_Req_n) TXC_DMC_Req_Func_Num <= #`SD requestFunctionNum;
372
373	always @(posedge SysClk)
374	if (!Reset_L) TXC_DMC_Req_Port_Num <= #`SD 2'h0;
375	else if (tXC_DMC_Req_n) TXC_DMC_Req_Port_Num <= #`SD portArbSelect;
376
377	always @(posedge SysClk)
378	if (!Reset_L) TXC_DMC_Req_DMA_Num <= #`SD 5'h0;
379	else if (tXC_DMC_Req_n) TXC_DMC_Req_DMA_Num <= #`SD requestDMAChannel;
380
381	assign TXC_DMC_Req_Length = {1'b0, txcDmcRequestLength};
382
383	always @(posedge SysClk)
384	if (!Reset_L) txcDmcRequestLength <= #`SD 13'h0;
385	else if (tXC_DMC_Req_n) txcDmcRequestLength <= #`SD requestLength;
386
387	always @(posedge SysClk)
388	if (!Reset_L) TXC_DMC_Req_Address <= #`SD 64'h0;
389	else if (tXC_DMC_Req_n) TXC_DMC_Req_Address <= #`SD requestAddress;
390
391	/--------------------------------------------------------------/
392	// Local Variables
393	/--------------------------------------------------------------/
394
395	always @(posedge SysClk)
396	if (!Reset_L) requestDone <= #`SD 1'b0;
397	else requestDone <= #`SD requestDone_n;
398
399	always @(posedge SysClk)
400	if (!Reset_L) portArbSelect <= #`SD 2'b0;
401	else if (latchArbSelect) portArbSelect <= #`SD portArbSelect_n;
402
403	/--------------------------------------------------------------/
404	// Port Select & Data Fetch State Vector
405	/--------------------------------------------------------------/
406	always @(posedge SysClk)
407	if (!Reset_L) PortSelect_State <= #`SD PORT_REQ_IDLE;
408	else PortSelect_State <= #`SD nextPortState;
409
410	always @(posedge SysClk)
411	if (!Reset_L) DataFetch_State <= #`SD FETCH_IDLE;
412	else DataFetch_State <= #`SD nextFetchState;
413
414	/--------------------------------------------------------------/
415	// Ports Select Round Robin Arbiter
416	/--------------------------------------------------------------/
417	function [3:0] PortDefaults;
418	input [3:0] currentState;
419	begin
420	PortDefaults = currentState;
421	ldPortGranted = 1'b0;
422	end
423	endfunction
424
425
426	always @(/AUTOSENSE/PortSelect_State or Txc_Enabled
427	or requestValid or dMC_TXC_Req_AckD1
428	)
429
430	case(PortSelect_State) // synopsys full_case parallel_case
431	/* 0in < case -full -parallel */
432	PORT_REQ_IDLE:
433	begin
434	nextPortState = PortDefaults(PortSelect_State);
435
436	if (Txc_Enabled)
437	begin
438	if (requestValid)
439	nextPortState = PORT_ARB_SELECT;
440	end
441	end
442
443	PORT_ARB_SELECT:
444	begin
445	nextPortState = PortDefaults(PortSelect_State);
446	ldPortGranted = 1'b1;
447	nextPortState = WAIT_FOR_PORT_DONE;
448	end
449
450
451	WAIT_FOR_PORT_DONE: begin
452	begin
453	nextPortState = PortDefaults(PortSelect_State);
454
455	if (dMC_TXC_Req_AckD1)
456	nextPortState = PORT_REQ_IDLE;
457
458	end
459	end
460
461	endcase
462
463
464	/--------------------------------------------------------------/
465	// Data Fetch State Machine
466	/--------------------------------------------------------------/
467	function [3:0] FetchDefaults;
468	input [3:0] currentState;
469	begin
470	FetchDefaults = currentState;
471	portArbSelect_n = 2'b0;
472	latchArbSelect = 1'b0;
473	tXC_DMC_Req_n = 1'b0;
474	requestDone_n = 1'b0;
475	end
476	endfunction
477
478
479	always @(/AUTOSENSE/DataFetch_State or Txc_Enabled or requestValid
480	or selectPortZero or selectPortOne or selectPortTwo or selectPortThree
481	or dMC_TXC_Req_AckD1 or portSelectValid or requestDone
482	)
483
484	case(DataFetch_State) // synopsys full_case parallel_case
485	/* 0in < case -full -parallel */
486	FETCH_IDLE:
487	begin
488	nextFetchState = FetchDefaults(DataFetch_State);
489
490	if (Txc_Enabled)
491	begin
492	if (requestValid)
493	nextFetchState = CHECK_PORTS_STATE;
494	end
495	end
496
497	CHECK_PORTS_STATE:
498	begin
499	nextFetchState = FetchDefaults(DataFetch_State);
500
501	if (~requestValid)
502	nextFetchState = FETCH_IDLE;
503	else if (portSelectValid)
504	nextFetchState = PORT_SELECT;
505
506	end
507
508	PORT_SELECT:
509	begin
510	nextFetchState = FetchDefaults(DataFetch_State);
511	latchArbSelect = 1'b1;
512
513	if (portSelectValid)
514	begin
515
516	if (selectPortZero)
517	portArbSelect_n = `PORT_ZERO;
518	else if (selectPortOne)
519	portArbSelect_n = `PORT_ONE;
520	else if (selectPortTwo)
521	portArbSelect_n = `PORT_TWO;
522	else if (selectPortThree)
523	portArbSelect_n = `PORT_THREE;
524
525	nextFetchState = TRANSACTION_REQ;
526	end
527	end
528
529	TRANSACTION_REQ:
530	begin
531	nextFetchState = FetchDefaults(DataFetch_State);
532	tXC_DMC_Req_n = 1'b1;
533	nextFetchState = WAIT_FOR_REQ_ACCEPT;
534	end
535
536	WAIT_FOR_REQ_ACCEPT:
537	begin
538	nextFetchState = FetchDefaults(DataFetch_State);
539
540	if (dMC_TXC_Req_AckD1)
541	begin
542	nextFetchState = WAIT_FOR_REQUEST_DONE;
543	requestDone_n = 1'b1;
544	end
545	end
546
547	WAIT_FOR_REQUEST_DONE:
548	begin
549	nextFetchState = FetchDefaults(DataFetch_State);
550
551	if (requestDone)
552	begin
553	if (!requestValid)
554	nextFetchState = FETCH_IDLE;
555	else
556	nextFetchState = CHECK_PORTS_STATE;
557	end
558	end
559
560	endcase
561
562	endmodule