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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: niu_txc_debug.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | /********************************************************************* | |
36 | * | |
37 | * niu_txc_debug.v | |
38 | * | |
39 | * NIU TXC Top Level Debug Module | |
40 | * | |
41 | * Orignal Author(s): Rahoul Puri | |
42 | * Modifier(s): | |
43 | * Project(s): Neptune/Niagara 2 | |
44 | * | |
45 | * Copyright (c) 2004 Sun Microsystems, Inc. | |
46 | * | |
47 | * All Rights Reserved. | |
48 | * | |
49 | * This verilog model is the confidential and proprietary property of | |
50 | * Sun Microsystems, Inc., and the possession or use of this model | |
51 | * requires a written license from Sun Microsystems, Inc. | |
52 | * | |
53 | **********************************************************************/ | |
54 | ||
55 | `include "timescale.v" | |
56 | ||
57 | module niu_txc_debug( | |
58 | SysClk, | |
59 | Reset_L, | |
60 | Debug_Select, | |
61 | TrainingVector, | |
62 | PortSelect_State, | |
63 | DataFetch_State, | |
64 | Port0_LatchActiveDMA, | |
65 | Port0_Anchor_State, | |
66 | Port0_ReOrder_State, | |
67 | Port0_Pointer_State, | |
68 | Port0_PacketAssy_State, | |
69 | Port0_DRR_ArbState, | |
70 | Port0_Mac_Xfer_State, | |
71 | Port0_DataPortReq_State, | |
72 | Port0_ContextActiveList, | |
73 | Port0_Sum_prt_state, | |
74 | Port1_LatchActiveDMA, | |
75 | Port1_Anchor_State, | |
76 | Port1_ReOrder_State, | |
77 | Port1_Pointer_State, | |
78 | Port1_PacketAssy_State, | |
79 | Port1_DRR_ArbState, | |
80 | Port1_Mac_Xfer_State, | |
81 | Port1_DataPortReq_State, | |
82 | Port1_ContextActiveList, | |
83 | Port1_Sum_prt_state, | |
84 | Port2_LatchActiveDMA, | |
85 | Port2_Anchor_State, | |
86 | Port2_ReOrder_State, | |
87 | Port2_Pointer_State, | |
88 | Port2_PacketAssy_State, | |
89 | Port2_DRR_ArbState, | |
90 | Port2_Mac_Xfer_State, | |
91 | Port2_DataPortReq_State, | |
92 | Port2_ContextActiveList, | |
93 | Port2_Sum_prt_state, | |
94 | Port3_LatchActiveDMA, | |
95 | Port3_Anchor_State, | |
96 | Port3_ReOrder_State, | |
97 | Port3_Pointer_State, | |
98 | Port3_PacketAssy_State, | |
99 | Port3_DRR_ArbState, | |
100 | Port3_Mac_Xfer_State, | |
101 | Port3_DataPortReq_State, | |
102 | Port3_ContextActiveList, | |
103 | Port3_Sum_prt_state, | |
104 | Txc_Debug_Port | |
105 | ); | |
106 | ||
107 | `include "txc_defines.h" | |
108 | ||
109 | // Global Signals | |
110 | input SysClk; | |
111 | input Reset_L; | |
112 | ||
113 | // Control Registers | |
114 | input [5:0] Debug_Select; | |
115 | input [31:0] TrainingVector; | |
116 | ||
117 | // Data Fetch State Machine | |
118 | input [3:0] PortSelect_State; | |
119 | input [3:0] DataFetch_State; | |
120 | ||
121 | // Port 0 State Machine | |
122 | input Port0_LatchActiveDMA; | |
123 | input [3:0] Port0_Anchor_State; | |
124 | input [3:0] Port0_ReOrder_State; | |
125 | input [3:0] Port0_Pointer_State; | |
126 | input [3:0] Port0_PacketAssy_State; | |
127 | input [3:0] Port0_DRR_ArbState; | |
128 | input [3:0] Port0_Mac_Xfer_State; | |
129 | input [3:0] Port0_DataPortReq_State; | |
130 | input [23:0] Port0_ContextActiveList; | |
131 | input [31:0] Port0_Sum_prt_state; | |
132 | ||
133 | // Port 1 State Machine | |
134 | input Port1_LatchActiveDMA; | |
135 | input [3:0] Port1_Anchor_State; | |
136 | input [3:0] Port1_ReOrder_State; | |
137 | input [3:0] Port1_Pointer_State; | |
138 | input [3:0] Port1_PacketAssy_State; | |
139 | input [3:0] Port1_DRR_ArbState; | |
140 | input [3:0] Port1_Mac_Xfer_State; | |
141 | input [3:0] Port1_DataPortReq_State; | |
142 | input [23:0] Port1_ContextActiveList; | |
143 | input [31:0] Port1_Sum_prt_state; | |
144 | ||
145 | // Port 2 State Machine | |
146 | input Port2_LatchActiveDMA; | |
147 | input [3:0] Port2_Anchor_State; | |
148 | input [3:0] Port2_ReOrder_State; | |
149 | input [3:0] Port2_Pointer_State; | |
150 | input [3:0] Port2_PacketAssy_State; | |
151 | input [3:0] Port2_DRR_ArbState; | |
152 | input [3:0] Port2_Mac_Xfer_State; | |
153 | input [3:0] Port2_DataPortReq_State; | |
154 | input [23:0] Port2_ContextActiveList; | |
155 | input [31:0] Port2_Sum_prt_state; | |
156 | ||
157 | // Port 3 State Machine | |
158 | input Port3_LatchActiveDMA; | |
159 | input [3:0] Port3_Anchor_State; | |
160 | input [3:0] Port3_ReOrder_State; | |
161 | input [3:0] Port3_Pointer_State; | |
162 | input [3:0] Port3_PacketAssy_State; | |
163 | input [3:0] Port3_DRR_ArbState; | |
164 | input [3:0] Port3_Mac_Xfer_State; | |
165 | input [3:0] Port3_DataPortReq_State; | |
166 | input [23:0] Port3_ContextActiveList; | |
167 | input [31:0] Port3_Sum_prt_state; | |
168 | ||
169 | // To Debug Module | |
170 | output [31:0] Txc_Debug_Port; | |
171 | ||
172 | reg [31:0] Txc_Debug_Port; | |
173 | ||
174 | /*--------------------------------------------------------------*/ | |
175 | // Wires & Regs | |
176 | /*--------------------------------------------------------------*/ | |
177 | wire [31:0] dataFetch_engine; | |
178 | wire [31:0] port0_states; | |
179 | wire [31:0] port0_drr; | |
180 | wire [31:0] port1_states; | |
181 | wire [31:0] port1_drr; | |
182 | wire [31:0] port2_states; | |
183 | wire [31:0] port2_drr; | |
184 | wire [31:0] port3_states; | |
185 | wire [31:0] port3_drr; | |
186 | ||
187 | /*--------------------------------------------------------------*/ | |
188 | // Assigns | |
189 | /*--------------------------------------------------------------*/ | |
190 | assign dataFetch_engine = {24'h0, | |
191 | PortSelect_State, DataFetch_State | |
192 | }; | |
193 | ||
194 | assign port0_states = {4'h0, | |
195 | Port0_Anchor_State, Port0_ReOrder_State, | |
196 | Port0_Pointer_State, Port0_PacketAssy_State, | |
197 | Port0_DRR_ArbState, Port0_Mac_Xfer_State, | |
198 | Port0_DataPortReq_State | |
199 | }; | |
200 | ||
201 | assign port0_drr = {Port0_LatchActiveDMA, 7'h0, Port0_ContextActiveList}; | |
202 | ||
203 | assign port1_states = {4'h0, | |
204 | Port1_Anchor_State, Port1_ReOrder_State, | |
205 | Port1_Pointer_State, Port1_PacketAssy_State, | |
206 | Port1_DRR_ArbState, Port1_Mac_Xfer_State, | |
207 | Port1_DataPortReq_State | |
208 | }; | |
209 | ||
210 | assign port1_drr = {Port1_LatchActiveDMA, 7'h0, Port1_ContextActiveList}; | |
211 | ||
212 | assign port2_states = {4'h0, | |
213 | Port2_Anchor_State, Port2_ReOrder_State, | |
214 | Port2_Pointer_State, Port2_PacketAssy_State, | |
215 | Port2_DRR_ArbState, Port2_Mac_Xfer_State, | |
216 | Port2_DataPortReq_State | |
217 | }; | |
218 | ||
219 | assign port2_drr = {Port2_LatchActiveDMA, 7'h0, Port2_ContextActiveList}; | |
220 | ||
221 | assign port3_states = {4'h0, | |
222 | Port3_Anchor_State, Port3_ReOrder_State, | |
223 | Port3_Pointer_State, Port3_PacketAssy_State, | |
224 | Port3_DRR_ArbState, Port3_Mac_Xfer_State, | |
225 | Port3_DataPortReq_State | |
226 | }; | |
227 | ||
228 | assign port3_drr = {Port3_LatchActiveDMA, 7'h0, Port3_ContextActiveList}; | |
229 | ||
230 | /*--------------------------------------------------------------*/ | |
231 | // Debug Block | |
232 | /*--------------------------------------------------------------*/ | |
233 | ||
234 | always @(posedge SysClk) | |
235 | if (!Reset_L) Txc_Debug_Port <= #`SD 32'h0; | |
236 | else | |
237 | case(Debug_Select) | |
238 | `DATA_FETCH_ENGINE: Txc_Debug_Port <= #`SD dataFetch_engine; | |
239 | `PORT0_ENGINE: Txc_Debug_Port <= #`SD port0_states; | |
240 | `PORT0_CKSUM: Txc_Debug_Port <= #`SD Port0_Sum_prt_state; | |
241 | `PORT0_DRR: Txc_Debug_Port <= #`SD port0_drr; | |
242 | `PORT1_ENGINE: Txc_Debug_Port <= #`SD port1_states; | |
243 | `PORT1_CKSUM: Txc_Debug_Port <= #`SD Port1_Sum_prt_state; | |
244 | `PORT1_DRR: Txc_Debug_Port <= #`SD port1_drr; | |
245 | `PORT2_ENGINE: Txc_Debug_Port <= #`SD port2_states; | |
246 | `PORT2_CKSUM: Txc_Debug_Port <= #`SD Port2_Sum_prt_state; | |
247 | `PORT2_DRR: Txc_Debug_Port <= #`SD port2_drr; | |
248 | `PORT3_ENGINE: Txc_Debug_Port <= #`SD port3_states; | |
249 | `PORT3_CKSUM: Txc_Debug_Port <= #`SD Port3_Sum_prt_state; | |
250 | `PORT3_DRR: Txc_Debug_Port <= #`SD port3_drr; | |
251 | `TRAINING_SET: Txc_Debug_Port <= #`SD ~Txc_Debug_Port; | |
252 | `TRAINING_LOAD: Txc_Debug_Port <= #`SD TrainingVector; | |
253 | ||
254 | default: Txc_Debug_Port <= Txc_Debug_Port; | |
255 | ||
256 | endcase | |
257 | ||
258 | endmodule |