Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / design / sys / iop / niu / rtl / niu_txc_meta_resp_ifc.v
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1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: niu_txc_meta_resp_ifc.v
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35/*********************************************************************
36 *
37 * niu_txc_meta_resp_ifc.v
38 *
39 * Meta Interface Logic
40 *
41 * Orignal Author(s): Rahoul Puri
42 * Modifier(s):
43 * Project(s): Neptune
44 *
45 * Copyright (c) 2005 Sun Microsystems, Inc.
46 *
47 * All Rights Reserved.
48 *
49 * This verilog model is the confidential and proprietary property of
50 * Sun Microsystems, Inc., and the possession or use of this model
51 * requires a written license from Sun Microsystems, Inc.
52 *
53 **********************************************************************/
54
55`include "timescale.v"
56
57module niu_txc_meta_resp_ifc (
58 SysClk, // Clock
59 Reset_L, // Reset_L
60 meta_dmc_resp_ready,
61 meta_dmc_resp_complete,
62 meta_dmc_resp_transfer_cmpl,
63 meta_dmc_data_valid,
64 meta_dmc_resp_client,
65 meta_dmc_resp_port_num,
66 meta_dmc_resp_cmd_status,
67 meta_dmc_resp_data_status,
68 meta_dmc_resp_dma_num,
69 meta_dmc_resp_transID,
70 meta_dmc_resp_cmd,
71 meta_dmc_resp_byteenable,
72 meta_dmc_resp_length,
73 meta_dmc_resp_address,
74 meta_dmc_data,
75 dmc_meta_resp_accept,
76 Port0_TXC_DMC_Resp_Accept,
77 Port1_TXC_DMC_Resp_Accept,
78 Port2_TXC_DMC_Resp_Accept,
79 Port3_TXC_DMC_Resp_Accept,
80 DMC_TXC_Resp_Rdy,
81 DMC_TXC_Resp_Complete,
82 DMC_TXC_Trans_Complete,
83 DMC_TXC_Resp_Data_Valid,
84 DMC_TXC_Resp_Client,
85 DMC_TXC_Resp_Port_Num,
86 DMC_TXC_Resp_Cmd_Status,
87 DMC_TXC_Resp_Data_Status,
88 DMC_TXC_Resp_DMA_Num,
89 DMC_TXC_Resp_TransID,
90 DMC_TXC_Resp_Cmd,
91 DMC_TXC_Resp_Data_Length,
92 DMC_TXC_Resp_ByteEnables,
93 DMC_TXC_Resp_Address,
94 DMC_TXC_Resp_Data
95 );
96
97`include "txc_defines.h"
98
99// MAC Global Signals
100input SysClk;
101input Reset_L;
102
103// Meta Response Interface
104input meta_dmc_resp_ready;
105input meta_dmc_resp_complete;
106input meta_dmc_resp_transfer_cmpl;
107input meta_dmc_data_valid;
108input meta_dmc_resp_client;
109input [1:0] meta_dmc_resp_port_num;
110input [3:0] meta_dmc_resp_cmd_status;
111input [3:0] meta_dmc_resp_data_status;
112input [4:0] meta_dmc_resp_dma_num;
113input [5:0] meta_dmc_resp_transID;
114input [7:0] meta_dmc_resp_cmd;
115input [13:0] meta_dmc_resp_length;
116input [15:0] meta_dmc_resp_byteenable;
117input [63:0] meta_dmc_resp_address;
118input [127:0] meta_dmc_data;
119
120output dmc_meta_resp_accept;
121
122reg dmc_meta_resp_accept;
123
124// NIU Internal Response Interface
125input Port0_TXC_DMC_Resp_Accept;
126input Port1_TXC_DMC_Resp_Accept;
127input Port2_TXC_DMC_Resp_Accept;
128input Port3_TXC_DMC_Resp_Accept;
129
130output DMC_TXC_Resp_Rdy;
131output DMC_TXC_Resp_Complete;
132output DMC_TXC_Trans_Complete;
133output DMC_TXC_Resp_Data_Valid;
134output DMC_TXC_Resp_Client;
135output [1:0] DMC_TXC_Resp_Port_Num;
136output [3:0] DMC_TXC_Resp_Cmd_Status;
137output [3:0] DMC_TXC_Resp_Data_Status;
138output [4:0] DMC_TXC_Resp_DMA_Num;
139output [5:0] DMC_TXC_Resp_TransID;
140output [7:0] DMC_TXC_Resp_Cmd;
141output [13:0] DMC_TXC_Resp_Data_Length;
142output [15:0] DMC_TXC_Resp_ByteEnables;
143output [63:0] DMC_TXC_Resp_Address;
144output [127:0] DMC_TXC_Resp_Data;
145
146reg DMC_TXC_Resp_Data_Valid;
147reg [3:0] DMC_TXC_Resp_Data_Status;
148reg [13:0] DMC_TXC_Resp_Data_Length;
149reg [15:0] DMC_TXC_Resp_ByteEnables;
150reg [127:0] DMC_TXC_Resp_Data;
151
152/*--------------------------------------------------------------*/
153// Reg & Wires
154/*--------------------------------------------------------------*/
155
156/*--------------------------------------------------------------*/
157// Assigns CMD Phase
158/*--------------------------------------------------------------*/
159assign DMC_TXC_Resp_Rdy = meta_dmc_resp_ready;
160assign DMC_TXC_Resp_Complete = meta_dmc_resp_complete;
161assign DMC_TXC_Trans_Complete = meta_dmc_resp_transfer_cmpl;
162assign DMC_TXC_Resp_Client = meta_dmc_resp_client;
163assign DMC_TXC_Resp_Port_Num = meta_dmc_resp_port_num;
164assign DMC_TXC_Resp_Cmd_Status = meta_dmc_resp_cmd_status;
165assign DMC_TXC_Resp_DMA_Num = meta_dmc_resp_dma_num;
166assign DMC_TXC_Resp_TransID = meta_dmc_resp_transID;
167assign DMC_TXC_Resp_Cmd = meta_dmc_resp_cmd;
168assign DMC_TXC_Resp_Address = meta_dmc_resp_address;
169
170
171/*--------------------------------------------------------------*/
172// Logic Cmd Phase
173/*--------------------------------------------------------------*/
174always @(posedge SysClk)
175 if (!Reset_L)
176 dmc_meta_resp_accept <= #`SD 1'b0;
177 else
178 dmc_meta_resp_accept <= #`SD (Port3_TXC_DMC_Resp_Accept
179 |
180 Port2_TXC_DMC_Resp_Accept
181 |
182 Port1_TXC_DMC_Resp_Accept
183 |
184 Port0_TXC_DMC_Resp_Accept);
185
186/*--------------------------------------------------------------*/
187// Logic Data Phase
188/*--------------------------------------------------------------*/
189always @(posedge SysClk)
190 if (!Reset_L) DMC_TXC_Resp_Data_Valid <= #`SD 1'b0;
191 else DMC_TXC_Resp_Data_Valid <= #`SD meta_dmc_data_valid;
192
193always @(posedge SysClk)
194 if (!Reset_L) DMC_TXC_Resp_Data_Status <= #`SD 4'h0;
195 else DMC_TXC_Resp_Data_Status <= #`SD meta_dmc_resp_data_status;
196
197always @(posedge SysClk)
198 if (!Reset_L) DMC_TXC_Resp_Data_Length <= #`SD 14'h0;
199 else DMC_TXC_Resp_Data_Length <= #`SD meta_dmc_resp_length;
200
201always @(posedge SysClk)
202 if (!Reset_L) DMC_TXC_Resp_ByteEnables <= #`SD 16'h0;
203 else DMC_TXC_Resp_ByteEnables <= #`SD meta_dmc_resp_byteenable;
204
205always @(posedge SysClk)
206 if (!Reset_L) DMC_TXC_Resp_Data <= #`SD 128'h0;
207 else DMC_TXC_Resp_Data <= #`SD meta_dmc_data;
208
209endmodule