Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / design / sys / iop / niu / rtl / niu_txc_packetEngine.v
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1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: niu_txc_packetEngine.v
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35/*********************************************************************
36 *
37 * niu_txc_packetEngine.v
38 *
39 * NIU Txc Packet Engine (Fifo Size is abstracted out)
40 *
41 * Orignal Author (s): Rahoul Puri
42 * Modifier (s):
43 * Project (s): Neptune
44 *
45 * Copyright (c) 2004 Sun Microsystems, Inc.
46 *
47 * All Rights Reserved.
48 *
49 * This verilog model is the confidential and proprietary property of
50 * Sun Microsystems, Inc., and the possession or use of this model
51 * requires a written license from Sun Microsystems, Inc.
52 *
53 **********************************************************************/
54
55`include "timescale.v"
56
57module niu_txc_packetEngine (
58 SysClk, // System Clock
59 Reset_L, // Reset_L
60 Txc_Enabled, // NTx Enable
61 PortIndentifier,
62 EnableGMACMode, // Enable GMAC mode only
63 MAC_Enabled,
64 FlushEngine, // Flush Engine State
65 PacketAssyDead,
66 ReOrder_Error,
67
68 MAC_Req, // Request from the MAC to OPP
69 MAC_Ack, // Acknowledge Signal to the MAC from OPP
70 MAC_Tag, // End of Packet and Status Word Indicator
71 MAC_Status, // Abort Signal from OPP to Xmac
72 MAC_Abort, // Abort Signal from OPP to Xmac
73 MAC_Data, // 8 Byte Wide Data Bus from the OPP to MAC
74
75 WrPacketStuffed,
76 WrPacketRequested,
77 WrPacketXmitted,
78 WrTidsInUse,
79 WrDuplicateTid,
80 WrUnInitializedTID,
81 WrTimedoutTids,
82 WrReOrderStateLogic,
83 WrReOrderStateControl,
84 WrReOrderStateData0,
85 WrReOrderStateData1,
86 WrReOrderStateData2,
87 WrReOrderStateData3,
88 PioDataIn,
89 GatherRequestCount,
90 PacketRequestCount,
91 PktErrAbortCount,
92 ReOrdersStuffed,
93 TidsInUse,
94 DuplicateTid,
95 UnInitializedTID,
96 TimedoutTids,
97 ReOrderStateLogic,
98 ReOrderStateControl,
99 ReOrderStateData0,
100 ReOrderStateData1,
101 ReOrderStateData2,
102 ReOrderStateData3,
103
104 ClearStatistics,
105 PacketsStuffed,
106 PacketsTransmitted,
107 BytesTransmitted,
108
109 Pkt_Size_Err,
110 DMA_Pkt_Size_Err,
111 Pkt_Size_Err_Addr,
112 Nack_Pkt_Rd,
113 DMA_Nack_Pkt_Rd,
114 Nack_Pkt_Rd_Addr,
115
116 DMA0_Active,
117 DMA0_EofList,
118 DMA0_Error,
119 DMA0_CacheReady,
120 DMA0_Partial,
121 DMA0_Reset_Scheduled,
122 DMA0_GotNxtDesc,
123 DMA0_Mark,
124 DMA0_SOP,
125 DMA0_Func_Num,
126 DMA0_DescList,
127 DMA0_Length,
128 DMA0_PageHandle,
129 DMA0_Address,
130 DMA0_Inc_Head,
131 DMA0_Reset_Done,
132 DMA0_Mark_Bit,
133 DMA0_Inc_Pkt_Cnt,
134 SetGetNextDescDMA0,
135 DMA1_Active,
136 DMA1_EofList,
137 DMA1_Error,
138 DMA1_CacheReady,
139 DMA1_Partial,
140 DMA1_Reset_Scheduled,
141 DMA1_GotNxtDesc,
142 DMA1_Mark,
143 DMA1_SOP,
144 DMA1_Func_Num,
145 DMA1_DescList,
146 DMA1_Length,
147 DMA1_PageHandle,
148 DMA1_Address,
149 DMA1_Inc_Head,
150 DMA1_Reset_Done,
151 DMA1_Mark_Bit,
152 DMA1_Inc_Pkt_Cnt,
153 SetGetNextDescDMA1,
154 DMA2_Active,
155 DMA2_EofList,
156 DMA2_Error,
157 DMA2_CacheReady,
158 DMA2_Partial,
159 DMA2_Reset_Scheduled,
160 DMA2_GotNxtDesc,
161 DMA2_Mark,
162 DMA2_SOP,
163 DMA2_Func_Num,
164 DMA2_DescList,
165 DMA2_Length,
166 DMA2_PageHandle,
167 DMA2_Address,
168 DMA2_Inc_Head,
169 DMA2_Reset_Done,
170 DMA2_Mark_Bit,
171 DMA2_Inc_Pkt_Cnt,
172 SetGetNextDescDMA2,
173 DMA3_Active,
174 DMA3_EofList,
175 DMA3_Error,
176 DMA3_CacheReady,
177 DMA3_Partial,
178 DMA3_Reset_Scheduled,
179 DMA3_GotNxtDesc,
180 DMA3_Mark,
181 DMA3_SOP,
182 DMA3_Func_Num,
183 DMA3_DescList,
184 DMA3_Length,
185 DMA3_PageHandle,
186 DMA3_Address,
187 DMA3_Inc_Head,
188 DMA3_Reset_Done,
189 DMA3_Mark_Bit,
190 DMA3_Inc_Pkt_Cnt,
191 SetGetNextDescDMA3,
192 DMA4_Active,
193 DMA4_EofList,
194 DMA4_Error,
195 DMA4_CacheReady,
196 DMA4_Partial,
197 DMA4_Reset_Scheduled,
198 DMA4_GotNxtDesc,
199 DMA4_Mark,
200 DMA4_SOP,
201 DMA4_Func_Num,
202 DMA4_DescList,
203 DMA4_Length,
204 DMA4_PageHandle,
205 DMA4_Address,
206 DMA4_Inc_Head,
207 DMA4_Reset_Done,
208 DMA4_Mark_Bit,
209 DMA4_Inc_Pkt_Cnt,
210 SetGetNextDescDMA4,
211 DMA5_Active,
212 DMA5_EofList,
213 DMA5_Error,
214 DMA5_CacheReady,
215 DMA5_Partial,
216 DMA5_Reset_Scheduled,
217 DMA5_GotNxtDesc,
218 DMA5_Mark,
219 DMA5_SOP,
220 DMA5_Func_Num,
221 DMA5_DescList,
222 DMA5_Length,
223 DMA5_PageHandle,
224 DMA5_Address,
225 DMA5_Inc_Head,
226 DMA5_Reset_Done,
227 DMA5_Mark_Bit,
228 DMA5_Inc_Pkt_Cnt,
229 SetGetNextDescDMA5,
230 DMA6_Active,
231 DMA6_EofList,
232 DMA6_Error,
233 DMA6_CacheReady,
234 DMA6_Partial,
235 DMA6_Reset_Scheduled,
236 DMA6_GotNxtDesc,
237 DMA6_Mark,
238 DMA6_SOP,
239 DMA6_Func_Num,
240 DMA6_DescList,
241 DMA6_Length,
242 DMA6_PageHandle,
243 DMA6_Address,
244 DMA6_Inc_Head,
245 DMA6_Reset_Done,
246 DMA6_Mark_Bit,
247 DMA6_Inc_Pkt_Cnt,
248 SetGetNextDescDMA6,
249 DMA7_Active,
250 DMA7_EofList,
251 DMA7_Error,
252 DMA7_CacheReady,
253 DMA7_Partial,
254 DMA7_Reset_Scheduled,
255 DMA7_GotNxtDesc,
256 DMA7_Mark,
257 DMA7_SOP,
258 DMA7_Func_Num,
259 DMA7_DescList,
260 DMA7_Length,
261 DMA7_PageHandle,
262 DMA7_Address,
263 DMA7_Inc_Head,
264 DMA7_Reset_Done,
265 DMA7_Mark_Bit,
266 DMA7_Inc_Pkt_Cnt,
267 SetGetNextDescDMA7,
268 DMA8_Active,
269 DMA8_EofList,
270 DMA8_Error,
271 DMA8_CacheReady,
272 DMA8_Partial,
273 DMA8_Reset_Scheduled,
274 DMA8_GotNxtDesc,
275 DMA8_Mark,
276 DMA8_SOP,
277 DMA8_Func_Num,
278 DMA8_DescList,
279 DMA8_Length,
280 DMA8_PageHandle,
281 DMA8_Address,
282 DMA8_Inc_Head,
283 DMA8_Reset_Done,
284 DMA8_Mark_Bit,
285 DMA8_Inc_Pkt_Cnt,
286 SetGetNextDescDMA8,
287 DMA9_Active,
288 DMA9_EofList,
289 DMA9_Error,
290 DMA9_CacheReady,
291 DMA9_Partial,
292 DMA9_Reset_Scheduled,
293 DMA9_GotNxtDesc,
294 DMA9_Mark,
295 DMA9_SOP,
296 DMA9_Func_Num,
297 DMA9_DescList,
298 DMA9_Length,
299 DMA9_PageHandle,
300 DMA9_Address,
301 DMA9_Inc_Head,
302 DMA9_Reset_Done,
303 DMA9_Mark_Bit,
304 DMA9_Inc_Pkt_Cnt,
305 SetGetNextDescDMA9,
306 DMA10_Active,
307 DMA10_EofList,
308 DMA10_Error,
309 DMA10_CacheReady,
310 DMA10_Partial,
311 DMA10_Reset_Scheduled,
312 DMA10_GotNxtDesc,
313 DMA10_Mark,
314 DMA10_SOP,
315 DMA10_Func_Num,
316 DMA10_DescList,
317 DMA10_Length,
318 DMA10_PageHandle,
319 DMA10_Address,
320 DMA10_Inc_Head,
321 DMA10_Reset_Done,
322 DMA10_Mark_Bit,
323 DMA10_Inc_Pkt_Cnt,
324 SetGetNextDescDMA10,
325 DMA11_Active,
326 DMA11_EofList,
327 DMA11_Error,
328 DMA11_CacheReady,
329 DMA11_Partial,
330 DMA11_Reset_Scheduled,
331 DMA11_GotNxtDesc,
332 DMA11_Mark,
333 DMA11_SOP,
334 DMA11_Func_Num,
335 DMA11_DescList,
336 DMA11_Length,
337 DMA11_PageHandle,
338 DMA11_Address,
339 DMA11_Inc_Head,
340 DMA11_Reset_Done,
341 DMA11_Mark_Bit,
342 DMA11_Inc_Pkt_Cnt,
343 SetGetNextDescDMA11,
344 DMA12_Active,
345 DMA12_EofList,
346 DMA12_Error,
347 DMA12_CacheReady,
348 DMA12_Partial,
349 DMA12_Reset_Scheduled,
350 DMA12_GotNxtDesc,
351 DMA12_Mark,
352 DMA12_SOP,
353 DMA12_Func_Num,
354 DMA12_DescList,
355 DMA12_Length,
356 DMA12_PageHandle,
357 DMA12_Address,
358 DMA12_Inc_Head,
359 DMA12_Reset_Done,
360 DMA12_Mark_Bit,
361 DMA12_Inc_Pkt_Cnt,
362 SetGetNextDescDMA12,
363 DMA13_Active,
364 DMA13_EofList,
365 DMA13_Error,
366 DMA13_CacheReady,
367 DMA13_Partial,
368 DMA13_Reset_Scheduled,
369 DMA13_GotNxtDesc,
370 DMA13_Mark,
371 DMA13_SOP,
372 DMA13_Func_Num,
373 DMA13_DescList,
374 DMA13_Length,
375 DMA13_PageHandle,
376 DMA13_Address,
377 DMA13_Inc_Head,
378 DMA13_Reset_Done,
379 DMA13_Mark_Bit,
380 DMA13_Inc_Pkt_Cnt,
381 SetGetNextDescDMA13,
382 DMA14_Active,
383 DMA14_EofList,
384 DMA14_Error,
385 DMA14_CacheReady,
386 DMA14_Partial,
387 DMA14_Reset_Scheduled,
388 DMA14_GotNxtDesc,
389 DMA14_Mark,
390 DMA14_SOP,
391 DMA14_Func_Num,
392 DMA14_DescList,
393 DMA14_Length,
394 DMA14_PageHandle,
395 DMA14_Address,
396 DMA14_Inc_Head,
397 DMA14_Reset_Done,
398 DMA14_Mark_Bit,
399 DMA14_Inc_Pkt_Cnt,
400 SetGetNextDescDMA14,
401 DMA15_Active,
402 DMA15_EofList,
403 DMA15_Error,
404 DMA15_CacheReady,
405 DMA15_Partial,
406 DMA15_Reset_Scheduled,
407 DMA15_GotNxtDesc,
408 DMA15_Mark,
409 DMA15_SOP,
410 DMA15_Func_Num,
411 DMA15_DescList,
412 DMA15_Length,
413 DMA15_PageHandle,
414 DMA15_Address,
415 DMA15_Inc_Head,
416 DMA15_Reset_Done,
417 DMA15_Mark_Bit,
418 DMA15_Inc_Pkt_Cnt,
419 SetGetNextDescDMA15,
420 DMA16_Active,
421 DMA16_EofList,
422 DMA16_Error,
423 DMA16_CacheReady,
424 DMA16_Partial,
425 DMA16_Reset_Scheduled,
426 DMA16_GotNxtDesc,
427 DMA16_Mark,
428 DMA16_SOP,
429 DMA16_Func_Num,
430 DMA16_DescList,
431 DMA16_Length,
432 DMA16_PageHandle,
433 DMA16_Address,
434 DMA16_Inc_Head,
435 DMA16_Reset_Done,
436 DMA16_Mark_Bit,
437 DMA16_Inc_Pkt_Cnt,
438 SetGetNextDescDMA16,
439 DMA17_Active,
440 DMA17_EofList,
441 DMA17_Error,
442 DMA17_CacheReady,
443 DMA17_Partial,
444 DMA17_Reset_Scheduled,
445 DMA17_GotNxtDesc,
446 DMA17_Mark,
447 DMA17_SOP,
448 DMA17_Func_Num,
449 DMA17_DescList,
450 DMA17_Length,
451 DMA17_PageHandle,
452 DMA17_Address,
453 DMA17_Inc_Head,
454 DMA17_Reset_Done,
455 DMA17_Mark_Bit,
456 DMA17_Inc_Pkt_Cnt,
457 SetGetNextDescDMA17,
458 DMA18_Active,
459 DMA18_EofList,
460 DMA18_Error,
461 DMA18_CacheReady,
462 DMA18_Partial,
463 DMA18_Reset_Scheduled,
464 DMA18_GotNxtDesc,
465 DMA18_Mark,
466 DMA18_SOP,
467 DMA18_Func_Num,
468 DMA18_DescList,
469 DMA18_Length,
470 DMA18_PageHandle,
471 DMA18_Address,
472 DMA18_Inc_Head,
473 DMA18_Reset_Done,
474 DMA18_Mark_Bit,
475 DMA18_Inc_Pkt_Cnt,
476 SetGetNextDescDMA18,
477 DMA19_Active,
478 DMA19_EofList,
479 DMA19_Error,
480 DMA19_CacheReady,
481 DMA19_Partial,
482 DMA19_Reset_Scheduled,
483 DMA19_GotNxtDesc,
484 DMA19_Mark,
485 DMA19_SOP,
486 DMA19_Func_Num,
487 DMA19_DescList,
488 DMA19_Length,
489 DMA19_PageHandle,
490 DMA19_Address,
491 DMA19_Inc_Head,
492 DMA19_Reset_Done,
493 DMA19_Mark_Bit,
494 DMA19_Inc_Pkt_Cnt,
495 SetGetNextDescDMA19,
496 DMA20_Active,
497 DMA20_EofList,
498 DMA20_Error,
499 DMA20_CacheReady,
500 DMA20_Partial,
501 DMA20_Reset_Scheduled,
502 DMA20_GotNxtDesc,
503 DMA20_Mark,
504 DMA20_SOP,
505 DMA20_Func_Num,
506 DMA20_DescList,
507 DMA20_Length,
508 DMA20_PageHandle,
509 DMA20_Address,
510 DMA20_Inc_Head,
511 DMA20_Reset_Done,
512 DMA20_Mark_Bit,
513 DMA20_Inc_Pkt_Cnt,
514 SetGetNextDescDMA20,
515 DMA21_Active,
516 DMA21_EofList,
517 DMA21_Error,
518 DMA21_CacheReady,
519 DMA21_Partial,
520 DMA21_Reset_Scheduled,
521 DMA21_GotNxtDesc,
522 DMA21_Mark,
523 DMA21_SOP,
524 DMA21_Func_Num,
525 DMA21_DescList,
526 DMA21_Length,
527 DMA21_PageHandle,
528 DMA21_Address,
529 DMA21_Inc_Head,
530 DMA21_Reset_Done,
531 DMA21_Mark_Bit,
532 DMA21_Inc_Pkt_Cnt,
533 SetGetNextDescDMA21,
534 DMA22_Active,
535 DMA22_EofList,
536 DMA22_Error,
537 DMA22_CacheReady,
538 DMA22_Partial,
539 DMA22_Reset_Scheduled,
540 DMA22_GotNxtDesc,
541 DMA22_Mark,
542 DMA22_SOP,
543 DMA22_Func_Num,
544 DMA22_DescList,
545 DMA22_Length,
546 DMA22_PageHandle,
547 DMA22_Address,
548 DMA22_Inc_Head,
549 DMA22_Reset_Done,
550 DMA22_Mark_Bit,
551 DMA22_Inc_Pkt_Cnt,
552 SetGetNextDescDMA22,
553 DMA23_Active,
554 DMA23_EofList,
555 DMA23_Error,
556 DMA23_CacheReady,
557 DMA23_Partial,
558 DMA23_Reset_Scheduled,
559 DMA23_GotNxtDesc,
560 DMA23_Mark,
561 DMA23_SOP,
562 DMA23_Func_Num,
563 DMA23_DescList,
564 DMA23_Length,
565 DMA23_PageHandle,
566 DMA23_Address,
567 DMA23_Inc_Head,
568 DMA23_Reset_Done,
569 DMA23_Mark_Bit,
570 DMA23_Inc_Pkt_Cnt,
571 SetGetNextDescDMA23,
572 DMA0_NewMaxBurst,
573 DMA1_NewMaxBurst,
574 DMA2_NewMaxBurst,
575 DMA3_NewMaxBurst,
576 DMA4_NewMaxBurst,
577 DMA5_NewMaxBurst,
578 DMA6_NewMaxBurst,
579 DMA7_NewMaxBurst,
580 DMA8_NewMaxBurst,
581 DMA9_NewMaxBurst,
582 DMA10_NewMaxBurst,
583 DMA11_NewMaxBurst,
584 DMA12_NewMaxBurst,
585 DMA13_NewMaxBurst,
586 DMA14_NewMaxBurst,
587 DMA15_NewMaxBurst,
588 DMA16_NewMaxBurst,
589 DMA17_NewMaxBurst,
590 DMA18_NewMaxBurst,
591 DMA19_NewMaxBurst,
592 DMA20_NewMaxBurst,
593 DMA21_NewMaxBurst,
594 DMA22_NewMaxBurst,
595 DMA23_NewMaxBurst,
596 DMA0_MaxBurst,
597 DMA1_MaxBurst,
598 DMA2_MaxBurst,
599 DMA3_MaxBurst,
600 DMA4_MaxBurst,
601 DMA5_MaxBurst,
602 DMA6_MaxBurst,
603 DMA7_MaxBurst,
604 DMA8_MaxBurst,
605 DMA9_MaxBurst,
606 DMA10_MaxBurst,
607 DMA11_MaxBurst,
608 DMA12_MaxBurst,
609 DMA13_MaxBurst,
610 DMA14_MaxBurst,
611 DMA15_MaxBurst,
612 DMA16_MaxBurst,
613 DMA17_MaxBurst,
614 DMA18_MaxBurst,
615 DMA19_MaxBurst,
616 DMA20_MaxBurst,
617 DMA21_MaxBurst,
618 DMA22_MaxBurst,
619 DMA23_MaxBurst,
620 MaxReorderNumber,
621 Port_DMA_List,
622 ClrMaxBurst,
623 UpdateDMA,
624 UpdateDMALength,
625 UpdateDMANumber,
626
627 DMC_TXC_Req_Ack,
628 DMC_TXC_Req_TransID,
629
630 Port_Selected,
631 Port_Request,
632 Port_Request_Func_Num,
633 Port_Request_DMA_Num,
634 Port_Request_Length,
635 Port_Request_Address,
636
637 DMC_TXC_Resp_Rdy,
638 DMC_TXC_Resp_Complete,
639 DMC_TXC_Trans_Complete,
640 DMC_TXC_Resp_Data_Valid,
641 DMC_TXC_Resp_Client,
642 DMC_TXC_Resp_Port_Num,
643 DMC_TXC_Resp_Cmd_Status,
644 DMC_TXC_Resp_Data_Status,
645 DMC_TXC_Resp_DMA_Num,
646 DMC_TXC_Resp_TransID,
647 DMC_TXC_Resp_Cmd,
648 DMC_TXC_Resp_Data_Length,
649 DMC_TXC_Resp_ByteEnables,
650 DMC_TXC_Resp_Address,
651 DMC_TXC_Resp_Data,
652 TXC_DMC_Resp_Accept,
653
654 ReOrderFifoDataValid,
655 ReOrderUnCorrectError,
656 ReOrderEccControl,
657 PacketAssyEngineDataIn,
658 ReOrderCorruptECCSingle,
659 ReOrderCorruptECCDouble,
660 ReOrderFifoWrite,
661 ReOrderFifoReadStrobe,
662 ReOrderWritePtr,
663 ReOrderReadPtr,
664 ReOrderEngineDataOut,
665
666 StoreForwardUnCorrectError,
667 StoreForwardEccControl,
668 MacXferEngineDataIn,
669 StoreForward_CorruptECCSingle,
670 StoreForward_CorruptECCDouble,
671 StoreForwardFifoWrite,
672 StoreForwardFifoReadStrobe,
673 StoreForwardWritePtr,
674 StoreForwardReadPtr,
675 PacketAssyEngineDataOut,
676
677 LatchActiveDMA,
678 ContextActiveList,
679
680 Anchor_State,
681 ReOrder_State,
682 Pointer_State,
683 PacketAssy_State,
684 DRR_ArbState,
685 Mac_Xfer_State,
686 DataPortReq_State,
687 Sum_prt_state
688 );
689
690`include "txc_defines.h"
691
692// Global signals
693input SysClk;
694input Reset_L;
695input Txc_Enabled;
696input [1:0] PortIndentifier;
697input EnableGMACMode;
698input FlushEngine;
699
700// Data Error Interface
701output PacketAssyDead;
702output ReOrder_Error;
703
704// Mac Interface
705input MAC_Req;
706
707output MAC_Ack;
708output MAC_Tag;
709output MAC_Abort;
710output [3:0] MAC_Status;
711output [63:0] MAC_Data;
712
713// ReOrder PIO Control Registers
714input WrPacketStuffed;
715input WrPacketRequested;
716input WrPacketXmitted;
717input WrTidsInUse;
718input WrDuplicateTid;
719input WrUnInitializedTID;
720input WrTimedoutTids;
721input WrReOrderStateLogic;
722input WrReOrderStateControl;
723input WrReOrderStateData0;
724input WrReOrderStateData1;
725input WrReOrderStateData2;
726input WrReOrderStateData3;
727input [31:0] PioDataIn;
728
729output [3:0] GatherRequestCount;
730output [11:0] PacketRequestCount;
731output [15:0] PktErrAbortCount;
732output [15:0] ReOrdersStuffed;
733output [31:0] TidsInUse;
734output [31:0] DuplicateTid;
735output [31:0] UnInitializedTID;
736output [31:0] TimedoutTids;
737output [31:0] ReOrderStateLogic;
738output [31:0] ReOrderStateControl;
739output [31:0] ReOrderStateData0;
740output [31:0] ReOrderStateData1;
741output [31:0] ReOrderStateData2;
742output [31:0] ReOrderStateData3;
743
744//TXC Transaction Timeout -> TDMC Interface
745output Pkt_Size_Err;
746output [23:0] DMA_Pkt_Size_Err;
747output [43:0] Pkt_Size_Err_Addr;
748
749output Nack_Pkt_Rd;
750output [23:0] DMA_Nack_Pkt_Rd;
751output [43:0] Nack_Pkt_Rd_Addr;
752
753//TXC -> TDMC Interface
754//DMA0
755input DMA0_Active;
756input DMA0_EofList;
757input DMA0_Error;
758input DMA0_CacheReady;
759input DMA0_Partial;
760input DMA0_Reset_Scheduled;
761input DMA0_GotNxtDesc;
762input DMA0_Mark;
763input DMA0_SOP;
764input [1:0] DMA0_Func_Num;
765input [3:0] DMA0_DescList;
766input [12:0] DMA0_Length;
767input [19:0] DMA0_PageHandle;
768input [43:0] DMA0_Address;
769
770output DMA0_Inc_Head;
771output DMA0_Reset_Done;
772output DMA0_Mark_Bit;
773output DMA0_Inc_Pkt_Cnt;
774output SetGetNextDescDMA0;
775
776//DMA1
777input DMA1_Active;
778input DMA1_EofList;
779input DMA1_Error;
780input DMA1_CacheReady;
781input DMA1_Partial;
782input DMA1_Reset_Scheduled;
783input DMA1_GotNxtDesc;
784input DMA1_Mark;
785input DMA1_SOP;
786input [1:0] DMA1_Func_Num;
787input [3:0] DMA1_DescList;
788input [12:0] DMA1_Length;
789input [19:0] DMA1_PageHandle;
790input [43:0] DMA1_Address;
791
792output DMA1_Inc_Head;
793output DMA1_Reset_Done;
794output DMA1_Mark_Bit;
795output DMA1_Inc_Pkt_Cnt;
796output SetGetNextDescDMA1;
797
798//DMA2
799input DMA2_Active;
800input DMA2_EofList;
801input DMA2_Error;
802input DMA2_CacheReady;
803input DMA2_Partial;
804input DMA2_Reset_Scheduled;
805input DMA2_GotNxtDesc;
806input DMA2_Mark;
807input DMA2_SOP;
808input [1:0] DMA2_Func_Num;
809input [3:0] DMA2_DescList;
810input [12:0] DMA2_Length;
811input [19:0] DMA2_PageHandle;
812input [43:0] DMA2_Address;
813
814output DMA2_Inc_Head;
815output DMA2_Reset_Done;
816output DMA2_Mark_Bit;
817output DMA2_Inc_Pkt_Cnt;
818output SetGetNextDescDMA2;
819
820//DMA3
821input DMA3_Active;
822input DMA3_EofList;
823input DMA3_Error;
824input DMA3_CacheReady;
825input DMA3_Partial;
826input DMA3_Reset_Scheduled;
827input DMA3_GotNxtDesc;
828input DMA3_Mark;
829input DMA3_SOP;
830input [1:0] DMA3_Func_Num;
831input [3:0] DMA3_DescList;
832input [12:0] DMA3_Length;
833input [19:0] DMA3_PageHandle;
834input [43:0] DMA3_Address;
835
836output DMA3_Inc_Head;
837output DMA3_Reset_Done;
838output DMA3_Mark_Bit;
839output DMA3_Inc_Pkt_Cnt;
840output SetGetNextDescDMA3;
841
842//DMA4
843input DMA4_Active;
844input DMA4_EofList;
845input DMA4_Error;
846input DMA4_CacheReady;
847input DMA4_Partial;
848input DMA4_Reset_Scheduled;
849input DMA4_GotNxtDesc;
850input DMA4_Mark;
851input DMA4_SOP;
852input [1:0] DMA4_Func_Num;
853input [3:0] DMA4_DescList;
854input [12:0] DMA4_Length;
855input [19:0] DMA4_PageHandle;
856input [43:0] DMA4_Address;
857
858output DMA4_Inc_Head;
859output DMA4_Reset_Done;
860output DMA4_Mark_Bit;
861output DMA4_Inc_Pkt_Cnt;
862output SetGetNextDescDMA4;
863
864//DMA5
865input DMA5_Active;
866input DMA5_EofList;
867input DMA5_Error;
868input DMA5_CacheReady;
869input DMA5_Partial;
870input DMA5_Reset_Scheduled;
871input DMA5_GotNxtDesc;
872input DMA5_Mark;
873input DMA5_SOP;
874input [1:0] DMA5_Func_Num;
875input [3:0] DMA5_DescList;
876input [12:0] DMA5_Length;
877input [19:0] DMA5_PageHandle;
878input [43:0] DMA5_Address;
879
880output DMA5_Inc_Head;
881output DMA5_Reset_Done;
882output DMA5_Mark_Bit;
883output DMA5_Inc_Pkt_Cnt;
884output SetGetNextDescDMA5;
885
886//DMA6
887input DMA6_Active;
888input DMA6_EofList;
889input DMA6_Error;
890input DMA6_CacheReady;
891input DMA6_Partial;
892input DMA6_Reset_Scheduled;
893input DMA6_GotNxtDesc;
894input DMA6_Mark;
895input DMA6_SOP;
896input [1:0] DMA6_Func_Num;
897input [3:0] DMA6_DescList;
898input [12:0] DMA6_Length;
899input [19:0] DMA6_PageHandle;
900input [43:0] DMA6_Address;
901
902output DMA6_Inc_Head;
903output DMA6_Reset_Done;
904output DMA6_Mark_Bit;
905output DMA6_Inc_Pkt_Cnt;
906output SetGetNextDescDMA6;
907
908//DMA7
909input DMA7_Active;
910input DMA7_EofList;
911input DMA7_Error;
912input DMA7_CacheReady;
913input DMA7_Partial;
914input DMA7_Reset_Scheduled;
915input DMA7_GotNxtDesc;
916input DMA7_Mark;
917input DMA7_SOP;
918input [1:0] DMA7_Func_Num;
919input [3:0] DMA7_DescList;
920input [12:0] DMA7_Length;
921input [19:0] DMA7_PageHandle;
922input [43:0] DMA7_Address;
923
924output DMA7_Inc_Head;
925output DMA7_Reset_Done;
926output DMA7_Mark_Bit;
927output DMA7_Inc_Pkt_Cnt;
928output SetGetNextDescDMA7;
929
930//DMA8
931input DMA8_Active;
932input DMA8_EofList;
933input DMA8_Error;
934input DMA8_CacheReady;
935input DMA8_Partial;
936input DMA8_Reset_Scheduled;
937input DMA8_GotNxtDesc;
938input DMA8_Mark;
939input DMA8_SOP;
940input [1:0] DMA8_Func_Num;
941input [3:0] DMA8_DescList;
942input [12:0] DMA8_Length;
943input [19:0] DMA8_PageHandle;
944input [43:0] DMA8_Address;
945
946output DMA8_Inc_Head;
947output DMA8_Reset_Done;
948output DMA8_Mark_Bit;
949output DMA8_Inc_Pkt_Cnt;
950output SetGetNextDescDMA8;
951
952//DMA9
953input DMA9_Active;
954input DMA9_EofList;
955input DMA9_Error;
956input DMA9_CacheReady;
957input DMA9_Partial;
958input DMA9_Reset_Scheduled;
959input DMA9_GotNxtDesc;
960input DMA9_Mark;
961input DMA9_SOP;
962input [1:0] DMA9_Func_Num;
963input [3:0] DMA9_DescList;
964input [12:0] DMA9_Length;
965input [19:0] DMA9_PageHandle;
966input [43:0] DMA9_Address;
967
968output DMA9_Inc_Head;
969output DMA9_Reset_Done;
970output DMA9_Mark_Bit;
971output DMA9_Inc_Pkt_Cnt;
972output SetGetNextDescDMA9;
973
974//DMA10
975input DMA10_Active;
976input DMA10_EofList;
977input DMA10_Error;
978input DMA10_CacheReady;
979input DMA10_Partial;
980input DMA10_Reset_Scheduled;
981input DMA10_GotNxtDesc;
982input DMA10_Mark;
983input DMA10_SOP;
984input [1:0] DMA10_Func_Num;
985input [3:0] DMA10_DescList;
986input [12:0] DMA10_Length;
987input [19:0] DMA10_PageHandle;
988input [43:0] DMA10_Address;
989
990output DMA10_Inc_Head;
991output DMA10_Reset_Done;
992output DMA10_Mark_Bit;
993output DMA10_Inc_Pkt_Cnt;
994output SetGetNextDescDMA10;
995
996//DMA11
997input DMA11_Active;
998input DMA11_EofList;
999input DMA11_Error;
1000input DMA11_CacheReady;
1001input DMA11_Partial;
1002input DMA11_Reset_Scheduled;
1003input DMA11_GotNxtDesc;
1004input DMA11_Mark;
1005input DMA11_SOP;
1006input [1:0] DMA11_Func_Num;
1007input [3:0] DMA11_DescList;
1008input [12:0] DMA11_Length;
1009input [19:0] DMA11_PageHandle;
1010input [43:0] DMA11_Address;
1011
1012output DMA11_Inc_Head;
1013output DMA11_Reset_Done;
1014output DMA11_Mark_Bit;
1015output DMA11_Inc_Pkt_Cnt;
1016output SetGetNextDescDMA11;
1017
1018//DMA12
1019input DMA12_Active;
1020input DMA12_EofList;
1021input DMA12_Error;
1022input DMA12_CacheReady;
1023input DMA12_Partial;
1024input DMA12_Reset_Scheduled;
1025input DMA12_GotNxtDesc;
1026input DMA12_Mark;
1027input DMA12_SOP;
1028input [1:0] DMA12_Func_Num;
1029input [3:0] DMA12_DescList;
1030input [12:0] DMA12_Length;
1031input [19:0] DMA12_PageHandle;
1032input [43:0] DMA12_Address;
1033
1034output DMA12_Inc_Head;
1035output DMA12_Reset_Done;
1036output DMA12_Mark_Bit;
1037output DMA12_Inc_Pkt_Cnt;
1038output SetGetNextDescDMA12;
1039
1040//DMA13
1041input DMA13_Active;
1042input DMA13_EofList;
1043input DMA13_Error;
1044input DMA13_CacheReady;
1045input DMA13_Partial;
1046input DMA13_Reset_Scheduled;
1047input DMA13_GotNxtDesc;
1048input DMA13_Mark;
1049input DMA13_SOP;
1050input [1:0] DMA13_Func_Num;
1051input [3:0] DMA13_DescList;
1052input [12:0] DMA13_Length;
1053input [19:0] DMA13_PageHandle;
1054input [43:0] DMA13_Address;
1055
1056output DMA13_Inc_Head;
1057output DMA13_Reset_Done;
1058output DMA13_Mark_Bit;
1059output DMA13_Inc_Pkt_Cnt;
1060output SetGetNextDescDMA13;
1061
1062//DMA14
1063input DMA14_Active;
1064input DMA14_EofList;
1065input DMA14_Error;
1066input DMA14_CacheReady;
1067input DMA14_Partial;
1068input DMA14_Reset_Scheduled;
1069input DMA14_GotNxtDesc;
1070input DMA14_Mark;
1071input DMA14_SOP;
1072input [1:0] DMA14_Func_Num;
1073input [3:0] DMA14_DescList;
1074input [12:0] DMA14_Length;
1075input [19:0] DMA14_PageHandle;
1076input [43:0] DMA14_Address;
1077
1078output DMA14_Inc_Head;
1079output DMA14_Reset_Done;
1080output DMA14_Mark_Bit;
1081output DMA14_Inc_Pkt_Cnt;
1082output SetGetNextDescDMA14;
1083
1084//DMA15
1085input DMA15_Active;
1086input DMA15_EofList;
1087input DMA15_Error;
1088input DMA15_CacheReady;
1089input DMA15_Partial;
1090input DMA15_Reset_Scheduled;
1091input DMA15_GotNxtDesc;
1092input DMA15_Mark;
1093input DMA15_SOP;
1094input [1:0] DMA15_Func_Num;
1095input [3:0] DMA15_DescList;
1096input [12:0] DMA15_Length;
1097input [19:0] DMA15_PageHandle;
1098input [43:0] DMA15_Address;
1099
1100output DMA15_Inc_Head;
1101output DMA15_Reset_Done;
1102output DMA15_Mark_Bit;
1103output DMA15_Inc_Pkt_Cnt;
1104output SetGetNextDescDMA15;
1105
1106//DMA16
1107input DMA16_Active;
1108input DMA16_EofList;
1109input DMA16_Error;
1110input DMA16_CacheReady;
1111input DMA16_Partial;
1112input DMA16_Reset_Scheduled;
1113input DMA16_GotNxtDesc;
1114input DMA16_Mark;
1115input DMA16_SOP;
1116input [1:0] DMA16_Func_Num;
1117input [3:0] DMA16_DescList;
1118input [12:0] DMA16_Length;
1119input [19:0] DMA16_PageHandle;
1120input [43:0] DMA16_Address;
1121
1122output DMA16_Inc_Head;
1123output DMA16_Reset_Done;
1124output DMA16_Mark_Bit;
1125output DMA16_Inc_Pkt_Cnt;
1126output SetGetNextDescDMA16;
1127
1128//DMA17
1129input DMA17_Active;
1130input DMA17_EofList;
1131input DMA17_Error;
1132input DMA17_CacheReady;
1133input DMA17_Partial;
1134input DMA17_Reset_Scheduled;
1135input DMA17_GotNxtDesc;
1136input DMA17_Mark;
1137input DMA17_SOP;
1138input [1:0] DMA17_Func_Num;
1139input [3:0] DMA17_DescList;
1140input [12:0] DMA17_Length;
1141input [19:0] DMA17_PageHandle;
1142input [43:0] DMA17_Address;
1143
1144output DMA17_Inc_Head;
1145output DMA17_Reset_Done;
1146output DMA17_Mark_Bit;
1147output DMA17_Inc_Pkt_Cnt;
1148output SetGetNextDescDMA17;
1149
1150//DMA18
1151input DMA18_Active;
1152input DMA18_EofList;
1153input DMA18_Error;
1154input DMA18_CacheReady;
1155input DMA18_Partial;
1156input DMA18_Reset_Scheduled;
1157input DMA18_GotNxtDesc;
1158input DMA18_Mark;
1159input DMA18_SOP;
1160input [1:0] DMA18_Func_Num;
1161input [3:0] DMA18_DescList;
1162input [12:0] DMA18_Length;
1163input [19:0] DMA18_PageHandle;
1164input [43:0] DMA18_Address;
1165
1166output DMA18_Inc_Head;
1167output DMA18_Reset_Done;
1168output DMA18_Mark_Bit;
1169output DMA18_Inc_Pkt_Cnt;
1170output SetGetNextDescDMA18;
1171
1172//DMA19
1173input DMA19_Active;
1174input DMA19_EofList;
1175input DMA19_Error;
1176input DMA19_CacheReady;
1177input DMA19_Partial;
1178input DMA19_Reset_Scheduled;
1179input DMA19_GotNxtDesc;
1180input DMA19_Mark;
1181input DMA19_SOP;
1182input [1:0] DMA19_Func_Num;
1183input [3:0] DMA19_DescList;
1184input [12:0] DMA19_Length;
1185input [19:0] DMA19_PageHandle;
1186input [43:0] DMA19_Address;
1187
1188output DMA19_Inc_Head;
1189output DMA19_Reset_Done;
1190output DMA19_Mark_Bit;
1191output DMA19_Inc_Pkt_Cnt;
1192output SetGetNextDescDMA19;
1193
1194//DMA20
1195input DMA20_Active;
1196input DMA20_EofList;
1197input DMA20_Error;
1198input DMA20_CacheReady;
1199input DMA20_Partial;
1200input DMA20_Reset_Scheduled;
1201input DMA20_GotNxtDesc;
1202input DMA20_Mark;
1203input DMA20_SOP;
1204input [1:0] DMA20_Func_Num;
1205input [3:0] DMA20_DescList;
1206input [12:0] DMA20_Length;
1207input [19:0] DMA20_PageHandle;
1208input [43:0] DMA20_Address;
1209
1210output DMA20_Inc_Head;
1211output DMA20_Reset_Done;
1212output DMA20_Mark_Bit;
1213output DMA20_Inc_Pkt_Cnt;
1214output SetGetNextDescDMA20;
1215
1216//DMA21
1217input DMA21_Active;
1218input DMA21_EofList;
1219input DMA21_Error;
1220input DMA21_CacheReady;
1221input DMA21_Partial;
1222input DMA21_Reset_Scheduled;
1223input DMA21_GotNxtDesc;
1224input DMA21_Mark;
1225input DMA21_SOP;
1226input [1:0] DMA21_Func_Num;
1227input [3:0] DMA21_DescList;
1228input [12:0] DMA21_Length;
1229input [19:0] DMA21_PageHandle;
1230input [43:0] DMA21_Address;
1231
1232output DMA21_Inc_Head;
1233output DMA21_Reset_Done;
1234output DMA21_Mark_Bit;
1235output DMA21_Inc_Pkt_Cnt;
1236output SetGetNextDescDMA21;
1237
1238//DMA22
1239input DMA22_Active;
1240input DMA22_EofList;
1241input DMA22_Error;
1242input DMA22_CacheReady;
1243input DMA22_Partial;
1244input DMA22_Reset_Scheduled;
1245input DMA22_GotNxtDesc;
1246input DMA22_Mark;
1247input DMA22_SOP;
1248input [1:0] DMA22_Func_Num;
1249input [3:0] DMA22_DescList;
1250input [12:0] DMA22_Length;
1251input [19:0] DMA22_PageHandle;
1252input [43:0] DMA22_Address;
1253
1254output DMA22_Inc_Head;
1255output DMA22_Reset_Done;
1256output DMA22_Mark_Bit;
1257output DMA22_Inc_Pkt_Cnt;
1258output SetGetNextDescDMA22;
1259
1260//DMA23
1261input DMA23_Active;
1262input DMA23_EofList;
1263input DMA23_Error;
1264input DMA23_CacheReady;
1265input DMA23_Partial;
1266input DMA23_Reset_Scheduled;
1267input DMA23_GotNxtDesc;
1268input DMA23_Mark;
1269input DMA23_SOP;
1270input [1:0] DMA23_Func_Num;
1271input [3:0] DMA23_DescList;
1272input [12:0] DMA23_Length;
1273input [19:0] DMA23_PageHandle;
1274input [43:0] DMA23_Address;
1275
1276output DMA23_Inc_Head;
1277output DMA23_Reset_Done;
1278output DMA23_Mark_Bit;
1279output DMA23_Inc_Pkt_Cnt;
1280output SetGetNextDescDMA23;
1281
1282// Diag Control Regs Interface
1283input MAC_Enabled;
1284input ClearStatistics;
1285
1286output [15:0] PacketsStuffed;
1287output [15:0] PacketsTransmitted;
1288output [15:0] BytesTransmitted;
1289
1290// DMA Control Registers
1291input DMA0_NewMaxBurst;
1292input DMA1_NewMaxBurst;
1293input DMA2_NewMaxBurst;
1294input DMA3_NewMaxBurst;
1295input DMA4_NewMaxBurst;
1296input DMA5_NewMaxBurst;
1297input DMA6_NewMaxBurst;
1298input DMA7_NewMaxBurst;
1299input DMA8_NewMaxBurst;
1300input DMA9_NewMaxBurst;
1301input DMA10_NewMaxBurst;
1302input DMA11_NewMaxBurst;
1303input DMA12_NewMaxBurst;
1304input DMA13_NewMaxBurst;
1305input DMA14_NewMaxBurst;
1306input DMA15_NewMaxBurst;
1307input DMA16_NewMaxBurst;
1308input DMA17_NewMaxBurst;
1309input DMA18_NewMaxBurst;
1310input DMA19_NewMaxBurst;
1311input DMA20_NewMaxBurst;
1312input DMA21_NewMaxBurst;
1313input DMA22_NewMaxBurst;
1314input DMA23_NewMaxBurst;
1315input [19:0] DMA0_MaxBurst;
1316input [19:0] DMA1_MaxBurst;
1317input [19:0] DMA2_MaxBurst;
1318input [19:0] DMA3_MaxBurst;
1319input [19:0] DMA4_MaxBurst;
1320input [19:0] DMA5_MaxBurst;
1321input [19:0] DMA6_MaxBurst;
1322input [19:0] DMA7_MaxBurst;
1323input [19:0] DMA8_MaxBurst;
1324input [19:0] DMA9_MaxBurst;
1325input [19:0] DMA10_MaxBurst;
1326input [19:0] DMA11_MaxBurst;
1327input [19:0] DMA12_MaxBurst;
1328input [19:0] DMA13_MaxBurst;
1329input [19:0] DMA14_MaxBurst;
1330input [19:0] DMA15_MaxBurst;
1331input [19:0] DMA16_MaxBurst;
1332input [19:0] DMA17_MaxBurst;
1333input [19:0] DMA18_MaxBurst;
1334input [19:0] DMA19_MaxBurst;
1335input [19:0] DMA20_MaxBurst;
1336input [19:0] DMA21_MaxBurst;
1337input [19:0] DMA22_MaxBurst;
1338input [19:0] DMA23_MaxBurst;
1339
1340input [3:0] MaxReorderNumber;
1341input [23:0] Port_DMA_List;
1342
1343output ClrMaxBurst;
1344output UpdateDMA;
1345output [13:0] UpdateDMALength;
1346output [23:0] UpdateDMANumber;
1347
1348// Data Fetch Interface
1349wire dRR_PacketDone;
1350wire [15:0] dRR_PacketByteCount;
1351
1352wire dRR_Arb_Valid;
1353wire [4:0] dRR_NextDMAChannel;
1354
1355// Meta Bus
1356input DMC_TXC_Req_Ack;
1357input [5:0] DMC_TXC_Req_TransID;
1358
1359// Data Fetch Interface
1360input Port_Selected;
1361
1362output Port_Request;
1363output [1:0] Port_Request_Func_Num;
1364output [4:0] Port_Request_DMA_Num;
1365output [12:0] Port_Request_Length;
1366output [63:0] Port_Request_Address;
1367
1368// Tx DMA Response Interface
1369input DMC_TXC_Resp_Rdy;
1370input DMC_TXC_Resp_Complete;
1371input DMC_TXC_Trans_Complete;
1372input DMC_TXC_Resp_Data_Valid;
1373input DMC_TXC_Resp_Client;
1374input [1:0] DMC_TXC_Resp_Port_Num;
1375input [3:0] DMC_TXC_Resp_Cmd_Status;
1376input [3:0] DMC_TXC_Resp_Data_Status;
1377input [4:0] DMC_TXC_Resp_DMA_Num;
1378input [5:0] DMC_TXC_Resp_TransID;
1379input [7:0] DMC_TXC_Resp_Cmd;
1380input [13:0] DMC_TXC_Resp_Data_Length;
1381input [15:0] DMC_TXC_Resp_ByteEnables;
1382input [63:0] DMC_TXC_Resp_Address;
1383input [127:0] DMC_TXC_Resp_Data;
1384
1385output TXC_DMC_Resp_Accept;
1386
1387// Re-Order Fifo Interface
1388input ReOrderFifoDataValid;
1389input ReOrderUnCorrectError;
1390input [31:0] ReOrderEccControl;
1391input [135:0] PacketAssyEngineDataIn;
1392
1393output ReOrderCorruptECCSingle;
1394output ReOrderCorruptECCDouble;
1395output ReOrderFifoWrite;
1396output ReOrderFifoReadStrobe;
1397output [9:0] ReOrderWritePtr;
1398output [9:0] ReOrderReadPtr;
1399output [135:0] ReOrderEngineDataOut;
1400
1401// Store & Forward Fifo Interface
1402input StoreForwardUnCorrectError;
1403input [31:0] StoreForwardEccControl;
1404input [135:0] MacXferEngineDataIn;
1405
1406output StoreForward_CorruptECCSingle;
1407output StoreForward_CorruptECCDouble;
1408output StoreForwardFifoWrite;
1409output StoreForwardFifoReadStrobe;
1410output [9:0] StoreForwardWritePtr;
1411output [9:0] StoreForwardReadPtr;
1412output [135:0] PacketAssyEngineDataOut;
1413
1414// Debug Block
1415output LatchActiveDMA;
1416output [23:0] ContextActiveList;
1417
1418// State Machine
1419output [3:0] Anchor_State;
1420output [3:0] ReOrder_State;
1421output [3:0] Pointer_State;
1422output [3:0] PacketAssy_State;
1423output [3:0] DRR_ArbState;
1424output [3:0] Mac_Xfer_State;
1425output [3:0] DataPortReq_State;
1426output [31:0] Sum_prt_state;
1427
1428/*--------------------------------------------------------------*/
1429// Wires
1430/*--------------------------------------------------------------*/
1431wire anchor_LoadTID;
1432wire req_Anchor;
1433wire anchor_MarkBit;
1434wire anchor_SopBit;
1435wire anchor_GatherLast;
1436wire anchor_Done;
1437wire reOrderFifoRead;
1438wire reOrderFifoEmpty;
1439wire reOrderFifoAlmostEmpty;
1440wire startTCPchecksum;
1441wire checksumPacketDone;
1442wire checkSumValid;
1443wire storeForwardFifoEmpty;
1444wire storeForwardFifoRead;
1445wire [1:0] packetType;
1446wire [1:0] layer3Version;
1447wire [1:0] layer3Start;
1448wire [3:0] iPv4IPHeaderLen;
1449wire [4:0] anchor_DMA;
1450wire [5:0] anchor_TransID;
1451wire [12:0] anchor_Length;
1452wire [15:0] checksumValue;
1453wire [63:0] anchor_Address;
1454
1455/*--------------------------------------------------------------*/
1456// Assigns
1457/*--------------------------------------------------------------*/
1458
1459/*--------------------------------------------------------------*/
1460// Overload Parameters
1461/*--------------------------------------------------------------*/
1462parameter REORDER_SIZE = 16,
1463 REORDER_PTR = 4;
1464
1465/*--------------------------------------------------------------*/
1466// Module Instantiations
1467/*--------------------------------------------------------------*/
1468
1469niu_txc_drr_engine niu_txc_drr_engine (
1470 .SysClk (SysClk),
1471 .Reset_L (Reset_L),
1472 .Txc_Enabled (Txc_Enabled),
1473 .MAC_Enabled (MAC_Enabled),
1474 .FlushEngine (FlushEngine),
1475 .DMA0_Active (DMA0_Active),
1476 .DMA0_Error (DMA0_Error),
1477 .DMA0_EofList (DMA0_EofList),
1478 .DMA0_CacheReady (DMA0_CacheReady),
1479 .DMA0_Partial (DMA0_Partial),
1480 .DMA0_Reset_Scheduled (DMA0_Reset_Scheduled),
1481 .DMA0_Reset_Done (DMA0_Reset_Done),
1482 .DMA1_Active (DMA1_Active),
1483 .DMA1_Error (DMA1_Error),
1484 .DMA1_EofList (DMA1_EofList),
1485 .DMA1_CacheReady (DMA1_CacheReady),
1486 .DMA1_Partial (DMA1_Partial),
1487 .DMA1_Reset_Scheduled (DMA1_Reset_Scheduled),
1488 .DMA1_Reset_Done (DMA1_Reset_Done),
1489 .DMA2_Active (DMA2_Active),
1490 .DMA2_Error (DMA2_Error),
1491 .DMA2_EofList (DMA2_EofList),
1492 .DMA2_CacheReady (DMA2_CacheReady),
1493 .DMA2_Partial (DMA2_Partial),
1494 .DMA2_Reset_Scheduled (DMA2_Reset_Scheduled),
1495 .DMA2_Reset_Done (DMA2_Reset_Done),
1496 .DMA3_Active (DMA3_Active),
1497 .DMA3_Error (DMA3_Error),
1498 .DMA3_EofList (DMA3_EofList),
1499 .DMA3_CacheReady (DMA3_CacheReady),
1500 .DMA3_Partial (DMA3_Partial),
1501 .DMA3_Reset_Scheduled (DMA3_Reset_Scheduled),
1502 .DMA3_Reset_Done (DMA3_Reset_Done),
1503 .DMA4_Active (DMA4_Active),
1504 .DMA4_Error (DMA4_Error),
1505 .DMA4_EofList (DMA4_EofList),
1506 .DMA4_CacheReady (DMA4_CacheReady),
1507 .DMA4_Partial (DMA4_Partial),
1508 .DMA4_Reset_Scheduled (DMA4_Reset_Scheduled),
1509 .DMA4_Reset_Done (DMA4_Reset_Done),
1510 .DMA5_Active (DMA5_Active),
1511 .DMA5_Error (DMA5_Error),
1512 .DMA5_EofList (DMA5_EofList),
1513 .DMA5_CacheReady (DMA5_CacheReady),
1514 .DMA5_Partial (DMA5_Partial),
1515 .DMA5_Reset_Scheduled (DMA5_Reset_Scheduled),
1516 .DMA5_Reset_Done (DMA5_Reset_Done),
1517 .DMA6_Active (DMA6_Active),
1518 .DMA6_Error (DMA6_Error),
1519 .DMA6_EofList (DMA6_EofList),
1520 .DMA6_CacheReady (DMA6_CacheReady),
1521 .DMA6_Partial (DMA6_Partial),
1522 .DMA6_Reset_Scheduled (DMA6_Reset_Scheduled),
1523 .DMA6_Reset_Done (DMA6_Reset_Done),
1524 .DMA7_Active (DMA7_Active),
1525 .DMA7_Error (DMA7_Error),
1526 .DMA7_EofList (DMA7_EofList),
1527 .DMA7_CacheReady (DMA7_CacheReady),
1528 .DMA7_Partial (DMA7_Partial),
1529 .DMA7_Reset_Scheduled (DMA7_Reset_Scheduled),
1530 .DMA7_Reset_Done (DMA7_Reset_Done),
1531 .DMA8_Active (DMA8_Active),
1532 .DMA8_Error (DMA8_Error),
1533 .DMA8_EofList (DMA8_EofList),
1534 .DMA8_CacheReady (DMA8_CacheReady),
1535 .DMA8_Partial (DMA8_Partial),
1536 .DMA8_Reset_Scheduled (DMA8_Reset_Scheduled),
1537 .DMA8_Reset_Done (DMA8_Reset_Done),
1538 .DMA9_Active (DMA9_Active),
1539 .DMA9_Error (DMA9_Error),
1540 .DMA9_EofList (DMA9_EofList),
1541 .DMA9_CacheReady (DMA9_CacheReady),
1542 .DMA9_Partial (DMA9_Partial),
1543 .DMA9_Reset_Scheduled (DMA9_Reset_Scheduled),
1544 .DMA9_Reset_Done (DMA9_Reset_Done),
1545 .DMA10_Active (DMA10_Active),
1546 .DMA10_Error (DMA10_Error),
1547 .DMA10_EofList (DMA10_EofList),
1548 .DMA10_CacheReady (DMA10_CacheReady),
1549 .DMA10_Partial (DMA10_Partial),
1550 .DMA10_Reset_Scheduled (DMA10_Reset_Scheduled),
1551 .DMA10_Reset_Done (DMA10_Reset_Done),
1552 .DMA11_Active (DMA11_Active),
1553 .DMA11_Error (DMA11_Error),
1554 .DMA11_EofList (DMA11_EofList),
1555 .DMA11_CacheReady (DMA11_CacheReady),
1556 .DMA11_Partial (DMA11_Partial),
1557 .DMA11_Reset_Scheduled (DMA11_Reset_Scheduled),
1558 .DMA11_Reset_Done (DMA11_Reset_Done),
1559 .DMA12_Active (DMA12_Active),
1560 .DMA12_Error (DMA12_Error),
1561 .DMA12_EofList (DMA12_EofList),
1562 .DMA12_CacheReady (DMA12_CacheReady),
1563 .DMA12_Partial (DMA12_Partial),
1564 .DMA12_Reset_Scheduled (DMA12_Reset_Scheduled),
1565 .DMA12_Reset_Done (DMA12_Reset_Done),
1566 .DMA13_Active (DMA13_Active),
1567 .DMA13_Error (DMA13_Error),
1568 .DMA13_EofList (DMA13_EofList),
1569 .DMA13_CacheReady (DMA13_CacheReady),
1570 .DMA13_Partial (DMA13_Partial),
1571 .DMA13_Reset_Scheduled (DMA13_Reset_Scheduled),
1572 .DMA13_Reset_Done (DMA13_Reset_Done),
1573 .DMA14_Active (DMA14_Active),
1574 .DMA14_Error (DMA14_Error),
1575 .DMA14_EofList (DMA14_EofList),
1576 .DMA14_CacheReady (DMA14_CacheReady),
1577 .DMA14_Partial (DMA14_Partial),
1578 .DMA14_Reset_Scheduled (DMA14_Reset_Scheduled),
1579 .DMA14_Reset_Done (DMA14_Reset_Done),
1580 .DMA15_Active (DMA15_Active),
1581 .DMA15_Error (DMA15_Error),
1582 .DMA15_EofList (DMA15_EofList),
1583 .DMA15_CacheReady (DMA15_CacheReady),
1584 .DMA15_Partial (DMA15_Partial),
1585 .DMA15_Reset_Scheduled (DMA15_Reset_Scheduled),
1586 .DMA15_Reset_Done (DMA15_Reset_Done),
1587 .DMA16_Active (DMA16_Active),
1588 .DMA16_Error (DMA16_Error),
1589 .DMA16_EofList (DMA16_EofList),
1590 .DMA16_CacheReady (DMA16_CacheReady),
1591 .DMA16_Partial (DMA16_Partial),
1592 .DMA16_Reset_Scheduled (DMA16_Reset_Scheduled),
1593 .DMA16_Reset_Done (DMA16_Reset_Done),
1594 .DMA17_Active (DMA17_Active),
1595 .DMA17_Error (DMA17_Error),
1596 .DMA17_EofList (DMA17_EofList),
1597 .DMA17_CacheReady (DMA17_CacheReady),
1598 .DMA17_Partial (DMA17_Partial),
1599 .DMA17_Reset_Scheduled (DMA17_Reset_Scheduled),
1600 .DMA17_Reset_Done (DMA17_Reset_Done),
1601 .DMA18_Active (DMA18_Active),
1602 .DMA18_Error (DMA18_Error),
1603 .DMA18_EofList (DMA18_EofList),
1604 .DMA18_CacheReady (DMA18_CacheReady),
1605 .DMA18_Partial (DMA18_Partial),
1606 .DMA18_Reset_Scheduled (DMA18_Reset_Scheduled),
1607 .DMA18_Reset_Done (DMA18_Reset_Done),
1608 .DMA19_Active (DMA19_Active),
1609 .DMA19_Error (DMA19_Error),
1610 .DMA19_EofList (DMA19_EofList),
1611 .DMA19_CacheReady (DMA19_CacheReady),
1612 .DMA19_Partial (DMA19_Partial),
1613 .DMA19_Reset_Scheduled (DMA19_Reset_Scheduled),
1614 .DMA19_Reset_Done (DMA19_Reset_Done),
1615 .DMA20_Active (DMA20_Active),
1616 .DMA20_Error (DMA20_Error),
1617 .DMA20_EofList (DMA20_EofList),
1618 .DMA20_CacheReady (DMA20_CacheReady),
1619 .DMA20_Partial (DMA20_Partial),
1620 .DMA20_Reset_Scheduled (DMA20_Reset_Scheduled),
1621 .DMA20_Reset_Done (DMA20_Reset_Done),
1622 .DMA21_Active (DMA21_Active),
1623 .DMA21_Error (DMA21_Error),
1624 .DMA21_EofList (DMA21_EofList),
1625 .DMA21_CacheReady (DMA21_CacheReady),
1626 .DMA21_Partial (DMA21_Partial),
1627 .DMA21_Reset_Scheduled (DMA21_Reset_Scheduled),
1628 .DMA21_Reset_Done (DMA21_Reset_Done),
1629 .DMA22_Active (DMA22_Active),
1630 .DMA22_Error (DMA22_Error),
1631 .DMA22_EofList (DMA22_EofList),
1632 .DMA22_CacheReady (DMA22_CacheReady),
1633 .DMA22_Partial (DMA22_Partial),
1634 .DMA22_Reset_Scheduled (DMA22_Reset_Scheduled),
1635 .DMA22_Reset_Done (DMA22_Reset_Done),
1636 .DMA23_Active (DMA23_Active),
1637 .DMA23_Error (DMA23_Error),
1638 .DMA23_EofList (DMA23_EofList),
1639 .DMA23_CacheReady (DMA23_CacheReady),
1640 .DMA23_Partial (DMA23_Partial),
1641 .DMA23_Reset_Scheduled (DMA23_Reset_Scheduled),
1642 .DMA23_Reset_Done (DMA23_Reset_Done),
1643 .DMA0_NewMaxBurst (DMA0_NewMaxBurst),
1644 .DMA1_NewMaxBurst (DMA1_NewMaxBurst),
1645 .DMA2_NewMaxBurst (DMA2_NewMaxBurst),
1646 .DMA3_NewMaxBurst (DMA3_NewMaxBurst),
1647 .DMA4_NewMaxBurst (DMA4_NewMaxBurst),
1648 .DMA5_NewMaxBurst (DMA5_NewMaxBurst),
1649 .DMA6_NewMaxBurst (DMA6_NewMaxBurst),
1650 .DMA7_NewMaxBurst (DMA7_NewMaxBurst),
1651 .DMA8_NewMaxBurst (DMA8_NewMaxBurst),
1652 .DMA9_NewMaxBurst (DMA9_NewMaxBurst),
1653 .DMA10_NewMaxBurst (DMA10_NewMaxBurst),
1654 .DMA11_NewMaxBurst (DMA11_NewMaxBurst),
1655 .DMA12_NewMaxBurst (DMA12_NewMaxBurst),
1656 .DMA13_NewMaxBurst (DMA13_NewMaxBurst),
1657 .DMA14_NewMaxBurst (DMA14_NewMaxBurst),
1658 .DMA15_NewMaxBurst (DMA15_NewMaxBurst),
1659 .DMA16_NewMaxBurst (DMA16_NewMaxBurst),
1660 .DMA17_NewMaxBurst (DMA17_NewMaxBurst),
1661 .DMA18_NewMaxBurst (DMA18_NewMaxBurst),
1662 .DMA19_NewMaxBurst (DMA19_NewMaxBurst),
1663 .DMA20_NewMaxBurst (DMA20_NewMaxBurst),
1664 .DMA21_NewMaxBurst (DMA21_NewMaxBurst),
1665 .DMA22_NewMaxBurst (DMA22_NewMaxBurst),
1666 .DMA23_NewMaxBurst (DMA23_NewMaxBurst),
1667 .DMA0_MaxBurst (DMA0_MaxBurst),
1668 .DMA1_MaxBurst (DMA1_MaxBurst),
1669 .DMA2_MaxBurst (DMA2_MaxBurst),
1670 .DMA3_MaxBurst (DMA3_MaxBurst),
1671 .DMA4_MaxBurst (DMA4_MaxBurst),
1672 .DMA5_MaxBurst (DMA5_MaxBurst),
1673 .DMA6_MaxBurst (DMA6_MaxBurst),
1674 .DMA7_MaxBurst (DMA7_MaxBurst),
1675 .DMA8_MaxBurst (DMA8_MaxBurst),
1676 .DMA9_MaxBurst (DMA9_MaxBurst),
1677 .DMA10_MaxBurst (DMA10_MaxBurst),
1678 .DMA11_MaxBurst (DMA11_MaxBurst),
1679 .DMA12_MaxBurst (DMA12_MaxBurst),
1680 .DMA13_MaxBurst (DMA13_MaxBurst),
1681 .DMA14_MaxBurst (DMA14_MaxBurst),
1682 .DMA15_MaxBurst (DMA15_MaxBurst),
1683 .DMA16_MaxBurst (DMA16_MaxBurst),
1684 .DMA17_MaxBurst (DMA17_MaxBurst),
1685 .DMA18_MaxBurst (DMA18_MaxBurst),
1686 .DMA19_MaxBurst (DMA19_MaxBurst),
1687 .DMA20_MaxBurst (DMA20_MaxBurst),
1688 .DMA21_MaxBurst (DMA21_MaxBurst),
1689 .DMA22_MaxBurst (DMA22_MaxBurst),
1690 .DMA23_MaxBurst (DMA23_MaxBurst),
1691 .Port_DMA_List (Port_DMA_List),
1692 .ClrMaxBurst (ClrMaxBurst),
1693
1694 .DRR_PacketDone (dRR_PacketDone),
1695 .DRR_PacketByteCount (dRR_PacketByteCount),
1696 .DRR_Arb_Valid (dRR_Arb_Valid),
1697 .DRR_NextDMAChannel (dRR_NextDMAChannel),
1698
1699 .LatchActiveDMA (LatchActiveDMA),
1700 .ContextActiveList (ContextActiveList),
1701
1702 .DRR_ArbState (DRR_ArbState)
1703 );
1704
1705
1706niu_txc_portRequest niu_txc_portRequest (
1707 .SysClk (SysClk),
1708 .Reset_L (Reset_L),
1709 .Txc_Enabled (Txc_Enabled),
1710
1711 .Port_Enabled (MAC_Enabled),
1712
1713 .Pkt_Size_Err (Pkt_Size_Err),
1714 .DMA_Pkt_Size_Err (DMA_Pkt_Size_Err),
1715 .Pkt_Size_Err_Addr (Pkt_Size_Err_Addr),
1716
1717 .DMA0_EofList (DMA0_EofList),
1718 .DMA0_Error (DMA0_Error),
1719 .DMA0_GotNxtDesc (DMA0_GotNxtDesc),
1720 .DMA0_SOP (DMA0_SOP),
1721 .DMA0_Mark (DMA0_Mark),
1722 .DMA0_Func_Num (DMA0_Func_Num),
1723 .DMA0_DescList (DMA0_DescList),
1724 .DMA0_Length (DMA0_Length),
1725 .DMA0_PageHandle (DMA0_PageHandle),
1726 .DMA0_Address (DMA0_Address),
1727 .SetGetNextDescDMA0 (SetGetNextDescDMA0),
1728
1729 .DMA1_EofList (DMA1_EofList),
1730 .DMA1_Error (DMA1_Error),
1731 .DMA1_GotNxtDesc (DMA1_GotNxtDesc),
1732 .DMA1_SOP (DMA1_SOP),
1733 .DMA1_Mark (DMA1_Mark),
1734 .DMA1_Func_Num (DMA1_Func_Num),
1735 .DMA1_DescList (DMA1_DescList),
1736 .DMA1_Length (DMA1_Length),
1737 .DMA1_PageHandle (DMA1_PageHandle),
1738 .DMA1_Address (DMA1_Address),
1739 .SetGetNextDescDMA1 (SetGetNextDescDMA1),
1740
1741 .DMA2_EofList (DMA2_EofList),
1742 .DMA2_Error (DMA2_Error),
1743 .DMA2_GotNxtDesc (DMA2_GotNxtDesc),
1744 .DMA2_SOP (DMA2_SOP),
1745 .DMA2_Mark (DMA2_Mark),
1746 .DMA2_Func_Num (DMA2_Func_Num),
1747 .DMA2_DescList (DMA2_DescList),
1748 .DMA2_Length (DMA2_Length),
1749 .DMA2_PageHandle (DMA2_PageHandle),
1750 .DMA2_Address (DMA2_Address),
1751 .SetGetNextDescDMA2 (SetGetNextDescDMA2),
1752
1753 .DMA3_EofList (DMA3_EofList),
1754 .DMA3_Error (DMA3_Error),
1755 .DMA3_GotNxtDesc (DMA3_GotNxtDesc),
1756 .DMA3_SOP (DMA3_SOP),
1757 .DMA3_Mark (DMA3_Mark),
1758 .DMA3_Func_Num (DMA3_Func_Num),
1759 .DMA3_DescList (DMA3_DescList),
1760 .DMA3_Length (DMA3_Length),
1761 .DMA3_PageHandle (DMA3_PageHandle),
1762 .DMA3_Address (DMA3_Address),
1763 .SetGetNextDescDMA3 (SetGetNextDescDMA3),
1764
1765 .DMA4_EofList (DMA4_EofList),
1766 .DMA4_Error (DMA4_Error),
1767 .DMA4_GotNxtDesc (DMA4_GotNxtDesc),
1768 .DMA4_SOP (DMA4_SOP),
1769 .DMA4_Mark (DMA4_Mark),
1770 .DMA4_Func_Num (DMA4_Func_Num),
1771 .DMA4_DescList (DMA4_DescList),
1772 .DMA4_Length (DMA4_Length),
1773 .DMA4_PageHandle (DMA4_PageHandle),
1774 .DMA4_Address (DMA4_Address),
1775 .SetGetNextDescDMA4 (SetGetNextDescDMA4),
1776
1777 .DMA5_EofList (DMA5_EofList),
1778 .DMA5_Error (DMA5_Error),
1779 .DMA5_GotNxtDesc (DMA5_GotNxtDesc),
1780 .DMA5_SOP (DMA5_SOP),
1781 .DMA5_Mark (DMA5_Mark),
1782 .DMA5_Func_Num (DMA5_Func_Num),
1783 .DMA5_DescList (DMA5_DescList),
1784 .DMA5_Length (DMA5_Length),
1785 .DMA5_PageHandle (DMA5_PageHandle),
1786 .DMA5_Address (DMA5_Address),
1787 .SetGetNextDescDMA5 (SetGetNextDescDMA5),
1788
1789 .DMA6_EofList (DMA6_EofList),
1790 .DMA6_Error (DMA6_Error),
1791 .DMA6_GotNxtDesc (DMA6_GotNxtDesc),
1792 .DMA6_SOP (DMA6_SOP),
1793 .DMA6_Mark (DMA6_Mark),
1794 .DMA6_Func_Num (DMA6_Func_Num),
1795 .DMA6_DescList (DMA6_DescList),
1796 .DMA6_Length (DMA6_Length),
1797 .DMA6_PageHandle (DMA6_PageHandle),
1798 .DMA6_Address (DMA6_Address),
1799 .SetGetNextDescDMA6 (SetGetNextDescDMA6),
1800
1801 .DMA7_EofList (DMA7_EofList),
1802 .DMA7_Error (DMA7_Error),
1803 .DMA7_GotNxtDesc (DMA7_GotNxtDesc),
1804 .DMA7_SOP (DMA7_SOP),
1805 .DMA7_Mark (DMA7_Mark),
1806 .DMA7_Func_Num (DMA7_Func_Num),
1807 .DMA7_DescList (DMA7_DescList),
1808 .DMA7_Length (DMA7_Length),
1809 .DMA7_PageHandle (DMA7_PageHandle),
1810 .DMA7_Address (DMA7_Address),
1811 .SetGetNextDescDMA7 (SetGetNextDescDMA7),
1812
1813 .DMA8_EofList (DMA8_EofList),
1814 .DMA8_Error (DMA8_Error),
1815 .DMA8_GotNxtDesc (DMA8_GotNxtDesc),
1816 .DMA8_SOP (DMA8_SOP),
1817 .DMA8_Mark (DMA8_Mark),
1818 .DMA8_Func_Num (DMA8_Func_Num),
1819 .DMA8_DescList (DMA8_DescList),
1820 .DMA8_Length (DMA8_Length),
1821 .DMA8_PageHandle (DMA8_PageHandle),
1822 .DMA8_Address (DMA8_Address),
1823 .SetGetNextDescDMA8 (SetGetNextDescDMA8),
1824
1825 .DMA9_EofList (DMA9_EofList),
1826 .DMA9_Error (DMA9_Error),
1827 .DMA9_GotNxtDesc (DMA9_GotNxtDesc),
1828 .DMA9_SOP (DMA9_SOP),
1829 .DMA9_Mark (DMA9_Mark),
1830 .DMA9_Func_Num (DMA9_Func_Num),
1831 .DMA9_DescList (DMA9_DescList),
1832 .DMA9_Length (DMA9_Length),
1833 .DMA9_PageHandle (DMA9_PageHandle),
1834 .DMA9_Address (DMA9_Address),
1835 .SetGetNextDescDMA9 (SetGetNextDescDMA9),
1836
1837 .DMA10_EofList (DMA10_EofList),
1838 .DMA10_Error (DMA10_Error),
1839 .DMA10_GotNxtDesc (DMA10_GotNxtDesc),
1840 .DMA10_SOP (DMA10_SOP),
1841 .DMA10_Mark (DMA10_Mark),
1842 .DMA10_Func_Num (DMA10_Func_Num),
1843 .DMA10_DescList (DMA10_DescList),
1844 .DMA10_Length (DMA10_Length),
1845 .DMA10_PageHandle (DMA10_PageHandle),
1846 .DMA10_Address (DMA10_Address),
1847 .SetGetNextDescDMA10 (SetGetNextDescDMA10),
1848
1849 .DMA11_EofList (DMA11_EofList),
1850 .DMA11_Error (DMA11_Error),
1851 .DMA11_GotNxtDesc (DMA11_GotNxtDesc),
1852 .DMA11_SOP (DMA11_SOP),
1853 .DMA11_Mark (DMA11_Mark),
1854 .DMA11_Func_Num (DMA11_Func_Num),
1855 .DMA11_DescList (DMA11_DescList),
1856 .DMA11_Length (DMA11_Length),
1857 .DMA11_PageHandle (DMA11_PageHandle),
1858 .DMA11_Address (DMA11_Address),
1859 .SetGetNextDescDMA11 (SetGetNextDescDMA11),
1860
1861 .DMA12_EofList (DMA12_EofList),
1862 .DMA12_Error (DMA12_Error),
1863 .DMA12_GotNxtDesc (DMA12_GotNxtDesc),
1864 .DMA12_SOP (DMA12_SOP),
1865 .DMA12_Mark (DMA12_Mark),
1866 .DMA12_Func_Num (DMA12_Func_Num),
1867 .DMA12_DescList (DMA12_DescList),
1868 .DMA12_Length (DMA12_Length),
1869 .DMA12_PageHandle (DMA12_PageHandle),
1870 .DMA12_Address (DMA12_Address),
1871 .SetGetNextDescDMA12 (SetGetNextDescDMA12),
1872
1873 .DMA13_EofList (DMA13_EofList),
1874 .DMA13_Error (DMA13_Error),
1875 .DMA13_GotNxtDesc (DMA13_GotNxtDesc),
1876 .DMA13_SOP (DMA13_SOP),
1877 .DMA13_Mark (DMA13_Mark),
1878 .DMA13_Func_Num (DMA13_Func_Num),
1879 .DMA13_DescList (DMA13_DescList),
1880 .DMA13_Length (DMA13_Length),
1881 .DMA13_PageHandle (DMA13_PageHandle),
1882 .DMA13_Address (DMA13_Address),
1883 .SetGetNextDescDMA13 (SetGetNextDescDMA13),
1884
1885 .DMA14_EofList (DMA14_EofList),
1886 .DMA14_Error (DMA14_Error),
1887 .DMA14_GotNxtDesc (DMA14_GotNxtDesc),
1888 .DMA14_SOP (DMA14_SOP),
1889 .DMA14_Mark (DMA14_Mark),
1890 .DMA14_Func_Num (DMA14_Func_Num),
1891 .DMA14_DescList (DMA14_DescList),
1892 .DMA14_Length (DMA14_Length),
1893 .DMA14_PageHandle (DMA14_PageHandle),
1894 .DMA14_Address (DMA14_Address),
1895 .SetGetNextDescDMA14 (SetGetNextDescDMA14),
1896
1897 .DMA15_EofList (DMA15_EofList),
1898 .DMA15_Error (DMA15_Error),
1899 .DMA15_GotNxtDesc (DMA15_GotNxtDesc),
1900 .DMA15_SOP (DMA15_SOP),
1901 .DMA15_Mark (DMA15_Mark),
1902 .DMA15_Func_Num (DMA15_Func_Num),
1903 .DMA15_DescList (DMA15_DescList),
1904 .DMA15_Length (DMA15_Length),
1905 .DMA15_PageHandle (DMA15_PageHandle),
1906 .DMA15_Address (DMA15_Address),
1907 .SetGetNextDescDMA15 (SetGetNextDescDMA15),
1908
1909 .DMA16_EofList (DMA16_EofList),
1910 .DMA16_Error (DMA16_Error),
1911 .DMA16_GotNxtDesc (DMA16_GotNxtDesc),
1912 .DMA16_SOP (DMA16_SOP),
1913 .DMA16_Mark (DMA16_Mark),
1914 .DMA16_Func_Num (DMA16_Func_Num),
1915 .DMA16_DescList (DMA16_DescList),
1916 .DMA16_Length (DMA16_Length),
1917 .DMA16_PageHandle (DMA16_PageHandle),
1918 .DMA16_Address (DMA16_Address),
1919 .SetGetNextDescDMA16 (SetGetNextDescDMA16),
1920
1921 .DMA17_EofList (DMA17_EofList),
1922 .DMA17_Error (DMA17_Error),
1923 .DMA17_GotNxtDesc (DMA17_GotNxtDesc),
1924 .DMA17_SOP (DMA17_SOP),
1925 .DMA17_Mark (DMA17_Mark),
1926 .DMA17_Func_Num (DMA17_Func_Num),
1927 .DMA17_DescList (DMA17_DescList),
1928 .DMA17_Length (DMA17_Length),
1929 .DMA17_PageHandle (DMA17_PageHandle),
1930 .DMA17_Address (DMA17_Address),
1931 .SetGetNextDescDMA17 (SetGetNextDescDMA17),
1932
1933 .DMA18_EofList (DMA18_EofList),
1934 .DMA18_Error (DMA18_Error),
1935 .DMA18_GotNxtDesc (DMA18_GotNxtDesc),
1936 .DMA18_SOP (DMA18_SOP),
1937 .DMA18_Mark (DMA18_Mark),
1938 .DMA18_Func_Num (DMA18_Func_Num),
1939 .DMA18_DescList (DMA18_DescList),
1940 .DMA18_Length (DMA18_Length),
1941 .DMA18_PageHandle (DMA18_PageHandle),
1942 .DMA18_Address (DMA18_Address),
1943 .SetGetNextDescDMA18 (SetGetNextDescDMA18),
1944
1945 .DMA19_EofList (DMA19_EofList),
1946 .DMA19_Error (DMA19_Error),
1947 .DMA19_GotNxtDesc (DMA19_GotNxtDesc),
1948 .DMA19_SOP (DMA19_SOP),
1949 .DMA19_Mark (DMA19_Mark),
1950 .DMA19_Func_Num (DMA19_Func_Num),
1951 .DMA19_DescList (DMA19_DescList),
1952 .DMA19_Length (DMA19_Length),
1953 .DMA19_PageHandle (DMA19_PageHandle),
1954 .DMA19_Address (DMA19_Address),
1955 .SetGetNextDescDMA19 (SetGetNextDescDMA19),
1956
1957 .DMA20_EofList (DMA20_EofList),
1958 .DMA20_Error (DMA20_Error),
1959 .DMA20_GotNxtDesc (DMA20_GotNxtDesc),
1960 .DMA20_SOP (DMA20_SOP),
1961 .DMA20_Mark (DMA20_Mark),
1962 .DMA20_Func_Num (DMA20_Func_Num),
1963 .DMA20_DescList (DMA20_DescList),
1964 .DMA20_Length (DMA20_Length),
1965 .DMA20_PageHandle (DMA20_PageHandle),
1966 .DMA20_Address (DMA20_Address),
1967 .SetGetNextDescDMA20 (SetGetNextDescDMA20),
1968
1969 .DMA21_EofList (DMA21_EofList),
1970 .DMA21_Error (DMA21_Error),
1971 .DMA21_GotNxtDesc (DMA21_GotNxtDesc),
1972 .DMA21_SOP (DMA21_SOP),
1973 .DMA21_Mark (DMA21_Mark),
1974 .DMA21_Func_Num (DMA21_Func_Num),
1975 .DMA21_DescList (DMA21_DescList),
1976 .DMA21_Length (DMA21_Length),
1977 .DMA21_PageHandle (DMA21_PageHandle),
1978 .DMA21_Address (DMA21_Address),
1979 .SetGetNextDescDMA21 (SetGetNextDescDMA21),
1980
1981 .DMA22_EofList (DMA22_EofList),
1982 .DMA22_Error (DMA22_Error),
1983 .DMA22_GotNxtDesc (DMA22_GotNxtDesc),
1984 .DMA22_SOP (DMA22_SOP),
1985 .DMA22_Mark (DMA22_Mark),
1986 .DMA22_Func_Num (DMA22_Func_Num),
1987 .DMA22_DescList (DMA22_DescList),
1988 .DMA22_Length (DMA22_Length),
1989 .DMA22_PageHandle (DMA22_PageHandle),
1990 .DMA22_Address (DMA22_Address),
1991 .SetGetNextDescDMA22 (SetGetNextDescDMA22),
1992
1993 .DMA23_EofList (DMA23_EofList),
1994 .DMA23_Error (DMA23_Error),
1995 .DMA23_GotNxtDesc (DMA23_GotNxtDesc),
1996 .DMA23_SOP (DMA23_SOP),
1997 .DMA23_Mark (DMA23_Mark),
1998 .DMA23_Func_Num (DMA23_Func_Num),
1999 .DMA23_DescList (DMA23_DescList),
2000 .DMA23_Length (DMA23_Length),
2001 .DMA23_PageHandle (DMA23_PageHandle),
2002 .DMA23_Address (DMA23_Address),
2003 .SetGetNextDescDMA23 (SetGetNextDescDMA23),
2004
2005 .DRR_Arb_Valid (dRR_Arb_Valid),
2006 .DRR_NextDMAChannel (dRR_NextDMAChannel),
2007 .DRR_PacketDone (dRR_PacketDone),
2008 .PacketByteCount (dRR_PacketByteCount),
2009
2010 .Anchor_Done (anchor_Done),
2011 .Req_Anchor (req_Anchor),
2012 .Anchor_LoadTID (anchor_LoadTID),
2013 .Anchor_MarkBit (anchor_MarkBit),
2014 .Anchor_SopBit (anchor_SopBit),
2015 .Anchor_GatherLast (anchor_GatherLast),
2016 .Anchor_DMA (anchor_DMA),
2017 .Anchor_TransID (anchor_TransID),
2018 .Anchor_Length (anchor_Length),
2019 .Anchor_Address (anchor_Address),
2020
2021 .DMC_TXC_Req_Ack (DMC_TXC_Req_Ack),
2022 .DMC_TXC_Req_TransID (DMC_TXC_Req_TransID),
2023
2024 .Port_Selected (Port_Selected),
2025 .Port_Request (Port_Request),
2026 .Port_Request_Func_Num (Port_Request_Func_Num),
2027 .Port_Request_DMA_Num (Port_Request_DMA_Num),
2028 .Port_Request_Length (Port_Request_Length),
2029 .Port_Request_Address (Port_Request_Address),
2030
2031 .DataPortReq_State (DataPortReq_State)
2032 );
2033
2034
2035niu_txc_reAligner #(REORDER_SIZE, REORDER_PTR) niu_txc_reAligner (
2036 .SysClk (SysClk),
2037 .Reset_L (Reset_L),
2038 .Txc_Enabled (Txc_Enabled),
2039 .EnableGMACMode (EnableGMACMode),
2040 .PortIndentifier (PortIndentifier),
2041
2042 .ClearStatistics (ClearStatistics),
2043 .WrPacketRequested (WrPacketRequested),
2044 .WrPacketStuffed (WrPacketStuffed),
2045 .WrTidsInUse (WrTidsInUse),
2046 .WrDuplicateTid (WrDuplicateTid),
2047 .WrUnInitializedTID (WrUnInitializedTID),
2048 .WrTimedoutTids (WrTimedoutTids),
2049 .WrReOrderStateLogic (WrReOrderStateLogic),
2050 .WrReOrderStateControl (WrReOrderStateControl),
2051 .WrReOrderStateData0 (WrReOrderStateData0),
2052 .WrReOrderStateData1 (WrReOrderStateData1),
2053 .WrReOrderStateData2 (WrReOrderStateData2),
2054 .WrReOrderStateData3 (WrReOrderStateData3),
2055 .PioDataIn (PioDataIn),
2056 .GatherRequestCount (GatherRequestCount),
2057 .PacketRequestCount (PacketRequestCount),
2058 .ReOrdersStuffed (ReOrdersStuffed),
2059 .TidsInUse (TidsInUse),
2060 .DuplicateTid (DuplicateTid),
2061 .UnInitializedTID (UnInitializedTID),
2062 .TimedoutTids (TimedoutTids),
2063 .ReOrderStateLogic (ReOrderStateLogic),
2064 .ReOrderStateControl (ReOrderStateControl),
2065 .ReOrderStateData0 (ReOrderStateData0),
2066 .ReOrderStateData1 (ReOrderStateData1),
2067 .ReOrderStateData2 (ReOrderStateData2),
2068 .ReOrderStateData3 (ReOrderStateData3),
2069
2070 .MAC_Enabled (MAC_Enabled),
2071
2072 .MaxReorderNumber (MaxReorderNumber),
2073 .UpdateDMA (UpdateDMA),
2074 .UpdateDMALength (UpdateDMALength),
2075 .UpdateDMANumber (UpdateDMANumber),
2076
2077 .ReOrderFifoRead (reOrderFifoRead),
2078 .ReOrderEccControl (ReOrderEccControl),
2079 .ReOrderCorruptECCSingle (ReOrderCorruptECCSingle),
2080 .ReOrderCorruptECCDouble (ReOrderCorruptECCDouble),
2081 .ReOrderFifoWrite (ReOrderFifoWrite),
2082 .ReOrderFifoReadStrobe (ReOrderFifoReadStrobe),
2083 .ReOrderFifoEmpty (reOrderFifoEmpty),
2084 .ReOrderFifoAlmostEmpty (reOrderFifoAlmostEmpty),
2085 .ReOrderWritePtr (ReOrderWritePtr),
2086 .ReOrderReadPtr (ReOrderReadPtr),
2087 .ReOrderEngineDataOut (ReOrderEngineDataOut),
2088
2089 .Req_Anchor (req_Anchor),
2090 .Anchor_MarkBit (anchor_MarkBit),
2091 .Anchor_SopBit (anchor_SopBit),
2092 .Anchor_GatherLast (anchor_GatherLast),
2093 .Anchor_DMA (anchor_DMA),
2094 .Anchor_Length (anchor_Length),
2095 .Anchor_Address (anchor_Address),
2096 .Anchor_Done (anchor_Done),
2097
2098 .Anchor_LoadTID (anchor_LoadTID),
2099 .Anchor_TransID (anchor_TransID),
2100
2101 .DMC_TXC_Resp_Rdy (DMC_TXC_Resp_Rdy),
2102 .DMC_TXC_Resp_Complete (DMC_TXC_Resp_Complete),
2103 .DMC_TXC_Trans_Complete (DMC_TXC_Trans_Complete),
2104 .DMC_TXC_Resp_Data_Valid (DMC_TXC_Resp_Data_Valid),
2105 .DMC_TXC_Resp_Client (DMC_TXC_Resp_Client),
2106 .DMC_TXC_Resp_Port_Num (DMC_TXC_Resp_Port_Num),
2107 .DMC_TXC_Resp_Cmd_Status (DMC_TXC_Resp_Cmd_Status),
2108 .DMC_TXC_Resp_Data_Status (DMC_TXC_Resp_Data_Status),
2109 .DMC_TXC_Resp_DMA_Num (DMC_TXC_Resp_DMA_Num),
2110 .DMC_TXC_Resp_TransID (DMC_TXC_Resp_TransID),
2111 .DMC_TXC_Resp_Cmd (DMC_TXC_Resp_Cmd),
2112 .DMC_TXC_Resp_ByteEnables (DMC_TXC_Resp_ByteEnables),
2113 .DMC_TXC_Resp_Data_Length (DMC_TXC_Resp_Data_Length),
2114 .DMC_TXC_Resp_Address (DMC_TXC_Resp_Address),
2115 .DMC_TXC_Resp_Data (DMC_TXC_Resp_Data),
2116 .TXC_DMC_Resp_Accept (TXC_DMC_Resp_Accept),
2117
2118 .ReOrder_Error (ReOrder_Error),
2119
2120 .Nack_Pkt_Rd (Nack_Pkt_Rd),
2121 .DMA_Nack_Pkt_Rd (DMA_Nack_Pkt_Rd),
2122 .Nack_Pkt_Rd_Addr (Nack_Pkt_Rd_Addr),
2123
2124 .DMA0_Inc_Head (DMA0_Inc_Head),
2125 .DMA0_Mark_Bit (DMA0_Mark_Bit),
2126 .DMA0_Inc_Pkt_Cnt (DMA0_Inc_Pkt_Cnt),
2127 .DMA1_Inc_Head (DMA1_Inc_Head),
2128 .DMA1_Mark_Bit (DMA1_Mark_Bit),
2129 .DMA1_Inc_Pkt_Cnt (DMA1_Inc_Pkt_Cnt),
2130 .DMA2_Inc_Head (DMA2_Inc_Head),
2131 .DMA2_Mark_Bit (DMA2_Mark_Bit),
2132 .DMA2_Inc_Pkt_Cnt (DMA2_Inc_Pkt_Cnt),
2133 .DMA3_Inc_Head (DMA3_Inc_Head),
2134 .DMA3_Mark_Bit (DMA3_Mark_Bit),
2135 .DMA3_Inc_Pkt_Cnt (DMA3_Inc_Pkt_Cnt),
2136 .DMA4_Inc_Head (DMA4_Inc_Head),
2137 .DMA4_Mark_Bit (DMA4_Mark_Bit),
2138 .DMA4_Inc_Pkt_Cnt (DMA4_Inc_Pkt_Cnt),
2139 .DMA5_Inc_Head (DMA5_Inc_Head),
2140 .DMA5_Mark_Bit (DMA5_Mark_Bit),
2141 .DMA5_Inc_Pkt_Cnt (DMA5_Inc_Pkt_Cnt),
2142 .DMA6_Inc_Head (DMA6_Inc_Head),
2143 .DMA6_Mark_Bit (DMA6_Mark_Bit),
2144 .DMA6_Inc_Pkt_Cnt (DMA6_Inc_Pkt_Cnt),
2145 .DMA7_Inc_Head (DMA7_Inc_Head),
2146 .DMA7_Mark_Bit (DMA7_Mark_Bit),
2147 .DMA7_Inc_Pkt_Cnt (DMA7_Inc_Pkt_Cnt),
2148 .DMA8_Inc_Head (DMA8_Inc_Head),
2149 .DMA8_Mark_Bit (DMA8_Mark_Bit),
2150 .DMA8_Inc_Pkt_Cnt (DMA8_Inc_Pkt_Cnt),
2151 .DMA9_Inc_Head (DMA9_Inc_Head),
2152 .DMA9_Mark_Bit (DMA9_Mark_Bit),
2153 .DMA9_Inc_Pkt_Cnt (DMA9_Inc_Pkt_Cnt),
2154 .DMA10_Inc_Head (DMA10_Inc_Head),
2155 .DMA10_Mark_Bit (DMA10_Mark_Bit),
2156 .DMA10_Inc_Pkt_Cnt (DMA10_Inc_Pkt_Cnt),
2157 .DMA11_Inc_Head (DMA11_Inc_Head),
2158 .DMA11_Mark_Bit (DMA11_Mark_Bit),
2159 .DMA11_Inc_Pkt_Cnt (DMA11_Inc_Pkt_Cnt),
2160 .DMA12_Inc_Head (DMA12_Inc_Head),
2161 .DMA12_Mark_Bit (DMA12_Mark_Bit),
2162 .DMA12_Inc_Pkt_Cnt (DMA12_Inc_Pkt_Cnt),
2163 .DMA13_Inc_Head (DMA13_Inc_Head),
2164 .DMA13_Mark_Bit (DMA13_Mark_Bit),
2165 .DMA13_Inc_Pkt_Cnt (DMA13_Inc_Pkt_Cnt),
2166 .DMA14_Inc_Head (DMA14_Inc_Head),
2167 .DMA14_Mark_Bit (DMA14_Mark_Bit),
2168 .DMA14_Inc_Pkt_Cnt (DMA14_Inc_Pkt_Cnt),
2169 .DMA15_Inc_Head (DMA15_Inc_Head),
2170 .DMA15_Mark_Bit (DMA15_Mark_Bit),
2171 .DMA15_Inc_Pkt_Cnt (DMA15_Inc_Pkt_Cnt),
2172 .DMA16_Inc_Head (DMA16_Inc_Head),
2173 .DMA16_Mark_Bit (DMA16_Mark_Bit),
2174 .DMA16_Inc_Pkt_Cnt (DMA16_Inc_Pkt_Cnt),
2175 .DMA17_Inc_Head (DMA17_Inc_Head),
2176 .DMA17_Mark_Bit (DMA17_Mark_Bit),
2177 .DMA17_Inc_Pkt_Cnt (DMA17_Inc_Pkt_Cnt),
2178 .DMA18_Inc_Head (DMA18_Inc_Head),
2179 .DMA18_Mark_Bit (DMA18_Mark_Bit),
2180 .DMA18_Inc_Pkt_Cnt (DMA18_Inc_Pkt_Cnt),
2181 .DMA19_Inc_Head (DMA19_Inc_Head),
2182 .DMA19_Mark_Bit (DMA19_Mark_Bit),
2183 .DMA19_Inc_Pkt_Cnt (DMA19_Inc_Pkt_Cnt),
2184 .DMA20_Inc_Head (DMA20_Inc_Head),
2185 .DMA20_Mark_Bit (DMA20_Mark_Bit),
2186 .DMA20_Inc_Pkt_Cnt (DMA20_Inc_Pkt_Cnt),
2187 .DMA21_Inc_Head (DMA21_Inc_Head),
2188 .DMA21_Mark_Bit (DMA21_Mark_Bit),
2189 .DMA21_Inc_Pkt_Cnt (DMA21_Inc_Pkt_Cnt),
2190 .DMA22_Inc_Head (DMA22_Inc_Head),
2191 .DMA22_Mark_Bit (DMA22_Mark_Bit),
2192 .DMA22_Inc_Pkt_Cnt (DMA22_Inc_Pkt_Cnt),
2193 .DMA23_Inc_Head (DMA23_Inc_Head),
2194 .DMA23_Mark_Bit (DMA23_Mark_Bit),
2195 .DMA23_Inc_Pkt_Cnt (DMA23_Inc_Pkt_Cnt),
2196
2197 .Anchor_State (Anchor_State),
2198 .ReOrder_State (ReOrder_State),
2199 .Pointer_State (Pointer_State)
2200 );
2201
2202
2203niu_txc_packetAssy niu_txc_packetAssy (
2204 .SysClk (SysClk),
2205 .Reset_L (Reset_L),
2206 .PacketAssyDead (PacketAssyDead),
2207 .Txc_Enabled (Txc_Enabled),
2208 .MAC_Enabled (MAC_Enabled),
2209
2210 .StoreForwardFifoRead (storeForwardFifoRead),
2211 .StoreForwardEccControl (StoreForwardEccControl),
2212 .StoreForwardFifoEmpty (storeForwardFifoEmpty),
2213 .StoreForward_CorruptECCSingle (StoreForward_CorruptECCSingle),
2214 .StoreForward_CorruptECCDouble (StoreForward_CorruptECCDouble),
2215 .StoreForwardFifoWrite (StoreForwardFifoWrite),
2216 .StoreForwardFifoReadStrobe (StoreForwardFifoReadStrobe),
2217 .StoreForwardReadPtr (StoreForwardReadPtr),
2218 .StoreForwardWritePtr (StoreForwardWritePtr),
2219 .PacketAssyEngineDataOut (PacketAssyEngineDataOut),
2220
2221 .ReOrderFifoEmpty (reOrderFifoEmpty),
2222 .ReOrderUnCorrectError (ReOrderUnCorrectError),
2223 .ReOrderFifoAlmostEmpty (reOrderFifoAlmostEmpty),
2224 .ReOrderFifoDataValid (ReOrderFifoDataValid),
2225 .DisableEccCheking (ReOrderEccControl[31]),
2226 .PacketAssyEngineDataIn (PacketAssyEngineDataIn),
2227 .ReOrderFifoRead (reOrderFifoRead),
2228
2229 .CheckSumValid (checkSumValid),
2230 .ChecksumValue (checksumValue),
2231 .StartTCPChecksum (startTCPchecksum),
2232 .ChecksumPacketDone (checksumPacketDone),
2233 .PacketType (packetType),
2234 .Layer3Version (layer3Version),
2235 .Layer3Start (layer3Start),
2236 .IPv4IPHeaderLen (iPv4IPHeaderLen),
2237
2238 .ClearStatistics (ClearStatistics),
2239 .WrPacketRequested (WrPacketRequested),
2240 .WrPacketStuffed (WrPacketStuffed),
2241 .PioDataIn (PioDataIn[15:0]),
2242 .PacketsStuffed (PacketsStuffed),
2243 .PktErrAbortCount (PktErrAbortCount),
2244
2245 .PacketAssy_State (PacketAssy_State)
2246 );
2247
2248
2249niu_ipp_sum_unit txc_sum_unit (
2250 .clk (SysClk),
2251 .reset (~Reset_L),
2252 .ipp_din_dat (PacketAssyEngineDataOut[127:0]),
2253 .port_num (1'b1),
2254 .ipp_full_cksum (1'b0),
2255 .ipp_la4_prot (packetType),
2256 .ipp_la3_vers (layer3Version),
2257 .ipp_la2_opti (layer3Start),
2258 .ip4_hdr_leng (iPv4IPHeaderLen),
2259 .ipp_info_valid (StoreForwardFifoWrite),
2260 .ipp_start_tcp (startTCPchecksum),
2261 .ipp_pkt_end (checksumPacketDone),
2262 .ipp_max_bytes (17'h1FFFF),
2263 .sum_prt_started (),
2264 .sum_prt_valid (checkSumValid),
2265 .sum_prt_fail (),
2266 .sum_prt_cksum (checksumValue),
2267 .sum_prt_length (),
2268 .sum_prt_state (Sum_prt_state)
2269 );
2270
2271niu_txc_mac_transfer niu_txc_mac_transfer (
2272 .SysClk (SysClk),
2273 .Reset_L (Reset_L),
2274 .Txc_Enabled (Txc_Enabled),
2275 .EnableGMACMode (EnableGMACMode),
2276 .DisableEccCheking (StoreForwardEccControl[31]),
2277 .UnCorrectError (StoreForwardUnCorrectError),
2278 .FifoEmpty (storeForwardFifoEmpty),
2279 .FifoDataOut (MacXferEngineDataIn),
2280 .FifoRead (storeForwardFifoRead),
2281 .ClearStatistics (ClearStatistics),
2282 .WrPacketXmitted (WrPacketXmitted),
2283 .PioDataIn (PioDataIn),
2284 .PacketsTransmitted (PacketsTransmitted),
2285 .BytesTransmitted (BytesTransmitted),
2286 .MAC_Req (MAC_Req),
2287 .MAC_Ack (MAC_Ack),
2288 .MAC_Tag (MAC_Tag),
2289 .MAC_Abort (MAC_Abort),
2290 .MAC_Status (MAC_Status),
2291 .MAC_Data (MAC_Data),
2292 .Mac_Xfer_State (Mac_Xfer_State)
2293 );
2294
2295
2296endmodule