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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / design / sys / iop / niu / rtl / niu_txc_tdmc_ifc.v
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AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: niu_txc_tdmc_ifc.v
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
19// along with this program; if not, write to the Free Software
20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
23// choice is available it will apply instead, Sun elects to use only
24// the General Public License version 2 (GPLv2) at this time for any
25// software where a choice of GPL license versions is made
26// available with the language indicating that GPLv2 or any later version
27// may be used, or where a choice of which version of the GPL is applied is
28// otherwise unspecified.
29//
30// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
31// CA 95054 USA or visit www.sun.com if you need additional information or
32// have any questions.
33//
34// ========== Copyright Header End ============================================
35/*********************************************************************
36 *
37 * niu_txc_tdmc_ifc.v
38 *
39 * NIU TXC To TDMC Grouped Interface
40 *
41 * Orignal Author(s): Rahoul Puri
42 * Modifier(s):
43 * Project(s): Neptune
44 *
45 * Copyright (c) 2004 Sun Microsystems, Inc.
46 *
47 * All Rights Reserved.
48 *
49 * This verilog model is the confidential and proprietary property of
50 * Sun Microsystems, Inc., and the possession or use of this model
51 * requires a written license from Sun Microsystems, Inc.
52 *
53 **********************************************************************/
54
55`include "timescale.v"
56
57module niu_txc_tdmc_ifc (
58 SysClk,
59 Reset_L,
60 Port0_Nack_Pkt_Rd,
61 Port0_DMA_Nack_Pkt_Rd,
62 Port0_Nack_Pkt_Rd_Addr,
63 Port0_DMA0_inc_head,
64 Port0_DMA0_reset_done,
65 Port0_DMA0_mark_bit,
66 Port0_DMA0_inc_pkt_cnt,
67 Port0_SetGetNextDescDMA0,
68 Port0_DMA1_inc_head,
69 Port0_DMA1_reset_done,
70 Port0_DMA1_mark_bit,
71 Port0_DMA1_inc_pkt_cnt,
72 Port0_SetGetNextDescDMA1,
73 Port0_DMA2_inc_head,
74 Port0_DMA2_reset_done,
75 Port0_DMA2_mark_bit,
76 Port0_DMA2_inc_pkt_cnt,
77 Port0_SetGetNextDescDMA2,
78 Port0_DMA3_inc_head,
79 Port0_DMA3_reset_done,
80 Port0_DMA3_mark_bit,
81 Port0_DMA3_inc_pkt_cnt,
82 Port0_SetGetNextDescDMA3,
83 Port0_DMA4_inc_head,
84 Port0_DMA4_reset_done,
85 Port0_DMA4_mark_bit,
86 Port0_DMA4_inc_pkt_cnt,
87 Port0_SetGetNextDescDMA4,
88 Port0_DMA5_inc_head,
89 Port0_DMA5_reset_done,
90 Port0_DMA5_mark_bit,
91 Port0_DMA5_inc_pkt_cnt,
92 Port0_SetGetNextDescDMA5,
93 Port0_DMA6_inc_head,
94 Port0_DMA6_reset_done,
95 Port0_DMA6_mark_bit,
96 Port0_DMA6_inc_pkt_cnt,
97 Port0_SetGetNextDescDMA6,
98 Port0_DMA7_inc_head,
99 Port0_DMA7_reset_done,
100 Port0_DMA7_mark_bit,
101 Port0_DMA7_inc_pkt_cnt,
102 Port0_SetGetNextDescDMA7,
103 Port0_DMA8_inc_head,
104 Port0_DMA8_reset_done,
105 Port0_DMA8_mark_bit,
106 Port0_DMA8_inc_pkt_cnt,
107 Port0_SetGetNextDescDMA8,
108 Port0_DMA9_inc_head,
109 Port0_DMA9_reset_done,
110 Port0_DMA9_mark_bit,
111 Port0_DMA9_inc_pkt_cnt,
112 Port0_SetGetNextDescDMA9,
113 Port0_DMA10_inc_head,
114 Port0_DMA10_reset_done,
115 Port0_DMA10_mark_bit,
116 Port0_DMA10_inc_pkt_cnt,
117 Port0_SetGetNextDescDMA10,
118 Port0_DMA11_inc_head,
119 Port0_DMA11_reset_done,
120 Port0_DMA11_mark_bit,
121 Port0_DMA11_inc_pkt_cnt,
122 Port0_SetGetNextDescDMA11,
123 Port0_DMA12_inc_head,
124 Port0_DMA12_reset_done,
125 Port0_DMA12_mark_bit,
126 Port0_DMA12_inc_pkt_cnt,
127 Port0_SetGetNextDescDMA12,
128 Port0_DMA13_inc_head,
129 Port0_DMA13_reset_done,
130 Port0_DMA13_mark_bit,
131 Port0_DMA13_inc_pkt_cnt,
132 Port0_SetGetNextDescDMA13,
133 Port0_DMA14_inc_head,
134 Port0_DMA14_reset_done,
135 Port0_DMA14_mark_bit,
136 Port0_DMA14_inc_pkt_cnt,
137 Port0_SetGetNextDescDMA14,
138 Port0_DMA15_inc_head,
139 Port0_DMA15_reset_done,
140 Port0_DMA15_mark_bit,
141 Port0_DMA15_inc_pkt_cnt,
142 Port0_SetGetNextDescDMA15,
143 Port0_DMA16_inc_head,
144 Port0_DMA16_reset_done,
145 Port0_DMA16_mark_bit,
146 Port0_DMA16_inc_pkt_cnt,
147 Port0_SetGetNextDescDMA16,
148 Port0_DMA17_inc_head,
149 Port0_DMA17_reset_done,
150 Port0_DMA17_mark_bit,
151 Port0_DMA17_inc_pkt_cnt,
152 Port0_SetGetNextDescDMA17,
153 Port0_DMA18_inc_head,
154 Port0_DMA18_reset_done,
155 Port0_DMA18_mark_bit,
156 Port0_DMA18_inc_pkt_cnt,
157 Port0_SetGetNextDescDMA18,
158 Port0_DMA19_inc_head,
159 Port0_DMA19_reset_done,
160 Port0_DMA19_mark_bit,
161 Port0_DMA19_inc_pkt_cnt,
162 Port0_SetGetNextDescDMA19,
163 Port0_DMA20_inc_head,
164 Port0_DMA20_reset_done,
165 Port0_DMA20_mark_bit,
166 Port0_DMA20_inc_pkt_cnt,
167 Port0_SetGetNextDescDMA20,
168 Port0_DMA21_inc_head,
169 Port0_DMA21_reset_done,
170 Port0_DMA21_mark_bit,
171 Port0_DMA21_inc_pkt_cnt,
172 Port0_SetGetNextDescDMA21,
173 Port0_DMA22_inc_head,
174 Port0_DMA22_reset_done,
175 Port0_DMA22_mark_bit,
176 Port0_DMA22_inc_pkt_cnt,
177 Port0_SetGetNextDescDMA22,
178 Port0_DMA23_inc_head,
179 Port0_DMA23_reset_done,
180 Port0_DMA23_mark_bit,
181 Port0_DMA23_inc_pkt_cnt,
182 Port0_SetGetNextDescDMA23,
183 Port1_Nack_Pkt_Rd,
184 Port1_DMA_Nack_Pkt_Rd,
185 Port1_Nack_Pkt_Rd_Addr,
186 Port1_DMA0_inc_head,
187 Port1_DMA0_reset_done,
188 Port1_DMA0_mark_bit,
189 Port1_DMA0_inc_pkt_cnt,
190 Port1_SetGetNextDescDMA0,
191 Port1_DMA1_inc_head,
192 Port1_DMA1_reset_done,
193 Port1_DMA1_mark_bit,
194 Port1_DMA1_inc_pkt_cnt,
195 Port1_SetGetNextDescDMA1,
196 Port1_DMA2_inc_head,
197 Port1_DMA2_reset_done,
198 Port1_DMA2_mark_bit,
199 Port1_DMA2_inc_pkt_cnt,
200 Port1_SetGetNextDescDMA2,
201 Port1_DMA3_inc_head,
202 Port1_DMA3_reset_done,
203 Port1_DMA3_mark_bit,
204 Port1_DMA3_inc_pkt_cnt,
205 Port1_SetGetNextDescDMA3,
206 Port1_DMA4_inc_head,
207 Port1_DMA4_reset_done,
208 Port1_DMA4_mark_bit,
209 Port1_DMA4_inc_pkt_cnt,
210 Port1_SetGetNextDescDMA4,
211 Port1_DMA5_inc_head,
212 Port1_DMA5_reset_done,
213 Port1_DMA5_mark_bit,
214 Port1_DMA5_inc_pkt_cnt,
215 Port1_SetGetNextDescDMA5,
216 Port1_DMA6_inc_head,
217 Port1_DMA6_reset_done,
218 Port1_DMA6_mark_bit,
219 Port1_DMA6_inc_pkt_cnt,
220 Port1_SetGetNextDescDMA6,
221 Port1_DMA7_inc_head,
222 Port1_DMA7_reset_done,
223 Port1_DMA7_mark_bit,
224 Port1_DMA7_inc_pkt_cnt,
225 Port1_SetGetNextDescDMA7,
226 Port1_DMA8_inc_head,
227 Port1_DMA8_reset_done,
228 Port1_DMA8_mark_bit,
229 Port1_DMA8_inc_pkt_cnt,
230 Port1_SetGetNextDescDMA8,
231 Port1_DMA9_inc_head,
232 Port1_DMA9_reset_done,
233 Port1_DMA9_mark_bit,
234 Port1_DMA9_inc_pkt_cnt,
235 Port1_SetGetNextDescDMA9,
236 Port1_DMA10_inc_head,
237 Port1_DMA10_reset_done,
238 Port1_DMA10_mark_bit,
239 Port1_DMA10_inc_pkt_cnt,
240 Port1_SetGetNextDescDMA10,
241 Port1_DMA11_inc_head,
242 Port1_DMA11_reset_done,
243 Port1_DMA11_mark_bit,
244 Port1_DMA11_inc_pkt_cnt,
245 Port1_SetGetNextDescDMA11,
246 Port1_DMA12_inc_head,
247 Port1_DMA12_reset_done,
248 Port1_DMA12_mark_bit,
249 Port1_DMA12_inc_pkt_cnt,
250 Port1_SetGetNextDescDMA12,
251 Port1_DMA13_inc_head,
252 Port1_DMA13_reset_done,
253 Port1_DMA13_mark_bit,
254 Port1_DMA13_inc_pkt_cnt,
255 Port1_SetGetNextDescDMA13,
256 Port1_DMA14_inc_head,
257 Port1_DMA14_reset_done,
258 Port1_DMA14_mark_bit,
259 Port1_DMA14_inc_pkt_cnt,
260 Port1_SetGetNextDescDMA14,
261 Port1_DMA15_inc_head,
262 Port1_DMA15_reset_done,
263 Port1_DMA15_mark_bit,
264 Port1_DMA15_inc_pkt_cnt,
265 Port1_SetGetNextDescDMA15,
266 Port1_DMA16_inc_head,
267 Port1_DMA16_reset_done,
268 Port1_DMA16_mark_bit,
269 Port1_DMA16_inc_pkt_cnt,
270 Port1_SetGetNextDescDMA16,
271 Port1_DMA17_inc_head,
272 Port1_DMA17_reset_done,
273 Port1_DMA17_mark_bit,
274 Port1_DMA17_inc_pkt_cnt,
275 Port1_SetGetNextDescDMA17,
276 Port1_DMA18_inc_head,
277 Port1_DMA18_reset_done,
278 Port1_DMA18_mark_bit,
279 Port1_DMA18_inc_pkt_cnt,
280 Port1_SetGetNextDescDMA18,
281 Port1_DMA19_inc_head,
282 Port1_DMA19_reset_done,
283 Port1_DMA19_mark_bit,
284 Port1_DMA19_inc_pkt_cnt,
285 Port1_SetGetNextDescDMA19,
286 Port1_DMA20_inc_head,
287 Port1_DMA20_reset_done,
288 Port1_DMA20_mark_bit,
289 Port1_DMA20_inc_pkt_cnt,
290 Port1_SetGetNextDescDMA20,
291 Port1_DMA21_inc_head,
292 Port1_DMA21_reset_done,
293 Port1_DMA21_mark_bit,
294 Port1_DMA21_inc_pkt_cnt,
295 Port1_SetGetNextDescDMA21,
296 Port1_DMA22_inc_head,
297 Port1_DMA22_reset_done,
298 Port1_DMA22_mark_bit,
299 Port1_DMA22_inc_pkt_cnt,
300 Port1_SetGetNextDescDMA22,
301 Port1_DMA23_inc_head,
302 Port1_DMA23_reset_done,
303 Port1_DMA23_mark_bit,
304 Port1_DMA23_inc_pkt_cnt,
305 Port1_SetGetNextDescDMA23,
306 Port2_Nack_Pkt_Rd,
307 Port2_DMA_Nack_Pkt_Rd,
308 Port2_Nack_Pkt_Rd_Addr,
309 Port2_DMA0_inc_head,
310 Port2_DMA0_reset_done,
311 Port2_DMA0_mark_bit,
312 Port2_DMA0_inc_pkt_cnt,
313 Port2_SetGetNextDescDMA0,
314 Port2_DMA1_inc_head,
315 Port2_DMA1_reset_done,
316 Port2_DMA1_mark_bit,
317 Port2_DMA1_inc_pkt_cnt,
318 Port2_SetGetNextDescDMA1,
319 Port2_DMA2_inc_head,
320 Port2_DMA2_reset_done,
321 Port2_DMA2_mark_bit,
322 Port2_DMA2_inc_pkt_cnt,
323 Port2_SetGetNextDescDMA2,
324 Port2_DMA3_inc_head,
325 Port2_DMA3_reset_done,
326 Port2_DMA3_mark_bit,
327 Port2_DMA3_inc_pkt_cnt,
328 Port2_SetGetNextDescDMA3,
329 Port2_DMA4_inc_head,
330 Port2_DMA4_reset_done,
331 Port2_DMA4_mark_bit,
332 Port2_DMA4_inc_pkt_cnt,
333 Port2_SetGetNextDescDMA4,
334 Port2_DMA5_inc_head,
335 Port2_DMA5_reset_done,
336 Port2_DMA5_mark_bit,
337 Port2_DMA5_inc_pkt_cnt,
338 Port2_SetGetNextDescDMA5,
339 Port2_DMA6_inc_head,
340 Port2_DMA6_reset_done,
341 Port2_DMA6_mark_bit,
342 Port2_DMA6_inc_pkt_cnt,
343 Port2_SetGetNextDescDMA6,
344 Port2_DMA7_inc_head,
345 Port2_DMA7_reset_done,
346 Port2_DMA7_mark_bit,
347 Port2_DMA7_inc_pkt_cnt,
348 Port2_SetGetNextDescDMA7,
349 Port2_DMA8_inc_head,
350 Port2_DMA8_reset_done,
351 Port2_DMA8_mark_bit,
352 Port2_DMA8_inc_pkt_cnt,
353 Port2_SetGetNextDescDMA8,
354 Port2_DMA9_inc_head,
355 Port2_DMA9_reset_done,
356 Port2_DMA9_mark_bit,
357 Port2_DMA9_inc_pkt_cnt,
358 Port2_SetGetNextDescDMA9,
359 Port2_DMA10_inc_head,
360 Port2_DMA10_reset_done,
361 Port2_DMA10_mark_bit,
362 Port2_DMA10_inc_pkt_cnt,
363 Port2_SetGetNextDescDMA10,
364 Port2_DMA11_inc_head,
365 Port2_DMA11_reset_done,
366 Port2_DMA11_mark_bit,
367 Port2_DMA11_inc_pkt_cnt,
368 Port2_SetGetNextDescDMA11,
369 Port2_DMA12_inc_head,
370 Port2_DMA12_reset_done,
371 Port2_DMA12_mark_bit,
372 Port2_DMA12_inc_pkt_cnt,
373 Port2_SetGetNextDescDMA12,
374 Port2_DMA13_inc_head,
375 Port2_DMA13_reset_done,
376 Port2_DMA13_mark_bit,
377 Port2_DMA13_inc_pkt_cnt,
378 Port2_SetGetNextDescDMA13,
379 Port2_DMA14_inc_head,
380 Port2_DMA14_reset_done,
381 Port2_DMA14_mark_bit,
382 Port2_DMA14_inc_pkt_cnt,
383 Port2_SetGetNextDescDMA14,
384 Port2_DMA15_inc_head,
385 Port2_DMA15_reset_done,
386 Port2_DMA15_mark_bit,
387 Port2_DMA15_inc_pkt_cnt,
388 Port2_SetGetNextDescDMA15,
389 Port2_DMA16_inc_head,
390 Port2_DMA16_reset_done,
391 Port2_DMA16_mark_bit,
392 Port2_DMA16_inc_pkt_cnt,
393 Port2_SetGetNextDescDMA16,
394 Port2_DMA17_inc_head,
395 Port2_DMA17_reset_done,
396 Port2_DMA17_mark_bit,
397 Port2_DMA17_inc_pkt_cnt,
398 Port2_SetGetNextDescDMA17,
399 Port2_DMA18_inc_head,
400 Port2_DMA18_reset_done,
401 Port2_DMA18_mark_bit,
402 Port2_DMA18_inc_pkt_cnt,
403 Port2_SetGetNextDescDMA18,
404 Port2_DMA19_inc_head,
405 Port2_DMA19_reset_done,
406 Port2_DMA19_mark_bit,
407 Port2_DMA19_inc_pkt_cnt,
408 Port2_SetGetNextDescDMA19,
409 Port2_DMA20_inc_head,
410 Port2_DMA20_reset_done,
411 Port2_DMA20_mark_bit,
412 Port2_DMA20_inc_pkt_cnt,
413 Port2_SetGetNextDescDMA20,
414 Port2_DMA21_inc_head,
415 Port2_DMA21_reset_done,
416 Port2_DMA21_mark_bit,
417 Port2_DMA21_inc_pkt_cnt,
418 Port2_SetGetNextDescDMA21,
419 Port2_DMA22_inc_head,
420 Port2_DMA22_reset_done,
421 Port2_DMA22_mark_bit,
422 Port2_DMA22_inc_pkt_cnt,
423 Port2_SetGetNextDescDMA22,
424 Port2_DMA23_inc_head,
425 Port2_DMA23_reset_done,
426 Port2_DMA23_mark_bit,
427 Port2_DMA23_inc_pkt_cnt,
428 Port2_SetGetNextDescDMA23,
429 Port3_Nack_Pkt_Rd,
430 Port3_DMA_Nack_Pkt_Rd,
431 Port3_Nack_Pkt_Rd_Addr,
432 Port3_DMA0_inc_head,
433 Port3_DMA0_reset_done,
434 Port3_DMA0_mark_bit,
435 Port3_DMA0_inc_pkt_cnt,
436 Port3_SetGetNextDescDMA0,
437 Port3_DMA1_inc_head,
438 Port3_DMA1_reset_done,
439 Port3_DMA1_mark_bit,
440 Port3_DMA1_inc_pkt_cnt,
441 Port3_SetGetNextDescDMA1,
442 Port3_DMA2_inc_head,
443 Port3_DMA2_reset_done,
444 Port3_DMA2_mark_bit,
445 Port3_DMA2_inc_pkt_cnt,
446 Port3_SetGetNextDescDMA2,
447 Port3_DMA3_inc_head,
448 Port3_DMA3_reset_done,
449 Port3_DMA3_mark_bit,
450 Port3_DMA3_inc_pkt_cnt,
451 Port3_SetGetNextDescDMA3,
452 Port3_DMA4_inc_head,
453 Port3_DMA4_reset_done,
454 Port3_DMA4_mark_bit,
455 Port3_DMA4_inc_pkt_cnt,
456 Port3_SetGetNextDescDMA4,
457 Port3_DMA5_inc_head,
458 Port3_DMA5_reset_done,
459 Port3_DMA5_mark_bit,
460 Port3_DMA5_inc_pkt_cnt,
461 Port3_SetGetNextDescDMA5,
462 Port3_DMA6_inc_head,
463 Port3_DMA6_reset_done,
464 Port3_DMA6_mark_bit,
465 Port3_DMA6_inc_pkt_cnt,
466 Port3_SetGetNextDescDMA6,
467 Port3_DMA7_inc_head,
468 Port3_DMA7_reset_done,
469 Port3_DMA7_mark_bit,
470 Port3_DMA7_inc_pkt_cnt,
471 Port3_SetGetNextDescDMA7,
472 Port3_DMA8_inc_head,
473 Port3_DMA8_reset_done,
474 Port3_DMA8_mark_bit,
475 Port3_DMA8_inc_pkt_cnt,
476 Port3_SetGetNextDescDMA8,
477 Port3_DMA9_inc_head,
478 Port3_DMA9_reset_done,
479 Port3_DMA9_mark_bit,
480 Port3_DMA9_inc_pkt_cnt,
481 Port3_SetGetNextDescDMA9,
482 Port3_DMA10_inc_head,
483 Port3_DMA10_reset_done,
484 Port3_DMA10_mark_bit,
485 Port3_DMA10_inc_pkt_cnt,
486 Port3_SetGetNextDescDMA10,
487 Port3_DMA11_inc_head,
488 Port3_DMA11_reset_done,
489 Port3_DMA11_mark_bit,
490 Port3_DMA11_inc_pkt_cnt,
491 Port3_SetGetNextDescDMA11,
492 Port3_DMA12_inc_head,
493 Port3_DMA12_reset_done,
494 Port3_DMA12_mark_bit,
495 Port3_DMA12_inc_pkt_cnt,
496 Port3_SetGetNextDescDMA12,
497 Port3_DMA13_inc_head,
498 Port3_DMA13_reset_done,
499 Port3_DMA13_mark_bit,
500 Port3_DMA13_inc_pkt_cnt,
501 Port3_SetGetNextDescDMA13,
502 Port3_DMA14_inc_head,
503 Port3_DMA14_reset_done,
504 Port3_DMA14_mark_bit,
505 Port3_DMA14_inc_pkt_cnt,
506 Port3_SetGetNextDescDMA14,
507 Port3_DMA15_inc_head,
508 Port3_DMA15_reset_done,
509 Port3_DMA15_mark_bit,
510 Port3_DMA15_inc_pkt_cnt,
511 Port3_SetGetNextDescDMA15,
512 Port3_DMA16_inc_head,
513 Port3_DMA16_reset_done,
514 Port3_DMA16_mark_bit,
515 Port3_DMA16_inc_pkt_cnt,
516 Port3_SetGetNextDescDMA16,
517 Port3_DMA17_inc_head,
518 Port3_DMA17_reset_done,
519 Port3_DMA17_mark_bit,
520 Port3_DMA17_inc_pkt_cnt,
521 Port3_SetGetNextDescDMA17,
522 Port3_DMA18_inc_head,
523 Port3_DMA18_reset_done,
524 Port3_DMA18_mark_bit,
525 Port3_DMA18_inc_pkt_cnt,
526 Port3_SetGetNextDescDMA18,
527 Port3_DMA19_inc_head,
528 Port3_DMA19_reset_done,
529 Port3_DMA19_mark_bit,
530 Port3_DMA19_inc_pkt_cnt,
531 Port3_SetGetNextDescDMA19,
532 Port3_DMA20_inc_head,
533 Port3_DMA20_reset_done,
534 Port3_DMA20_mark_bit,
535 Port3_DMA20_inc_pkt_cnt,
536 Port3_SetGetNextDescDMA20,
537 Port3_DMA21_inc_head,
538 Port3_DMA21_reset_done,
539 Port3_DMA21_mark_bit,
540 Port3_DMA21_inc_pkt_cnt,
541 Port3_SetGetNextDescDMA21,
542 Port3_DMA22_inc_head,
543 Port3_DMA22_reset_done,
544 Port3_DMA22_mark_bit,
545 Port3_DMA22_inc_pkt_cnt,
546 Port3_SetGetNextDescDMA22,
547 Port3_DMA23_inc_head,
548 Port3_DMA23_reset_done,
549 Port3_DMA23_mark_bit,
550 Port3_DMA23_inc_pkt_cnt,
551 Port3_SetGetNextDescDMA23,
552 TXC_DMC_Nack_Pkt_Rd,
553 TXC_DMC_DMA_Nack_Pkt_Rd,
554 TXC_DMC_Nack_Pkt_Rd_Addr,
555 DMC_TXC_DMA0_GotNxtDesc,
556 TXC_DMC_DMA0_GetNxtDesc,
557 TXC_DMC_DMA0_inc_head,
558 TXC_DMC_DMA0_reset_done,
559 TXC_DMC_DMA0_mark_bit,
560 TXC_DMC_DMA0_inc_pkt_cnt,
561 DMC_TXC_DMA1_GotNxtDesc,
562 TXC_DMC_DMA1_GetNxtDesc,
563 TXC_DMC_DMA1_inc_head,
564 TXC_DMC_DMA1_reset_done,
565 TXC_DMC_DMA1_mark_bit,
566 TXC_DMC_DMA1_inc_pkt_cnt,
567 DMC_TXC_DMA2_GotNxtDesc,
568 TXC_DMC_DMA2_GetNxtDesc,
569 TXC_DMC_DMA2_inc_head,
570 TXC_DMC_DMA2_reset_done,
571 TXC_DMC_DMA2_mark_bit,
572 TXC_DMC_DMA2_inc_pkt_cnt,
573 DMC_TXC_DMA3_GotNxtDesc,
574 TXC_DMC_DMA3_GetNxtDesc,
575 TXC_DMC_DMA3_inc_head,
576 TXC_DMC_DMA3_reset_done,
577 TXC_DMC_DMA3_mark_bit,
578 TXC_DMC_DMA3_inc_pkt_cnt,
579 DMC_TXC_DMA4_GotNxtDesc,
580 TXC_DMC_DMA4_GetNxtDesc,
581 TXC_DMC_DMA4_inc_head,
582 TXC_DMC_DMA4_reset_done,
583 TXC_DMC_DMA4_mark_bit,
584 TXC_DMC_DMA4_inc_pkt_cnt,
585 DMC_TXC_DMA5_GotNxtDesc,
586 TXC_DMC_DMA5_GetNxtDesc,
587 TXC_DMC_DMA5_inc_head,
588 TXC_DMC_DMA5_reset_done,
589 TXC_DMC_DMA5_mark_bit,
590 TXC_DMC_DMA5_inc_pkt_cnt,
591 DMC_TXC_DMA6_GotNxtDesc,
592 TXC_DMC_DMA6_GetNxtDesc,
593 TXC_DMC_DMA6_inc_head,
594 TXC_DMC_DMA6_reset_done,
595 TXC_DMC_DMA6_mark_bit,
596 TXC_DMC_DMA6_inc_pkt_cnt,
597 DMC_TXC_DMA7_GotNxtDesc,
598 TXC_DMC_DMA7_GetNxtDesc,
599 TXC_DMC_DMA7_inc_head,
600 TXC_DMC_DMA7_reset_done,
601 TXC_DMC_DMA7_mark_bit,
602 TXC_DMC_DMA7_inc_pkt_cnt,
603 DMC_TXC_DMA8_GotNxtDesc,
604 TXC_DMC_DMA8_GetNxtDesc,
605 TXC_DMC_DMA8_inc_head,
606 TXC_DMC_DMA8_reset_done,
607 TXC_DMC_DMA8_mark_bit,
608 TXC_DMC_DMA8_inc_pkt_cnt,
609 DMC_TXC_DMA9_GotNxtDesc,
610 TXC_DMC_DMA9_GetNxtDesc,
611 TXC_DMC_DMA9_inc_head,
612 TXC_DMC_DMA9_reset_done,
613 TXC_DMC_DMA9_mark_bit,
614 TXC_DMC_DMA9_inc_pkt_cnt,
615 DMC_TXC_DMA10_GotNxtDesc,
616 TXC_DMC_DMA10_GetNxtDesc,
617 TXC_DMC_DMA10_inc_head,
618 TXC_DMC_DMA10_reset_done,
619 TXC_DMC_DMA10_mark_bit,
620 TXC_DMC_DMA10_inc_pkt_cnt,
621 DMC_TXC_DMA11_GotNxtDesc,
622 TXC_DMC_DMA11_GetNxtDesc,
623 TXC_DMC_DMA11_inc_head,
624 TXC_DMC_DMA11_reset_done,
625 TXC_DMC_DMA11_mark_bit,
626 TXC_DMC_DMA11_inc_pkt_cnt,
627 DMC_TXC_DMA12_GotNxtDesc,
628 TXC_DMC_DMA12_GetNxtDesc,
629 TXC_DMC_DMA12_inc_head,
630 TXC_DMC_DMA12_reset_done,
631 TXC_DMC_DMA12_mark_bit,
632 TXC_DMC_DMA12_inc_pkt_cnt,
633 DMC_TXC_DMA13_GotNxtDesc,
634 TXC_DMC_DMA13_GetNxtDesc,
635 TXC_DMC_DMA13_inc_head,
636 TXC_DMC_DMA13_reset_done,
637 TXC_DMC_DMA13_mark_bit,
638 TXC_DMC_DMA13_inc_pkt_cnt,
639 DMC_TXC_DMA14_GotNxtDesc,
640 TXC_DMC_DMA14_GetNxtDesc,
641 TXC_DMC_DMA14_inc_head,
642 TXC_DMC_DMA14_reset_done,
643 TXC_DMC_DMA14_mark_bit,
644 TXC_DMC_DMA14_inc_pkt_cnt,
645 DMC_TXC_DMA15_GotNxtDesc,
646 TXC_DMC_DMA15_GetNxtDesc,
647 TXC_DMC_DMA15_inc_head,
648 TXC_DMC_DMA15_reset_done,
649 TXC_DMC_DMA15_mark_bit,
650 TXC_DMC_DMA15_inc_pkt_cnt,
651 DMC_TXC_DMA16_GotNxtDesc,
652 TXC_DMC_DMA16_GetNxtDesc,
653 TXC_DMC_DMA16_inc_head,
654 TXC_DMC_DMA16_reset_done,
655 TXC_DMC_DMA16_mark_bit,
656 TXC_DMC_DMA16_inc_pkt_cnt,
657 DMC_TXC_DMA17_GotNxtDesc,
658 TXC_DMC_DMA17_GetNxtDesc,
659 TXC_DMC_DMA17_inc_head,
660 TXC_DMC_DMA17_reset_done,
661 TXC_DMC_DMA17_mark_bit,
662 TXC_DMC_DMA17_inc_pkt_cnt,
663 DMC_TXC_DMA18_GotNxtDesc,
664 TXC_DMC_DMA18_GetNxtDesc,
665 TXC_DMC_DMA18_inc_head,
666 TXC_DMC_DMA18_reset_done,
667 TXC_DMC_DMA18_mark_bit,
668 TXC_DMC_DMA18_inc_pkt_cnt,
669 DMC_TXC_DMA19_GotNxtDesc,
670 TXC_DMC_DMA19_GetNxtDesc,
671 TXC_DMC_DMA19_inc_head,
672 TXC_DMC_DMA19_reset_done,
673 TXC_DMC_DMA19_mark_bit,
674 TXC_DMC_DMA19_inc_pkt_cnt,
675 DMC_TXC_DMA20_GotNxtDesc,
676 TXC_DMC_DMA20_GetNxtDesc,
677 TXC_DMC_DMA20_inc_head,
678 TXC_DMC_DMA20_reset_done,
679 TXC_DMC_DMA20_mark_bit,
680 TXC_DMC_DMA20_inc_pkt_cnt,
681 DMC_TXC_DMA21_GotNxtDesc,
682 TXC_DMC_DMA21_GetNxtDesc,
683 TXC_DMC_DMA21_inc_head,
684 TXC_DMC_DMA21_reset_done,
685 TXC_DMC_DMA21_mark_bit,
686 TXC_DMC_DMA21_inc_pkt_cnt,
687 DMC_TXC_DMA22_GotNxtDesc,
688 TXC_DMC_DMA22_GetNxtDesc,
689 TXC_DMC_DMA22_inc_head,
690 TXC_DMC_DMA22_reset_done,
691 TXC_DMC_DMA22_mark_bit,
692 TXC_DMC_DMA22_inc_pkt_cnt,
693 DMC_TXC_DMA23_GotNxtDesc,
694 TXC_DMC_DMA23_GetNxtDesc,
695 TXC_DMC_DMA23_inc_head,
696 TXC_DMC_DMA23_reset_done,
697 TXC_DMC_DMA23_mark_bit,
698 TXC_DMC_DMA23_inc_pkt_cnt
699 );
700
701`include "txc_defines.h"
702
703// Global Signals
704input SysClk;
705input Reset_L;
706
707// Port 0 DMA Signals
708input Port0_Nack_Pkt_Rd;
709input [23:0] Port0_DMA_Nack_Pkt_Rd;
710input [43:0] Port0_Nack_Pkt_Rd_Addr;
711
712input Port0_DMA0_inc_head;
713input Port0_DMA0_reset_done;
714input Port0_DMA0_mark_bit;
715input Port0_DMA0_inc_pkt_cnt;
716input Port0_SetGetNextDescDMA0;
717
718input Port0_DMA1_inc_head;
719input Port0_DMA1_reset_done;
720input Port0_DMA1_mark_bit;
721input Port0_DMA1_inc_pkt_cnt;
722input Port0_SetGetNextDescDMA1;
723
724input Port0_DMA2_inc_head;
725input Port0_DMA2_reset_done;
726input Port0_DMA2_mark_bit;
727input Port0_DMA2_inc_pkt_cnt;
728input Port0_SetGetNextDescDMA2;
729
730input Port0_DMA3_inc_head;
731input Port0_DMA3_reset_done;
732input Port0_DMA3_mark_bit;
733input Port0_DMA3_inc_pkt_cnt;
734input Port0_SetGetNextDescDMA3;
735
736input Port0_DMA4_inc_head;
737input Port0_DMA4_reset_done;
738input Port0_DMA4_mark_bit;
739input Port0_DMA4_inc_pkt_cnt;
740input Port0_SetGetNextDescDMA4;
741
742input Port0_DMA5_inc_head;
743input Port0_DMA5_reset_done;
744input Port0_DMA5_mark_bit;
745input Port0_DMA5_inc_pkt_cnt;
746input Port0_SetGetNextDescDMA5;
747
748input Port0_DMA6_inc_head;
749input Port0_DMA6_reset_done;
750input Port0_DMA6_mark_bit;
751input Port0_DMA6_inc_pkt_cnt;
752input Port0_SetGetNextDescDMA6;
753
754input Port0_DMA7_inc_head;
755input Port0_DMA7_reset_done;
756input Port0_DMA7_mark_bit;
757input Port0_DMA7_inc_pkt_cnt;
758input Port0_SetGetNextDescDMA7;
759
760input Port0_DMA8_inc_head;
761input Port0_DMA8_reset_done;
762input Port0_DMA8_mark_bit;
763input Port0_DMA8_inc_pkt_cnt;
764input Port0_SetGetNextDescDMA8;
765
766input Port0_DMA9_inc_head;
767input Port0_DMA9_reset_done;
768input Port0_DMA9_mark_bit;
769input Port0_DMA9_inc_pkt_cnt;
770input Port0_SetGetNextDescDMA9;
771
772input Port0_DMA10_inc_head;
773input Port0_DMA10_reset_done;
774input Port0_DMA10_mark_bit;
775input Port0_DMA10_inc_pkt_cnt;
776input Port0_SetGetNextDescDMA10;
777
778input Port0_DMA11_inc_head;
779input Port0_DMA11_reset_done;
780input Port0_DMA11_mark_bit;
781input Port0_DMA11_inc_pkt_cnt;
782input Port0_SetGetNextDescDMA11;
783
784input Port0_DMA12_inc_head;
785input Port0_DMA12_reset_done;
786input Port0_DMA12_mark_bit;
787input Port0_DMA12_inc_pkt_cnt;
788input Port0_SetGetNextDescDMA12;
789
790input Port0_DMA13_inc_head;
791input Port0_DMA13_reset_done;
792input Port0_DMA13_mark_bit;
793input Port0_DMA13_inc_pkt_cnt;
794input Port0_SetGetNextDescDMA13;
795
796input Port0_DMA14_inc_head;
797input Port0_DMA14_reset_done;
798input Port0_DMA14_mark_bit;
799input Port0_DMA14_inc_pkt_cnt;
800input Port0_SetGetNextDescDMA14;
801
802input Port0_DMA15_inc_head;
803input Port0_DMA15_reset_done;
804input Port0_DMA15_mark_bit;
805input Port0_DMA15_inc_pkt_cnt;
806input Port0_SetGetNextDescDMA15;
807
808input Port0_DMA16_inc_head;
809input Port0_DMA16_reset_done;
810input Port0_DMA16_mark_bit;
811input Port0_DMA16_inc_pkt_cnt;
812input Port0_SetGetNextDescDMA16;
813
814input Port0_DMA17_inc_head;
815input Port0_DMA17_reset_done;
816input Port0_DMA17_mark_bit;
817input Port0_DMA17_inc_pkt_cnt;
818input Port0_SetGetNextDescDMA17;
819
820input Port0_DMA18_inc_head;
821input Port0_DMA18_reset_done;
822input Port0_DMA18_mark_bit;
823input Port0_DMA18_inc_pkt_cnt;
824input Port0_SetGetNextDescDMA18;
825
826input Port0_DMA19_inc_head;
827input Port0_DMA19_reset_done;
828input Port0_DMA19_mark_bit;
829input Port0_DMA19_inc_pkt_cnt;
830input Port0_SetGetNextDescDMA19;
831
832input Port0_DMA20_inc_head;
833input Port0_DMA20_reset_done;
834input Port0_DMA20_mark_bit;
835input Port0_DMA20_inc_pkt_cnt;
836input Port0_SetGetNextDescDMA20;
837
838input Port0_DMA21_inc_head;
839input Port0_DMA21_reset_done;
840input Port0_DMA21_mark_bit;
841input Port0_DMA21_inc_pkt_cnt;
842input Port0_SetGetNextDescDMA21;
843
844input Port0_DMA22_inc_head;
845input Port0_DMA22_reset_done;
846input Port0_DMA22_mark_bit;
847input Port0_DMA22_inc_pkt_cnt;
848input Port0_SetGetNextDescDMA22;
849
850input Port0_DMA23_inc_head;
851input Port0_DMA23_reset_done;
852input Port0_DMA23_mark_bit;
853input Port0_DMA23_inc_pkt_cnt;
854input Port0_SetGetNextDescDMA23;
855
856// Port 1 DMA Signals
857input Port1_Nack_Pkt_Rd;
858input [23:0] Port1_DMA_Nack_Pkt_Rd;
859input [43:0] Port1_Nack_Pkt_Rd_Addr;
860
861input Port1_DMA0_inc_head;
862input Port1_DMA0_reset_done;
863input Port1_DMA0_mark_bit;
864input Port1_DMA0_inc_pkt_cnt;
865input Port1_SetGetNextDescDMA0;
866
867input Port1_DMA1_inc_head;
868input Port1_DMA1_reset_done;
869input Port1_DMA1_mark_bit;
870input Port1_DMA1_inc_pkt_cnt;
871input Port1_SetGetNextDescDMA1;
872
873input Port1_DMA2_inc_head;
874input Port1_DMA2_reset_done;
875input Port1_DMA2_mark_bit;
876input Port1_DMA2_inc_pkt_cnt;
877input Port1_SetGetNextDescDMA2;
878
879input Port1_DMA3_inc_head;
880input Port1_DMA3_reset_done;
881input Port1_DMA3_mark_bit;
882input Port1_DMA3_inc_pkt_cnt;
883input Port1_SetGetNextDescDMA3;
884
885input Port1_DMA4_inc_head;
886input Port1_DMA4_reset_done;
887input Port1_DMA4_mark_bit;
888input Port1_DMA4_inc_pkt_cnt;
889input Port1_SetGetNextDescDMA4;
890
891input Port1_DMA5_inc_head;
892input Port1_DMA5_reset_done;
893input Port1_DMA5_mark_bit;
894input Port1_DMA5_inc_pkt_cnt;
895input Port1_SetGetNextDescDMA5;
896
897input Port1_DMA6_inc_head;
898input Port1_DMA6_reset_done;
899input Port1_DMA6_mark_bit;
900input Port1_DMA6_inc_pkt_cnt;
901input Port1_SetGetNextDescDMA6;
902
903input Port1_DMA7_inc_head;
904input Port1_DMA7_reset_done;
905input Port1_DMA7_mark_bit;
906input Port1_DMA7_inc_pkt_cnt;
907input Port1_SetGetNextDescDMA7;
908
909input Port1_DMA8_inc_head;
910input Port1_DMA8_reset_done;
911input Port1_DMA8_mark_bit;
912input Port1_DMA8_inc_pkt_cnt;
913input Port1_SetGetNextDescDMA8;
914
915input Port1_DMA9_inc_head;
916input Port1_DMA9_reset_done;
917input Port1_DMA9_mark_bit;
918input Port1_DMA9_inc_pkt_cnt;
919input Port1_SetGetNextDescDMA9;
920
921input Port1_DMA10_inc_head;
922input Port1_DMA10_reset_done;
923input Port1_DMA10_mark_bit;
924input Port1_DMA10_inc_pkt_cnt;
925input Port1_SetGetNextDescDMA10;
926
927input Port1_DMA11_inc_head;
928input Port1_DMA11_reset_done;
929input Port1_DMA11_mark_bit;
930input Port1_DMA11_inc_pkt_cnt;
931input Port1_SetGetNextDescDMA11;
932
933input Port1_DMA12_inc_head;
934input Port1_DMA12_reset_done;
935input Port1_DMA12_mark_bit;
936input Port1_DMA12_inc_pkt_cnt;
937input Port1_SetGetNextDescDMA12;
938
939input Port1_DMA13_inc_head;
940input Port1_DMA13_reset_done;
941input Port1_DMA13_mark_bit;
942input Port1_DMA13_inc_pkt_cnt;
943input Port1_SetGetNextDescDMA13;
944
945input Port1_DMA14_inc_head;
946input Port1_DMA14_reset_done;
947input Port1_DMA14_mark_bit;
948input Port1_DMA14_inc_pkt_cnt;
949input Port1_SetGetNextDescDMA14;
950
951input Port1_DMA15_inc_head;
952input Port1_DMA15_reset_done;
953input Port1_DMA15_mark_bit;
954input Port1_DMA15_inc_pkt_cnt;
955input Port1_SetGetNextDescDMA15;
956
957input Port1_DMA16_inc_head;
958input Port1_DMA16_reset_done;
959input Port1_DMA16_mark_bit;
960input Port1_DMA16_inc_pkt_cnt;
961input Port1_SetGetNextDescDMA16;
962
963input Port1_DMA17_inc_head;
964input Port1_DMA17_reset_done;
965input Port1_DMA17_mark_bit;
966input Port1_DMA17_inc_pkt_cnt;
967input Port1_SetGetNextDescDMA17;
968
969input Port1_DMA18_inc_head;
970input Port1_DMA18_reset_done;
971input Port1_DMA18_mark_bit;
972input Port1_DMA18_inc_pkt_cnt;
973input Port1_SetGetNextDescDMA18;
974
975input Port1_DMA19_inc_head;
976input Port1_DMA19_reset_done;
977input Port1_DMA19_mark_bit;
978input Port1_DMA19_inc_pkt_cnt;
979input Port1_SetGetNextDescDMA19;
980
981input Port1_DMA20_inc_head;
982input Port1_DMA20_reset_done;
983input Port1_DMA20_mark_bit;
984input Port1_DMA20_inc_pkt_cnt;
985input Port1_SetGetNextDescDMA20;
986
987input Port1_DMA21_inc_head;
988input Port1_DMA21_reset_done;
989input Port1_DMA21_mark_bit;
990input Port1_DMA21_inc_pkt_cnt;
991input Port1_SetGetNextDescDMA21;
992
993input Port1_DMA22_inc_head;
994input Port1_DMA22_reset_done;
995input Port1_DMA22_mark_bit;
996input Port1_DMA22_inc_pkt_cnt;
997input Port1_SetGetNextDescDMA22;
998
999input Port1_DMA23_inc_head;
1000input Port1_DMA23_reset_done;
1001input Port1_DMA23_mark_bit;
1002input Port1_DMA23_inc_pkt_cnt;
1003input Port1_SetGetNextDescDMA23;
1004
1005// Port 2 DMA Signals
1006input Port2_Nack_Pkt_Rd;
1007input [23:0] Port2_DMA_Nack_Pkt_Rd;
1008input [43:0] Port2_Nack_Pkt_Rd_Addr;
1009
1010input Port2_DMA0_inc_head;
1011input Port2_DMA0_reset_done;
1012input Port2_DMA0_mark_bit;
1013input Port2_DMA0_inc_pkt_cnt;
1014input Port2_SetGetNextDescDMA0;
1015
1016input Port2_DMA1_inc_head;
1017input Port2_DMA1_reset_done;
1018input Port2_DMA1_mark_bit;
1019input Port2_DMA1_inc_pkt_cnt;
1020input Port2_SetGetNextDescDMA1;
1021
1022input Port2_DMA2_inc_head;
1023input Port2_DMA2_reset_done;
1024input Port2_DMA2_mark_bit;
1025input Port2_DMA2_inc_pkt_cnt;
1026input Port2_SetGetNextDescDMA2;
1027
1028input Port2_DMA3_inc_head;
1029input Port2_DMA3_reset_done;
1030input Port2_DMA3_mark_bit;
1031input Port2_DMA3_inc_pkt_cnt;
1032input Port2_SetGetNextDescDMA3;
1033
1034input Port2_DMA4_inc_head;
1035input Port2_DMA4_reset_done;
1036input Port2_DMA4_mark_bit;
1037input Port2_DMA4_inc_pkt_cnt;
1038input Port2_SetGetNextDescDMA4;
1039
1040input Port2_DMA5_inc_head;
1041input Port2_DMA5_reset_done;
1042input Port2_DMA5_mark_bit;
1043input Port2_DMA5_inc_pkt_cnt;
1044input Port2_SetGetNextDescDMA5;
1045
1046input Port2_DMA6_inc_head;
1047input Port2_DMA6_reset_done;
1048input Port2_DMA6_mark_bit;
1049input Port2_DMA6_inc_pkt_cnt;
1050input Port2_SetGetNextDescDMA6;
1051
1052input Port2_DMA7_inc_head;
1053input Port2_DMA7_reset_done;
1054input Port2_DMA7_mark_bit;
1055input Port2_DMA7_inc_pkt_cnt;
1056input Port2_SetGetNextDescDMA7;
1057
1058input Port2_DMA8_inc_head;
1059input Port2_DMA8_reset_done;
1060input Port2_DMA8_mark_bit;
1061input Port2_DMA8_inc_pkt_cnt;
1062input Port2_SetGetNextDescDMA8;
1063
1064input Port2_DMA9_inc_head;
1065input Port2_DMA9_reset_done;
1066input Port2_DMA9_mark_bit;
1067input Port2_DMA9_inc_pkt_cnt;
1068input Port2_SetGetNextDescDMA9;
1069
1070input Port2_DMA10_inc_head;
1071input Port2_DMA10_reset_done;
1072input Port2_DMA10_mark_bit;
1073input Port2_DMA10_inc_pkt_cnt;
1074input Port2_SetGetNextDescDMA10;
1075
1076input Port2_DMA11_inc_head;
1077input Port2_DMA11_reset_done;
1078input Port2_DMA11_mark_bit;
1079input Port2_DMA11_inc_pkt_cnt;
1080input Port2_SetGetNextDescDMA11;
1081
1082input Port2_DMA12_inc_head;
1083input Port2_DMA12_reset_done;
1084input Port2_DMA12_mark_bit;
1085input Port2_DMA12_inc_pkt_cnt;
1086input Port2_SetGetNextDescDMA12;
1087
1088input Port2_DMA13_inc_head;
1089input Port2_DMA13_reset_done;
1090input Port2_DMA13_mark_bit;
1091input Port2_DMA13_inc_pkt_cnt;
1092input Port2_SetGetNextDescDMA13;
1093
1094input Port2_DMA14_inc_head;
1095input Port2_DMA14_reset_done;
1096input Port2_DMA14_mark_bit;
1097input Port2_DMA14_inc_pkt_cnt;
1098input Port2_SetGetNextDescDMA14;
1099
1100input Port2_DMA15_inc_head;
1101input Port2_DMA15_reset_done;
1102input Port2_DMA15_mark_bit;
1103input Port2_DMA15_inc_pkt_cnt;
1104input Port2_SetGetNextDescDMA15;
1105
1106input Port2_DMA16_inc_head;
1107input Port2_DMA16_reset_done;
1108input Port2_DMA16_mark_bit;
1109input Port2_DMA16_inc_pkt_cnt;
1110input Port2_SetGetNextDescDMA16;
1111
1112input Port2_DMA17_inc_head;
1113input Port2_DMA17_reset_done;
1114input Port2_DMA17_mark_bit;
1115input Port2_DMA17_inc_pkt_cnt;
1116input Port2_SetGetNextDescDMA17;
1117
1118input Port2_DMA18_inc_head;
1119input Port2_DMA18_reset_done;
1120input Port2_DMA18_mark_bit;
1121input Port2_DMA18_inc_pkt_cnt;
1122input Port2_SetGetNextDescDMA18;
1123
1124input Port2_DMA19_inc_head;
1125input Port2_DMA19_reset_done;
1126input Port2_DMA19_mark_bit;
1127input Port2_DMA19_inc_pkt_cnt;
1128input Port2_SetGetNextDescDMA19;
1129
1130input Port2_DMA20_inc_head;
1131input Port2_DMA20_reset_done;
1132input Port2_DMA20_mark_bit;
1133input Port2_DMA20_inc_pkt_cnt;
1134input Port2_SetGetNextDescDMA20;
1135
1136input Port2_DMA21_inc_head;
1137input Port2_DMA21_reset_done;
1138input Port2_DMA21_mark_bit;
1139input Port2_DMA21_inc_pkt_cnt;
1140input Port2_SetGetNextDescDMA21;
1141
1142input Port2_DMA22_inc_head;
1143input Port2_DMA22_reset_done;
1144input Port2_DMA22_mark_bit;
1145input Port2_DMA22_inc_pkt_cnt;
1146input Port2_SetGetNextDescDMA22;
1147
1148input Port2_DMA23_inc_head;
1149input Port2_DMA23_reset_done;
1150input Port2_DMA23_mark_bit;
1151input Port2_DMA23_inc_pkt_cnt;
1152input Port2_SetGetNextDescDMA23;
1153
1154// Port 3 DMA Signals
1155input Port3_Nack_Pkt_Rd;
1156input [23:0] Port3_DMA_Nack_Pkt_Rd;
1157input [43:0] Port3_Nack_Pkt_Rd_Addr;
1158
1159input Port3_DMA0_inc_head;
1160input Port3_DMA0_reset_done;
1161input Port3_DMA0_mark_bit;
1162input Port3_DMA0_inc_pkt_cnt;
1163input Port3_SetGetNextDescDMA0;
1164
1165input Port3_DMA1_inc_head;
1166input Port3_DMA1_reset_done;
1167input Port3_DMA1_mark_bit;
1168input Port3_DMA1_inc_pkt_cnt;
1169input Port3_SetGetNextDescDMA1;
1170
1171input Port3_DMA2_inc_head;
1172input Port3_DMA2_reset_done;
1173input Port3_DMA2_mark_bit;
1174input Port3_DMA2_inc_pkt_cnt;
1175input Port3_SetGetNextDescDMA2;
1176
1177input Port3_DMA3_inc_head;
1178input Port3_DMA3_reset_done;
1179input Port3_DMA3_mark_bit;
1180input Port3_DMA3_inc_pkt_cnt;
1181input Port3_SetGetNextDescDMA3;
1182
1183input Port3_DMA4_inc_head;
1184input Port3_DMA4_reset_done;
1185input Port3_DMA4_mark_bit;
1186input Port3_DMA4_inc_pkt_cnt;
1187input Port3_SetGetNextDescDMA4;
1188
1189input Port3_DMA5_inc_head;
1190input Port3_DMA5_reset_done;
1191input Port3_DMA5_mark_bit;
1192input Port3_DMA5_inc_pkt_cnt;
1193input Port3_SetGetNextDescDMA5;
1194
1195input Port3_DMA6_inc_head;
1196input Port3_DMA6_reset_done;
1197input Port3_DMA6_mark_bit;
1198input Port3_DMA6_inc_pkt_cnt;
1199input Port3_SetGetNextDescDMA6;
1200
1201input Port3_DMA7_inc_head;
1202input Port3_DMA7_reset_done;
1203input Port3_DMA7_mark_bit;
1204input Port3_DMA7_inc_pkt_cnt;
1205input Port3_SetGetNextDescDMA7;
1206
1207input Port3_DMA8_inc_head;
1208input Port3_DMA8_reset_done;
1209input Port3_DMA8_mark_bit;
1210input Port3_DMA8_inc_pkt_cnt;
1211input Port3_SetGetNextDescDMA8;
1212
1213input Port3_DMA9_inc_head;
1214input Port3_DMA9_reset_done;
1215input Port3_DMA9_mark_bit;
1216input Port3_DMA9_inc_pkt_cnt;
1217input Port3_SetGetNextDescDMA9;
1218
1219input Port3_DMA10_inc_head;
1220input Port3_DMA10_reset_done;
1221input Port3_DMA10_mark_bit;
1222input Port3_DMA10_inc_pkt_cnt;
1223input Port3_SetGetNextDescDMA10;
1224
1225input Port3_DMA11_inc_head;
1226input Port3_DMA11_reset_done;
1227input Port3_DMA11_mark_bit;
1228input Port3_DMA11_inc_pkt_cnt;
1229input Port3_SetGetNextDescDMA11;
1230
1231input Port3_DMA12_inc_head;
1232input Port3_DMA12_reset_done;
1233input Port3_DMA12_mark_bit;
1234input Port3_DMA12_inc_pkt_cnt;
1235input Port3_SetGetNextDescDMA12;
1236
1237input Port3_DMA13_inc_head;
1238input Port3_DMA13_reset_done;
1239input Port3_DMA13_mark_bit;
1240input Port3_DMA13_inc_pkt_cnt;
1241input Port3_SetGetNextDescDMA13;
1242
1243input Port3_DMA14_inc_head;
1244input Port3_DMA14_reset_done;
1245input Port3_DMA14_mark_bit;
1246input Port3_DMA14_inc_pkt_cnt;
1247input Port3_SetGetNextDescDMA14;
1248
1249input Port3_DMA15_inc_head;
1250input Port3_DMA15_reset_done;
1251input Port3_DMA15_mark_bit;
1252input Port3_DMA15_inc_pkt_cnt;
1253input Port3_SetGetNextDescDMA15;
1254
1255input Port3_DMA16_inc_head;
1256input Port3_DMA16_reset_done;
1257input Port3_DMA16_mark_bit;
1258input Port3_DMA16_inc_pkt_cnt;
1259input Port3_SetGetNextDescDMA16;
1260
1261input Port3_DMA17_inc_head;
1262input Port3_DMA17_reset_done;
1263input Port3_DMA17_mark_bit;
1264input Port3_DMA17_inc_pkt_cnt;
1265input Port3_SetGetNextDescDMA17;
1266
1267input Port3_DMA18_inc_head;
1268input Port3_DMA18_reset_done;
1269input Port3_DMA18_mark_bit;
1270input Port3_DMA18_inc_pkt_cnt;
1271input Port3_SetGetNextDescDMA18;
1272
1273input Port3_DMA19_inc_head;
1274input Port3_DMA19_reset_done;
1275input Port3_DMA19_mark_bit;
1276input Port3_DMA19_inc_pkt_cnt;
1277input Port3_SetGetNextDescDMA19;
1278
1279input Port3_DMA20_inc_head;
1280input Port3_DMA20_reset_done;
1281input Port3_DMA20_mark_bit;
1282input Port3_DMA20_inc_pkt_cnt;
1283input Port3_SetGetNextDescDMA20;
1284
1285input Port3_DMA21_inc_head;
1286input Port3_DMA21_reset_done;
1287input Port3_DMA21_mark_bit;
1288input Port3_DMA21_inc_pkt_cnt;
1289input Port3_SetGetNextDescDMA21;
1290
1291input Port3_DMA22_inc_head;
1292input Port3_DMA22_reset_done;
1293input Port3_DMA22_mark_bit;
1294input Port3_DMA22_inc_pkt_cnt;
1295input Port3_SetGetNextDescDMA22;
1296
1297input Port3_DMA23_inc_head;
1298input Port3_DMA23_reset_done;
1299input Port3_DMA23_mark_bit;
1300input Port3_DMA23_inc_pkt_cnt;
1301input Port3_SetGetNextDescDMA23;
1302
1303// TXC To TDMC Error Interface Signals
1304output TXC_DMC_Nack_Pkt_Rd;
1305output [23:0] TXC_DMC_DMA_Nack_Pkt_Rd;
1306output [43:0] TXC_DMC_Nack_Pkt_Rd_Addr;
1307
1308// TXC To TDMC DMA Interface Signals
1309input DMC_TXC_DMA0_GotNxtDesc;
1310
1311output TXC_DMC_DMA0_GetNxtDesc;
1312output TXC_DMC_DMA0_inc_head;
1313output TXC_DMC_DMA0_reset_done;
1314output TXC_DMC_DMA0_mark_bit;
1315output TXC_DMC_DMA0_inc_pkt_cnt;
1316
1317input DMC_TXC_DMA1_GotNxtDesc;
1318
1319output TXC_DMC_DMA1_GetNxtDesc;
1320output TXC_DMC_DMA1_inc_head;
1321output TXC_DMC_DMA1_reset_done;
1322output TXC_DMC_DMA1_mark_bit;
1323output TXC_DMC_DMA1_inc_pkt_cnt;
1324
1325input DMC_TXC_DMA2_GotNxtDesc;
1326
1327output TXC_DMC_DMA2_GetNxtDesc;
1328output TXC_DMC_DMA2_inc_head;
1329output TXC_DMC_DMA2_reset_done;
1330output TXC_DMC_DMA2_mark_bit;
1331output TXC_DMC_DMA2_inc_pkt_cnt;
1332
1333input DMC_TXC_DMA3_GotNxtDesc;
1334
1335output TXC_DMC_DMA3_GetNxtDesc;
1336output TXC_DMC_DMA3_inc_head;
1337output TXC_DMC_DMA3_reset_done;
1338output TXC_DMC_DMA3_mark_bit;
1339output TXC_DMC_DMA3_inc_pkt_cnt;
1340
1341input DMC_TXC_DMA4_GotNxtDesc;
1342
1343output TXC_DMC_DMA4_GetNxtDesc;
1344output TXC_DMC_DMA4_inc_head;
1345output TXC_DMC_DMA4_reset_done;
1346output TXC_DMC_DMA4_mark_bit;
1347output TXC_DMC_DMA4_inc_pkt_cnt;
1348
1349input DMC_TXC_DMA5_GotNxtDesc;
1350
1351output TXC_DMC_DMA5_GetNxtDesc;
1352output TXC_DMC_DMA5_inc_head;
1353output TXC_DMC_DMA5_reset_done;
1354output TXC_DMC_DMA5_mark_bit;
1355output TXC_DMC_DMA5_inc_pkt_cnt;
1356
1357input DMC_TXC_DMA6_GotNxtDesc;
1358
1359output TXC_DMC_DMA6_GetNxtDesc;
1360output TXC_DMC_DMA6_inc_head;
1361output TXC_DMC_DMA6_reset_done;
1362output TXC_DMC_DMA6_mark_bit;
1363output TXC_DMC_DMA6_inc_pkt_cnt;
1364
1365input DMC_TXC_DMA7_GotNxtDesc;
1366
1367output TXC_DMC_DMA7_GetNxtDesc;
1368output TXC_DMC_DMA7_inc_head;
1369output TXC_DMC_DMA7_reset_done;
1370output TXC_DMC_DMA7_mark_bit;
1371output TXC_DMC_DMA7_inc_pkt_cnt;
1372
1373input DMC_TXC_DMA8_GotNxtDesc;
1374
1375output TXC_DMC_DMA8_GetNxtDesc;
1376output TXC_DMC_DMA8_inc_head;
1377output TXC_DMC_DMA8_reset_done;
1378output TXC_DMC_DMA8_mark_bit;
1379output TXC_DMC_DMA8_inc_pkt_cnt;
1380
1381input DMC_TXC_DMA9_GotNxtDesc;
1382
1383output TXC_DMC_DMA9_GetNxtDesc;
1384output TXC_DMC_DMA9_inc_head;
1385output TXC_DMC_DMA9_reset_done;
1386output TXC_DMC_DMA9_mark_bit;
1387output TXC_DMC_DMA9_inc_pkt_cnt;
1388
1389input DMC_TXC_DMA10_GotNxtDesc;
1390
1391output TXC_DMC_DMA10_GetNxtDesc;
1392output TXC_DMC_DMA10_inc_head;
1393output TXC_DMC_DMA10_reset_done;
1394output TXC_DMC_DMA10_mark_bit;
1395output TXC_DMC_DMA10_inc_pkt_cnt;
1396
1397input DMC_TXC_DMA11_GotNxtDesc;
1398
1399output TXC_DMC_DMA11_GetNxtDesc;
1400output TXC_DMC_DMA11_inc_head;
1401output TXC_DMC_DMA11_reset_done;
1402output TXC_DMC_DMA11_mark_bit;
1403output TXC_DMC_DMA11_inc_pkt_cnt;
1404
1405input DMC_TXC_DMA12_GotNxtDesc;
1406
1407output TXC_DMC_DMA12_GetNxtDesc;
1408output TXC_DMC_DMA12_inc_head;
1409output TXC_DMC_DMA12_reset_done;
1410output TXC_DMC_DMA12_mark_bit;
1411output TXC_DMC_DMA12_inc_pkt_cnt;
1412
1413input DMC_TXC_DMA13_GotNxtDesc;
1414
1415output TXC_DMC_DMA13_GetNxtDesc;
1416output TXC_DMC_DMA13_inc_head;
1417output TXC_DMC_DMA13_reset_done;
1418output TXC_DMC_DMA13_mark_bit;
1419output TXC_DMC_DMA13_inc_pkt_cnt;
1420
1421input DMC_TXC_DMA14_GotNxtDesc;
1422
1423output TXC_DMC_DMA14_GetNxtDesc;
1424output TXC_DMC_DMA14_inc_head;
1425output TXC_DMC_DMA14_reset_done;
1426output TXC_DMC_DMA14_mark_bit;
1427output TXC_DMC_DMA14_inc_pkt_cnt;
1428
1429input DMC_TXC_DMA15_GotNxtDesc;
1430
1431output TXC_DMC_DMA15_GetNxtDesc;
1432output TXC_DMC_DMA15_inc_head;
1433output TXC_DMC_DMA15_reset_done;
1434output TXC_DMC_DMA15_mark_bit;
1435output TXC_DMC_DMA15_inc_pkt_cnt;
1436
1437input DMC_TXC_DMA16_GotNxtDesc;
1438
1439output TXC_DMC_DMA16_GetNxtDesc;
1440output TXC_DMC_DMA16_inc_head;
1441output TXC_DMC_DMA16_reset_done;
1442output TXC_DMC_DMA16_mark_bit;
1443output TXC_DMC_DMA16_inc_pkt_cnt;
1444
1445input DMC_TXC_DMA17_GotNxtDesc;
1446
1447output TXC_DMC_DMA17_GetNxtDesc;
1448output TXC_DMC_DMA17_inc_head;
1449output TXC_DMC_DMA17_reset_done;
1450output TXC_DMC_DMA17_mark_bit;
1451output TXC_DMC_DMA17_inc_pkt_cnt;
1452
1453input DMC_TXC_DMA18_GotNxtDesc;
1454
1455output TXC_DMC_DMA18_GetNxtDesc;
1456output TXC_DMC_DMA18_inc_head;
1457output TXC_DMC_DMA18_reset_done;
1458output TXC_DMC_DMA18_mark_bit;
1459output TXC_DMC_DMA18_inc_pkt_cnt;
1460
1461input DMC_TXC_DMA19_GotNxtDesc;
1462
1463output TXC_DMC_DMA19_GetNxtDesc;
1464output TXC_DMC_DMA19_inc_head;
1465output TXC_DMC_DMA19_reset_done;
1466output TXC_DMC_DMA19_mark_bit;
1467output TXC_DMC_DMA19_inc_pkt_cnt;
1468
1469input DMC_TXC_DMA20_GotNxtDesc;
1470
1471output TXC_DMC_DMA20_GetNxtDesc;
1472output TXC_DMC_DMA20_inc_head;
1473output TXC_DMC_DMA20_reset_done;
1474output TXC_DMC_DMA20_mark_bit;
1475output TXC_DMC_DMA20_inc_pkt_cnt;
1476
1477input DMC_TXC_DMA21_GotNxtDesc;
1478
1479output TXC_DMC_DMA21_GetNxtDesc;
1480output TXC_DMC_DMA21_inc_head;
1481output TXC_DMC_DMA21_reset_done;
1482output TXC_DMC_DMA21_mark_bit;
1483output TXC_DMC_DMA21_inc_pkt_cnt;
1484
1485input DMC_TXC_DMA22_GotNxtDesc;
1486
1487output TXC_DMC_DMA22_GetNxtDesc;
1488output TXC_DMC_DMA22_inc_head;
1489output TXC_DMC_DMA22_reset_done;
1490output TXC_DMC_DMA22_mark_bit;
1491output TXC_DMC_DMA22_inc_pkt_cnt;
1492
1493input DMC_TXC_DMA23_GotNxtDesc;
1494
1495output TXC_DMC_DMA23_GetNxtDesc;
1496output TXC_DMC_DMA23_inc_head;
1497output TXC_DMC_DMA23_reset_done;
1498output TXC_DMC_DMA23_mark_bit;
1499output TXC_DMC_DMA23_inc_pkt_cnt;
1500
1501/*--------------------------------------------------------------*/
1502// Wires & Registers
1503/*--------------------------------------------------------------*/
1504
1505/*--------------------------------------------------------------*/
1506// Assigns
1507/*--------------------------------------------------------------*/
1508
1509/*--------------------------------------------------------------*/
1510// Module Instantiations
1511/*--------------------------------------------------------------*/
1512niu_txc_tdmc_error niu_txc_tdmc_error (
1513 .SysClk (SysClk),
1514 .Reset_L (Reset_L),
1515 .Port0_Nack_Pkt_Rd (Port0_Nack_Pkt_Rd),
1516 .Port0_DMA_Nack_Pkt_Rd (Port0_DMA_Nack_Pkt_Rd),
1517 .Port0_Nack_Pkt_Rd_Addr (Port0_Nack_Pkt_Rd_Addr),
1518 .Port1_Nack_Pkt_Rd (Port1_Nack_Pkt_Rd),
1519 .Port1_DMA_Nack_Pkt_Rd (Port1_DMA_Nack_Pkt_Rd),
1520 .Port1_Nack_Pkt_Rd_Addr (Port1_Nack_Pkt_Rd_Addr),
1521 .Port2_Nack_Pkt_Rd (Port2_Nack_Pkt_Rd),
1522 .Port2_DMA_Nack_Pkt_Rd (Port2_DMA_Nack_Pkt_Rd),
1523 .Port2_Nack_Pkt_Rd_Addr (Port2_Nack_Pkt_Rd_Addr),
1524 .Port3_Nack_Pkt_Rd (Port3_Nack_Pkt_Rd),
1525 .Port3_DMA_Nack_Pkt_Rd (Port3_DMA_Nack_Pkt_Rd),
1526 .Port3_Nack_Pkt_Rd_Addr (Port3_Nack_Pkt_Rd_Addr),
1527 .TXC_DMC_Nack_Pkt_Rd (TXC_DMC_Nack_Pkt_Rd),
1528 .TXC_DMC_DMA_Nack_Pkt_Rd (TXC_DMC_DMA_Nack_Pkt_Rd),
1529 .TXC_DMC_Nack_Pkt_Rd_Addr (TXC_DMC_Nack_Pkt_Rd_Addr)
1530 );
1531
1532
1533niu_txc_tdmc_context niu_txc_tdmc_context0 (
1534 .SysClk (SysClk),
1535 .Reset_L (Reset_L),
1536 .Port0_DMA_inc_head (Port0_DMA0_inc_head),
1537 .Port0_DMA_reset_done (Port0_DMA0_reset_done),
1538 .Port0_DMA_mark_bit (Port0_DMA0_mark_bit),
1539 .Port0_DMA_inc_pkt_cnt (Port0_DMA0_inc_pkt_cnt),
1540 .Port0_SetGetNextDescDMA (Port0_SetGetNextDescDMA0),
1541 .Port1_DMA_inc_head (Port1_DMA0_inc_head),
1542 .Port1_DMA_reset_done (Port1_DMA0_reset_done),
1543 .Port1_DMA_mark_bit (Port1_DMA0_mark_bit),
1544 .Port1_DMA_inc_pkt_cnt (Port1_DMA0_inc_pkt_cnt),
1545 .Port1_SetGetNextDescDMA (Port1_SetGetNextDescDMA0),
1546 .Port2_DMA_inc_head (Port2_DMA0_inc_head),
1547 .Port2_DMA_reset_done (Port2_DMA0_reset_done),
1548 .Port2_DMA_mark_bit (Port2_DMA0_mark_bit),
1549 .Port2_DMA_inc_pkt_cnt (Port2_DMA0_inc_pkt_cnt),
1550 .Port2_SetGetNextDescDMA (Port2_SetGetNextDescDMA0),
1551 .Port3_DMA_inc_head (Port3_DMA0_inc_head),
1552 .Port3_DMA_reset_done (Port3_DMA0_reset_done),
1553 .Port3_DMA_mark_bit (Port3_DMA0_mark_bit),
1554 .Port3_DMA_inc_pkt_cnt (Port3_DMA0_inc_pkt_cnt),
1555 .Port3_SetGetNextDescDMA (Port3_SetGetNextDescDMA0),
1556 .DMC_TXC_DMA_GotNxtDesc (DMC_TXC_DMA0_GotNxtDesc),
1557 .TXC_DMC_DMA_GetNxtDesc (TXC_DMC_DMA0_GetNxtDesc),
1558 .TXC_DMC_DMA_inc_head (TXC_DMC_DMA0_inc_head),
1559 .TXC_DMC_DMA_reset_done (TXC_DMC_DMA0_reset_done),
1560 .TXC_DMC_DMA_mark_bit (TXC_DMC_DMA0_mark_bit),
1561 .TXC_DMC_DMA_inc_pkt_cnt (TXC_DMC_DMA0_inc_pkt_cnt)
1562 );
1563
1564niu_txc_tdmc_context niu_txc_tdmc_context1 (
1565 .SysClk (SysClk),
1566 .Reset_L (Reset_L),
1567 .Port0_DMA_inc_head (Port0_DMA1_inc_head),
1568 .Port0_DMA_reset_done (Port0_DMA1_reset_done),
1569 .Port0_DMA_mark_bit (Port0_DMA1_mark_bit),
1570 .Port0_DMA_inc_pkt_cnt (Port0_DMA1_inc_pkt_cnt),
1571 .Port0_SetGetNextDescDMA (Port0_SetGetNextDescDMA1),
1572 .Port1_DMA_inc_head (Port1_DMA1_inc_head),
1573 .Port1_DMA_reset_done (Port1_DMA1_reset_done),
1574 .Port1_DMA_mark_bit (Port1_DMA1_mark_bit),
1575 .Port1_DMA_inc_pkt_cnt (Port1_DMA1_inc_pkt_cnt),
1576 .Port1_SetGetNextDescDMA (Port1_SetGetNextDescDMA1),
1577 .Port2_DMA_inc_head (Port2_DMA1_inc_head),
1578 .Port2_DMA_reset_done (Port2_DMA1_reset_done),
1579 .Port2_DMA_mark_bit (Port2_DMA1_mark_bit),
1580 .Port2_DMA_inc_pkt_cnt (Port2_DMA1_inc_pkt_cnt),
1581 .Port2_SetGetNextDescDMA (Port2_SetGetNextDescDMA1),
1582 .Port3_DMA_inc_head (Port3_DMA1_inc_head),
1583 .Port3_DMA_reset_done (Port3_DMA1_reset_done),
1584 .Port3_DMA_mark_bit (Port3_DMA1_mark_bit),
1585 .Port3_DMA_inc_pkt_cnt (Port3_DMA1_inc_pkt_cnt),
1586 .Port3_SetGetNextDescDMA (Port3_SetGetNextDescDMA1),
1587 .DMC_TXC_DMA_GotNxtDesc (DMC_TXC_DMA1_GotNxtDesc),
1588 .TXC_DMC_DMA_GetNxtDesc (TXC_DMC_DMA1_GetNxtDesc),
1589 .TXC_DMC_DMA_inc_head (TXC_DMC_DMA1_inc_head),
1590 .TXC_DMC_DMA_reset_done (TXC_DMC_DMA1_reset_done),
1591 .TXC_DMC_DMA_mark_bit (TXC_DMC_DMA1_mark_bit),
1592 .TXC_DMC_DMA_inc_pkt_cnt (TXC_DMC_DMA1_inc_pkt_cnt)
1593 );
1594
1595niu_txc_tdmc_context niu_txc_tdmc_context2 (
1596 .SysClk (SysClk),
1597 .Reset_L (Reset_L),
1598 .Port0_DMA_inc_head (Port0_DMA2_inc_head),
1599 .Port0_DMA_reset_done (Port0_DMA2_reset_done),
1600 .Port0_DMA_mark_bit (Port0_DMA2_mark_bit),
1601 .Port0_DMA_inc_pkt_cnt (Port0_DMA2_inc_pkt_cnt),
1602 .Port0_SetGetNextDescDMA (Port0_SetGetNextDescDMA2),
1603 .Port1_DMA_inc_head (Port1_DMA2_inc_head),
1604 .Port1_DMA_reset_done (Port1_DMA2_reset_done),
1605 .Port1_DMA_mark_bit (Port1_DMA2_mark_bit),
1606 .Port1_DMA_inc_pkt_cnt (Port1_DMA2_inc_pkt_cnt),
1607 .Port1_SetGetNextDescDMA (Port1_SetGetNextDescDMA2),
1608 .Port2_DMA_inc_head (Port2_DMA2_inc_head),
1609 .Port2_DMA_reset_done (Port2_DMA2_reset_done),
1610 .Port2_DMA_mark_bit (Port2_DMA2_mark_bit),
1611 .Port2_DMA_inc_pkt_cnt (Port2_DMA2_inc_pkt_cnt),
1612 .Port2_SetGetNextDescDMA (Port2_SetGetNextDescDMA2),
1613 .Port3_DMA_inc_head (Port3_DMA2_inc_head),
1614 .Port3_DMA_reset_done (Port3_DMA2_reset_done),
1615 .Port3_DMA_mark_bit (Port3_DMA2_mark_bit),
1616 .Port3_DMA_inc_pkt_cnt (Port3_DMA2_inc_pkt_cnt),
1617 .Port3_SetGetNextDescDMA (Port3_SetGetNextDescDMA2),
1618 .DMC_TXC_DMA_GotNxtDesc (DMC_TXC_DMA2_GotNxtDesc),
1619 .TXC_DMC_DMA_GetNxtDesc (TXC_DMC_DMA2_GetNxtDesc),
1620 .TXC_DMC_DMA_inc_head (TXC_DMC_DMA2_inc_head),
1621 .TXC_DMC_DMA_reset_done (TXC_DMC_DMA2_reset_done),
1622 .TXC_DMC_DMA_mark_bit (TXC_DMC_DMA2_mark_bit),
1623 .TXC_DMC_DMA_inc_pkt_cnt (TXC_DMC_DMA2_inc_pkt_cnt)
1624 );
1625
1626niu_txc_tdmc_context niu_txc_tdmc_context3 (
1627 .SysClk (SysClk),
1628 .Reset_L (Reset_L),
1629 .Port0_DMA_inc_head (Port0_DMA3_inc_head),
1630 .Port0_DMA_reset_done (Port0_DMA3_reset_done),
1631 .Port0_DMA_mark_bit (Port0_DMA3_mark_bit),
1632 .Port0_DMA_inc_pkt_cnt (Port0_DMA3_inc_pkt_cnt),
1633 .Port0_SetGetNextDescDMA (Port0_SetGetNextDescDMA3),
1634 .Port1_DMA_inc_head (Port1_DMA3_inc_head),
1635 .Port1_DMA_reset_done (Port1_DMA3_reset_done),
1636 .Port1_DMA_mark_bit (Port1_DMA3_mark_bit),
1637 .Port1_DMA_inc_pkt_cnt (Port1_DMA3_inc_pkt_cnt),
1638 .Port1_SetGetNextDescDMA (Port1_SetGetNextDescDMA3),
1639 .Port2_DMA_inc_head (Port2_DMA3_inc_head),
1640 .Port2_DMA_reset_done (Port2_DMA3_reset_done),
1641 .Port2_DMA_mark_bit (Port2_DMA3_mark_bit),
1642 .Port2_DMA_inc_pkt_cnt (Port2_DMA3_inc_pkt_cnt),
1643 .Port2_SetGetNextDescDMA (Port2_SetGetNextDescDMA3),
1644 .Port3_DMA_inc_head (Port3_DMA3_inc_head),
1645 .Port3_DMA_reset_done (Port3_DMA3_reset_done),
1646 .Port3_DMA_mark_bit (Port3_DMA3_mark_bit),
1647 .Port3_DMA_inc_pkt_cnt (Port3_DMA3_inc_pkt_cnt),
1648 .Port3_SetGetNextDescDMA (Port3_SetGetNextDescDMA3),
1649 .DMC_TXC_DMA_GotNxtDesc (DMC_TXC_DMA3_GotNxtDesc),
1650 .TXC_DMC_DMA_GetNxtDesc (TXC_DMC_DMA3_GetNxtDesc),
1651 .TXC_DMC_DMA_inc_head (TXC_DMC_DMA3_inc_head),
1652 .TXC_DMC_DMA_reset_done (TXC_DMC_DMA3_reset_done),
1653 .TXC_DMC_DMA_mark_bit (TXC_DMC_DMA3_mark_bit),
1654 .TXC_DMC_DMA_inc_pkt_cnt (TXC_DMC_DMA3_inc_pkt_cnt)
1655 );
1656
1657niu_txc_tdmc_context niu_txc_tdmc_context4 (
1658 .SysClk (SysClk),
1659 .Reset_L (Reset_L),
1660 .Port0_DMA_inc_head (Port0_DMA4_inc_head),
1661 .Port0_DMA_reset_done (Port0_DMA4_reset_done),
1662 .Port0_DMA_mark_bit (Port0_DMA4_mark_bit),
1663 .Port0_DMA_inc_pkt_cnt (Port0_DMA4_inc_pkt_cnt),
1664 .Port0_SetGetNextDescDMA (Port0_SetGetNextDescDMA4),
1665 .Port1_DMA_inc_head (Port1_DMA4_inc_head),
1666 .Port1_DMA_reset_done (Port1_DMA4_reset_done),
1667 .Port1_DMA_mark_bit (Port1_DMA4_mark_bit),
1668 .Port1_DMA_inc_pkt_cnt (Port1_DMA4_inc_pkt_cnt),
1669 .Port1_SetGetNextDescDMA (Port1_SetGetNextDescDMA4),
1670 .Port2_DMA_inc_head (Port2_DMA4_inc_head),
1671 .Port2_DMA_reset_done (Port2_DMA4_reset_done),
1672 .Port2_DMA_mark_bit (Port2_DMA4_mark_bit),
1673 .Port2_DMA_inc_pkt_cnt (Port2_DMA4_inc_pkt_cnt),
1674 .Port2_SetGetNextDescDMA (Port2_SetGetNextDescDMA4),
1675 .Port3_DMA_inc_head (Port3_DMA4_inc_head),
1676 .Port3_DMA_reset_done (Port3_DMA4_reset_done),
1677 .Port3_DMA_mark_bit (Port3_DMA4_mark_bit),
1678 .Port3_DMA_inc_pkt_cnt (Port3_DMA4_inc_pkt_cnt),
1679 .Port3_SetGetNextDescDMA (Port3_SetGetNextDescDMA4),
1680 .DMC_TXC_DMA_GotNxtDesc (DMC_TXC_DMA4_GotNxtDesc),
1681 .TXC_DMC_DMA_GetNxtDesc (TXC_DMC_DMA4_GetNxtDesc),
1682 .TXC_DMC_DMA_inc_head (TXC_DMC_DMA4_inc_head),
1683 .TXC_DMC_DMA_reset_done (TXC_DMC_DMA4_reset_done),
1684 .TXC_DMC_DMA_mark_bit (TXC_DMC_DMA4_mark_bit),
1685 .TXC_DMC_DMA_inc_pkt_cnt (TXC_DMC_DMA4_inc_pkt_cnt)
1686 );
1687
1688niu_txc_tdmc_context niu_txc_tdmc_context5 (
1689 .SysClk (SysClk),
1690 .Reset_L (Reset_L),
1691 .Port0_DMA_inc_head (Port0_DMA5_inc_head),
1692 .Port0_DMA_reset_done (Port0_DMA5_reset_done),
1693 .Port0_DMA_mark_bit (Port0_DMA5_mark_bit),
1694 .Port0_DMA_inc_pkt_cnt (Port0_DMA5_inc_pkt_cnt),
1695 .Port0_SetGetNextDescDMA (Port0_SetGetNextDescDMA5),
1696 .Port1_DMA_inc_head (Port1_DMA5_inc_head),
1697 .Port1_DMA_reset_done (Port1_DMA5_reset_done),
1698 .Port1_DMA_mark_bit (Port1_DMA5_mark_bit),
1699 .Port1_DMA_inc_pkt_cnt (Port1_DMA5_inc_pkt_cnt),
1700 .Port1_SetGetNextDescDMA (Port1_SetGetNextDescDMA5),
1701 .Port2_DMA_inc_head (Port2_DMA5_inc_head),
1702 .Port2_DMA_reset_done (Port2_DMA5_reset_done),
1703 .Port2_DMA_mark_bit (Port2_DMA5_mark_bit),
1704 .Port2_DMA_inc_pkt_cnt (Port2_DMA5_inc_pkt_cnt),
1705 .Port2_SetGetNextDescDMA (Port2_SetGetNextDescDMA5),
1706 .Port3_DMA_inc_head (Port3_DMA5_inc_head),
1707 .Port3_DMA_reset_done (Port3_DMA5_reset_done),
1708 .Port3_DMA_mark_bit (Port3_DMA5_mark_bit),
1709 .Port3_DMA_inc_pkt_cnt (Port3_DMA5_inc_pkt_cnt),
1710 .Port3_SetGetNextDescDMA (Port3_SetGetNextDescDMA5),
1711 .DMC_TXC_DMA_GotNxtDesc (DMC_TXC_DMA5_GotNxtDesc),
1712 .TXC_DMC_DMA_GetNxtDesc (TXC_DMC_DMA5_GetNxtDesc),
1713 .TXC_DMC_DMA_inc_head (TXC_DMC_DMA5_inc_head),
1714 .TXC_DMC_DMA_reset_done (TXC_DMC_DMA5_reset_done),
1715 .TXC_DMC_DMA_mark_bit (TXC_DMC_DMA5_mark_bit),
1716 .TXC_DMC_DMA_inc_pkt_cnt (TXC_DMC_DMA5_inc_pkt_cnt)
1717 );
1718
1719niu_txc_tdmc_context niu_txc_tdmc_context6 (
1720 .SysClk (SysClk),
1721 .Reset_L (Reset_L),
1722 .Port0_DMA_inc_head (Port0_DMA6_inc_head),
1723 .Port0_DMA_reset_done (Port0_DMA6_reset_done),
1724 .Port0_DMA_mark_bit (Port0_DMA6_mark_bit),
1725 .Port0_DMA_inc_pkt_cnt (Port0_DMA6_inc_pkt_cnt),
1726 .Port0_SetGetNextDescDMA (Port0_SetGetNextDescDMA6),
1727 .Port1_DMA_inc_head (Port1_DMA6_inc_head),
1728 .Port1_DMA_reset_done (Port1_DMA6_reset_done),
1729 .Port1_DMA_mark_bit (Port1_DMA6_mark_bit),
1730 .Port1_DMA_inc_pkt_cnt (Port1_DMA6_inc_pkt_cnt),
1731 .Port1_SetGetNextDescDMA (Port1_SetGetNextDescDMA6),
1732 .Port2_DMA_inc_head (Port2_DMA6_inc_head),
1733 .Port2_DMA_reset_done (Port2_DMA6_reset_done),
1734 .Port2_DMA_mark_bit (Port2_DMA6_mark_bit),
1735 .Port2_DMA_inc_pkt_cnt (Port2_DMA6_inc_pkt_cnt),
1736 .Port2_SetGetNextDescDMA (Port2_SetGetNextDescDMA6),
1737 .Port3_DMA_inc_head (Port3_DMA6_inc_head),
1738 .Port3_DMA_reset_done (Port3_DMA6_reset_done),
1739 .Port3_DMA_mark_bit (Port3_DMA6_mark_bit),
1740 .Port3_DMA_inc_pkt_cnt (Port3_DMA6_inc_pkt_cnt),
1741 .Port3_SetGetNextDescDMA (Port3_SetGetNextDescDMA6),
1742 .DMC_TXC_DMA_GotNxtDesc (DMC_TXC_DMA6_GotNxtDesc),
1743 .TXC_DMC_DMA_GetNxtDesc (TXC_DMC_DMA6_GetNxtDesc),
1744 .TXC_DMC_DMA_inc_head (TXC_DMC_DMA6_inc_head),
1745 .TXC_DMC_DMA_reset_done (TXC_DMC_DMA6_reset_done),
1746 .TXC_DMC_DMA_mark_bit (TXC_DMC_DMA6_mark_bit),
1747 .TXC_DMC_DMA_inc_pkt_cnt (TXC_DMC_DMA6_inc_pkt_cnt)
1748 );
1749
1750niu_txc_tdmc_context niu_txc_tdmc_context7 (
1751 .SysClk (SysClk),
1752 .Reset_L (Reset_L),
1753 .Port0_DMA_inc_head (Port0_DMA7_inc_head),
1754 .Port0_DMA_reset_done (Port0_DMA7_reset_done),
1755 .Port0_DMA_mark_bit (Port0_DMA7_mark_bit),
1756 .Port0_DMA_inc_pkt_cnt (Port0_DMA7_inc_pkt_cnt),
1757 .Port0_SetGetNextDescDMA (Port0_SetGetNextDescDMA7),
1758 .Port1_DMA_inc_head (Port1_DMA7_inc_head),
1759 .Port1_DMA_reset_done (Port1_DMA7_reset_done),
1760 .Port1_DMA_mark_bit (Port1_DMA7_mark_bit),
1761 .Port1_DMA_inc_pkt_cnt (Port1_DMA7_inc_pkt_cnt),
1762 .Port1_SetGetNextDescDMA (Port1_SetGetNextDescDMA7),
1763 .Port2_DMA_inc_head (Port2_DMA7_inc_head),
1764 .Port2_DMA_reset_done (Port2_DMA7_reset_done),
1765 .Port2_DMA_mark_bit (Port2_DMA7_mark_bit),
1766 .Port2_DMA_inc_pkt_cnt (Port2_DMA7_inc_pkt_cnt),
1767 .Port2_SetGetNextDescDMA (Port2_SetGetNextDescDMA7),
1768 .Port3_DMA_inc_head (Port3_DMA7_inc_head),
1769 .Port3_DMA_reset_done (Port3_DMA7_reset_done),
1770 .Port3_DMA_mark_bit (Port3_DMA7_mark_bit),
1771 .Port3_DMA_inc_pkt_cnt (Port3_DMA7_inc_pkt_cnt),
1772 .Port3_SetGetNextDescDMA (Port3_SetGetNextDescDMA7),
1773 .DMC_TXC_DMA_GotNxtDesc (DMC_TXC_DMA7_GotNxtDesc),
1774 .TXC_DMC_DMA_GetNxtDesc (TXC_DMC_DMA7_GetNxtDesc),
1775 .TXC_DMC_DMA_inc_head (TXC_DMC_DMA7_inc_head),
1776 .TXC_DMC_DMA_reset_done (TXC_DMC_DMA7_reset_done),
1777 .TXC_DMC_DMA_mark_bit (TXC_DMC_DMA7_mark_bit),
1778 .TXC_DMC_DMA_inc_pkt_cnt (TXC_DMC_DMA7_inc_pkt_cnt)
1779 );
1780
1781niu_txc_tdmc_context niu_txc_tdmc_context8 (
1782 .SysClk (SysClk),
1783 .Reset_L (Reset_L),
1784 .Port0_DMA_inc_head (Port0_DMA8_inc_head),
1785 .Port0_DMA_reset_done (Port0_DMA8_reset_done),
1786 .Port0_DMA_mark_bit (Port0_DMA8_mark_bit),
1787 .Port0_DMA_inc_pkt_cnt (Port0_DMA8_inc_pkt_cnt),
1788 .Port0_SetGetNextDescDMA (Port0_SetGetNextDescDMA8),
1789 .Port1_DMA_inc_head (Port1_DMA8_inc_head),
1790 .Port1_DMA_reset_done (Port1_DMA8_reset_done),
1791 .Port1_DMA_mark_bit (Port1_DMA8_mark_bit),
1792 .Port1_DMA_inc_pkt_cnt (Port1_DMA8_inc_pkt_cnt),
1793 .Port1_SetGetNextDescDMA (Port1_SetGetNextDescDMA8),
1794 .Port2_DMA_inc_head (Port2_DMA8_inc_head),
1795 .Port2_DMA_reset_done (Port2_DMA8_reset_done),
1796 .Port2_DMA_mark_bit (Port2_DMA8_mark_bit),
1797 .Port2_DMA_inc_pkt_cnt (Port2_DMA8_inc_pkt_cnt),
1798 .Port2_SetGetNextDescDMA (Port2_SetGetNextDescDMA8),
1799 .Port3_DMA_inc_head (Port3_DMA8_inc_head),
1800 .Port3_DMA_reset_done (Port3_DMA8_reset_done),
1801 .Port3_DMA_mark_bit (Port3_DMA8_mark_bit),
1802 .Port3_DMA_inc_pkt_cnt (Port3_DMA8_inc_pkt_cnt),
1803 .Port3_SetGetNextDescDMA (Port3_SetGetNextDescDMA8),
1804 .DMC_TXC_DMA_GotNxtDesc (DMC_TXC_DMA8_GotNxtDesc),
1805 .TXC_DMC_DMA_GetNxtDesc (TXC_DMC_DMA8_GetNxtDesc),
1806 .TXC_DMC_DMA_inc_head (TXC_DMC_DMA8_inc_head),
1807 .TXC_DMC_DMA_reset_done (TXC_DMC_DMA8_reset_done),
1808 .TXC_DMC_DMA_mark_bit (TXC_DMC_DMA8_mark_bit),
1809 .TXC_DMC_DMA_inc_pkt_cnt (TXC_DMC_DMA8_inc_pkt_cnt)
1810 );
1811
1812niu_txc_tdmc_context niu_txc_tdmc_context9 (
1813 .SysClk (SysClk),
1814 .Reset_L (Reset_L),
1815 .Port0_DMA_inc_head (Port0_DMA9_inc_head),
1816 .Port0_DMA_reset_done (Port0_DMA9_reset_done),
1817 .Port0_DMA_mark_bit (Port0_DMA9_mark_bit),
1818 .Port0_DMA_inc_pkt_cnt (Port0_DMA9_inc_pkt_cnt),
1819 .Port0_SetGetNextDescDMA (Port0_SetGetNextDescDMA9),
1820 .Port1_DMA_inc_head (Port1_DMA9_inc_head),
1821 .Port1_DMA_reset_done (Port1_DMA9_reset_done),
1822 .Port1_DMA_mark_bit (Port1_DMA9_mark_bit),
1823 .Port1_DMA_inc_pkt_cnt (Port1_DMA9_inc_pkt_cnt),
1824 .Port1_SetGetNextDescDMA (Port1_SetGetNextDescDMA9),
1825 .Port2_DMA_inc_head (Port2_DMA9_inc_head),
1826 .Port2_DMA_reset_done (Port2_DMA9_reset_done),
1827 .Port2_DMA_mark_bit (Port2_DMA9_mark_bit),
1828 .Port2_DMA_inc_pkt_cnt (Port2_DMA9_inc_pkt_cnt),
1829 .Port2_SetGetNextDescDMA (Port2_SetGetNextDescDMA9),
1830 .Port3_DMA_inc_head (Port3_DMA9_inc_head),
1831 .Port3_DMA_reset_done (Port3_DMA9_reset_done),
1832 .Port3_DMA_mark_bit (Port3_DMA9_mark_bit),
1833 .Port3_DMA_inc_pkt_cnt (Port3_DMA9_inc_pkt_cnt),
1834 .Port3_SetGetNextDescDMA (Port3_SetGetNextDescDMA9),
1835 .DMC_TXC_DMA_GotNxtDesc (DMC_TXC_DMA9_GotNxtDesc),
1836 .TXC_DMC_DMA_GetNxtDesc (TXC_DMC_DMA9_GetNxtDesc),
1837 .TXC_DMC_DMA_inc_head (TXC_DMC_DMA9_inc_head),
1838 .TXC_DMC_DMA_reset_done (TXC_DMC_DMA9_reset_done),
1839 .TXC_DMC_DMA_mark_bit (TXC_DMC_DMA9_mark_bit),
1840 .TXC_DMC_DMA_inc_pkt_cnt (TXC_DMC_DMA9_inc_pkt_cnt)
1841 );
1842
1843niu_txc_tdmc_context niu_txc_tdmc_context10 (
1844 .SysClk (SysClk),
1845 .Reset_L (Reset_L),
1846 .Port0_DMA_inc_head (Port0_DMA10_inc_head),
1847 .Port0_DMA_reset_done (Port0_DMA10_reset_done),
1848 .Port0_DMA_mark_bit (Port0_DMA10_mark_bit),
1849 .Port0_DMA_inc_pkt_cnt (Port0_DMA10_inc_pkt_cnt),
1850 .Port0_SetGetNextDescDMA (Port0_SetGetNextDescDMA10),
1851 .Port1_DMA_inc_head (Port1_DMA10_inc_head),
1852 .Port1_DMA_reset_done (Port1_DMA10_reset_done),
1853 .Port1_DMA_mark_bit (Port1_DMA10_mark_bit),
1854 .Port1_DMA_inc_pkt_cnt (Port1_DMA10_inc_pkt_cnt),
1855 .Port1_SetGetNextDescDMA (Port1_SetGetNextDescDMA10),
1856 .Port2_DMA_inc_head (Port2_DMA10_inc_head),
1857 .Port2_DMA_reset_done (Port2_DMA10_reset_done),
1858 .Port2_DMA_mark_bit (Port2_DMA10_mark_bit),
1859 .Port2_DMA_inc_pkt_cnt (Port2_DMA10_inc_pkt_cnt),
1860 .Port2_SetGetNextDescDMA (Port2_SetGetNextDescDMA10),
1861 .Port3_DMA_inc_head (Port3_DMA10_inc_head),
1862 .Port3_DMA_reset_done (Port3_DMA10_reset_done),
1863 .Port3_DMA_mark_bit (Port3_DMA10_mark_bit),
1864 .Port3_DMA_inc_pkt_cnt (Port3_DMA10_inc_pkt_cnt),
1865 .Port3_SetGetNextDescDMA (Port3_SetGetNextDescDMA10),
1866 .DMC_TXC_DMA_GotNxtDesc (DMC_TXC_DMA10_GotNxtDesc),
1867 .TXC_DMC_DMA_GetNxtDesc (TXC_DMC_DMA10_GetNxtDesc),
1868 .TXC_DMC_DMA_inc_head (TXC_DMC_DMA10_inc_head),
1869 .TXC_DMC_DMA_reset_done (TXC_DMC_DMA10_reset_done),
1870 .TXC_DMC_DMA_mark_bit (TXC_DMC_DMA10_mark_bit),
1871 .TXC_DMC_DMA_inc_pkt_cnt (TXC_DMC_DMA10_inc_pkt_cnt)
1872 );
1873
1874niu_txc_tdmc_context niu_txc_tdmc_context11 (
1875 .SysClk (SysClk),
1876 .Reset_L (Reset_L),
1877 .Port0_DMA_inc_head (Port0_DMA11_inc_head),
1878 .Port0_DMA_reset_done (Port0_DMA11_reset_done),
1879 .Port0_DMA_mark_bit (Port0_DMA11_mark_bit),
1880 .Port0_DMA_inc_pkt_cnt (Port0_DMA11_inc_pkt_cnt),
1881 .Port0_SetGetNextDescDMA (Port0_SetGetNextDescDMA11),
1882 .Port1_DMA_inc_head (Port1_DMA11_inc_head),
1883 .Port1_DMA_reset_done (Port1_DMA11_reset_done),
1884 .Port1_DMA_mark_bit (Port1_DMA11_mark_bit),
1885 .Port1_DMA_inc_pkt_cnt (Port1_DMA11_inc_pkt_cnt),
1886 .Port1_SetGetNextDescDMA (Port1_SetGetNextDescDMA11),
1887 .Port2_DMA_inc_head (Port2_DMA11_inc_head),
1888 .Port2_DMA_reset_done (Port2_DMA11_reset_done),
1889 .Port2_DMA_mark_bit (Port2_DMA11_mark_bit),
1890 .Port2_DMA_inc_pkt_cnt (Port2_DMA11_inc_pkt_cnt),
1891 .Port2_SetGetNextDescDMA (Port2_SetGetNextDescDMA11),
1892 .Port3_DMA_inc_head (Port3_DMA11_inc_head),
1893 .Port3_DMA_reset_done (Port3_DMA11_reset_done),
1894 .Port3_DMA_mark_bit (Port3_DMA11_mark_bit),
1895 .Port3_DMA_inc_pkt_cnt (Port3_DMA11_inc_pkt_cnt),
1896 .Port3_SetGetNextDescDMA (Port3_SetGetNextDescDMA11),
1897 .DMC_TXC_DMA_GotNxtDesc (DMC_TXC_DMA11_GotNxtDesc),
1898 .TXC_DMC_DMA_GetNxtDesc (TXC_DMC_DMA11_GetNxtDesc),
1899 .TXC_DMC_DMA_inc_head (TXC_DMC_DMA11_inc_head),
1900 .TXC_DMC_DMA_reset_done (TXC_DMC_DMA11_reset_done),
1901 .TXC_DMC_DMA_mark_bit (TXC_DMC_DMA11_mark_bit),
1902 .TXC_DMC_DMA_inc_pkt_cnt (TXC_DMC_DMA11_inc_pkt_cnt)
1903 );
1904
1905niu_txc_tdmc_context niu_txc_tdmc_context12 (
1906 .SysClk (SysClk),
1907 .Reset_L (Reset_L),
1908 .Port0_DMA_inc_head (Port0_DMA12_inc_head),
1909 .Port0_DMA_reset_done (Port0_DMA12_reset_done),
1910 .Port0_DMA_mark_bit (Port0_DMA12_mark_bit),
1911 .Port0_DMA_inc_pkt_cnt (Port0_DMA12_inc_pkt_cnt),
1912 .Port0_SetGetNextDescDMA (Port0_SetGetNextDescDMA12),
1913 .Port1_DMA_inc_head (Port1_DMA12_inc_head),
1914 .Port1_DMA_reset_done (Port1_DMA12_reset_done),
1915 .Port1_DMA_mark_bit (Port1_DMA12_mark_bit),
1916 .Port1_DMA_inc_pkt_cnt (Port1_DMA12_inc_pkt_cnt),
1917 .Port1_SetGetNextDescDMA (Port1_SetGetNextDescDMA12),
1918 .Port2_DMA_inc_head (Port2_DMA12_inc_head),
1919 .Port2_DMA_reset_done (Port2_DMA12_reset_done),
1920 .Port2_DMA_mark_bit (Port2_DMA12_mark_bit),
1921 .Port2_DMA_inc_pkt_cnt (Port2_DMA12_inc_pkt_cnt),
1922 .Port2_SetGetNextDescDMA (Port2_SetGetNextDescDMA12),
1923 .Port3_DMA_inc_head (Port3_DMA12_inc_head),
1924 .Port3_DMA_reset_done (Port3_DMA12_reset_done),
1925 .Port3_DMA_mark_bit (Port3_DMA12_mark_bit),
1926 .Port3_DMA_inc_pkt_cnt (Port3_DMA12_inc_pkt_cnt),
1927 .Port3_SetGetNextDescDMA (Port3_SetGetNextDescDMA12),
1928 .DMC_TXC_DMA_GotNxtDesc (DMC_TXC_DMA12_GotNxtDesc),
1929 .TXC_DMC_DMA_GetNxtDesc (TXC_DMC_DMA12_GetNxtDesc),
1930 .TXC_DMC_DMA_inc_head (TXC_DMC_DMA12_inc_head),
1931 .TXC_DMC_DMA_reset_done (TXC_DMC_DMA12_reset_done),
1932 .TXC_DMC_DMA_mark_bit (TXC_DMC_DMA12_mark_bit),
1933 .TXC_DMC_DMA_inc_pkt_cnt (TXC_DMC_DMA12_inc_pkt_cnt)
1934 );
1935
1936niu_txc_tdmc_context niu_txc_tdmc_context13 (
1937 .SysClk (SysClk),
1938 .Reset_L (Reset_L),
1939 .Port0_DMA_inc_head (Port0_DMA13_inc_head),
1940 .Port0_DMA_reset_done (Port0_DMA13_reset_done),
1941 .Port0_DMA_mark_bit (Port0_DMA13_mark_bit),
1942 .Port0_DMA_inc_pkt_cnt (Port0_DMA13_inc_pkt_cnt),
1943 .Port0_SetGetNextDescDMA (Port0_SetGetNextDescDMA13),
1944 .Port1_DMA_inc_head (Port1_DMA13_inc_head),
1945 .Port1_DMA_reset_done (Port1_DMA13_reset_done),
1946 .Port1_DMA_mark_bit (Port1_DMA13_mark_bit),
1947 .Port1_DMA_inc_pkt_cnt (Port1_DMA13_inc_pkt_cnt),
1948 .Port1_SetGetNextDescDMA (Port1_SetGetNextDescDMA13),
1949 .Port2_DMA_inc_head (Port2_DMA13_inc_head),
1950 .Port2_DMA_reset_done (Port2_DMA13_reset_done),
1951 .Port2_DMA_mark_bit (Port2_DMA13_mark_bit),
1952 .Port2_DMA_inc_pkt_cnt (Port2_DMA13_inc_pkt_cnt),
1953 .Port2_SetGetNextDescDMA (Port2_SetGetNextDescDMA13),
1954 .Port3_DMA_inc_head (Port3_DMA13_inc_head),
1955 .Port3_DMA_reset_done (Port3_DMA13_reset_done),
1956 .Port3_DMA_mark_bit (Port3_DMA13_mark_bit),
1957 .Port3_DMA_inc_pkt_cnt (Port3_DMA13_inc_pkt_cnt),
1958 .Port3_SetGetNextDescDMA (Port3_SetGetNextDescDMA13),
1959 .DMC_TXC_DMA_GotNxtDesc (DMC_TXC_DMA13_GotNxtDesc),
1960 .TXC_DMC_DMA_GetNxtDesc (TXC_DMC_DMA13_GetNxtDesc),
1961 .TXC_DMC_DMA_inc_head (TXC_DMC_DMA13_inc_head),
1962 .TXC_DMC_DMA_reset_done (TXC_DMC_DMA13_reset_done),
1963 .TXC_DMC_DMA_mark_bit (TXC_DMC_DMA13_mark_bit),
1964 .TXC_DMC_DMA_inc_pkt_cnt (TXC_DMC_DMA13_inc_pkt_cnt)
1965 );
1966
1967niu_txc_tdmc_context niu_txc_tdmc_context14 (
1968 .SysClk (SysClk),
1969 .Reset_L (Reset_L),
1970 .Port0_DMA_inc_head (Port0_DMA14_inc_head),
1971 .Port0_DMA_reset_done (Port0_DMA14_reset_done),
1972 .Port0_DMA_mark_bit (Port0_DMA14_mark_bit),
1973 .Port0_DMA_inc_pkt_cnt (Port0_DMA14_inc_pkt_cnt),
1974 .Port0_SetGetNextDescDMA (Port0_SetGetNextDescDMA14),
1975 .Port1_DMA_inc_head (Port1_DMA14_inc_head),
1976 .Port1_DMA_reset_done (Port1_DMA14_reset_done),
1977 .Port1_DMA_mark_bit (Port1_DMA14_mark_bit),
1978 .Port1_DMA_inc_pkt_cnt (Port1_DMA14_inc_pkt_cnt),
1979 .Port1_SetGetNextDescDMA (Port1_SetGetNextDescDMA14),
1980 .Port2_DMA_inc_head (Port2_DMA14_inc_head),
1981 .Port2_DMA_reset_done (Port2_DMA14_reset_done),
1982 .Port2_DMA_mark_bit (Port2_DMA14_mark_bit),
1983 .Port2_DMA_inc_pkt_cnt (Port2_DMA14_inc_pkt_cnt),
1984 .Port2_SetGetNextDescDMA (Port2_SetGetNextDescDMA14),
1985 .Port3_DMA_inc_head (Port3_DMA14_inc_head),
1986 .Port3_DMA_reset_done (Port3_DMA14_reset_done),
1987 .Port3_DMA_mark_bit (Port3_DMA14_mark_bit),
1988 .Port3_DMA_inc_pkt_cnt (Port3_DMA14_inc_pkt_cnt),
1989 .Port3_SetGetNextDescDMA (Port3_SetGetNextDescDMA14),
1990 .DMC_TXC_DMA_GotNxtDesc (DMC_TXC_DMA14_GotNxtDesc),
1991 .TXC_DMC_DMA_GetNxtDesc (TXC_DMC_DMA14_GetNxtDesc),
1992 .TXC_DMC_DMA_inc_head (TXC_DMC_DMA14_inc_head),
1993 .TXC_DMC_DMA_reset_done (TXC_DMC_DMA14_reset_done),
1994 .TXC_DMC_DMA_mark_bit (TXC_DMC_DMA14_mark_bit),
1995 .TXC_DMC_DMA_inc_pkt_cnt (TXC_DMC_DMA14_inc_pkt_cnt)
1996 );
1997
1998niu_txc_tdmc_context niu_txc_tdmc_context15 (
1999 .SysClk (SysClk),
2000 .Reset_L (Reset_L),
2001 .Port0_DMA_inc_head (Port0_DMA15_inc_head),
2002 .Port0_DMA_reset_done (Port0_DMA15_reset_done),
2003 .Port0_DMA_mark_bit (Port0_DMA15_mark_bit),
2004 .Port0_DMA_inc_pkt_cnt (Port0_DMA15_inc_pkt_cnt),
2005 .Port0_SetGetNextDescDMA (Port0_SetGetNextDescDMA15),
2006 .Port1_DMA_inc_head (Port1_DMA15_inc_head),
2007 .Port1_DMA_reset_done (Port1_DMA15_reset_done),
2008 .Port1_DMA_mark_bit (Port1_DMA15_mark_bit),
2009 .Port1_DMA_inc_pkt_cnt (Port1_DMA15_inc_pkt_cnt),
2010 .Port1_SetGetNextDescDMA (Port1_SetGetNextDescDMA15),
2011 .Port2_DMA_inc_head (Port2_DMA15_inc_head),
2012 .Port2_DMA_reset_done (Port2_DMA15_reset_done),
2013 .Port2_DMA_mark_bit (Port2_DMA15_mark_bit),
2014 .Port2_DMA_inc_pkt_cnt (Port2_DMA15_inc_pkt_cnt),
2015 .Port2_SetGetNextDescDMA (Port2_SetGetNextDescDMA15),
2016 .Port3_DMA_inc_head (Port3_DMA15_inc_head),
2017 .Port3_DMA_reset_done (Port3_DMA15_reset_done),
2018 .Port3_DMA_mark_bit (Port3_DMA15_mark_bit),
2019 .Port3_DMA_inc_pkt_cnt (Port3_DMA15_inc_pkt_cnt),
2020 .Port3_SetGetNextDescDMA (Port3_SetGetNextDescDMA15),
2021 .DMC_TXC_DMA_GotNxtDesc (DMC_TXC_DMA15_GotNxtDesc),
2022 .TXC_DMC_DMA_GetNxtDesc (TXC_DMC_DMA15_GetNxtDesc),
2023 .TXC_DMC_DMA_inc_head (TXC_DMC_DMA15_inc_head),
2024 .TXC_DMC_DMA_reset_done (TXC_DMC_DMA15_reset_done),
2025 .TXC_DMC_DMA_mark_bit (TXC_DMC_DMA15_mark_bit),
2026 .TXC_DMC_DMA_inc_pkt_cnt (TXC_DMC_DMA15_inc_pkt_cnt)
2027 );
2028
2029niu_txc_tdmc_context niu_txc_tdmc_context16 (
2030 .SysClk (SysClk),
2031 .Reset_L (Reset_L),
2032 .Port0_DMA_inc_head (Port0_DMA16_inc_head),
2033 .Port0_DMA_reset_done (Port0_DMA16_reset_done),
2034 .Port0_DMA_mark_bit (Port0_DMA16_mark_bit),
2035 .Port0_DMA_inc_pkt_cnt (Port0_DMA16_inc_pkt_cnt),
2036 .Port0_SetGetNextDescDMA (Port0_SetGetNextDescDMA16),
2037 .Port1_DMA_inc_head (Port1_DMA16_inc_head),
2038 .Port1_DMA_reset_done (Port1_DMA16_reset_done),
2039 .Port1_DMA_mark_bit (Port1_DMA16_mark_bit),
2040 .Port1_DMA_inc_pkt_cnt (Port1_DMA16_inc_pkt_cnt),
2041 .Port1_SetGetNextDescDMA (Port1_SetGetNextDescDMA16),
2042 .Port2_DMA_inc_head (Port2_DMA16_inc_head),
2043 .Port2_DMA_reset_done (Port2_DMA16_reset_done),
2044 .Port2_DMA_mark_bit (Port2_DMA16_mark_bit),
2045 .Port2_DMA_inc_pkt_cnt (Port2_DMA16_inc_pkt_cnt),
2046 .Port2_SetGetNextDescDMA (Port2_SetGetNextDescDMA16),
2047 .Port3_DMA_inc_head (Port3_DMA16_inc_head),
2048 .Port3_DMA_reset_done (Port3_DMA16_reset_done),
2049 .Port3_DMA_mark_bit (Port3_DMA16_mark_bit),
2050 .Port3_DMA_inc_pkt_cnt (Port3_DMA16_inc_pkt_cnt),
2051 .Port3_SetGetNextDescDMA (Port3_SetGetNextDescDMA16),
2052 .DMC_TXC_DMA_GotNxtDesc (DMC_TXC_DMA16_GotNxtDesc),
2053 .TXC_DMC_DMA_GetNxtDesc (TXC_DMC_DMA16_GetNxtDesc),
2054 .TXC_DMC_DMA_inc_head (TXC_DMC_DMA16_inc_head),
2055 .TXC_DMC_DMA_reset_done (TXC_DMC_DMA16_reset_done),
2056 .TXC_DMC_DMA_mark_bit (TXC_DMC_DMA16_mark_bit),
2057 .TXC_DMC_DMA_inc_pkt_cnt (TXC_DMC_DMA16_inc_pkt_cnt)
2058 );
2059
2060niu_txc_tdmc_context niu_txc_tdmc_context17 (
2061 .SysClk (SysClk),
2062 .Reset_L (Reset_L),
2063 .Port0_DMA_inc_head (Port0_DMA17_inc_head),
2064 .Port0_DMA_reset_done (Port0_DMA17_reset_done),
2065 .Port0_DMA_mark_bit (Port0_DMA17_mark_bit),
2066 .Port0_DMA_inc_pkt_cnt (Port0_DMA17_inc_pkt_cnt),
2067 .Port0_SetGetNextDescDMA (Port0_SetGetNextDescDMA17),
2068 .Port1_DMA_inc_head (Port1_DMA17_inc_head),
2069 .Port1_DMA_reset_done (Port1_DMA17_reset_done),
2070 .Port1_DMA_mark_bit (Port1_DMA17_mark_bit),
2071 .Port1_DMA_inc_pkt_cnt (Port1_DMA17_inc_pkt_cnt),
2072 .Port1_SetGetNextDescDMA (Port1_SetGetNextDescDMA17),
2073 .Port2_DMA_inc_head (Port2_DMA17_inc_head),
2074 .Port2_DMA_reset_done (Port2_DMA17_reset_done),
2075 .Port2_DMA_mark_bit (Port2_DMA17_mark_bit),
2076 .Port2_DMA_inc_pkt_cnt (Port2_DMA17_inc_pkt_cnt),
2077 .Port2_SetGetNextDescDMA (Port2_SetGetNextDescDMA17),
2078 .Port3_DMA_inc_head (Port3_DMA17_inc_head),
2079 .Port3_DMA_reset_done (Port3_DMA17_reset_done),
2080 .Port3_DMA_mark_bit (Port3_DMA17_mark_bit),
2081 .Port3_DMA_inc_pkt_cnt (Port3_DMA17_inc_pkt_cnt),
2082 .Port3_SetGetNextDescDMA (Port3_SetGetNextDescDMA17),
2083 .DMC_TXC_DMA_GotNxtDesc (DMC_TXC_DMA17_GotNxtDesc),
2084 .TXC_DMC_DMA_GetNxtDesc (TXC_DMC_DMA17_GetNxtDesc),
2085 .TXC_DMC_DMA_inc_head (TXC_DMC_DMA17_inc_head),
2086 .TXC_DMC_DMA_reset_done (TXC_DMC_DMA17_reset_done),
2087 .TXC_DMC_DMA_mark_bit (TXC_DMC_DMA17_mark_bit),
2088 .TXC_DMC_DMA_inc_pkt_cnt (TXC_DMC_DMA17_inc_pkt_cnt)
2089 );
2090
2091niu_txc_tdmc_context niu_txc_tdmc_context18 (
2092 .SysClk (SysClk),
2093 .Reset_L (Reset_L),
2094 .Port0_DMA_inc_head (Port0_DMA18_inc_head),
2095 .Port0_DMA_reset_done (Port0_DMA18_reset_done),
2096 .Port0_DMA_mark_bit (Port0_DMA18_mark_bit),
2097 .Port0_DMA_inc_pkt_cnt (Port0_DMA18_inc_pkt_cnt),
2098 .Port0_SetGetNextDescDMA (Port0_SetGetNextDescDMA18),
2099 .Port1_DMA_inc_head (Port1_DMA18_inc_head),
2100 .Port1_DMA_reset_done (Port1_DMA18_reset_done),
2101 .Port1_DMA_mark_bit (Port1_DMA18_mark_bit),
2102 .Port1_DMA_inc_pkt_cnt (Port1_DMA18_inc_pkt_cnt),
2103 .Port1_SetGetNextDescDMA (Port1_SetGetNextDescDMA18),
2104 .Port2_DMA_inc_head (Port2_DMA18_inc_head),
2105 .Port2_DMA_reset_done (Port2_DMA18_reset_done),
2106 .Port2_DMA_mark_bit (Port2_DMA18_mark_bit),
2107 .Port2_DMA_inc_pkt_cnt (Port2_DMA18_inc_pkt_cnt),
2108 .Port2_SetGetNextDescDMA (Port2_SetGetNextDescDMA18),
2109 .Port3_DMA_inc_head (Port3_DMA18_inc_head),
2110 .Port3_DMA_reset_done (Port3_DMA18_reset_done),
2111 .Port3_DMA_mark_bit (Port3_DMA18_mark_bit),
2112 .Port3_DMA_inc_pkt_cnt (Port3_DMA18_inc_pkt_cnt),
2113 .Port3_SetGetNextDescDMA (Port3_SetGetNextDescDMA18),
2114 .DMC_TXC_DMA_GotNxtDesc (DMC_TXC_DMA18_GotNxtDesc),
2115 .TXC_DMC_DMA_GetNxtDesc (TXC_DMC_DMA18_GetNxtDesc),
2116 .TXC_DMC_DMA_inc_head (TXC_DMC_DMA18_inc_head),
2117 .TXC_DMC_DMA_reset_done (TXC_DMC_DMA18_reset_done),
2118 .TXC_DMC_DMA_mark_bit (TXC_DMC_DMA18_mark_bit),
2119 .TXC_DMC_DMA_inc_pkt_cnt (TXC_DMC_DMA18_inc_pkt_cnt)
2120 );
2121
2122niu_txc_tdmc_context niu_txc_tdmc_context19 (
2123 .SysClk (SysClk),
2124 .Reset_L (Reset_L),
2125 .Port0_DMA_inc_head (Port0_DMA19_inc_head),
2126 .Port0_DMA_reset_done (Port0_DMA19_reset_done),
2127 .Port0_DMA_mark_bit (Port0_DMA19_mark_bit),
2128 .Port0_DMA_inc_pkt_cnt (Port0_DMA19_inc_pkt_cnt),
2129 .Port0_SetGetNextDescDMA (Port0_SetGetNextDescDMA19),
2130 .Port1_DMA_inc_head (Port1_DMA19_inc_head),
2131 .Port1_DMA_reset_done (Port1_DMA19_reset_done),
2132 .Port1_DMA_mark_bit (Port1_DMA19_mark_bit),
2133 .Port1_DMA_inc_pkt_cnt (Port1_DMA19_inc_pkt_cnt),
2134 .Port1_SetGetNextDescDMA (Port1_SetGetNextDescDMA19),
2135 .Port2_DMA_inc_head (Port2_DMA19_inc_head),
2136 .Port2_DMA_reset_done (Port2_DMA19_reset_done),
2137 .Port2_DMA_mark_bit (Port2_DMA19_mark_bit),
2138 .Port2_DMA_inc_pkt_cnt (Port2_DMA19_inc_pkt_cnt),
2139 .Port2_SetGetNextDescDMA (Port2_SetGetNextDescDMA19),
2140 .Port3_DMA_inc_head (Port3_DMA19_inc_head),
2141 .Port3_DMA_reset_done (Port3_DMA19_reset_done),
2142 .Port3_DMA_mark_bit (Port3_DMA19_mark_bit),
2143 .Port3_DMA_inc_pkt_cnt (Port3_DMA19_inc_pkt_cnt),
2144 .Port3_SetGetNextDescDMA (Port3_SetGetNextDescDMA19),
2145 .DMC_TXC_DMA_GotNxtDesc (DMC_TXC_DMA19_GotNxtDesc),
2146 .TXC_DMC_DMA_GetNxtDesc (TXC_DMC_DMA19_GetNxtDesc),
2147 .TXC_DMC_DMA_inc_head (TXC_DMC_DMA19_inc_head),
2148 .TXC_DMC_DMA_reset_done (TXC_DMC_DMA19_reset_done),
2149 .TXC_DMC_DMA_mark_bit (TXC_DMC_DMA19_mark_bit),
2150 .TXC_DMC_DMA_inc_pkt_cnt (TXC_DMC_DMA19_inc_pkt_cnt)
2151 );
2152
2153niu_txc_tdmc_context niu_txc_tdmc_context20 (
2154 .SysClk (SysClk),
2155 .Reset_L (Reset_L),
2156 .Port0_DMA_inc_head (Port0_DMA20_inc_head),
2157 .Port0_DMA_reset_done (Port0_DMA20_reset_done),
2158 .Port0_DMA_mark_bit (Port0_DMA20_mark_bit),
2159 .Port0_DMA_inc_pkt_cnt (Port0_DMA20_inc_pkt_cnt),
2160 .Port0_SetGetNextDescDMA (Port0_SetGetNextDescDMA20),
2161 .Port1_DMA_inc_head (Port1_DMA20_inc_head),
2162 .Port1_DMA_reset_done (Port1_DMA20_reset_done),
2163 .Port1_DMA_mark_bit (Port1_DMA20_mark_bit),
2164 .Port1_DMA_inc_pkt_cnt (Port1_DMA20_inc_pkt_cnt),
2165 .Port1_SetGetNextDescDMA (Port1_SetGetNextDescDMA20),
2166 .Port2_DMA_inc_head (Port2_DMA20_inc_head),
2167 .Port2_DMA_reset_done (Port2_DMA20_reset_done),
2168 .Port2_DMA_mark_bit (Port2_DMA20_mark_bit),
2169 .Port2_DMA_inc_pkt_cnt (Port2_DMA20_inc_pkt_cnt),
2170 .Port2_SetGetNextDescDMA (Port2_SetGetNextDescDMA20),
2171 .Port3_DMA_inc_head (Port3_DMA20_inc_head),
2172 .Port3_DMA_reset_done (Port3_DMA20_reset_done),
2173 .Port3_DMA_mark_bit (Port3_DMA20_mark_bit),
2174 .Port3_DMA_inc_pkt_cnt (Port3_DMA20_inc_pkt_cnt),
2175 .Port3_SetGetNextDescDMA (Port3_SetGetNextDescDMA20),
2176 .DMC_TXC_DMA_GotNxtDesc (DMC_TXC_DMA20_GotNxtDesc),
2177 .TXC_DMC_DMA_GetNxtDesc (TXC_DMC_DMA20_GetNxtDesc),
2178 .TXC_DMC_DMA_inc_head (TXC_DMC_DMA20_inc_head),
2179 .TXC_DMC_DMA_reset_done (TXC_DMC_DMA20_reset_done),
2180 .TXC_DMC_DMA_mark_bit (TXC_DMC_DMA20_mark_bit),
2181 .TXC_DMC_DMA_inc_pkt_cnt (TXC_DMC_DMA20_inc_pkt_cnt)
2182 );
2183
2184niu_txc_tdmc_context niu_txc_tdmc_context21 (
2185 .SysClk (SysClk),
2186 .Reset_L (Reset_L),
2187 .Port0_DMA_inc_head (Port0_DMA21_inc_head),
2188 .Port0_DMA_reset_done (Port0_DMA21_reset_done),
2189 .Port0_DMA_mark_bit (Port0_DMA21_mark_bit),
2190 .Port0_DMA_inc_pkt_cnt (Port0_DMA21_inc_pkt_cnt),
2191 .Port0_SetGetNextDescDMA (Port0_SetGetNextDescDMA21),
2192 .Port1_DMA_inc_head (Port1_DMA21_inc_head),
2193 .Port1_DMA_reset_done (Port1_DMA21_reset_done),
2194 .Port1_DMA_mark_bit (Port1_DMA21_mark_bit),
2195 .Port1_DMA_inc_pkt_cnt (Port1_DMA21_inc_pkt_cnt),
2196 .Port1_SetGetNextDescDMA (Port1_SetGetNextDescDMA21),
2197 .Port2_DMA_inc_head (Port2_DMA21_inc_head),
2198 .Port2_DMA_reset_done (Port2_DMA21_reset_done),
2199 .Port2_DMA_mark_bit (Port2_DMA21_mark_bit),
2200 .Port2_DMA_inc_pkt_cnt (Port2_DMA21_inc_pkt_cnt),
2201 .Port2_SetGetNextDescDMA (Port2_SetGetNextDescDMA21),
2202 .Port3_DMA_inc_head (Port3_DMA21_inc_head),
2203 .Port3_DMA_reset_done (Port3_DMA21_reset_done),
2204 .Port3_DMA_mark_bit (Port3_DMA21_mark_bit),
2205 .Port3_DMA_inc_pkt_cnt (Port3_DMA21_inc_pkt_cnt),
2206 .Port3_SetGetNextDescDMA (Port3_SetGetNextDescDMA21),
2207 .DMC_TXC_DMA_GotNxtDesc (DMC_TXC_DMA21_GotNxtDesc),
2208 .TXC_DMC_DMA_GetNxtDesc (TXC_DMC_DMA21_GetNxtDesc),
2209 .TXC_DMC_DMA_inc_head (TXC_DMC_DMA21_inc_head),
2210 .TXC_DMC_DMA_reset_done (TXC_DMC_DMA21_reset_done),
2211 .TXC_DMC_DMA_mark_bit (TXC_DMC_DMA21_mark_bit),
2212 .TXC_DMC_DMA_inc_pkt_cnt (TXC_DMC_DMA21_inc_pkt_cnt)
2213 );
2214
2215niu_txc_tdmc_context niu_txc_tdmc_context22 (
2216 .SysClk (SysClk),
2217 .Reset_L (Reset_L),
2218 .Port0_DMA_inc_head (Port0_DMA22_inc_head),
2219 .Port0_DMA_reset_done (Port0_DMA22_reset_done),
2220 .Port0_DMA_mark_bit (Port0_DMA22_mark_bit),
2221 .Port0_DMA_inc_pkt_cnt (Port0_DMA22_inc_pkt_cnt),
2222 .Port0_SetGetNextDescDMA (Port0_SetGetNextDescDMA22),
2223 .Port1_DMA_inc_head (Port1_DMA22_inc_head),
2224 .Port1_DMA_reset_done (Port1_DMA22_reset_done),
2225 .Port1_DMA_mark_bit (Port1_DMA22_mark_bit),
2226 .Port1_DMA_inc_pkt_cnt (Port1_DMA22_inc_pkt_cnt),
2227 .Port1_SetGetNextDescDMA (Port1_SetGetNextDescDMA22),
2228 .Port2_DMA_inc_head (Port2_DMA22_inc_head),
2229 .Port2_DMA_reset_done (Port2_DMA22_reset_done),
2230 .Port2_DMA_mark_bit (Port2_DMA22_mark_bit),
2231 .Port2_DMA_inc_pkt_cnt (Port2_DMA22_inc_pkt_cnt),
2232 .Port2_SetGetNextDescDMA (Port2_SetGetNextDescDMA22),
2233 .Port3_DMA_inc_head (Port3_DMA22_inc_head),
2234 .Port3_DMA_reset_done (Port3_DMA22_reset_done),
2235 .Port3_DMA_mark_bit (Port3_DMA22_mark_bit),
2236 .Port3_DMA_inc_pkt_cnt (Port3_DMA22_inc_pkt_cnt),
2237 .Port3_SetGetNextDescDMA (Port3_SetGetNextDescDMA22),
2238 .DMC_TXC_DMA_GotNxtDesc (DMC_TXC_DMA22_GotNxtDesc),
2239 .TXC_DMC_DMA_GetNxtDesc (TXC_DMC_DMA22_GetNxtDesc),
2240 .TXC_DMC_DMA_inc_head (TXC_DMC_DMA22_inc_head),
2241 .TXC_DMC_DMA_reset_done (TXC_DMC_DMA22_reset_done),
2242 .TXC_DMC_DMA_mark_bit (TXC_DMC_DMA22_mark_bit),
2243 .TXC_DMC_DMA_inc_pkt_cnt (TXC_DMC_DMA22_inc_pkt_cnt)
2244 );
2245
2246niu_txc_tdmc_context niu_txc_tdmc_context23 (
2247 .SysClk (SysClk),
2248 .Reset_L (Reset_L),
2249 .Port0_DMA_inc_head (Port0_DMA23_inc_head),
2250 .Port0_DMA_reset_done (Port0_DMA23_reset_done),
2251 .Port0_DMA_mark_bit (Port0_DMA23_mark_bit),
2252 .Port0_DMA_inc_pkt_cnt (Port0_DMA23_inc_pkt_cnt),
2253 .Port0_SetGetNextDescDMA (Port0_SetGetNextDescDMA23),
2254 .Port1_DMA_inc_head (Port1_DMA23_inc_head),
2255 .Port1_DMA_reset_done (Port1_DMA23_reset_done),
2256 .Port1_DMA_mark_bit (Port1_DMA23_mark_bit),
2257 .Port1_DMA_inc_pkt_cnt (Port1_DMA23_inc_pkt_cnt),
2258 .Port1_SetGetNextDescDMA (Port1_SetGetNextDescDMA23),
2259 .Port2_DMA_inc_head (Port2_DMA23_inc_head),
2260 .Port2_DMA_reset_done (Port2_DMA23_reset_done),
2261 .Port2_DMA_mark_bit (Port2_DMA23_mark_bit),
2262 .Port2_DMA_inc_pkt_cnt (Port2_DMA23_inc_pkt_cnt),
2263 .Port2_SetGetNextDescDMA (Port2_SetGetNextDescDMA23),
2264 .Port3_DMA_inc_head (Port3_DMA23_inc_head),
2265 .Port3_DMA_reset_done (Port3_DMA23_reset_done),
2266 .Port3_DMA_mark_bit (Port3_DMA23_mark_bit),
2267 .Port3_DMA_inc_pkt_cnt (Port3_DMA23_inc_pkt_cnt),
2268 .Port3_SetGetNextDescDMA (Port3_SetGetNextDescDMA23),
2269 .DMC_TXC_DMA_GotNxtDesc (DMC_TXC_DMA23_GotNxtDesc),
2270 .TXC_DMC_DMA_GetNxtDesc (TXC_DMC_DMA23_GetNxtDesc),
2271 .TXC_DMC_DMA_inc_head (TXC_DMC_DMA23_inc_head),
2272 .TXC_DMC_DMA_reset_done (TXC_DMC_DMA23_reset_done),
2273 .TXC_DMC_DMA_mark_bit (TXC_DMC_DMA23_mark_bit),
2274 .TXC_DMC_DMA_inc_pkt_cnt (TXC_DMC_DMA23_inc_pkt_cnt)
2275 );
2276
2277endmodule
Full OpenSPARC design & verification tarball including full HDL.