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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / design / sys / iop / niu / rtl / niu_wr_meta_arb.v
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AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: niu_wr_meta_arb.v
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35/*-----------------------------------------------------------------------------
36-------------------------------------------------------------------------------
37-- Company: Sun Microsystems, Inc.
38-- SUN CONFIDENTIAL/PROPRIETARY - Copyright 2004
39-- Description: [Verilog RTL Code]
40-- Write META Arb
41-- TransID Management
42-- Project: Niagara2/Neptune
43-- Platform:
44-- Parent Module: NIU
45-- Module: NIU_WR_META_ARB
46-- Designer: Carl Childers
47 : Nimita Taneja
48-- Date Created: 07/01/2004
49-- Date Modified 10/19/2004
50-- Notes:
51-- 1.
52-- 2.
53-- Rev: 0.1; Board Rev: P1.0
54-------------------------------------------------------------------------------
55-----------------------------------------------------------------------------*/
56
57/*--------------------------------------
58-- Module
59--------------------------------------*/
60
61module niu_wr_meta_arb ( /*AUTOARG*/
62 // Outputs
63 dmc_meta0_req_cmd, dmc_meta0_req_address, dmc_meta0_req_length,
64 dmc_meta0_req_transID, dmc_meta0_req_port_num,
65 dmc_meta0_req_dma_num, dmc_meta0_req_func_num,
66 dmc_meta0_req_client, dmc_meta0_req, dmc_meta0_transfer_complete,
67 dmc_meta0_data, dmc_meta0_req_byteenable, dmc_meta0_status,
68 dmc_meta0_data_valid, arb0_tdmc_req_accept, arb0_tdmc_data_req,
69 arb0_tdmc_req_errors, arb0_rdc_req_accept, arb0_rdc_data_req,
70 arb0_rdc_req_errors, arb0_rcr_req_accept, arb0_rcr_data_req,
71 arb0_rcr_req_errors, arb_pio_dirtid_npwstatus,
72 arb_pio_all_npwdirty,
73 // Inputs
74 meta_dmc0_req_accept, meta_dmc0_data_req, meta_dmc0_req_errors,
75 tdmc_arb0_req_cmd, tdmc_arb0_req_address, tdmc_arb0_req_length,
76 tdmc_arb0_req_port_num, tdmc_arb0_req_dma_num,
77 tdmc_arb0_req_func_num, tdmc_arb0_req,
78 tdmc_arb0_transfer_complete, tdmc_arb0_data,
79 tdmc_arb0_req_byteenable, tdmc_arb0_status, tdmc_arb0_data_valid,
80 rdc_arb0_req_cmd, rdc_arb0_req_address, rdc_arb0_req_length,
81 rdc_arb0_req_port_num, rdc_arb0_req_dma_num,
82 rdc_arb0_req_func_num, rdc_arb0_req, rdc_arb0_transfer_complete,
83 rdc_arb0_data, rdc_arb0_req_byteenable, rdc_arb0_status,
84 rdc_arb0_data_valid, rcr_arb0_req_cmd, rcr_arb0_req_address,
85 rcr_arb0_req_length, rcr_arb0_req_port_num, rcr_arb0_req_dma_num,
86 rcr_arb0_req_func_num, rcr_arb0_req, rcr_arb0_transfer_complete,
87 rcr_arb0_data, rcr_arb0_req_byteenable, rcr_arb0_status,
88 rcr_arb0_data_valid, meta_dmc_ack_transID, dmc_meta_ack_accept,
89 meta_dmc_ack_transfer_cmpl, meta_dmc_ack_cmd_status,
90 pio_arb_dirtid_enable, pio_arb_dirtid_clr, pio_arb_np_threshold,
91 clk, reset
92 ); // from reset
93
94
95/*-----------------------------------------------------------------------------
96-- Declarations
97-----------------------------------------------------------------------------*/
98/*--------------------------------------
99-- Port Declaration
100--------------------------------------*/
101
102 // META Request Outputs
103 output [7:0] dmc_meta0_req_cmd; // Command Request
104 output [63:0] dmc_meta0_req_address; // Memory Address
105 output [13:0] dmc_meta0_req_length; // Packet Length
106 output [5:0] dmc_meta0_req_transID; // Transaction ID
107 output [1:0] dmc_meta0_req_port_num; // Port Number
108 output [4:0] dmc_meta0_req_dma_num; // Channel Number
109 output [1:0] dmc_meta0_req_func_num; // Channel Number
110 output [7:0] dmc_meta0_req_client; // Client [vector]
111 output dmc_meta0_req; // Req Command Request
112 output dmc_meta0_transfer_complete; // Transfer Data Complete
113
114 output [127:0] dmc_meta0_data; // Transfer Data
115 output [15:0] dmc_meta0_req_byteenable; // First/Last BE
116 output [3:0] dmc_meta0_status; // Transfer Data Status
117 output dmc_meta0_data_valid; // Transfer Data Ack
118
119 // TDMC I/F Output
120 output arb0_tdmc_req_accept; // Response to REQ
121 output arb0_tdmc_data_req; // Memory line request
122 output arb0_tdmc_req_errors; // Error flag
123
124 // RDC I/F Output
125 output arb0_rdc_req_accept; // Response to REQ
126 output arb0_rdc_data_req; // Memory line request
127 output arb0_rdc_req_errors; // Error flag
128
129 // RCR I/F Output
130 output arb0_rcr_req_accept; // Response to REQ
131 output arb0_rcr_data_req; // Memory line request
132 output arb0_rcr_req_errors; // Error flag
133
134 output [5:0] arb_pio_dirtid_npwstatus;// count for number of np write TID's dirty
135 output arb_pio_all_npwdirty; // all dirty bin entries are dirty
136
137
138
139 // RBR I/F Output
140// output arb0_rbr_req_accept; // Response to REQ
141// output arb0_rbr_data_req; // Memory line request
142// output arb0_rbr_req_errors; // Error flag
143
144 // META Request Inputs
145 input meta_dmc0_req_accept; // Response to REQ
146 input meta_dmc0_data_req; // Memory line request
147 input meta_dmc0_req_errors; // Error flag
148
149 // TDMC I/F Inputs
150 input [7:0] tdmc_arb0_req_cmd; // Command Request
151 input [63:0] tdmc_arb0_req_address; // Memory Address
152 input [13:0] tdmc_arb0_req_length; // Packet Length
153 input [1:0] tdmc_arb0_req_port_num; // Port Number
154 input [4:0] tdmc_arb0_req_dma_num; // Channel Number
155 input [1:0] tdmc_arb0_req_func_num; // Func Number
156 input tdmc_arb0_req; // Req Command Request
157 input tdmc_arb0_transfer_complete; // Transfer Data Complete
158
159 input [127:0] tdmc_arb0_data; // Transfer Data
160 input [15:0] tdmc_arb0_req_byteenable; // First/Last BE
161 input [3:0] tdmc_arb0_status; // Transfer Data Status
162 input tdmc_arb0_data_valid; // Transfer Data Ack
163
164 // RDC I/F Inputs
165 input [7:0] rdc_arb0_req_cmd; // Command Request
166 input [63:0] rdc_arb0_req_address; // Memory Address
167 input [13:0] rdc_arb0_req_length; // Packet Length
168 input [1:0] rdc_arb0_req_port_num; // Port Number
169 input [4:0] rdc_arb0_req_dma_num; // Channel Number
170 input [1:0] rdc_arb0_req_func_num; // Channel Number
171 input rdc_arb0_req; // Req Command Request
172 input rdc_arb0_transfer_complete; // Transfer Data Complete
173
174 input [127:0] rdc_arb0_data; // Transfer Data
175 input [15:0] rdc_arb0_req_byteenable; // First/Last BE
176 input [3:0] rdc_arb0_status; // Transfer Data Status
177 input rdc_arb0_data_valid; // Transfer Data Ack
178
179 // RCR I/F Inputs
180 input [7:0] rcr_arb0_req_cmd; // Command Request
181 input [63:0] rcr_arb0_req_address; // Memory Address
182 input [13:0] rcr_arb0_req_length; // Packet Length
183 input [1:0] rcr_arb0_req_port_num; // Port Number
184 input [4:0] rcr_arb0_req_dma_num; // Channel Number
185 input [1:0] rcr_arb0_req_func_num; // Channel Number
186 input rcr_arb0_req; // Req Command Request
187 input rcr_arb0_transfer_complete; // Transfer Data Complete
188
189 input [127:0] rcr_arb0_data; // Transfer Data
190 input [15:0] rcr_arb0_req_byteenable; // First/Last BE
191 input [3:0] rcr_arb0_status; // Transfer Data Status
192 input rcr_arb0_data_valid; // Transfer Data Ack
193
194 // RBR I/F Inputs
195// input [7:0] rbr_arb0_req_cmd; // Command Request
196// input [63:0] rbr_arb0_req_address; // Memory Address
197// input [13:0] rbr_arb0_req_length; // Packet Length
198// input [1:0] rbr_arb0_req_port_num; // Port Number
199// input [4:0] rbr_arb0_req_dma_num; // Channel Number
200// input rbr_arb0_req; // Req Command Request
201// input rbr_arb0_transfer_complete; // Transfer Data Complete
202
203// input [127:0] rbr_arb0_data; // Transfer Data
204// input [15:0] rbr_arb0_req_byteenable; // First/Last BE
205// input [3:0] rbr_arb0_status; // Transfer Data Status
206// input rbr_arb0_data_valid; // Transfer Data Ack
207
208 // META Acknowledge Input
209 input [5:0] meta_dmc_ack_transID; // Free TransID
210 input [7:0] dmc_meta_ack_accept; // Valid TransID
211 input [7:0] meta_dmc_ack_transfer_cmpl; // Last trans of TransID
212 input [3:0] meta_dmc_ack_cmd_status; // status in command phase
213
214
215 //Dirty TID Interface
216 input pio_arb_dirtid_enable; // Enable Dirty TID logic
217 input pio_arb_dirtid_clr; // Clear all Dirty TID Entries
218 input [5:0] pio_arb_np_threshold; // np write threshold
219
220
221 // other inputs
222 input clk; // core clock
223 input reset; // reset
224
225/***************************************/
226/* Wire Declaration */
227/***************************************/
228 /*AUTOWIRE*/
229 // Beginning of automatic wires (for undeclared instantiated-module outputs)
230 // End of automatics
231
232 wire arb0_fifo_not_empty; // From arb_tagfifo of arb_tagfifo.v
233 wire [4:0] rdtagoutR; // From arb_tagfifo of arb_tagfifo.v
234
235 wire dmc_meta_ack_accept_ORd;
236
237 wire meta_dmc_ack_transfer_cmpl_ORd;
238 wire posted_req_accepted;
239 wire posted_req;
240
241
242 wire transaction_timeout;
243 wire [5:0] dirty_tag_count;
244 wire dirtybinfifo_not_empty;
245 wire dirtybinfifo_full;
246 wire [4:0] dirty_tag;
247 wire arb_pio_all_npwdirty;
248 wire npw_threshold_reached;
249
250/***************************************/
251/* Reg Declaration */
252/***************************************/
253 reg [2:0] arb_control_sel_ff,
254 arb_control_sel_in;
255 reg arb_control_sel_ld;
256// reg [2:0] arb_control_sel_ffR;
257
258 reg [2:0] arb_datapath_sel_ff,
259 arb_datapath_sel_in;
260 reg arb_datapath_sel_ld;
261
262 // Transaction ID tag read and write pointer incrementer
263 reg read_tag;
264 reg write_tag;
265 reg write_dirty_tag;
266 reg meta_dmc_ack_transfer_cmpl_ORdR;
267 reg [4:0] meta_dmc_ack_transID_cmpl;
268 reg [4:0] meta_dmc_ack_transIDR;
269 reg [4:0] meta_dmc_ack_transID0R;
270 reg [4:0] meta_dmc_ack_transID1R;
271 reg [4:0] meta_dmc_ack_transID2R;
272 reg [4:0] meta_dmc_ack_transID3R;
273 reg [4:0] meta_dmc_ack_transID4R;
274 reg [4:0] meta_dmc_ack_transID5R;
275 reg [4:0] meta_dmc_ack_transID6R;
276 reg [4:0] meta_dmc_ack_transID7R;
277 reg [4:0] dmc_meta0_req_transIDR;
278 reg [3:0] meta_dmc_ack_cmd_statusR;
279
280
281
282 // Arb Control MUX
283 reg [7:0] mux_dmc_meta0_req_cmd;
284 reg [63:0] mux_dmc_meta0_req_address;
285 reg [13:0] mux_dmc_meta0_req_length;
286 reg [1:0] mux_dmc_meta0_req_port_num;
287 reg [4:0] mux_dmc_meta0_req_dma_num;
288 reg [1:0] mux_dmc_meta0_req_func_num;
289 reg [7:0] mux_dmc_meta0_req_client;
290 reg mux_dmc_meta0_req;
291
292 reg demux_arb0_tdmc_req_accept;
293 reg demux_arb0_rdc_req_accept;
294 reg demux_arb0_rcr_req_accept;
295// reg demux_arb0_rbr_req_accept;
296
297 // Arb Control State Machine
298
299// reg fsm_start_datapath_fsm;
300// reg start_data_phase;
301// reg data_phase_started;
302
303 reg [2:0] current_arb_control_state_ff,
304 next_arb_control_state;
305
306 // Arb Datapath MUX
307 reg mux_dmc_meta0_transfer_complete;
308
309 reg [127:0] mux_dmc_meta0_data;
310 reg [15:0] mux_dmc_meta0_req_byteenable;
311 reg [3:0] mux_dmc_meta0_status;
312 reg mux_dmc_meta0_data_valid;
313
314 reg demux_arb0_tdmc_data_req;
315 reg demux_arb0_tdmc_req_errors;
316
317 reg demux_arb0_rdc_data_req;
318 reg demux_arb0_rdc_req_errors;
319
320 reg demux_arb0_rcr_data_req;
321 reg demux_arb0_rcr_req_errors;
322
323// reg demux_arb0_rbr_data_req;
324// reg demux_arb0_rbr_req_errors;
325
326 // Arb Datapath State Machine
327// reg [2:0] current_arb_datapath_state_ff,
328// next_arb_datapath_state;
329
330 // Returned TransID State Machine
331 reg sel_posted_tag;
332 //State Register
333
334 reg state, stateR;
335 reg [4:0] returned_tag;
336 reg posted_req_acceptedR;
337
338 // dirty bin registers
339 reg transfer_cmpl_pending;
340 reg [5:0] arb_pio_dirtid_npwstatus;
341 reg [1:0] dirbin_state, dirbin_stateR;
342 reg inc_dirtybinfifo_rp;
343 reg return_dirty_tag;
344 reg [5:0] outstanding_tid_cnt;
345
346 wire inc_outstanding_tid_cnt= (meta_dmc0_req_accept & ~posted_req) & ~meta_dmc_ack_transfer_cmpl_ORd;
347 wire dec_outstanding_tid_cnt= meta_dmc_ack_transfer_cmpl_ORd & ~(meta_dmc0_req_accept & ~posted_req);
348
349 wire [5:0] outstanding_tid_cnt_plus1= outstanding_tid_cnt + 1'b1;
350 wire [5:0] outstanding_tid_cnt_minus1= outstanding_tid_cnt - 1'b1;
351 wire [5:0] outstanding_tid_cnt_add_n= (outstanding_tid_cnt==6'd32)? 6'h0 : outstanding_tid_cnt_plus1;
352 wire [5:0] outstanding_tid_cnt_sub_n= (outstanding_tid_cnt==6'd0)? 6'h0 : outstanding_tid_cnt_minus1;
353
354
355wire tdmc_is_post= tdmc_arb0_req_cmd[5];
356wire rdc_is_post= rdc_arb0_req_cmd[5];
357wire rcr_is_post= rcr_arb0_req_cmd[5];
358
359// active low; mask off req if threshold reached and req is non-post
360wire mask_tdmc_req_l= ~(npw_threshold_reached & ~tdmc_is_post);
361wire mask_rdc_req_l= ~(npw_threshold_reached & ~rdc_is_post);
362wire mask_rcr_req_l= ~(npw_threshold_reached & ~rcr_is_post);
363
364wire tdmc_arb0_req_cond= tdmc_arb0_req & mask_tdmc_req_l;
365wire rdc_arb0_req_cond= rdc_arb0_req & mask_rdc_req_l;
366wire rcr_arb0_req_cond= rcr_arb0_req & mask_rcr_req_l;
367
368
369/***************************************/
370/* Parameter Declaration */
371/***************************************/
372
373 parameter [2:0] NULL = 3'b000,
374 TDMC = 3'b001,
375 RDC = 3'b010,
376 RCR = 3'b011;
377// RBR = 3'b100;
378
379
380
381 parameter [7:0] NULL_CLIENT = 8'h00,
382 TDMC_CLIENT = 8'h04,
383 RDC_CLIENT = 8'h08,
384 RCR_CLIENT = 8'h10;
385
386
387
388
389 parameter [2:0] CACS0 = 3'b000,
390 CACS1 = 3'b001,
391 CACS2 = 3'b010,
392 CACS3 = 3'b011,
393 CACS4 = 3'b100,
394 CACS5 = 3'b101,
395 CACS6 = 3'b110,
396 CACS7 = 3'b111;
397
398/*
399 parameter [2:0] CADS0 = 3'b000,
400 CADS1 = 3'b001,
401 CADS2 = 3'b010,
402 CADS3 = 3'b011,
403 CADS4 = 3'b100;
404*/
405
406
407
408 parameter ZERO_1 = 1'b0;
409 parameter [1:0] ZEROES_2 = 2'b00;
410 parameter [3:0] ZEROES_4 = 4'h0;
411 parameter [4:0] ZEROES_5 = 5'b00000;
412 parameter [7:0] ZEROES_8 = 8'b00000000;
413 parameter [13:0] ZEROES_14 = 14'b00000000000000;
414 parameter [15:0] ZEROES_16 = 16'h0;
415 parameter [63:0] ZEROES_64 = 64'h0000;
416 parameter [127:0] ZEROES_128 = 128'h00000000;
417
418 // misc
419 parameter ASSERT_H = 1'b1,
420 DEASSERT_L = 1'b0,
421 TRUE_H = 1'b1;
422
423
424 parameter IDLE = 1'b0,
425 TAG1 = 1'b1;
426
427 parameter [1:0] IDLEBIN = 2'b00,
428 CLRBIN = 2'b01,
429 RDBIN = 2'b10;
430
431/*-----------------------------------------------------------------------------
432-- Output Assignments
433-----------------------------------------------------------------------------*/
434 // META Request Outputs
435 assign dmc_meta0_req_cmd = mux_dmc_meta0_req_cmd;
436 assign dmc_meta0_req_address = mux_dmc_meta0_req_address;
437 assign dmc_meta0_req_length = mux_dmc_meta0_req_length;
438 assign dmc_meta0_req_transID = {1'b1,rdtagoutR};
439 assign dmc_meta0_req_port_num = mux_dmc_meta0_req_port_num;
440 assign dmc_meta0_req_dma_num = mux_dmc_meta0_req_dma_num;
441 assign dmc_meta0_req_func_num = mux_dmc_meta0_req_func_num;
442 assign dmc_meta0_req_client = mux_dmc_meta0_req_client;
443 assign dmc_meta0_req = mux_dmc_meta0_req;
444 assign dmc_meta0_transfer_complete = mux_dmc_meta0_transfer_complete;
445
446 assign dmc_meta0_data = mux_dmc_meta0_data;
447 assign dmc_meta0_req_byteenable = mux_dmc_meta0_req_byteenable;
448 assign dmc_meta0_status = mux_dmc_meta0_status;
449 assign dmc_meta0_data_valid = mux_dmc_meta0_data_valid;
450
451 // TDMC I/F Outputs
452 assign arb0_tdmc_req_accept = demux_arb0_tdmc_req_accept;
453 assign arb0_tdmc_data_req = demux_arb0_tdmc_data_req;
454 assign arb0_tdmc_req_errors = demux_arb0_tdmc_req_errors;
455
456 // RDC I/F Outputs
457 assign arb0_rdc_req_accept = demux_arb0_rdc_req_accept;
458 assign arb0_rdc_data_req = demux_arb0_rdc_data_req;
459 assign arb0_rdc_req_errors = demux_arb0_rdc_req_errors;
460
461 // RCR I/F Outputs
462 assign arb0_rcr_req_accept = demux_arb0_rcr_req_accept;
463 assign arb0_rcr_data_req = demux_arb0_rcr_data_req;
464 assign arb0_rcr_req_errors = demux_arb0_rcr_req_errors;
465
466 // RBR I/F Outputs
467// assign arb0_rbr_req_accept = demux_arb0_rbr_req_accept;
468// assign arb0_rbr_data_req = demux_arb0_rbr_data_req;
469// assign arb0_rbr_req_errors = demux_arb0_rbr_req_errors;
470
471
472/*-----------------------------------------------------------------------------
473-- Arbitration CONTROL
474-----------------------------------------------------------------------------*/
475/*--------------------------------------
476-- Concurrent combinatorial logic: Arbitration CONTROL MUX
477--------------------------------------*/
478
479 always @ (tdmc_arb0_req_cmd or tdmc_arb0_req_address or
480 tdmc_arb0_req_length or tdmc_arb0_req_port_num or
481 tdmc_arb0_req_dma_num or tdmc_arb0_req_cond or
482 tdmc_arb0_req_func_num or
483
484 rdc_arb0_req_cmd or rdc_arb0_req_address or
485 rdc_arb0_req_length or rdc_arb0_req_port_num or
486 rdc_arb0_req_dma_num or rdc_arb0_req_cond or
487 rdc_arb0_req_func_num or
488
489 rcr_arb0_req_cmd or rcr_arb0_req_address or
490 rcr_arb0_req_length or rcr_arb0_req_port_num or
491 rcr_arb0_req_dma_num or rcr_arb0_req_cond or
492 rcr_arb0_req_func_num or
493
494// rbr_arb0_req_cmd or rbr_arb0_req_address or
495// rbr_arb0_req_length or rbr_arb0_req_port_num or
496// rbr_arb0_req_dma_num or rbr_arb0_req or
497
498 meta_dmc0_req_accept or arb_control_sel_ff)
499
500 begin: arbitration_control_mux
501 mux_dmc_meta0_req_cmd = ZEROES_8;
502 mux_dmc_meta0_req_address = ZEROES_64;
503 mux_dmc_meta0_req_length = ZEROES_14;
504 mux_dmc_meta0_req_port_num = ZEROES_2;
505 mux_dmc_meta0_req_dma_num = ZEROES_5;
506 mux_dmc_meta0_req_func_num = ZEROES_2;
507 mux_dmc_meta0_req_client = NULL_CLIENT;
508 mux_dmc_meta0_req = ZERO_1;
509
510 demux_arb0_tdmc_req_accept = ZERO_1;
511 demux_arb0_rdc_req_accept = ZERO_1;
512 demux_arb0_rcr_req_accept = ZERO_1;
513// demux_arb0_rbr_req_accept = ZERO_1;
514
515 case (arb_control_sel_ff) /* synopsys parallel_case full_case */
516 NULL: begin
517 mux_dmc_meta0_req_cmd = ZEROES_8;
518 mux_dmc_meta0_req_address = ZEROES_64;
519 mux_dmc_meta0_req_length = ZEROES_14;
520 mux_dmc_meta0_req_port_num = ZEROES_2;
521 mux_dmc_meta0_req_dma_num = ZEROES_5;
522 mux_dmc_meta0_req_func_num = ZEROES_2;
523 mux_dmc_meta0_req_client = NULL_CLIENT;
524 mux_dmc_meta0_req = ZERO_1;
525 demux_arb0_tdmc_req_accept = ZERO_1;
526 demux_arb0_rdc_req_accept = ZERO_1;
527 demux_arb0_rcr_req_accept = ZERO_1;
528// demux_arb0_rbr_req_accept = ZERO_1;
529 end
530 TDMC: begin
531 mux_dmc_meta0_req_cmd = tdmc_arb0_req_cmd;
532 mux_dmc_meta0_req_address = tdmc_arb0_req_address;
533 mux_dmc_meta0_req_length = tdmc_arb0_req_length;
534 mux_dmc_meta0_req_port_num = tdmc_arb0_req_port_num;
535 mux_dmc_meta0_req_dma_num = tdmc_arb0_req_dma_num;
536 mux_dmc_meta0_req_func_num = tdmc_arb0_req_func_num;
537 mux_dmc_meta0_req_client = TDMC_CLIENT;
538 mux_dmc_meta0_req = tdmc_arb0_req_cond;
539
540 demux_arb0_tdmc_req_accept = meta_dmc0_req_accept;
541 end
542 RDC: begin
543 mux_dmc_meta0_req_cmd = rdc_arb0_req_cmd;
544 mux_dmc_meta0_req_address = rdc_arb0_req_address;
545 mux_dmc_meta0_req_length = rdc_arb0_req_length;
546 mux_dmc_meta0_req_port_num = rdc_arb0_req_port_num;
547 mux_dmc_meta0_req_dma_num = rdc_arb0_req_dma_num;
548 mux_dmc_meta0_req_func_num = rdc_arb0_req_func_num;
549 mux_dmc_meta0_req_client = RDC_CLIENT;
550 mux_dmc_meta0_req = rdc_arb0_req_cond;
551
552 demux_arb0_rdc_req_accept = meta_dmc0_req_accept;
553 end
554 RCR: begin
555 mux_dmc_meta0_req_cmd = rcr_arb0_req_cmd;
556 mux_dmc_meta0_req_address = rcr_arb0_req_address;
557 mux_dmc_meta0_req_length = rcr_arb0_req_length;
558 mux_dmc_meta0_req_port_num = rcr_arb0_req_port_num;
559 mux_dmc_meta0_req_dma_num = rcr_arb0_req_dma_num;
560 mux_dmc_meta0_req_func_num = rcr_arb0_req_func_num;
561 mux_dmc_meta0_req_client = RCR_CLIENT;
562 mux_dmc_meta0_req = rcr_arb0_req_cond;
563
564 demux_arb0_rcr_req_accept = meta_dmc0_req_accept;
565 end
566// RBR: begin
567// mux_dmc_meta0_req_cmd = rbr_arb0_req_cmd;
568// mux_dmc_meta0_req_address = rbr_arb0_req_address;
569// mux_dmc_meta0_req_length = rbr_arb0_req_length;
570// mux_dmc_meta0_req_port_num = rbr_arb0_req_port_num;
571// mux_dmc_meta0_req_dma_num = rbr_arb0_req_dma_num;
572// mux_dmc_meta0_req_client = RBR_CLIENT;
573// mux_dmc_meta0_req = rbr_arb0_req;
574
575// demux_arb0_rbr_req_accept = meta_dmc0_req_accept;
576// end
577 default: begin
578 mux_dmc_meta0_req_cmd = ZEROES_8;
579 mux_dmc_meta0_req_address = ZEROES_64;
580 mux_dmc_meta0_req_length = ZEROES_14;
581 mux_dmc_meta0_req_port_num = ZEROES_2;
582 mux_dmc_meta0_req_dma_num = ZEROES_5;
583 mux_dmc_meta0_req_func_num = ZEROES_2;
584 mux_dmc_meta0_req_client = NULL_CLIENT;
585 mux_dmc_meta0_req = ZERO_1;
586
587 demux_arb0_tdmc_req_accept = ZERO_1;
588 demux_arb0_rdc_req_accept = ZERO_1;
589 demux_arb0_rcr_req_accept = ZERO_1;
590// demux_arb0_rbr_req_accept = ZERO_1;
591 end
592 endcase
593 end
594
595/*--------------------------------------
596-- Concurrent combinatorial logic:Round Robin Arbitration CONTROL State Machine
597--------------------------------------*/
598 always @ (/*AUTOSENSE*/arb0_fifo_not_empty
599 or current_arb_control_state_ff or meta_dmc0_req_accept
600 or rcr_arb0_req_cond or rdc_arb0_req_cond or tdmc_arb0_req_cond or
601 arb_control_sel_ff)
602 begin: arbitration_control_fsm
603 arb_control_sel_in = NULL;
604 arb_control_sel_ld = DEASSERT_L;
605 arb_datapath_sel_ld= 1'b0; // @accept, datapath switch to that client;
606 arb_datapath_sel_in= NULL; // ok for pipeline since meta will not accept
607 // if diff client; same client loaded in data sel
608 read_tag = DEASSERT_L;
609// fsm_start_datapath_fsm = DEASSERT_L;
610 next_arb_control_state = CACS0;
611 case (current_arb_control_state_ff) /* synopsys parallel_case full_case */
612 CACS0: begin
613 if (arb0_fifo_not_empty) begin
614 if (tdmc_arb0_req_cond == TRUE_H) begin // TDMC Request
615 arb_control_sel_in = TDMC; // Select TDMC module
616 next_arb_control_state = CACS4; // next state
617 end
618 else if (rdc_arb0_req_cond == TRUE_H) begin // RDC Request
619 arb_control_sel_in = RDC; // Select RDC module
620 next_arb_control_state = CACS5; // next state
621 end
622 else if (rcr_arb0_req_cond == TRUE_H) begin // RCR Request
623 arb_control_sel_in = RCR; // Select RCR module
624 next_arb_control_state = CACS6; // next state
625 end
626 // else if (rbr_arb0_req == TRUE_H) begin // RBR Request
627 // arb_control_sel_in = RBR; // Select RBR module
628 // next_arb_control_state = CACS7; // next state
629 // end
630 else begin // No Request
631 arb_control_sel_in = NULL; // Select NULL module
632 next_arb_control_state = CACS0; // loop
633 end // else: !if(rcr_arb0_req == TRUE_H)
634 end
635 else begin // No Request
636 arb_control_sel_in = NULL; // Select NULL module
637 next_arb_control_state = CACS0; // loop
638 end
639 arb_control_sel_ld = ASSERT_H; // load register
640 end
641 CACS1: begin
642 if (arb0_fifo_not_empty) begin
643 if (rdc_arb0_req_cond == TRUE_H) begin // RDC Request
644 arb_control_sel_in = RDC; // Select RDC module
645 next_arb_control_state = CACS5; // next state
646 end
647 else if (rcr_arb0_req_cond == TRUE_H) begin // RCR Request
648 arb_control_sel_in = RCR; // Select RCR module
649 next_arb_control_state = CACS6; // next state
650 end
651 // else if (rbr_arb0_req == TRUE_H) begin // RBR Request
652 // arb_control_sel_in = RBR; // Select RBR module
653 // next_arb_control_state = CACS7; // next state
654 // end
655 else if (tdmc_arb0_req_cond == TRUE_H) begin // TDMC Request
656 arb_control_sel_in = TDMC; // Select TDMC module
657 next_arb_control_state = CACS4; // next state
658 end
659 else begin // No Request
660 arb_control_sel_in = NULL; // Select NULL module
661 next_arb_control_state = CACS1; // loop
662 end
663 end
664 else begin // No Request
665 arb_control_sel_in = NULL; // Select NULL module
666 next_arb_control_state = CACS1; // loop
667 end
668 arb_control_sel_ld = ASSERT_H; // load register
669 end
670 CACS2: begin
671 if (arb0_fifo_not_empty) begin
672 if (rcr_arb0_req_cond == TRUE_H) begin // RCR Request
673 arb_control_sel_in = RCR; // Select RCR module
674 next_arb_control_state = CACS6; // next state
675 end
676 // else if (rbr_arb0_req == TRUE_H) begin // RBR Request
677 // arb_control_sel_in = RBR; // Select RBR module
678 // next_arb_control_state = CACS7; // next state
679 // end
680 else if (tdmc_arb0_req_cond == TRUE_H) begin // TDMC Request
681 arb_control_sel_in = TDMC; // Select TDMC module
682 next_arb_control_state = CACS4; // next state
683 end
684 else if (rdc_arb0_req_cond == TRUE_H) begin // RDC Request
685 arb_control_sel_in = RDC; // Select RDC module
686 next_arb_control_state = CACS5; // next state
687 end
688 else begin // No Request
689 arb_control_sel_in = NULL; // Select NULL module
690 next_arb_control_state = CACS2; // loop
691 end // else: !if(rdc_arb0_req == TRUE_H)
692 end // if (arb0_fifo_not_empty)
693 else begin // No Request
694 arb_control_sel_in = NULL; // Select NULL module
695 next_arb_control_state = CACS2; // loop
696 end
697 arb_control_sel_ld = ASSERT_H; // load register
698 end
699 CACS3: begin
700 if (arb0_fifo_not_empty) begin
701 // if (rbr_arb0_req == TRUE_H) begin // RBR Request
702 // arb_control_sel_in = RBR; // Select RBR module
703 // next_arb_control_state = CACS7; // next state
704 // end
705 // else if (tdmc_arb0_req == TRUE_H) begin // TDMC Request
706 if (tdmc_arb0_req_cond == TRUE_H) begin // TDMC Request
707 arb_control_sel_in = TDMC; // Select TDMC module
708 next_arb_control_state = CACS4; // next state
709 end
710 else if (rdc_arb0_req_cond == TRUE_H) begin // RDC Request
711 arb_control_sel_in = RDC; // Select RDC module
712 next_arb_control_state = CACS5; // next state
713 end
714 else if (rcr_arb0_req_cond == TRUE_H) begin // RCR Request
715 arb_control_sel_in = RCR; // Select RCR module
716 next_arb_control_state = CACS6; // next state
717 end
718 else begin // No Request
719 arb_control_sel_in = NULL; // Select NULL module
720 next_arb_control_state = CACS3; // loop
721 end // else: !if(rcr_arb0_req == TRUE_H)
722 end
723 else begin // No Request
724 arb_control_sel_in = NULL; // Select NULL module
725 next_arb_control_state = CACS3; // loop
726 end
727 arb_control_sel_ld = ASSERT_H; // load register
728 end
729 CACS4: begin
730 if (meta_dmc0_req_accept == TRUE_H) begin // Control Complete
731 read_tag = ASSERT_H; // Select a new TransID
732// fsm_start_datapath_fsm = ASSERT_H; // Start Datapath FSM
733 next_arb_control_state = CACS1; // next state
734 arb_datapath_sel_ld= 1'b1;
735 arb_datapath_sel_in= arb_control_sel_ff;
736 end
737 else begin
738 next_arb_control_state = CACS4; // loop
739 end
740 end
741 CACS5: begin
742 if (meta_dmc0_req_accept == TRUE_H) begin // Control Complete
743 read_tag = ASSERT_H; // Select a new TransID
744// fsm_start_datapath_fsm = ASSERT_H; // Start Datapath FSM
745 next_arb_control_state = CACS2; // next state
746 arb_datapath_sel_ld= 1'b1;
747 arb_datapath_sel_in= arb_control_sel_ff;
748 end
749 else begin
750 next_arb_control_state = CACS5; // loop
751 end
752 end
753 CACS6: begin
754 if (meta_dmc0_req_accept == TRUE_H) begin // Control Complete
755 read_tag = ASSERT_H; // Select a new TransID
756// fsm_start_datapath_fsm = ASSERT_H; // Start Datapath FSM
757 next_arb_control_state = CACS3; // next state
758 arb_datapath_sel_ld= 1'b1;
759 arb_datapath_sel_in= arb_control_sel_ff;
760 end
761 else begin
762 next_arb_control_state = CACS6; // loop
763 end
764 end
765 CACS7: begin
766 if (meta_dmc0_req_accept == TRUE_H) begin // Control Complete
767 read_tag = ASSERT_H; // Select a new TransID
768// fsm_start_datapath_fsm = ASSERT_H; // Start Datapath FSM
769 next_arb_control_state = CACS0; // next state
770 arb_datapath_sel_ld= 1'b1;
771 arb_datapath_sel_in= arb_control_sel_ff;
772 end
773 else begin
774 next_arb_control_state = CACS7; // loop
775 end
776 end
777 default: begin
778 next_arb_control_state = CACS0; // next state
779 end
780 endcase
781 end
782
783
784/*-----------------------------------------------------------------------------
785-- Arbitration DATAPATH
786-----------------------------------------------------------------------------*/
787/*--------------------------------------
788-- Concurrent combinatorial logic: Arbitration DATAPATH MUX
789--------------------------------------*/
790
791 always @ (tdmc_arb0_transfer_complete or tdmc_arb0_data or
792 tdmc_arb0_req_byteenable or tdmc_arb0_status or
793 tdmc_arb0_data_valid or
794
795 rdc_arb0_transfer_complete or rdc_arb0_data or
796 rdc_arb0_req_byteenable or rdc_arb0_status or
797 rdc_arb0_data_valid or
798
799 rcr_arb0_transfer_complete or rcr_arb0_data or
800 rcr_arb0_req_byteenable or rcr_arb0_status or
801 rcr_arb0_data_valid or
802
803// rbr_arb0_transfer_complete or rbr_arb0_data or
804// rbr_arb0_req_byteenable or rbr_arb0_status or
805// rbr_arb0_data_valid or
806
807 meta_dmc0_data_req or meta_dmc0_req_errors or
808
809 arb_datapath_sel_ff)
810
811 begin: arbitration_datapath_mux
812 mux_dmc_meta0_transfer_complete = ZERO_1;
813
814 mux_dmc_meta0_data = ZEROES_128;
815 mux_dmc_meta0_req_byteenable = ZEROES_16;
816 mux_dmc_meta0_status = ZEROES_4;
817 mux_dmc_meta0_data_valid = ZERO_1;
818
819 demux_arb0_tdmc_data_req = ZERO_1;
820 demux_arb0_tdmc_req_errors = ZERO_1;
821
822 demux_arb0_rdc_data_req = ZERO_1;
823 demux_arb0_rdc_req_errors = ZERO_1;
824
825 demux_arb0_rcr_data_req = ZERO_1;
826 demux_arb0_rcr_req_errors = ZERO_1;
827
828// demux_arb0_rbr_data_req = ZERO_1;
829// demux_arb0_rbr_req_errors = ZERO_1;
830
831 case (arb_datapath_sel_ff) /* synopsys parallel_case full_case */
832 NULL: begin
833 mux_dmc_meta0_transfer_complete = ZERO_1;
834
835 mux_dmc_meta0_data = ZEROES_128;
836 mux_dmc_meta0_req_byteenable = ZEROES_16;
837 mux_dmc_meta0_status = ZEROES_4;
838 mux_dmc_meta0_data_valid = ZERO_1;
839
840 demux_arb0_tdmc_data_req = ZERO_1;
841 demux_arb0_tdmc_req_errors = ZERO_1;
842
843 demux_arb0_rdc_data_req = ZERO_1;
844 demux_arb0_rdc_req_errors = ZERO_1;
845
846 demux_arb0_rcr_data_req = ZERO_1;
847 demux_arb0_rcr_req_errors = ZERO_1;
848
849// demux_arb0_rbr_data_req = ZERO_1;
850// demux_arb0_rbr_req_errors = ZERO_1;
851 end
852 TDMC: begin
853 mux_dmc_meta0_transfer_complete = tdmc_arb0_transfer_complete;
854
855 mux_dmc_meta0_data = tdmc_arb0_data;
856 mux_dmc_meta0_req_byteenable = tdmc_arb0_req_byteenable;
857 mux_dmc_meta0_status = tdmc_arb0_status;
858 mux_dmc_meta0_data_valid = tdmc_arb0_data_valid;
859
860 demux_arb0_tdmc_data_req = meta_dmc0_data_req;
861 demux_arb0_tdmc_req_errors = meta_dmc0_req_errors;
862 end
863 RDC: begin
864 mux_dmc_meta0_transfer_complete = rdc_arb0_transfer_complete;
865
866 mux_dmc_meta0_data = rdc_arb0_data;
867 mux_dmc_meta0_req_byteenable = rdc_arb0_req_byteenable;
868 mux_dmc_meta0_status = rdc_arb0_status;
869 mux_dmc_meta0_data_valid = rdc_arb0_data_valid;
870
871 demux_arb0_rdc_data_req = meta_dmc0_data_req;
872 demux_arb0_rdc_req_errors = meta_dmc0_req_errors;
873 end
874 RCR: begin
875 mux_dmc_meta0_transfer_complete = rcr_arb0_transfer_complete;
876
877 mux_dmc_meta0_data = rcr_arb0_data;
878 mux_dmc_meta0_req_byteenable = rcr_arb0_req_byteenable;
879 mux_dmc_meta0_status = rcr_arb0_status;
880 mux_dmc_meta0_data_valid = rcr_arb0_data_valid;
881
882 demux_arb0_rcr_data_req = meta_dmc0_data_req;
883 demux_arb0_rcr_req_errors = meta_dmc0_req_errors;
884 end
885// RBR: begin
886// mux_dmc_meta0_transfer_complete = rbr_arb0_transfer_complete;
887
888// mux_dmc_meta0_data = rbr_arb0_data;
889// mux_dmc_meta0_req_byteenable = rbr_arb0_req_byteenable;
890// mux_dmc_meta0_status = rbr_arb0_status;
891// mux_dmc_meta0_data_valid = rbr_arb0_data_valid;
892
893// demux_arb0_rbr_data_req = meta_dmc0_data_req;
894// demux_arb0_rbr_req_errors = meta_dmc0_req_errors;
895// end
896 default: begin
897 mux_dmc_meta0_transfer_complete = ZERO_1;
898
899 mux_dmc_meta0_data = ZEROES_128;
900 mux_dmc_meta0_req_byteenable = ZEROES_16;
901 mux_dmc_meta0_status = ZEROES_4;
902 mux_dmc_meta0_data_valid = ZERO_1;
903
904 demux_arb0_tdmc_data_req = ZERO_1;
905 demux_arb0_tdmc_req_errors = ZERO_1;
906
907 demux_arb0_rdc_data_req = ZERO_1;
908 demux_arb0_rdc_req_errors = ZERO_1;
909
910 demux_arb0_rcr_data_req = ZERO_1;
911 demux_arb0_rcr_req_errors = ZERO_1;
912
913// demux_arb0_rbr_data_req = ZERO_1;
914// demux_arb0_rbr_req_errors = ZERO_1;
915 end
916 endcase
917 end
918
919/*--------------------------------------
920-- Concurrent combinatorial logic: Arbitration DATAPATH State Machine
921--------------------------------------*/
922`ifdef old_code_not_use
923 always @ (/*AUTOSENSE*/arb_control_sel_ff
924 or current_arb_datapath_state_ff
925 or rcr_arb0_transfer_complete
926 or rdc_arb0_transfer_complete or start_data_phase
927 or tdmc_arb0_transfer_complete)
928 begin: arbitration_datapath_fsm
929 arb_datapath_sel_in = NULL;
930 arb_datapath_sel_ld = DEASSERT_L;
931 next_arb_datapath_state = CADS0;
932 data_phase_started = DEASSERT_L;
933 case (current_arb_datapath_state_ff) /* synopsys parallel_case full_case */
934 CADS0: begin
935 if (start_data_phase == TRUE_H) begin
936 data_phase_started = ASSERT_H;
937 arb_datapath_sel_in = arb_control_sel_ff;
938 arb_datapath_sel_ld = ASSERT_H;
939 case (arb_control_sel_ff) /* synopsys parallel_case full_case */
940 NULL: begin
941 next_arb_datapath_state = CADS0; // next state
942 end
943 TDMC: begin
944 next_arb_datapath_state = CADS1; // next state
945 end
946 RDC: begin
947 next_arb_datapath_state = CADS2; // next state
948 end
949 RCR: begin
950 next_arb_datapath_state = CADS3; // next state
951 end
952 RBR: begin
953 next_arb_datapath_state = CADS4; // next state
954 end
955 default: begin
956 next_arb_datapath_state = CADS0; // next state
957 end
958 endcase
959 end
960 else begin
961 next_arb_datapath_state = CADS0; // next state
962 end
963 end
964 CADS1: begin
965 if (tdmc_arb0_transfer_complete == TRUE_H) begin // Data Complete
966 arb_datapath_sel_ld = ASSERT_H; // null datapath sel
967 next_arb_datapath_state = CADS0; // next state
968 end
969 else begin
970 next_arb_datapath_state = CADS1; // loop
971 end
972 end
973 CADS2: begin
974 if (rdc_arb0_transfer_complete == TRUE_H) begin // Data Complete
975 arb_datapath_sel_ld = ASSERT_H; // null datapath sel
976 next_arb_datapath_state = CADS0; // next state
977 end
978 else begin
979 next_arb_datapath_state = CADS2; // loop
980 end
981 end
982 CADS3: begin
983 if (rcr_arb0_transfer_complete == TRUE_H) begin // Data Complete
984 arb_datapath_sel_ld = ASSERT_H; // null datapath sel
985 next_arb_datapath_state = CADS0; // next state
986 end
987 else begin
988 next_arb_datapath_state = CADS3; // loop
989 end
990 end
991// CADS4: begin
992 // if (rbr_arb0_transfer_complete == TRUE_H) begin // Data Complete
993 // arb_datapath_sel_ld = ASSERT_H; // null datapath sel
994 // next_arb_datapath_state = CADS0; // next state
995 // end
996 // else begin
997 // next_arb_datapath_state = CADS4; // loop
998 // end
999// end
1000 default: begin
1001 arb_datapath_sel_ld = ASSERT_H; // null datapath sel
1002 next_arb_datapath_state = CADS0; // next state
1003 end
1004 endcase
1005 end
1006`endif
1007
1008/*-----------------------------------------------------------------------------
1009-- TransID Write Tag Management s/m
1010-----------------------------------------------------------------------------*/
1011
1012
1013assign posted_req_accepted = dmc_meta0_req_cmd[5] && meta_dmc0_req_accept;
1014assign posted_req = dmc_meta0_req_cmd[5];
1015
1016 always @ (/*AUTOSENSE*/dirty_tag or dmc_meta0_req_transIDR
1017 or meta_dmc_ack_transIDR or return_dirty_tag
1018 or sel_posted_tag) begin
1019 if (sel_posted_tag)
1020 returned_tag = dmc_meta0_req_transIDR;
1021 else if (return_dirty_tag)
1022 returned_tag = dirty_tag;
1023 else
1024 returned_tag = meta_dmc_ack_transIDR;
1025 end
1026
1027
1028 always @ (/*AUTOSENSE*/meta_dmc_ack_transfer_cmpl_ORdR
1029 or pio_arb_dirtid_enable or posted_req_acceptedR or stateR
1030 or transaction_timeout)
1031
1032 begin
1033 // set all default values here
1034 write_tag = 1'b0;
1035 write_dirty_tag = 1'b0;
1036 sel_posted_tag = 1'b0;
1037 state = stateR;
1038 case(stateR)
1039 IDLE:
1040 begin
1041 if (posted_req_acceptedR & meta_dmc_ack_transfer_cmpl_ORdR) begin
1042 write_tag = 1'b1;
1043 sel_posted_tag = 1'b1;
1044 state = TAG1;
1045 end
1046 else if (posted_req_acceptedR) begin
1047 write_tag = 1'b1;
1048 sel_posted_tag = 1'b1;
1049 state = IDLE;
1050 end // if (posted_req_accepted)
1051 else if (meta_dmc_ack_transfer_cmpl_ORdR & ( pio_arb_dirtid_enable ? !transaction_timeout : 1'b1 )) begin
1052 write_tag = 1'b1;
1053 sel_posted_tag = 1'b0;
1054 end
1055 else if (meta_dmc_ack_transfer_cmpl_ORdR & transaction_timeout & pio_arb_dirtid_enable) begin
1056 write_dirty_tag = 1'b1;
1057 sel_posted_tag = 1'b0;
1058 end
1059 else
1060 state = IDLE;
1061 end // case: IDLE
1062 TAG1:
1063 begin
1064 write_tag = 1'b1;
1065 sel_posted_tag = 1'b0;
1066 state = IDLE;
1067 end // case: TAG1
1068 endcase // case(stateR)
1069 end // always @ (...
1070
1071/*---------------------------------------------------------------------------
1072----Dirty TID handing state machine
1073 ---------------------------------------------------------------------------*/
1074
1075
1076 // synopsys translate_off
1077
1078 reg [55:0] DIR_BIN_STATE;
1079 always @(dirbin_stateR)
1080 begin
1081 case(dirbin_stateR)
1082 IDLEBIN : DIR_BIN_STATE = "IDLEBIN";
1083 CLRBIN : DIR_BIN_STATE = "CLRBIN";
1084 RDBIN : DIR_BIN_STATE = "RDBIN";
1085 default : DIR_BIN_STATE = "UNKNOWN";
1086 endcase
1087 end
1088
1089 // synopsys translate_on
1090
1091 always @ (/*AUTOSENSE*/dirbin_stateR or dirtybinfifo_not_empty
1092 or pio_arb_dirtid_clr or posted_req
1093 or transfer_cmpl_pending)
1094 begin
1095 // set all default values here
1096 return_dirty_tag = 1'b0;
1097 inc_dirtybinfifo_rp = 1'b0;
1098 dirbin_state = dirbin_stateR;
1099 case(dirbin_stateR)
1100 IDLEBIN:
1101 begin
1102 if (pio_arb_dirtid_clr ) begin
1103 dirbin_state = CLRBIN;
1104 end
1105 else
1106 dirbin_state = IDLEBIN;
1107 end // case: IDLEBIN
1108 CLRBIN:
1109 begin
1110 if (dirtybinfifo_not_empty) begin
1111 if (transfer_cmpl_pending || posted_req)
1112 dirbin_state = CLRBIN;
1113 else begin
1114 inc_dirtybinfifo_rp = 1'b1;
1115 return_dirty_tag = 1'b1;
1116 end
1117 end // if (dirtybinfifo_not_empty)
1118 else
1119 dirbin_state = IDLEBIN;
1120 end // case: CLRBIN
1121 RDBIN:
1122 begin
1123 inc_dirtybinfifo_rp = 1'b1;
1124 dirbin_state = CLRBIN;
1125 end
1126 default: dirbin_state = IDLEBIN;
1127 endcase
1128 end
1129
1130
1131// add stage to fix timing
1132reg write_tag_r;
1133reg return_dirty_tag_r;
1134reg [4:0] returned_tag_r;
1135
1136always @(posedge clk) begin
1137 if(reset) begin
1138 write_tag_r<= 1'b0;
1139 return_dirty_tag_r<= 1'b0;
1140 end
1141 else begin
1142 write_tag_r<= write_tag;
1143 return_dirty_tag_r<= return_dirty_tag;
1144 end
1145end
1146
1147always @(posedge clk) begin
1148 returned_tag_r<= returned_tag;
1149end
1150
1151
1152/*-----------------------------------------------------------------------------
1153-- TransID Management
1154-----------------------------------------------------------------------------*/
1155 niu_meta_wr_tagfifo niu_meta_wr_tagfifo (
1156 // Outputs
1157 .fifo_not_empty(arb0_fifo_not_empty),
1158 .fifo_full (),
1159 .rdout (rdtagoutR),
1160 .dout (),
1161 .count (),
1162 // Inputs
1163 .core_clk (clk),
1164 .reset (reset),
1165 .inc_rp (read_tag),
1166 .inc_wp (write_tag_r | return_dirty_tag_r),
1167 .din (returned_tag_r));
1168
1169
1170 /*------------------------------------------------------------------------
1171 ---Dirty Bin Fifo -----------------------------
1172 -------------------------------------------------------------------------*/
1173 niu_meta_arb_syncfifo #(5,32,5) wrdirtybinfifo (
1174 .core_clk (clk),
1175 .reset (reset),
1176 .inc_rp (inc_dirtybinfifo_rp),
1177 .inc_wp (write_dirty_tag),
1178 .fifo_not_empty (dirtybinfifo_not_empty),
1179 .fifo_full (dirtybinfifo_full),
1180 .count (dirty_tag_count),
1181 .din (meta_dmc_ack_transIDR),
1182 .rdout (),
1183 .dout (dirty_tag));
1184
1185
1186
1187
1188 //------------------------------------------------------------------
1189
1190 assign dmc_meta_ack_accept_ORd = dmc_meta_ack_accept[7] |
1191 dmc_meta_ack_accept[6] |
1192 dmc_meta_ack_accept[5] |
1193 dmc_meta_ack_accept[4] |
1194 dmc_meta_ack_accept[3] |
1195 dmc_meta_ack_accept[2] |
1196 dmc_meta_ack_accept[1] |
1197 dmc_meta_ack_accept[0];
1198
1199 assign meta_dmc_ack_transfer_cmpl_ORd = meta_dmc_ack_transfer_cmpl[7] |
1200 meta_dmc_ack_transfer_cmpl[6] |
1201 meta_dmc_ack_transfer_cmpl[5] |
1202 meta_dmc_ack_transfer_cmpl[4] |
1203 meta_dmc_ack_transfer_cmpl[3] |
1204 meta_dmc_ack_transfer_cmpl[2] |
1205 meta_dmc_ack_transfer_cmpl[1] |
1206 meta_dmc_ack_transfer_cmpl[0];
1207
1208 assign transaction_timeout = (meta_dmc_ack_cmd_statusR == 4'b1111);
1209
1210
1211always @ (/*AUTOSENSE*/meta_dmc_ack_transID0R
1212 or meta_dmc_ack_transID1R or meta_dmc_ack_transID2R
1213 or meta_dmc_ack_transID3R or meta_dmc_ack_transID4R
1214 or meta_dmc_ack_transID5R or meta_dmc_ack_transID6R
1215 or meta_dmc_ack_transID7R or meta_dmc_ack_transfer_cmpl) begin
1216 if ( meta_dmc_ack_transfer_cmpl[0])
1217 meta_dmc_ack_transID_cmpl = meta_dmc_ack_transID0R;
1218 else if (meta_dmc_ack_transfer_cmpl[1])
1219 meta_dmc_ack_transID_cmpl = meta_dmc_ack_transID1R;
1220 else if (meta_dmc_ack_transfer_cmpl[2])
1221 meta_dmc_ack_transID_cmpl = meta_dmc_ack_transID2R;
1222 else if (meta_dmc_ack_transfer_cmpl[3])
1223 meta_dmc_ack_transID_cmpl = meta_dmc_ack_transID3R;
1224 else if (meta_dmc_ack_transfer_cmpl[4])
1225 meta_dmc_ack_transID_cmpl = meta_dmc_ack_transID4R;
1226 else if (meta_dmc_ack_transfer_cmpl[5])
1227 meta_dmc_ack_transID_cmpl = meta_dmc_ack_transID5R;
1228 else if (meta_dmc_ack_transfer_cmpl[6])
1229 meta_dmc_ack_transID_cmpl = meta_dmc_ack_transID6R;
1230 else if (meta_dmc_ack_transfer_cmpl[7])
1231 meta_dmc_ack_transID_cmpl = meta_dmc_ack_transID7R;
1232 else
1233 meta_dmc_ack_transID_cmpl = 5'b00000;
1234 end
1235
1236
1237
1238/*-----------------------------------------------------------------------------
1239-- Implicit Registers
1240-----------------------------------------------------------------------------*/
1241/*--------------------------------------
1242-- Concurrent processes: State Machine Registers
1243--------------------------------------*/
1244
1245 always @ (posedge clk) begin: current_arb_control_state_reg
1246 if (reset == 1'b1)
1247 current_arb_control_state_ff <= 3'b000; // synchronous reset
1248 else
1249 current_arb_control_state_ff <= next_arb_control_state;
1250 end
1251
1252`ifdef old_code_not_use
1253 always @ (posedge clk) begin: current_arb_datapath_state_reg
1254 if (reset == 1'b1)
1255 current_arb_datapath_state_ff <= 3'b000; // synchronous reset
1256 else
1257 current_arb_datapath_state_ff <= next_arb_datapath_state;
1258 end
1259`endif
1260
1261
1262
1263
1264/*--------------------------------------
1265-- Concurrent processes: Registers
1266--------------------------------------*/
1267
1268 always @ (posedge clk) begin: arb_control_sel_reg
1269 if (reset == 1'b1)
1270 arb_control_sel_ff <= 3'b000; // synchronous reset
1271 else if (arb_control_sel_ld == TRUE_H)
1272 arb_control_sel_ff <= arb_control_sel_in;
1273 end
1274
1275 always @ (posedge clk) begin: arb_datapath_sel_reg
1276 if (reset == 1'b1)
1277 arb_datapath_sel_ff <= 3'b000; // synchronous reset
1278 else if (arb_datapath_sel_ld == TRUE_H)
1279 arb_datapath_sel_ff <= arb_datapath_sel_in;
1280 end // block: arb_datapath_sel_reg
1281
1282
1283 // Register the arb_control_sel_ff and fsm_start_datapath_fsm
1284 // after the accept of the request as the previous data can complete some
1285 // cycles after the accept has happened
1286`ifdef old_code_not_use
1287 always @(posedge clk) begin
1288 if (reset == 1'b1) begin
1289 arb_control_sel_ffR <= 0;
1290 start_data_phase <= 1'b0;
1291 end
1292 else begin
1293 arb_control_sel_ffR <= fsm_start_datapath_fsm ? arb_control_sel_ff : arb_control_sel_ffR;
1294 start_data_phase <= fsm_start_datapath_fsm ? 1'b1 : data_phase_started ? 1'b0 : start_data_phase;
1295 end
1296
1297 end // always @ (posedge clk)
1298`endif
1299
1300
1301
1302 always @ (posedge clk) begin
1303 if (reset == 1'b1) begin
1304 stateR <= IDLE;
1305 posted_req_acceptedR <= 1'b0;
1306 meta_dmc_ack_transfer_cmpl_ORdR <= 1'b0;
1307 meta_dmc_ack_transIDR <= 5'h0;
1308 dmc_meta0_req_transIDR <= 5'h0;
1309 meta_dmc_ack_transID0R <= 5'h0;
1310 meta_dmc_ack_transID1R <= 5'h0;
1311 meta_dmc_ack_transID2R <= 5'h0;
1312 meta_dmc_ack_transID3R <= 5'h0;
1313 meta_dmc_ack_transID4R <= 5'h0;
1314 meta_dmc_ack_transID5R <= 5'h0;
1315 meta_dmc_ack_transID6R <= 5'h0;
1316 meta_dmc_ack_transID7R <= 5'h0;
1317 meta_dmc_ack_cmd_statusR <= 4'h0;
1318 transfer_cmpl_pending <= 1'b0;
1319 dirbin_stateR <= 2'b00;
1320 arb_pio_dirtid_npwstatus <= 0;
1321 outstanding_tid_cnt <= 6'h0;
1322 end
1323 else begin
1324 stateR <= state;
1325 posted_req_acceptedR <= posted_req_accepted;
1326 meta_dmc_ack_transfer_cmpl_ORdR <= meta_dmc_ack_transfer_cmpl_ORd;
1327 if(meta_dmc_ack_transfer_cmpl_ORd) meta_dmc_ack_transIDR <= meta_dmc_ack_transID_cmpl;
1328 // this the selected xID to stay until next new ID
1329 dmc_meta0_req_transIDR <= posted_req_accepted ? dmc_meta0_req_transID[4:0]: dmc_meta0_req_transIDR;
1330 meta_dmc_ack_transID0R <= dmc_meta_ack_accept[0] ? meta_dmc_ack_transID[4:0] : meta_dmc_ack_transID0R;
1331 meta_dmc_ack_transID1R <= dmc_meta_ack_accept[1] ? meta_dmc_ack_transID[4:0] : meta_dmc_ack_transID1R;
1332 meta_dmc_ack_transID2R <= dmc_meta_ack_accept[2] ? meta_dmc_ack_transID[4:0] : meta_dmc_ack_transID2R;
1333 meta_dmc_ack_transID3R <= dmc_meta_ack_accept[3] ? meta_dmc_ack_transID[4:0] : meta_dmc_ack_transID3R;
1334 meta_dmc_ack_transID4R <= dmc_meta_ack_accept[4] ? meta_dmc_ack_transID[4:0] : meta_dmc_ack_transID4R;
1335 meta_dmc_ack_transID5R <= dmc_meta_ack_accept[5] ? meta_dmc_ack_transID[4:0] : meta_dmc_ack_transID5R;
1336 meta_dmc_ack_transID6R <= dmc_meta_ack_accept[6] ? meta_dmc_ack_transID[4:0] : meta_dmc_ack_transID6R;
1337 meta_dmc_ack_transID7R <= dmc_meta_ack_accept[7] ? meta_dmc_ack_transID[4:0] : meta_dmc_ack_transID7R;
1338 meta_dmc_ack_cmd_statusR <= dmc_meta_ack_accept_ORd ? meta_dmc_ack_cmd_status : meta_dmc_ack_cmd_statusR ;
1339 transfer_cmpl_pending <= dmc_meta_ack_accept_ORd ? 1'b1 : meta_dmc_ack_transfer_cmpl_ORd ? 1'b0 : transfer_cmpl_pending;
1340 dirbin_stateR <= dirbin_state;
1341 arb_pio_dirtid_npwstatus <= dirty_tag_count;
1342 if(inc_outstanding_tid_cnt) outstanding_tid_cnt<= outstanding_tid_cnt_add_n;
1343 else if(dec_outstanding_tid_cnt) outstanding_tid_cnt<= outstanding_tid_cnt_sub_n;
1344 end // else: !if(reset == 1'b1)
1345 end
1346
1347
1348 // assign threshold reached
1349
1350 assign npw_threshold_reached = !(pio_arb_np_threshold==6'd32) && (outstanding_tid_cnt >= pio_arb_np_threshold);
1351 // disable threshold when set to 32
1352// assign outputs
1353
1354assign arb_pio_all_npwdirty = dirtybinfifo_full;
1355
1356
1357endmodule
1358
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