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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / design / sys / iop / niu / rtl / niu_zcp.v
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AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: niu_zcp.v
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
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16// GNU General Public License for more details.
17//
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21//
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34// ========== Copyright Header End ============================================
35/*%W% %G%*/
36
37/*************************************************************************
38 *
39 * File Name : niu_zcp.v
40 * Author Name : John Lo
41 * Description : Zero Copy Processor
42 * Parent Module:
43 * Child Module:
44 * Interface Mod:
45 * Date Created : 3/25/2004
46 *
47 * Copyright (c) 2020, Sun Microsystems, Inc.
48 * Sun Proprietary and Confidential
49 *
50 * Modification :
51 *
52 * Synthesis Notes:
53 *
54 *************************************************************************/
55
56`include "niu_zcp.h"
57
58module niu_zcp (
59// pio broadcast signals
60 pio_clients_addr,
61 pio_clients_rd,
62 pio_clients_wdata,
63 pio_zcp_sel,
64 zcp_pio_ack,
65 zcp_pio_rdata,
66 zcp_pio_err,
67 zcp_pio_intr,
68// fflp intf
69 fflp_zcp_wr,
70 fflp_zcp_data,// 27 bytes = 216 bits
71// port0
72 dmc_zcp_req0,
73 zcp_dmc_ack0,
74 zcp_dmc_dat0,
75 zcp_dmc_dat_err0,
76 zcp_dmc_ful_pkt0,
77// port1
78 dmc_zcp_req1,
79 zcp_dmc_ack1,
80 zcp_dmc_dat1,
81 zcp_dmc_dat_err1,
82 zcp_dmc_ful_pkt1,
83`ifdef NEPTUNE
84// rdmc stuff
85 rdmc_zcp_func_num,
86 page_handle, // 20 bit per handle
87// port2
88 dmc_zcp_req2,
89 zcp_dmc_ack2,
90 zcp_dmc_dat2,
91 zcp_dmc_dat_err2,
92 zcp_dmc_ful_pkt2,
93// port3
94 dmc_zcp_req3,
95 zcp_dmc_ack3,
96 zcp_dmc_dat3,
97 zcp_dmc_dat_err3,
98 zcp_dmc_ful_pkt3,
99// ZCP arb1 req intf
100 zcp_arb1_req,
101 zcp_arb1_req_cmd,
102 zcp_arb1_req_address,
103 zcp_arb1_req_length,
104 zcp_arb1_req_port_num,
105 zcp_arb1_req_dma_num,
106 zcp_arb1_req_func_num,
107 arb1_zcp_req_accept,
108// META RESPONSE control info
109 meta_zcp_resp_ready, // Resp Command Request
110 meta_zcp_resp_cmd,
111 meta_zcp_resp_cmd_status, // Command Status
112 meta_zcp_resp_length, // Packet Length
113 meta_zcp_resp_client, // bit 0
114 meta_zcp_resp_dma_num, // Channel Number
115 meta_zcp_resp_complete, // bitwise ZCP_CLIENT[0]
116 meta_zcp_resp_transfer_cmpl,// bitwise ZCP_CLIENT[0]
117 zcp_meta_resp_accept, // bitwise client accept
118// META RESPONSE data
119 meta_zcp_data_valid, // Transfer Data Ack
120 meta_zcp_data, // Transfer Data
121 meta_zcp_resp_byteenable, // First/Last BE
122 meta_zcp_data_status, // Transfer Data Status
123//
124`else // N2
125 iol2clk,
126 tcu_mbist_user_mode,
127 tcu_aclk,
128 tcu_bclk,
129 tcu_se_scancollar_in,
130 tcu_se_scancollar_out,
131 tcu_array_wr_inhibit,
132 niu_mb7_cntrl_fifo_zcp_scan_in,
133 niu_mb7_cntrl_fifo_zcp_scan_out,
134 l2clk_2x,
135 hdr_sram_rvalue_zcp0,
136 hdr_sram_rid_zcp0,
137 hdr_sram_wr_en_zcp0,
138 hdr_sram_red_clr_zcp0,
139 sram_hdr_read_data_zcp0,
140 rtx_rxc_zcp0_mb7_dmo_dout,
141 hdr_sram_rvalue_zcp1,
142 hdr_sram_rid_zcp1,
143 hdr_sram_wr_en_zcp1,
144 hdr_sram_red_clr_zcp1,
145 sram_hdr_read_data_zcp1,
146 rtx_rxc_zcp1_mb7_dmo_dout,
147// mbist controller related
148 niu_tcu_mbist_fail_7,
149 niu_tcu_mbist_done_7,
150 mb7_scan_in,
151 mb7_scan_out,
152 tcu_niu_mbist_start_7,
153 tcu_mbist_bisi_en,
154 tcu_scan_en,
155// specific to mb8
156 niu_mb8_cntrl_fifo_zcp_scan_in,
157 niu_mb8_cntrl_fifo_zcp_scan_out,
158 niu_tcu_mbist_fail_8,
159 niu_tcu_mbist_done_8,
160 mb8_scan_in,
161 mb8_scan_out,
162 tcu_niu_mbist_start_8,
163`endif
164 reset_l,
165 clk,
166 zcp_debug_port
167 );
168 // pio broadcast signals
169 input [19:0] pio_clients_addr;
170 input pio_clients_rd;
171 input [31:0] pio_clients_wdata;
172 input pio_zcp_sel;
173 output zcp_pio_ack;
174 output [63:0] zcp_pio_rdata;
175 output zcp_pio_err;
176 output zcp_pio_intr;
177 // fflp intf
178 input [4:0] fflp_zcp_wr;
179 input [215:0] fflp_zcp_data;// 27 bytes = 216 bits
180 // port0
181 input dmc_zcp_req0;
182 output zcp_dmc_ack0;
183 output [129:0] zcp_dmc_dat0;
184 output zcp_dmc_dat_err0;
185 output zcp_dmc_ful_pkt0;
186 // port1
187 input dmc_zcp_req1;
188 output zcp_dmc_ack1;
189 output [129:0] zcp_dmc_dat1;
190 output zcp_dmc_dat_err1;
191 output zcp_dmc_ful_pkt1;
192`ifdef NEPTUNE
193 // rdmc stuff
194 input [31:0] rdmc_zcp_func_num;
195 input [319:0] page_handle; // 20 bit per handle
196 // port2
197 input dmc_zcp_req2;
198 output zcp_dmc_ack2;
199 output [129:0] zcp_dmc_dat2;
200 output zcp_dmc_dat_err2;
201 output zcp_dmc_ful_pkt2;
202 // port3
203 input dmc_zcp_req3;
204 output zcp_dmc_ack3;
205 output [129:0] zcp_dmc_dat3;
206 output zcp_dmc_dat_err3;
207 output zcp_dmc_ful_pkt3;
208 // ZCP arb1 req intf
209 output zcp_arb1_req;
210 output [7:0] zcp_arb1_req_cmd;
211 output [63:0] zcp_arb1_req_address;
212 output [13:0] zcp_arb1_req_length;
213 output [1:0] zcp_arb1_req_port_num;
214 output [4:0] zcp_arb1_req_dma_num;
215 output [1:0] zcp_arb1_req_func_num;
216 input arb1_zcp_req_accept;
217 // META RESPONSE control info
218 input meta_zcp_resp_ready; // Resp Command Request
219 input [7:0] meta_zcp_resp_cmd; // cmd
220 input [3:0] meta_zcp_resp_cmd_status; // cmd status
221 input [13:0] meta_zcp_resp_length; // Packet Length
222 input [4:0] meta_zcp_resp_dma_num; // Channel Number
223 input meta_zcp_resp_client; // bit 0
224 output zcp_meta_resp_accept; // bitwise client accept
225 // META RESPONSE data
226 input [127:0] meta_zcp_data; // Transfer Data
227 input [15:0] meta_zcp_resp_byteenable; // First/Last BE
228 input [3:0] meta_zcp_data_status; // Transfer Data Status
229 input meta_zcp_data_valid; // Transfer Data Ack
230 input meta_zcp_resp_complete; // bitwise ZCP_CLIENT[0]
231 input meta_zcp_resp_transfer_cmpl;// bitwise ZCP_CLIENT[0]
232 // DFT
233`else // N2
234 // DFT signals
235 // memory related
236 input iol2clk;
237 input tcu_mbist_user_mode;
238 input tcu_aclk;
239 input tcu_bclk;
240 input tcu_se_scancollar_in;
241 input tcu_se_scancollar_out;
242 input tcu_array_wr_inhibit;
243 input niu_mb7_cntrl_fifo_zcp_scan_in;
244 output niu_mb7_cntrl_fifo_zcp_scan_out;
245 input l2clk_2x;
246 input [6:0] hdr_sram_rvalue_zcp0;
247 input [1:0] hdr_sram_rid_zcp0;
248 input hdr_sram_wr_en_zcp0;
249 input hdr_sram_red_clr_zcp0;
250 output [6:0] sram_hdr_read_data_zcp0;
251 output [39:0] rtx_rxc_zcp0_mb7_dmo_dout;
252 input [6:0] hdr_sram_rvalue_zcp1;
253 input [1:0] hdr_sram_rid_zcp1;
254 input hdr_sram_wr_en_zcp1;
255 input hdr_sram_red_clr_zcp1;
256 output [6:0] sram_hdr_read_data_zcp1;
257 output [39:0] rtx_rxc_zcp1_mb7_dmo_dout;
258 // mbist controller related
259 output niu_tcu_mbist_fail_7;
260 output niu_tcu_mbist_done_7;
261 input mb7_scan_in;
262 output mb7_scan_out;
263 input tcu_niu_mbist_start_7;
264 input tcu_mbist_bisi_en;
265 input tcu_scan_en;
266 // specific to mb8
267 input niu_mb8_cntrl_fifo_zcp_scan_in;
268 output niu_mb8_cntrl_fifo_zcp_scan_out;
269 output niu_tcu_mbist_fail_8;
270 output niu_tcu_mbist_done_8;
271 input mb8_scan_in;
272 output mb8_scan_out;
273 input tcu_niu_mbist_start_8;
274`endif
275 input reset_l;
276 input clk;
277 output [31:0] zcp_debug_port;
278
279
280
281 // vlint flag_dangling_net_within_module off
282 // vlint flag_net_has_no_load off
283 // vlint flag_net_never_driven off
284 wire tt_ok_reg7;
285 wire buf_req_ok;
286 wire decode_default_rdc;
287 wire decode_table_rdc;
288 wire decode_zc_rdc;
289 wire cfifo_ren0; // From niu_zcp_slv of niu_zcp_slv.v
290 wire cfifo_ren1; // From niu_zcp_slv of niu_zcp_slv.v
291 wire cfifo_ren2; // From niu_zcp_slv of niu_zcp_slv.v
292 wire cfifo_ren3; // From niu_zcp_slv of niu_zcp_slv.v
293 wire cfifo_wen0; // From niu_zcp_slv of niu_zcp_slv.v
294 wire cfifo_wen1; // From niu_zcp_slv of niu_zcp_slv.v
295 wire cfifo_wen2; // From niu_zcp_slv of niu_zcp_slv.v
296 wire cfifo_wen3; // From niu_zcp_slv of niu_zcp_slv.v
297 wire [16:0] chk_bit_data; // From niu_zcp_slv of niu_zcp_slv.v
298 wire [4:0] default_rdc; // From niu_zcp_slv of niu_zcp_slv.v
299 wire [10:0] dmaw_threshold; // From niu_zcp_slv of niu_zcp_slv.v
300 wire dn_ram_ren; // From niu_zcp_slv of niu_zcp_slv.v
301 wire dn_ram_wen; // From niu_zcp_slv of niu_zcp_slv.v
302 wire [`DN_R] dram_slv_rdata; // From dn_ram of niu_dn_ram.v
303 wire [9:0] ds_offset0; // From niu_zcp_slv of niu_zcp_slv.v
304 wire [9:0] ds_offset1; // From niu_zcp_slv of niu_zcp_slv.v
305 wire [9:0] ds_offset2; // From niu_zcp_slv of niu_zcp_slv.v
306 wire [9:0] ds_offset3; // From niu_zcp_slv of niu_zcp_slv.v
307 wire ecc_chk_dis; // From niu_zcp_slv of niu_zcp_slv.v
308 wire [19:0] handle; // From niu_zcp_slv of niu_zcp_slv.v
309 wire latch_rspfifo_dout; // From niu_zcp_rsp_intf of niu_zcp_rsp_intf.v
310 wire par_chk_dis; // From niu_zcp_slv of niu_zcp_slv.v
311 wire req_dis; // From niu_zcp_slv of niu_zcp_slv.v
312 wire [1:0] req_load_state; // From niu_zcp_req_intf of niu_zcp_req_intf.v
313 wire [1:0] req_unload_state; // From niu_zcp_req_intf of niu_zcp_req_intf.v
314 wire reqfifo_uncorr_err; // From niu_zcp_req_intf of niu_zcp_req_intf.v
315 wire rrfifo_overrun; // From niu_zcp_req_intf
316 wire rrfifo_underrun; // From niu_zcp_req_intfrrun;
317 wire [`VAFIFO_A_PTR] reqfifo_wp; // From niu_zcp_req_intf of niu_zcp_req_intf.v
318 wire [`RRFIFO_W_R] rrfifo_rd_data; // From niu_zcp_req_intf of niu_zcp_req_intf.v
319 wire rsp_accepted; // From niu_zcp_arb2 of niu_zcp_arb2.v
320 wire rsp_dis; // From niu_zcp_slv of niu_zcp_slv.v
321 wire [3:0] rsp_load_state; // From niu_zcp_rsp_intf of niu_zcp_rsp_intf.v
322 wire [31:0] rsp_ram_mapped_in; // From niu_zcp_rsp_intf of niu_zcp_rsp_intf.v
323 wire [`RSPFIFO_W_R] rsp_ram_wr_data; // From niu_zcp_rsp_intf of niu_zcp_rsp_intf.v
324 wire rsp_request; // From niu_zcp_rsp_intf of niu_zcp_rsp_intf.v
325 wire [11:0] rsp_tt_index;
326 wire [11:0] rsp_tt_index1;
327 wire [11:0] rsp_tt_index2;
328 wire rsp_tt_index_err; // From va_ram of niu_va_ram.v
329 wire [3:0] rsp_unload_state; // From niu_zcp_rsp_intf of niu_zcp_rsp_intf.v
330 wire rspfifo_ren; // From niu_zcp_rsp_intf of niu_zcp_rsp_intf.v
331 wire [`VAFIFO_A_PTR] rspfifo_rp; // From niu_zcp_rsp_intf of niu_zcp_rsp_intf.v
332 wire rspfifo_uncorr_err; // From niu_zcp_rsp_intf of niu_zcp_rsp_intf.v
333 wire slv_accepted; // From niu_zcp_arb2 of niu_zcp_arb2.v
334 wire [10:0] slv_ram_addr; // From niu_zcp_slv of niu_zcp_slv.v
335 wire [16:0] slv_ram_be; // From niu_zcp_slv of niu_zcp_slv.v
336 wire [`DN_R] slv_ram_wdata; // From niu_zcp_slv of niu_zcp_slv.v
337 wire slv_request; // From niu_zcp_slv of niu_zcp_slv.v
338 wire [11:0] slv_tt_index; // From niu_zcp_slv of niu_zcp_slv.v
339 wire slv_tt_index_err; // From va_ram of niu_va_ram.v
340 wire [`ST_R] sram_slv_rdata; // From st_ram of niu_st_ram.v
341 wire st_ram_ren; // From niu_zcp_slv of niu_zcp_slv.v
342 wire st_ram_wen; // From niu_zcp_slv of niu_zcp_slv.v
343 wire [4:0] table_rdc; // From niu_zcp_slv of niu_zcp_slv.v
344 wire tt_en; // From niu_zcp_slv of niu_zcp_slv.v
345 wire tt_index_chk0; // From niu_zcp_slv of niu_zcp_slv.v
346 wire tt_index_chk1; // From niu_zcp_slv of niu_zcp_slv.v
347 wire tt_index_chk2; // From niu_zcp_slv of niu_zcp_slv.v
348 wire tt_index_chk3; // From niu_zcp_slv of niu_zcp_slv.v
349 wire [9:0] tt_index_end0; // From niu_zcp_slv of niu_zcp_slv.v
350 wire [9:0] tt_index_end1; // From niu_zcp_slv of niu_zcp_slv.v
351 wire [9:0] tt_index_end2; // From niu_zcp_slv of niu_zcp_slv.v
352 wire [9:0] tt_index_end3; // From niu_zcp_slv of niu_zcp_slv.v
353 wire [9:0] tt_index_start0; // From niu_zcp_slv of niu_zcp_slv.v
354 wire [9:0] tt_index_start1; // From niu_zcp_slv of niu_zcp_slv.v
355 wire [9:0] tt_index_start2; // From niu_zcp_slv of niu_zcp_slv.v
356 wire [9:0] tt_index_start3; // From niu_zcp_slv of niu_zcp_slv.v
357 wire [7:0] tt_offset0; // From niu_zcp_slv of niu_zcp_slv.v
358 wire [7:0] tt_offset1; // From niu_zcp_slv of niu_zcp_slv.v
359 wire [7:0] tt_offset2; // From niu_zcp_slv of niu_zcp_slv.v
360 wire [7:0] tt_offset3; // From niu_zcp_slv of niu_zcp_slv.v
361 wire va_ram_ren; // From niu_zcp_slv of niu_zcp_slv.v
362 wire va_ram_rwen; // From niu_zcp_slv of niu_zcp_slv.v
363 wire va_ram_rwen0; // From niu_zcp_slv of niu_zcp_slv.v
364 wire va_ram_rwen1; // From niu_zcp_slv of niu_zcp_slv.v
365 wire va_ram_rwen2; // From niu_zcp_slv of niu_zcp_slv.v
366 wire va_ram_rwen3; // From niu_zcp_slv of niu_zcp_slv.v
367 wire va_ram_rwen4; // From niu_zcp_slv of niu_zcp_slv.v
368 wire va_ram_rwen5; // From niu_zcp_slv of niu_zcp_slv.v
369 wire va_ram_rwen6; // From niu_zcp_slv of niu_zcp_slv.v
370 wire va_ram_rwen7; // From niu_zcp_slv of niu_zcp_slv.v
371 wire va_ram_wen; // From niu_zcp_slv of niu_zcp_slv.v
372 wire va_ram_ren0; // From niu_zcp_slv of niu_zcp_slv.v
373 wire va_ram_ren1; // From niu_zcp_slv of niu_zcp_slv.v
374 wire va_ram_ren2; // From niu_zcp_slv of niu_zcp_slv.v
375 wire va_ram_ren3; // From niu_zcp_slv of niu_zcp_slv.v
376 wire va_ram_ren4; // From niu_zcp_slv of niu_zcp_slv.v
377 wire va_ram_ren5; // From niu_zcp_slv of niu_zcp_slv.v
378 wire va_ram_ren6; // From niu_zcp_slv of niu_zcp_slv.v
379 wire va_ram_ren7; // From niu_zcp_slv of niu_zcp_slv.v
380 wire va_ram_wen0; // From niu_zcp_slv of niu_zcp_slv.v
381 wire va_ram_wen1; // From niu_zcp_slv of niu_zcp_slv.v
382 wire va_ram_wen2; // From niu_zcp_slv of niu_zcp_slv.v
383 wire va_ram_wen3; // From niu_zcp_slv of niu_zcp_slv.v
384 wire va_ram_wen4; // From niu_zcp_slv of niu_zcp_slv.v
385 wire va_ram_wen5; // From niu_zcp_slv of niu_zcp_slv.v
386 wire va_ram_wen6; // From niu_zcp_slv of niu_zcp_slv.v
387 wire va_ram_wen7; // From niu_zcp_slv of niu_zcp_slv.v
388 wire [1023:0] vram_slv_rdata; // From va_ram of niu_va_ram.v
389 wire [4:0] zc_rdc; // From niu_zcp_slv of niu_zcp_slv.v
390 wire [7:0] zcp_debug_sel; // From niu_zcp_slv of niu_zcp_slv.v
391 wire zcp_tt_index_err; // From va_ram of niu_va_ram.v
392 wire [`CFIFO_W_R] zcp_dmc_dat0;
393 wire [`CFIFO_W_R] zcp_dmc_dat1;
394 wire [`CFIFO_W_R] zcp_dmc_dat2;
395 wire [`CFIFO_W_R] zcp_dmc_dat3;
396 wire zcp_dmc_dat_err0;
397 wire zcp_dmc_dat_err1;
398 wire zcp_dmc_dat_err2;
399 wire zcp_dmc_dat_err3;
400 wire wr_en0;
401 wire wr_en1;
402 wire wr_en2;
403 wire wr_en3;
404 wire [`CFIFO_W_R] wr_data; // 130 bits: [129:0]
405 wire reset;
406 wire reset_l;
407 wire [3:0] tt_state;
408 wire [7:0] tt_rdc_reg;
409 wire [7:0] fflp_rdc;
410 wire [`IFIFO_W_R] fflp_data;
411 wire va_ram_perr;
412 wire dn_ram_perr;
413 wire st_ram_perr;
414 wire [31:0] zcp_debug_port;
415 wire [2:0] ram_access_state;
416 wire reset_cfifo0;
417 wire reset_cfifo1;
418 wire reset_cfifo2;
419 wire reset_cfifo3;
420 wire clk;
421 wire kickoff_tt_reg;
422 wire set_tt_program_err ; // zcp_slv.v
423 wire ecc_chk_bypass2;
424 wire double_bit_err2;
425 wire single_bit_err2;
426 wire last_line_err2;
427 wire second_line_err2;
428 wire first_line_err2;
429 wire ecc_chk_bypass3;
430 wire double_bit_err3;
431 wire single_bit_err3;
432 wire last_line_err3;
433 wire second_line_err3;
434 wire first_line_err3;
435 wire c0_reset;
436 wire c1_reset;
437 wire c2_reset;
438 wire c3_reset;
439 wire [21:0] slv_reset;
440 wire [5:0] fflp_reset;
441 wire [11:0] req_reset;
442 wire [25:0] rsp_reset;
443 wire [10:0] tt_reset;
444 wire [36:0] va_reset;
445 wire [4:0] dn_reset;
446 wire [3:0] st_reset;
447 wire zcp_32bit_mode;
448 // vlint flag_net_never_driven on
449 // vlint flag_net_has_no_load on
450 // vlint flag_dangling_net_within_module on
451
452 wire [3:0] reset_reg_l;
453 reg [3:0] inv_reset_reg_l;
454 wire [`CFIFO_W_R] cfifo_slv_rdata0;
455 wire [`CFIFO_W_R] cfifo_slv_rdata1;
456 wire [`CFIFO_W_R] cfifo_slv_rdata2;
457 wire [`CFIFO_W_R] cfifo_slv_rdata3;
458 wire [31:0] training_vector;
459 wire [1:0] fn;
460 wire [31:0] rdmc_zcp_func_num;
461 wire [`PMS15:0] page_handle;
462 wire [`IFIFO_W_R] ififo_dout;
463 wire [2:0] ififo_state;
464 wire [2:0] ififo_ren;
465 wire ififo_overrun;
466
467 wire ecc_chk_bypass0;
468 wire first_line0;
469 wire second_line0;
470 wire last_line0;
471 wire double_bit_err0;
472 wire single_bit_err0;
473 wire last_line_err0;
474 wire second_line_err0;
475 wire first_line_err0;
476
477 wire ecc_chk_bypass1;
478 wire first_line1;
479 wire second_line1;
480 wire last_line1;
481 wire double_bit_err1;
482 wire single_bit_err1;
483 wire last_line_err1;
484 wire second_line_err1;
485 wire first_line_err1;
486
487/////////////////////////////////////////////////////////////////
488// Start ifdef else endif instantiation section
489/////////////////////////////////////////////////////////////////
490
491`ifdef NEPTUNE
492
493/*AUTOWIRE*/
494// Beginning of automatic wires (for undeclared instantiated-module outputs)
495wire [5:0] bitmap_total_num_buf_requested;// From niu_zcp_req_intf of niu_zcp_req_intf.v
496wire [1:0] bitmap_tt_index_11_10; // From niu_zcp_req_intf of niu_zcp_req_intf.v
497wire [1:0] rot_sft1_tt_index_11_10;// From niu_zcp_req_intf of niu_zcp_req_intf.v
498wire [1:0] rot_sft32_tt_index_11_10;// From niu_zcp_req_intf of niu_zcp_req_intf.v
499wire rotate; // From niu_zcp_rsp_intf of niu_zcp_rsp_intf.v
500wire rotate_done; // From niu_zcp_req_intf of niu_zcp_req_intf.v
501wire rsp_ram_wr_en0; // From niu_zcp_rsp_intf of niu_zcp_rsp_intf.v
502wire rsp_ram_wr_en1; // From niu_zcp_rsp_intf of niu_zcp_rsp_intf.v
503wire rsp_ram_wr_en2; // From niu_zcp_rsp_intf of niu_zcp_rsp_intf.v
504wire [3:0] rspfifo_ren2; // From niu_zcp_rsp_intf of niu_zcp_rsp_intf.v
505wire rspfifo_ren3; // From niu_zcp_rsp_intf of niu_zcp_rsp_intf.v
506wire rst_rotate; // From niu_zcp_req_intf of niu_zcp_req_intf.v
507wire rst_shift; // From niu_zcp_req_intf of niu_zcp_req_intf.v
508wire shift; // From niu_zcp_rsp_intf of niu_zcp_rsp_intf.v
509wire shift_done; // From niu_zcp_req_intf of niu_zcp_req_intf.v
510// End of automatics
511
512 wire wb_tt0;
513 wire wb_tt1;
514 wire tt_rd_en0;
515 wire tt_rd_en1;
516 wire tt_rd_en2;
517 wire tt_rd_en3;
518 wire tt_sm_rw;
519
520 wire first_line2;
521 wire second_line2;
522 wire last_line2;
523
524 wire first_line3;
525 wire second_line3;
526 wire last_line3;
527
528 wire tt_active;
529 wire [11:0] tt_index;
530 wire [11:0] tt_index_4va; // from tt (fflp)
531 wire [11:0] tt_index_4dn; // from tt (fflp)
532 wire [11:0] tt_index_4st; // from tt (fflp)
533
534 wire [1023:0] va_dout;
535 wire [`ST_R] st_dout;
536 wire [`DN_R] dn_dout;
537 // req ptr intf
538 wire credit_ok;
539 wire zcp_tt_index_err_lv;
540 wire buf_req ;
541 wire [15:0] wptr_HoQ_reg ;
542 wire cross_q_end_reg ;
543 wire cross_4KB_reg ;
544 wire [3:0] ring_size_reg ;
545 wire [38:0] ring_base_addr_reg ;
546 wire reach_buf_end_reg ;
547 wire [5:0] total_num_buf_requested_reg;
548 // wb
549 wire [`DN_R] wb_dn_reg;
550 // debug
551 wire [15:0] tcp_payld_len;
552 wire [9:0] l2_hdr_len;
553 wire [9:0] l3_hdr_len;
554 wire [9:0] header_len;
555 // MCP debug
556 wire [`XPAN_TCP_SEQ_SPACE]TL;
557 wire [`XPAN_TCP_SEQ_SPACE]S;
558 wire [`PKT_LEN_R] payload_len; // registered wire .
559 wire [`PKT_LEN_R] header_delta; // registered wire .
560 wire [`XPAN_TCP_SEQ_SPACE]UE;
561 wire TL_bt_UE;
562 wire TL_eq_UE;
563 wire qual_ulp_end_fail_reg;
564 wire [`TCP_SEQ_SPACE] running_anchor_seq;
565 wire [5:0] first_byte_buf;
566 wire [20:0] last_byte_buf;
567 wire [5:0] index0;
568 wire [5:0] index1;
569 wire [5:0] index2;
570 wire [5:0] index3;
571 wire win_ok;
572 wire ulp_end_fail;
573 wire mapped_in_fail;
574 wire dmaw_threshold_fail;
575 wire unmap_on_left_oc;
576
577 // vlint flag_dangling_net_within_module off
578 // vlint flag_net_has_no_load off
579 wire neptune_signature;
580 // vlint flag_dangling_net_within_module on
581 // vlint flag_net_has_no_load on
582
583 assign neptune_signature = 1;
584
585/* --------------- request interface ------------------------- */
586niu_zcp_req_intf niu_zcp_req_intf
587 (/*AUTOINST*/
588 // Outputs
589 .credit_ok (credit_ok),
590 .rot_sft32_tt_index_11_10 (rot_sft32_tt_index_11_10[1:0]),
591 .rot_sft1_tt_index_11_10 (rot_sft1_tt_index_11_10[1:0]),
592 .bitmap_total_num_buf_requested (bitmap_total_num_buf_requested[5:0]),
593 .bitmap_tt_index_11_10 (bitmap_tt_index_11_10[1:0]),
594 .rotate_done (rotate_done),
595 .shift_done (shift_done),
596 .rst_rotate (rst_rotate),
597 .rst_shift (rst_shift),
598 .reqfifo_wp (reqfifo_wp[`VAFIFO_A_PTR]),
599 .zcp_arb1_req (zcp_arb1_req),
600 .zcp_arb1_req_cmd (zcp_arb1_req_cmd[7:0]),
601 .zcp_arb1_req_address (zcp_arb1_req_address[63:0]),
602 .zcp_arb1_req_length (zcp_arb1_req_length[13:0]),
603 .zcp_arb1_req_func_num (zcp_arb1_req_func_num[1:0]),
604 .zcp_arb1_req_port_num (zcp_arb1_req_port_num[1:0]),
605 .zcp_arb1_req_dma_num (zcp_arb1_req_dma_num[4:0]),
606 .req_load_state (req_load_state[1:0]),
607 .req_unload_state (req_unload_state[1:0]),
608 .rrfifo_overrun (rrfifo_overrun),
609 .rrfifo_underrun (rrfifo_underrun),
610 .rsp_tt_index (rsp_tt_index[11:0]),
611 .rsp_tt_index1 (rsp_tt_index1[11:0]),
612 .rsp_tt_index2 (rsp_tt_index2[11:0]),
613 .rrfifo_rd_data (rrfifo_rd_data[`RRFIFO_W_R]),
614 // Inputs
615 .clk (clk),
616 .req_reset (req_reset[11:0]),
617 .tt_index (tt_index[11:0]),
618 .fn (fn[1:0]),
619 .handle (handle[19:0]),
620 .buf_req (buf_req),
621 .wptr_HoQ_reg (wptr_HoQ_reg[14:0]),
622 .cross_q_end_reg (cross_q_end_reg),
623 .cross_4KB_reg (cross_4KB_reg),
624 .total_num_buf_requested_reg (total_num_buf_requested_reg[5:0]),
625 .ring_size_reg (ring_size_reg[3:0]),
626 .ring_base_addr_reg (ring_base_addr_reg[38:0]),
627 .rotate (rotate),
628 .shift (shift),
629 .rspfifo_rp (rspfifo_rp[`VAFIFO_A_PTR]),
630 .rspfifo_ren2 (rspfifo_ren2[3:0]),
631 .arb1_zcp_req_accept (arb1_zcp_req_accept),
632 .zcp_32bit_mode (zcp_32bit_mode),
633 .req_dis (req_dis));
634
635/* --------------- response interface ------------------------ */
636niu_zcp_rsp_intf niu_zcp_rsp_intf
637 (/*AUTOINST*/
638 // Outputs
639 .rsp_request (rsp_request),
640 .rsp_ram_wr_en0 (rsp_ram_wr_en0),
641 .rsp_ram_wr_en1 (rsp_ram_wr_en1),
642 .rsp_ram_wr_en2 (rsp_ram_wr_en2),
643 .rsp_ram_wr_data (rsp_ram_wr_data[`RSPFIFO_W_R]),
644 .rsp_ram_mapped_in (rsp_ram_mapped_in[31:0]),
645 .rotate (rotate),
646 .shift (shift),
647 .rspfifo_rp (rspfifo_rp[`VAFIFO_A_PTR]),
648 .rspfifo_ren2 (rspfifo_ren2[3:0]),
649 .rspfifo_ren3 (rspfifo_ren3),
650 .latch_rspfifo_dout (latch_rspfifo_dout),
651 .zcp_meta_resp_accept (zcp_meta_resp_accept),
652 .rsp_load_state (rsp_load_state[3:0]),
653 .rsp_unload_state (rsp_unload_state[3:0]),
654 .rspfifo_uncorr_err (rspfifo_uncorr_err),
655 // Inputs
656 .clk (clk),
657 .rsp_reset (rsp_reset[25:0]),
658 .rsp_accepted (rsp_accepted),
659 .rot_sft32_tt_index_11_10 (rot_sft32_tt_index_11_10[1:0]),
660 .rot_sft1_tt_index_11_10 (rot_sft1_tt_index_11_10[1:0]),
661 .bitmap_total_num_buf_requested (bitmap_total_num_buf_requested[5:0]),
662 .bitmap_tt_index_11_10 (bitmap_tt_index_11_10[1:0]),
663 .rotate_done (rotate_done),
664 .shift_done (shift_done),
665 .rst_rotate (rst_rotate),
666 .rst_shift (rst_shift),
667 .reqfifo_wp (reqfifo_wp[`VAFIFO_A_PTR]),
668 .meta_zcp_resp_cmd (meta_zcp_resp_cmd[7:0]),
669 .meta_zcp_resp_length (meta_zcp_resp_length[13:0]),
670 .meta_zcp_resp_ready (meta_zcp_resp_ready),
671 .meta_zcp_resp_cmd_status (meta_zcp_resp_cmd_status[3:0]),
672 .meta_zcp_resp_dma_num (meta_zcp_resp_dma_num[4:0]),
673 .meta_zcp_resp_client (meta_zcp_resp_client),
674 .meta_zcp_data (meta_zcp_data[127:0]),
675 .meta_zcp_resp_byteenable (meta_zcp_resp_byteenable[15:0]),
676 .meta_zcp_data_status (meta_zcp_data_status[3:0]),
677 .meta_zcp_data_valid (meta_zcp_data_valid),
678 .meta_zcp_resp_complete (meta_zcp_resp_complete),
679 .meta_zcp_resp_transfer_cmpl (meta_zcp_resp_transfer_cmpl),
680 .rsp_dis (rsp_dis));
681
682/* --------------- arbiter -------------------------- */
683niu_zcp_arb2 niu_zcp_arb2
684 (/*AUTOINST*/
685 // Outputs
686 .rsp_accepted (rsp_accepted),
687 .slv_accepted (slv_accepted),
688 // Inputs
689 .clk (clk),
690 .reset (reset),
691 .tt_active (tt_active),
692 .tt_index (tt_index[11:0]),
693 .tt_sm_rw (tt_sm_rw),
694 .rsp_request (rsp_request),
695 .rsp_tt_index (rsp_tt_index[11:0]),
696 .slv_request (slv_request),
697 .slv_tt_index (slv_tt_index[11:0]));
698
699/* --------------- translation table ------------------------- */
700niu_va_ram va_ram
701 (/*AUTOINST*/
702 // Outputs
703 .va_ram_perr (va_ram_perr),
704 .zcp_tt_index_err (zcp_tt_index_err),
705 .zcp_tt_index_err_lv (zcp_tt_index_err_lv),
706 .va_dout (va_dout[1023:0]),
707 .rsp_tt_index_err (rsp_tt_index_err),
708 .slv_tt_index_err (slv_tt_index_err),
709 .vram_slv_rdata (vram_slv_rdata[1023:0]),
710 // Inputs
711 .clk (clk),
712 .va_reset (va_reset[36:0]),
713 .par_chk_dis (par_chk_dis),
714 .chk_bit_data (chk_bit_data[15:0]),
715 .tt_offset0 (tt_offset0[7:0]),
716 .tt_index_start0 (tt_index_start0[9:0]),
717 .tt_index_end0 (tt_index_end0[9:0]),
718 .tt_index_chk0 (tt_index_chk0),
719 .tt_offset1 (tt_offset1[7:0]),
720 .tt_index_start1 (tt_index_start1[9:0]),
721 .tt_index_end1 (tt_index_end1[9:0]),
722 .tt_index_chk1 (tt_index_chk1),
723 .tt_offset2 (tt_offset2[7:0]),
724 .tt_index_start2 (tt_index_start2[9:0]),
725 .tt_index_end2 (tt_index_end2[9:0]),
726 .tt_index_chk2 (tt_index_chk2),
727 .tt_offset3 (tt_offset3[7:0]),
728 .tt_index_start3 (tt_index_start3[9:0]),
729 .tt_index_end3 (tt_index_end3[9:0]),
730 .tt_index_chk3 (tt_index_chk3),
731 .tt_rd_en3 (tt_rd_en3),
732 .tt_index_4va (tt_index_4va[11:0]),
733 .rsp_ram_wr_en0 (rsp_ram_wr_en0),
734 .rsp_ram_wr_data (rsp_ram_wr_data[`RSPFIFO_W_R]),
735 .rsp_ram_mapped_in (rsp_ram_mapped_in[31:0]),
736 .rsp_tt_index1 (rsp_tt_index1[11:0]),
737 .slv_tt_index (slv_tt_index[11:0]),
738 .slv_ram_wdata (slv_ram_wdata[`VA_R]),
739 .slv_ram_be (slv_ram_be[3:0]),
740 .va_ram_ren (va_ram_ren),
741 .va_ram_wen (va_ram_wen),
742 .va_ram_wen0 (va_ram_wen0),
743 .va_ram_wen1 (va_ram_wen1),
744 .va_ram_wen2 (va_ram_wen2),
745 .va_ram_wen3 (va_ram_wen3),
746 .va_ram_wen4 (va_ram_wen4),
747 .va_ram_wen5 (va_ram_wen5),
748 .va_ram_wen6 (va_ram_wen6),
749 .va_ram_wen7 (va_ram_wen7),
750 .va_ram_rwen (va_ram_rwen),
751 .va_ram_rwen0 (va_ram_rwen0),
752 .va_ram_rwen1 (va_ram_rwen1),
753 .va_ram_rwen2 (va_ram_rwen2),
754 .va_ram_rwen3 (va_ram_rwen3),
755 .va_ram_rwen4 (va_ram_rwen4),
756 .va_ram_rwen5 (va_ram_rwen5),
757 .va_ram_rwen6 (va_ram_rwen6),
758 .va_ram_rwen7 (va_ram_rwen7));
759
760niu_st_ram st_ram
761 (/*AUTOINST*/
762 // Outputs
763 .st_ram_perr (st_ram_perr),
764 .st_dout (st_dout[`ST_R]),
765 .sram_slv_rdata (sram_slv_rdata[`ST_R]),
766 // Inputs
767 .clk (clk),
768 .st_reset (st_reset[3:0]),
769 .par_chk_dis (par_chk_dis),
770 .chk_bit_data (chk_bit_data[13:0]),
771 .tt_index_4st (tt_index_4st[11:0]),
772 .tt_rd_en2 (tt_rd_en2),
773 .slv_tt_index (slv_tt_index[11:0]),
774 .st_ram_wen (st_ram_wen),
775 .st_ram_ren (st_ram_ren),
776 .slv_ram_wdata (slv_ram_wdata[`ST_R]),
777 .slv_ram_be (slv_ram_be[`ST_PR]),
778 .ds_offset0 (ds_offset0[9:0]),
779 .ds_offset1 (ds_offset1[9:0]),
780 .ds_offset2 (ds_offset2[9:0]),
781 .ds_offset3 (ds_offset3[9:0]));
782
783
784niu_dn_ram dn_ram
785 (/*AUTOINST*/
786 // Outputs
787 .dn_ram_perr (dn_ram_perr),
788 .dn_dout (dn_dout[`DN_R]),
789 .dram_slv_rdata (dram_slv_rdata[`DN_R]),
790 // Inputs
791 .clk (clk),
792 .dn_reset (dn_reset[4:0]),
793 .par_chk_dis (par_chk_dis),
794 .chk_bit_data (chk_bit_data[16:0]),
795 .tt_index_4dn (tt_index_4dn[11:0]),
796 .tt_rd_en1 (tt_rd_en1),
797 .wb_tt1 (wb_tt1),
798 .wb_dn_reg (wb_dn_reg[`DN_R]),
799 .slv_tt_index (slv_tt_index[11:0]),
800 .dn_ram_wen (dn_ram_wen),
801 .dn_ram_ren (dn_ram_ren),
802 .slv_ram_wdata (slv_ram_wdata[`DN_R]),
803 .slv_ram_be (slv_ram_be[`DN_PR]),
804 .ds_offset0 (ds_offset0[9:0]),
805 .ds_offset1 (ds_offset1[9:0]),
806 .ds_offset2 (ds_offset2[9:0]),
807 .ds_offset3 (ds_offset3[9:0]),
808 .rsp_ram_wr_en1 (rsp_ram_wr_en1),
809 .rsp_ram_mapped_in (rsp_ram_mapped_in[31:0]),
810 .rsp_tt_index2 (rsp_tt_index2[11:0]));
811
812/* --------------- control fifo instantiation ---------------- */
813// cfifo0
814niu_zcp_cfifo32KB niu_zcp_cfifo32KB_port0
815 (
816 // Outputs
817 .zcp_dmc_ack(zcp_dmc_ack0),
818 .zcp_dmc_dat(zcp_dmc_dat0[`CFIFO_W_R]),
819 .zcp_dmc_dat_err(zcp_dmc_dat_err0),
820 .zcp_dmc_ful_pkt(zcp_dmc_ful_pkt0),
821 // Inputs
822 .clk(clk),
823 .reset(c0_reset|reset_cfifo0),
824 .wr_en(wr_en0),
825 .wr_data(wr_data[`CFIFO_W_R]),
826 .dmc_zcp_req(dmc_zcp_req0),
827 .double_bit_err(double_bit_err0),
828 .single_bit_err(single_bit_err0),
829 .last_line_err(last_line_err0),
830 .second_line_err(second_line_err0),
831 .first_line_err(first_line_err0),
832 .last_line(last_line0),
833 .second_line(second_line0),
834 .first_line(first_line0),
835 .ecc_chk_dis(ecc_chk_dis | ecc_chk_bypass0),
836 .chk_bit_data(chk_bit_data[15:0]),
837 .cfifo_ren(cfifo_ren0),
838 .cfifo_slv_rdata(cfifo_slv_rdata0[`CFIFO_W_R]),
839 .cfifo_wen(cfifo_wen0),
840 .slv_ram_wdata(slv_ram_wdata[`CFIFO_W_R]),
841 .slv_ram_addr(slv_ram_addr[10:0])
842);
843
844// cfifo1
845niu_zcp_cfifo32KB niu_zcp_cfifo32KB_port1
846 (
847 // Outputs
848 .zcp_dmc_ack(zcp_dmc_ack1),
849 .zcp_dmc_dat(zcp_dmc_dat1[`CFIFO_W_R]),
850 .zcp_dmc_dat_err(zcp_dmc_dat_err1),
851 .zcp_dmc_ful_pkt(zcp_dmc_ful_pkt1),
852 // Inputs
853 .clk(clk),
854 .reset(c1_reset|reset_cfifo1),
855 .wr_en(wr_en1),
856 .wr_data(wr_data[`CFIFO_W_R]),
857 .dmc_zcp_req(dmc_zcp_req1),
858 .double_bit_err(double_bit_err1),
859 .single_bit_err(single_bit_err1),
860 .last_line_err(last_line_err1),
861 .second_line_err(second_line_err1),
862 .first_line_err(first_line_err1),
863 .last_line(last_line1),
864 .second_line(second_line1),
865 .first_line(first_line1),
866 .ecc_chk_dis(ecc_chk_dis | ecc_chk_bypass1),
867 .chk_bit_data(chk_bit_data[15:0]),
868 .cfifo_ren(cfifo_ren1),
869 .cfifo_slv_rdata(cfifo_slv_rdata1[`CFIFO_W_R]),
870 .cfifo_wen(cfifo_wen1),
871 .slv_ram_wdata(slv_ram_wdata[`CFIFO_W_R]),
872 .slv_ram_addr(slv_ram_addr[10:0])
873);
874
875// cfifo2
876niu_zcp_cfifo16KB niu_zcp_cfifo16KB_port2
877 (
878 // Outputs
879 .zcp_dmc_ack(zcp_dmc_ack2),
880 .zcp_dmc_dat(zcp_dmc_dat2[`CFIFO_W_R]),
881 .zcp_dmc_dat_err(zcp_dmc_dat_err2),
882 .zcp_dmc_ful_pkt(zcp_dmc_ful_pkt2),
883 // Inputs
884 .clk(clk),
885 .reset(c2_reset|reset_cfifo2),
886 .wr_en(wr_en2),
887 .wr_data(wr_data[`CFIFO_W_R]),
888 .dmc_zcp_req(dmc_zcp_req2),
889 .double_bit_err(double_bit_err2),
890 .single_bit_err(single_bit_err2),
891 .last_line_err(last_line_err2),
892 .second_line_err(second_line_err2),
893 .first_line_err(first_line_err2),
894 .last_line(last_line2),
895 .second_line(second_line2),
896 .first_line(first_line2),
897 .ecc_chk_dis(ecc_chk_dis | ecc_chk_bypass2),
898 .chk_bit_data(chk_bit_data[15:0]),
899 .cfifo_ren(cfifo_ren2),
900 .cfifo_slv_rdata(cfifo_slv_rdata2[`CFIFO_W_R]),
901 .cfifo_wen(cfifo_wen2),
902 .slv_ram_wdata(slv_ram_wdata[`CFIFO_W_R]),
903 .slv_ram_addr(slv_ram_addr[9:0])
904);
905
906// cfifo3
907niu_zcp_cfifo16KB niu_zcp_cfifo16KB_port3
908 (
909 // Outputs
910 .zcp_dmc_ack(zcp_dmc_ack3),
911 .zcp_dmc_dat(zcp_dmc_dat3[`CFIFO_W_R]),
912 .zcp_dmc_dat_err(zcp_dmc_dat_err3),
913 .zcp_dmc_ful_pkt(zcp_dmc_ful_pkt3),
914 // Inputs
915 .clk(clk),
916 .reset(c3_reset|reset_cfifo3),
917 .wr_en(wr_en3),
918 .wr_data(wr_data[`CFIFO_W_R]),
919 .dmc_zcp_req(dmc_zcp_req3),
920 .double_bit_err(double_bit_err3),
921 .single_bit_err(single_bit_err3),
922 .last_line_err(last_line_err3),
923 .second_line_err(second_line_err3),
924 .first_line_err(first_line_err3),
925 .last_line(last_line3),
926 .second_line(second_line3),
927 .first_line(first_line3),
928 .ecc_chk_dis(ecc_chk_dis | ecc_chk_bypass3),
929 .chk_bit_data(chk_bit_data[15:0]),
930 .cfifo_ren(cfifo_ren3),
931 .cfifo_slv_rdata(cfifo_slv_rdata3[`CFIFO_W_R]),
932 .cfifo_wen(cfifo_wen3),
933 .slv_ram_wdata(slv_ram_wdata[`CFIFO_W_R]),
934 .slv_ram_addr(slv_ram_addr[9:0])
935);
936
937
938`else // N2 mode
939
940 assign rdmc_zcp_func_num = 0;
941 assign page_handle = 0;
942 assign va_ram_perr = 0;
943 assign dn_ram_perr = 0;
944 assign st_ram_perr = 0;
945 assign zcp_dmc_dat2 = 0;
946 assign zcp_dmc_dat3 = 0;
947 assign zcp_dmc_dat_err2 = 0;
948 assign zcp_dmc_dat_err3 = 0;
949 assign dram_slv_rdata = 0;
950 assign sram_slv_rdata = 0;
951 assign vram_slv_rdata = 0;
952 assign slv_accepted = 1'b1;
953 assign rspfifo_uncorr_err = 0;
954 assign reqfifo_uncorr_err = 0;
955 assign rsp_tt_index_err = 0;
956 assign slv_tt_index_err = 0;
957 assign zcp_tt_index_err = 0;
958 assign rsp_unload_state = 0;
959 assign rsp_load_state = 0;
960 assign req_unload_state = 0;
961 assign req_load_state = 0;
962 assign rrfifo_overrun = 0;
963 assign rrfifo_underrun = 0;
964 assign cfifo_slv_rdata2 = 0;
965 assign cfifo_slv_rdata3 = 0;
966 wire [6:0] hdr_sram_rvalue_zcp0;
967 wire [1:0] hdr_sram_rid_zcp0;
968 wire [6:0] sram_hdr_read_data_zcp0;
969 wire [6:0] hdr_sram_rvalue_zcp1;
970 wire [1:0] hdr_sram_rid_zcp1;
971 wire [6:0] sram_hdr_read_data_zcp1;
972
973// cfifo0
974niu_zcp_cfifo8KB niu_zcp_cfifo8KB_port0(
975 .clk(clk),
976 .iol2clk(iol2clk),
977 .reset(c0_reset|reset_cfifo0),
978 // from niu_zcp_tt for write to cfifo
979 .wr_en(wr_en0),
980 .wr_data(wr_data[`CFIFO_W_R]),
981 // dmc intf for read from cfifo
982 .dmc_zcp_req(dmc_zcp_req0),
983 .zcp_dmc_ack(zcp_dmc_ack0),
984 .zcp_dmc_dat(zcp_dmc_dat0[`CFIFO_W_R]),
985 .zcp_dmc_dat_err(zcp_dmc_dat_err0),
986 .zcp_dmc_ful_pkt(zcp_dmc_ful_pkt0),
987 // slv intf
988 .double_bit_err(double_bit_err0),
989 .single_bit_err(single_bit_err0),
990 .last_line_err(last_line_err0),
991 .second_line_err(second_line_err0),
992 .first_line_err(first_line_err0),
993 .last_line(last_line0),
994 .second_line(second_line0),
995 .first_line(first_line0),
996 .ecc_chk_dis(ecc_chk_dis | ecc_chk_bypass0),
997 .chk_bit_data(chk_bit_data[15:0]),
998 .cfifo_ren(cfifo_ren0),
999 .cfifo_slv_rdata(cfifo_slv_rdata0[`CFIFO_W_R]),
1000 .cfifo_wen(cfifo_wen0),
1001 .slv_ram_wdata(slv_ram_wdata[`CFIFO_W_R]),
1002 .slv_ram_addr(slv_ram_addr[8:0]),
1003 // DFT signals
1004 // memory related
1005 .tcu_mbist_user_mode(tcu_mbist_user_mode),
1006 .tcu_aclk(tcu_aclk),
1007 .tcu_bclk(tcu_bclk),
1008 .tcu_se_scancollar_in(tcu_se_scancollar_in),
1009 .tcu_se_scancollar_out(tcu_se_scancollar_out),
1010 .tcu_array_wr_inhibit(tcu_array_wr_inhibit),
1011 .scan_in(niu_mb7_cntrl_fifo_zcp_scan_in),
1012 .scan_out(niu_mb7_cntrl_fifo_zcp_scan_out),
1013 .hdr_sram_rvalue(hdr_sram_rvalue_zcp0),
1014 .hdr_sram_rid(hdr_sram_rid_zcp0),
1015 .hdr_sram_wr_en(hdr_sram_wr_en_zcp0),
1016 .hdr_sram_red_clr(hdr_sram_red_clr_zcp0),
1017 .sram_hdr_read_data(sram_hdr_read_data_zcp0),
1018 .mb_dmo_dout(rtx_rxc_zcp0_mb7_dmo_dout[39:0]),
1019 .l2clk_2x(l2clk_2x),
1020 // mbist controller related
1021 .niu_tcu_mbist_fail(niu_tcu_mbist_fail_7),
1022 .niu_tcu_mbist_done(niu_tcu_mbist_done_7),
1023 .mb_scan_in(mb7_scan_in),
1024 .mb_scan_out(mb7_scan_out),
1025 .tcu_niu_mbist_start(tcu_niu_mbist_start_7), // exception
1026 .tcu_mbist_bisi_en(tcu_mbist_bisi_en),
1027 .tcu_scan_en(tcu_scan_en)
1028);
1029
1030// cfifo1
1031niu_zcp_cfifo8KB niu_zcp_cfifo8KB_port1(
1032 .clk(clk),
1033 .iol2clk(iol2clk),
1034 .reset(c1_reset|reset_cfifo1),
1035 // from niu_zcp_tt for write to cfifo
1036 .wr_en(wr_en1),
1037 .wr_data(wr_data[`CFIFO_W_R]),
1038 // dmc intf for read from cfifo
1039 .dmc_zcp_req(dmc_zcp_req1),
1040 .zcp_dmc_ack(zcp_dmc_ack1),
1041 .zcp_dmc_dat(zcp_dmc_dat1[`CFIFO_W_R]),
1042 .zcp_dmc_dat_err(zcp_dmc_dat_err1),
1043 .zcp_dmc_ful_pkt(zcp_dmc_ful_pkt1),
1044 // slv intf
1045 .double_bit_err(double_bit_err1),
1046 .single_bit_err(single_bit_err1),
1047 .last_line_err(last_line_err1),
1048 .second_line_err(second_line_err1),
1049 .first_line_err(first_line_err1),
1050 .last_line(last_line1),
1051 .second_line(second_line1),
1052 .first_line(first_line1),
1053 .ecc_chk_dis(ecc_chk_dis | ecc_chk_bypass1),
1054 .chk_bit_data(chk_bit_data[15:0]),
1055 .cfifo_ren(cfifo_ren1),
1056 .cfifo_slv_rdata(cfifo_slv_rdata1[`CFIFO_W_R]),
1057 .cfifo_wen(cfifo_wen1),
1058 .slv_ram_wdata(slv_ram_wdata[`CFIFO_W_R]),
1059 .slv_ram_addr(slv_ram_addr[8:0]),
1060 // DFT signals
1061 // memory related
1062 .tcu_mbist_user_mode(tcu_mbist_user_mode),
1063 .tcu_aclk(tcu_aclk),
1064 .tcu_bclk(tcu_bclk),
1065 .tcu_se_scancollar_in(tcu_se_scancollar_in),
1066 .tcu_se_scancollar_out(tcu_se_scancollar_out),
1067 .tcu_array_wr_inhibit(tcu_array_wr_inhibit),
1068 .scan_in(niu_mb8_cntrl_fifo_zcp_scan_in),
1069 .scan_out(niu_mb8_cntrl_fifo_zcp_scan_out),
1070 .hdr_sram_rvalue(hdr_sram_rvalue_zcp1),
1071 .hdr_sram_rid(hdr_sram_rid_zcp1),
1072 .hdr_sram_wr_en(hdr_sram_wr_en_zcp1),
1073 .hdr_sram_red_clr(hdr_sram_red_clr_zcp1),
1074 .sram_hdr_read_data(sram_hdr_read_data_zcp1),
1075 .mb_dmo_dout(rtx_rxc_zcp1_mb7_dmo_dout[39:0]),
1076 .l2clk_2x(l2clk_2x),
1077 // mbist controller related
1078 .niu_tcu_mbist_fail(niu_tcu_mbist_fail_8),
1079 .niu_tcu_mbist_done(niu_tcu_mbist_done_8),
1080 .mb_scan_in(mb8_scan_in),
1081 .mb_scan_out(mb8_scan_out),
1082 .tcu_niu_mbist_start(tcu_niu_mbist_start_8), // exception
1083 .tcu_mbist_bisi_en(tcu_mbist_bisi_en),
1084 .tcu_scan_en(tcu_scan_en)
1085);
1086
1087
1088`endif // !ifdef NEPTUNE
1089
1090/////////////////////////////////////////////////////////////////
1091// common shared modules instantiation section
1092/////////////////////////////////////////////////////////////////
1093
1094/* --------------- reset logic ------------------------- */
1095zcp_RegDff #(4) reset_reg_l_RegDff(.din({4{reset_l}}), .clk(clk),.qout(reset_reg_l[3:0]));
1096
1097always @ (posedge clk)
1098 inv_reset_reg_l <= ~reset_reg_l;
1099//
1100zcp_RegDff #(1) reset_RegDff (.din( inv_reset_reg_l[0]), .clk(clk),.qout(reset));
1101zcp_RegDff #(1) c0_reset_RegDff (.din( inv_reset_reg_l[0]), .clk(clk),.qout(c0_reset)); // cfifo0 local reset
1102zcp_RegDff #(1) c1_reset_RegDff (.din( inv_reset_reg_l[0]), .clk(clk),.qout(c1_reset)); // cfifo1 local reset
1103zcp_RegDff #(1) c2_reset_RegDff (.din( inv_reset_reg_l[0]), .clk(clk),.qout(c2_reset)); // cfifo2 local reset
1104zcp_RegDff #(1) c3_reset_RegDff (.din( inv_reset_reg_l[0]), .clk(clk),.qout(c3_reset)); // cfifo3 local reset
1105zcp_RegDff #(4) st_reset_RegDff (.din( {4{inv_reset_reg_l[0]}}),.clk(clk),.qout(st_reset[3:0]));
1106zcp_RegDff #(5) dn_reset_RegDff (.din( {5{inv_reset_reg_l[0]}}),.clk(clk),.qout(dn_reset[4:0]));
1107zcp_RegDff #(6) fflp_reset_RegDff(.din( {6{inv_reset_reg_l[0]}}),.clk(clk),.qout(fflp_reset[5:0]));// niu_zcp_fflp_intf
1108zcp_RegDff #(26) rsp_reset_RegDff(.din({26{inv_reset_reg_l[1]}}),.clk(clk),.qout(rsp_reset[25:0]));
1109zcp_RegDff #(11)tt_reset_RegDff (.din({11{inv_reset_reg_l[1]}}),.clk(clk),.qout(tt_reset[10:0])); // niu_zcp_tt
1110zcp_RegDff #(12) req_reset_RegDff(.din({12{inv_reset_reg_l[2]}}),.clk(clk),.qout(req_reset[11:0]));
1111zcp_RegDff #(22) slv_reset_RegDff(.din({22{inv_reset_reg_l[2]}}),.clk(clk),.qout(slv_reset[21:0])); // niu_zcp_slv
1112zcp_RegDff #(37)va_reset_RegDff (.din({37{inv_reset_reg_l[3]}}),.clk(clk),.qout(va_reset[36:0]));
1113
1114/* --------------- zcp_fflp_intf instantiation ------------------------- */
1115niu_zcp_fflp_intf niu_zcp_fflp_intf
1116 (/*AUTOINST*/
1117 // Outputs
1118 .ififo_ren (ififo_ren[2:0]),
1119 .ififo_dout (ififo_dout[`IFIFO_W_R]),
1120 .ififo_overrun (ififo_overrun),
1121 .ififo_state (ififo_state[2:0]),
1122 // Inputs
1123 .clk (clk),
1124 .fflp_reset (fflp_reset[5:0]),
1125 .fflp_zcp_wr (fflp_zcp_wr[4:0]),
1126 .fflp_zcp_data (fflp_zcp_data[`IFIFO_W_R]));
1127
1128/* --------------- tt instantiation -------------------------- */
1129 niu_zcp_tt niu_zcp_tt (
1130`ifdef NEPTUNE
1131 .dmaw_threshold(dmaw_threshold[10:0]),
1132 // error handling
1133 .va_ram_perr(va_ram_perr),
1134 .dn_ram_perr(dn_ram_perr),
1135 .st_ram_perr(st_ram_perr),
1136 // tt intf
1137 .va_dout(va_dout[1023:0]),
1138 .st_dout(st_dout[`ST_R]),
1139 .dn_dout(dn_dout[`DN_R]),
1140 .tt_index_4va(tt_index_4va[11:0]),
1141 .tt_index_4dn(tt_index_4dn[11:0]),
1142 .tt_index_4st(tt_index_4st[11:0]),
1143 // req ptr intf
1144 .credit_ok(credit_ok),
1145 .zcp_tt_index_err_lv(zcp_tt_index_err_lv),
1146 .tt_index(tt_index[11:0]),
1147 .buf_req(buf_req),
1148 .wptr_HoQ_reg(wptr_HoQ_reg[15:0]),
1149 .cross_q_end_reg(cross_q_end_reg),
1150 .cross_4KB_reg(cross_4KB_reg),
1151 .ring_size_reg(ring_size_reg[3:0]),
1152 .ring_base_addr_reg(ring_base_addr_reg[38:0]),
1153 .reach_buf_end_reg(reach_buf_end_reg),
1154 .total_num_buf_requested_reg(total_num_buf_requested_reg[5:0]),
1155 // wb
1156 .wb_dn_reg(wb_dn_reg[`DN_R]),
1157 .wb_tt0(wb_tt0),
1158 .wb_tt1(wb_tt1),
1159 //
1160 .tt_rd_en0(tt_rd_en0),
1161 .tt_rd_en1(tt_rd_en1),
1162 .tt_rd_en2(tt_rd_en2),
1163 .tt_rd_en3(tt_rd_en3),
1164 .tt_active(tt_active),
1165 .tt_sm_rw(tt_sm_rw),
1166 // debug
1167 .tcp_payld_len(tcp_payld_len[15:0]),
1168 .l2_hdr_len(l2_hdr_len[9:0]),
1169 .l3_hdr_len(l3_hdr_len[9:0]),
1170 .header_len(header_len[9:0]),
1171 .tt_ok_reg7(tt_ok_reg7),
1172 .buf_req_ok(buf_req_ok),
1173 // MCP debug
1174 .TL(TL[`XPAN_TCP_SEQ_SPACE]),
1175 .S(S[`XPAN_TCP_SEQ_SPACE]),
1176 .payload_len(payload_len[`PKT_LEN_R]),
1177 .header_delta(header_delta[`PKT_LEN_R]),
1178 .UE(UE[`XPAN_TCP_SEQ_SPACE]),
1179 .TL_bt_UE(TL_bt_UE),
1180 .TL_eq_UE(TL_eq_UE),
1181 .qual_ulp_end_fail_reg(qual_ulp_end_fail_reg),
1182 .running_anchor_seq(running_anchor_seq[`TCP_SEQ_SPACE]),
1183 .first_byte_buf(first_byte_buf[5:0]),
1184 .last_byte_buf(last_byte_buf[20:0]),
1185 .index0(index0[5:0]),
1186 .index1(index1[5:0]),
1187 .index2(index2[5:0]),
1188 .index3(index3[5:0]),
1189 .win_ok(win_ok),
1190 .ulp_end_fail(ulp_end_fail),
1191 .mapped_in_fail(mapped_in_fail),
1192 .dmaw_threshold_fail(dmaw_threshold_fail),
1193 .unmap_on_left_oc(unmap_on_left_oc),
1194 .last_line2(last_line2),
1195 .second_line2(second_line2),
1196 .first_line2(first_line2),
1197 .last_line3(last_line3),
1198 .second_line3(second_line3),
1199 .first_line3(first_line3),
1200`else // N2
1201`endif
1202 .last_line0(last_line0),
1203 .second_line0(second_line0),
1204 .first_line0(first_line0),
1205 .last_line1(last_line1),
1206 .second_line1(second_line1),
1207 .first_line1(first_line1),
1208 .clk(clk),
1209 .reset(tt_reset),
1210 .kickoff_tt_reg(kickoff_tt_reg),
1211 .set_tt_program_err(set_tt_program_err),
1212 .fflp_data(fflp_data[`IFIFO_W_R]),
1213 // zcp_slv intf
1214 .tt_en(tt_en),
1215 .fn(fn[1:0]),
1216 .handle(handle[19:0]),
1217 // fflp wr intf
1218 .ififo_ren(ififo_ren[2:0]),
1219 .ififo_dout(ififo_dout[`IFIFO_W_R]),
1220 // rx dmc stuff
1221 .decode_default_rdc(decode_default_rdc),
1222 .decode_table_rdc(decode_table_rdc),
1223 .decode_zc_rdc(decode_zc_rdc),
1224 .tt_rdc_reg(tt_rdc_reg[7:0]),
1225 .fflp_rdc(fflp_rdc[7:0]),
1226 .default_rdc(default_rdc[4:0]),
1227 .table_rdc(table_rdc[4:0]),
1228 .zc_rdc(zc_rdc[4:0]),
1229 .wr_data(wr_data[`CFIFO_W_R]),
1230 .wr_en0(wr_en0),
1231 .wr_en1(wr_en1),
1232 .wr_en2(wr_en2),
1233 .wr_en3(wr_en3),
1234 .tt_state(tt_state[3:0])
1235);
1236
1237/* --------------- pio interface ----------------------------- */
1238niu_zcp_slv niu_zcp_slv
1239 (/*AUTOINST*/
1240 // Outputs
1241 .zcp_debug_sel (zcp_debug_sel[7:0]),
1242 .ecc_chk_bypass0 (ecc_chk_bypass0),
1243 .double_bit_err0 (double_bit_err0),
1244 .single_bit_err0 (single_bit_err0),
1245 .last_line_err0 (last_line_err0),
1246 .second_line_err0 (second_line_err0),
1247 .first_line_err0 (first_line_err0),
1248 .ecc_chk_bypass1 (ecc_chk_bypass1),
1249 .double_bit_err1 (double_bit_err1),
1250 .single_bit_err1 (single_bit_err1),
1251 .last_line_err1 (last_line_err1),
1252 .second_line_err1 (second_line_err1),
1253 .first_line_err1 (first_line_err1),
1254 .ecc_chk_bypass2 (ecc_chk_bypass2),
1255 .double_bit_err2 (double_bit_err2),
1256 .single_bit_err2 (single_bit_err2),
1257 .last_line_err2 (last_line_err2),
1258 .second_line_err2 (second_line_err2),
1259 .first_line_err2 (first_line_err2),
1260 .ecc_chk_bypass3 (ecc_chk_bypass3),
1261 .double_bit_err3 (double_bit_err3),
1262 .single_bit_err3 (single_bit_err3),
1263 .last_line_err3 (last_line_err3),
1264 .second_line_err3 (second_line_err3),
1265 .first_line_err3 (first_line_err3),
1266 .zcp_pio_ack (zcp_pio_ack),
1267 .zcp_pio_rdata (zcp_pio_rdata[63:0]),
1268 .zcp_pio_err (zcp_pio_err),
1269 .zcp_pio_intr (zcp_pio_intr),
1270 .handle (handle[19:0]),
1271 .fn (fn[1:0]),
1272 .default_rdc (default_rdc[4:0]),
1273 .table_rdc (table_rdc[4:0]),
1274 .zc_rdc (zc_rdc[4:0]),
1275 .tt_en (tt_en),
1276 .zcp_32bit_mode (zcp_32bit_mode),
1277 .req_dis (req_dis),
1278 .rsp_dis (rsp_dis),
1279 .par_chk_dis (par_chk_dis),
1280 .ecc_chk_dis (ecc_chk_dis),
1281 .dmaw_threshold (dmaw_threshold[10:0]),
1282 .reset_cfifo0 (reset_cfifo0),
1283 .reset_cfifo1 (reset_cfifo1),
1284 .reset_cfifo2 (reset_cfifo2),
1285 .reset_cfifo3 (reset_cfifo3),
1286 .training_vector (training_vector[31:0]),
1287 .slv_request (slv_request),
1288 .slv_tt_index (slv_tt_index[11:0]),
1289 .slv_ram_addr (slv_ram_addr[10:0]),
1290 .slv_ram_wdata (slv_ram_wdata[`DN_R]),
1291 .slv_ram_be (slv_ram_be[16:0]),
1292 .va_ram_rwen (va_ram_rwen),
1293 .va_ram_rwen0 (va_ram_rwen0),
1294 .va_ram_rwen1 (va_ram_rwen1),
1295 .va_ram_rwen2 (va_ram_rwen2),
1296 .va_ram_rwen3 (va_ram_rwen3),
1297 .va_ram_rwen4 (va_ram_rwen4),
1298 .va_ram_rwen5 (va_ram_rwen5),
1299 .va_ram_rwen6 (va_ram_rwen6),
1300 .va_ram_rwen7 (va_ram_rwen7),
1301 .va_ram_ren (va_ram_ren),
1302 .va_ram_wen (va_ram_wen),
1303 .va_ram_ren0 (va_ram_ren0),
1304 .va_ram_wen0 (va_ram_wen0),
1305 .va_ram_ren1 (va_ram_ren1),
1306 .va_ram_wen1 (va_ram_wen1),
1307 .va_ram_ren2 (va_ram_ren2),
1308 .va_ram_wen2 (va_ram_wen2),
1309 .va_ram_ren3 (va_ram_ren3),
1310 .va_ram_wen3 (va_ram_wen3),
1311 .va_ram_ren4 (va_ram_ren4),
1312 .va_ram_wen4 (va_ram_wen4),
1313 .va_ram_ren5 (va_ram_ren5),
1314 .va_ram_wen5 (va_ram_wen5),
1315 .va_ram_ren6 (va_ram_ren6),
1316 .va_ram_wen6 (va_ram_wen6),
1317 .va_ram_ren7 (va_ram_ren7),
1318 .va_ram_wen7 (va_ram_wen7),
1319 .st_ram_ren (st_ram_ren),
1320 .st_ram_wen (st_ram_wen),
1321 .dn_ram_ren (dn_ram_ren),
1322 .dn_ram_wen (dn_ram_wen),
1323 .cfifo_ren0 (cfifo_ren0),
1324 .cfifo_wen0 (cfifo_wen0),
1325 .cfifo_ren1 (cfifo_ren1),
1326 .cfifo_wen1 (cfifo_wen1),
1327 .cfifo_ren2 (cfifo_ren2),
1328 .cfifo_wen2 (cfifo_wen2),
1329 .cfifo_ren3 (cfifo_ren3),
1330 .cfifo_wen3 (cfifo_wen3),
1331 .tt_offset0 (tt_offset0[7:0]),
1332 .tt_index_start0 (tt_index_start0[9:0]),
1333 .tt_index_end0 (tt_index_end0[9:0]),
1334 .tt_index_chk0 (tt_index_chk0),
1335 .tt_offset1 (tt_offset1[7:0]),
1336 .tt_index_start1 (tt_index_start1[9:0]),
1337 .tt_index_end1 (tt_index_end1[9:0]),
1338 .tt_index_chk1 (tt_index_chk1),
1339 .tt_offset2 (tt_offset2[7:0]),
1340 .tt_index_start2 (tt_index_start2[9:0]),
1341 .tt_index_end2 (tt_index_end2[9:0]),
1342 .tt_index_chk2 (tt_index_chk2),
1343 .tt_offset3 (tt_offset3[7:0]),
1344 .tt_index_start3 (tt_index_start3[9:0]),
1345 .tt_index_end3 (tt_index_end3[9:0]),
1346 .tt_index_chk3 (tt_index_chk3),
1347 .ds_offset0 (ds_offset0[9:0]),
1348 .ds_offset1 (ds_offset1[9:0]),
1349 .ds_offset2 (ds_offset2[9:0]),
1350 .ds_offset3 (ds_offset3[9:0]),
1351 .chk_bit_data (chk_bit_data[16:0]),
1352 .ram_access_state (ram_access_state[2:0]),
1353 // Inputs
1354 .clk (clk),
1355 .slv_reset (slv_reset[21:0]),
1356 .kickoff_tt_reg (kickoff_tt_reg),
1357 .ififo_state (ififo_state[2:0]),
1358 .tt_state (tt_state[3:0]),
1359 .req_load_state (req_load_state[1:0]),
1360 .req_unload_state (req_unload_state[1:0]),
1361 .rsp_load_state (rsp_load_state[3:0]),
1362 .rsp_unload_state (rsp_unload_state[3:0]),
1363 .ififo_overrun (ififo_overrun),
1364 .set_tt_program_err (set_tt_program_err),
1365 .zcp_tt_index_err (zcp_tt_index_err),
1366 .slv_tt_index_err (slv_tt_index_err),
1367 .rsp_tt_index_err (rsp_tt_index_err),
1368 .va_ram_perr (va_ram_perr),
1369 .dn_ram_perr (dn_ram_perr),
1370 .st_ram_perr (st_ram_perr),
1371 .rrfifo_overrun (rrfifo_overrun),
1372 .rrfifo_underrun (rrfifo_underrun),
1373 .rspfifo_uncorr_err (rspfifo_uncorr_err),
1374 .pio_clients_addr (pio_clients_addr[19:0]),
1375 .pio_clients_rd (pio_clients_rd),
1376 .pio_clients_wdata (pio_clients_wdata[31:0]),
1377 .pio_zcp_sel (pio_zcp_sel),
1378 .zcp_dmc_dat_err0 (zcp_dmc_dat_err0),
1379 .zcp_dmc_dat_err1 (zcp_dmc_dat_err1),
1380 .zcp_dmc_dat_err2 (zcp_dmc_dat_err2),
1381 .zcp_dmc_dat_err3 (zcp_dmc_dat_err3),
1382 .decode_default_rdc (decode_default_rdc),
1383 .decode_table_rdc (decode_table_rdc),
1384 .decode_zc_rdc (decode_zc_rdc),
1385 .tt_rdc_reg (tt_rdc_reg[7:0]),
1386 .fflp_rdc (fflp_rdc[7:0]),
1387 .rdmc_zcp_func_num (rdmc_zcp_func_num[31:0]),
1388 .page_handle (page_handle[`PMS15:0]),
1389 .slv_accepted (slv_accepted),
1390 .vram_slv_rdata (vram_slv_rdata[1023:0]),
1391 .sram_slv_rdata (sram_slv_rdata[`ST_R]),
1392 .dram_slv_rdata (dram_slv_rdata[`DN_R]),
1393 .cfifo_slv_rdata0 (cfifo_slv_rdata0[`CFIFO_W_R]),
1394 .cfifo_slv_rdata1 (cfifo_slv_rdata1[`CFIFO_W_R]),
1395 .cfifo_slv_rdata2 (cfifo_slv_rdata2[`CFIFO_W_R]),
1396 .cfifo_slv_rdata3 (cfifo_slv_rdata3[`CFIFO_W_R]));
1397
1398
1399niu_zcp_debug niu_zcp_debug (
1400`ifdef NEPTUNE
1401/* ----- tt module ----- */
1402 // error handling
1403 .va_ram_perr(va_ram_perr),
1404 .dn_ram_perr(dn_ram_perr),
1405 .st_ram_perr(st_ram_perr),
1406 // tt intf
1407 .tt_index_4va(tt_index_4va[11:0]),
1408 .tt_index_4dn(tt_index_4dn[11:0]),
1409 .tt_index_4st(tt_index_4st[11:0]),
1410 // req ptr intf
1411 .credit_ok(credit_ok),
1412 .zcp_tt_index_err_lv(zcp_tt_index_err_lv),
1413 .tt_index(tt_index[11:0]),
1414 .buf_req(buf_req),
1415 .wptr_HoQ_reg(wptr_HoQ_reg[15:0]),
1416 .cross_q_end_reg(cross_q_end_reg),
1417 .cross_4KB_reg(cross_4KB_reg),
1418 .ring_size_reg(ring_size_reg[3:0]),
1419 .ring_base_addr_reg(ring_base_addr_reg[38:0]),
1420 .reach_buf_end_reg(reach_buf_end_reg),
1421 .total_num_buf_requested_reg(total_num_buf_requested_reg[5:0]),
1422 // wb
1423 .wb_dn_reg(wb_dn_reg[`DN_R]),
1424 .wb_tt0(wb_tt0), // loj
1425 //
1426 .tt_rd_en0(tt_rd_en0), // loj
1427 .tt_active(tt_active),
1428 // Zero copy specific
1429 .tcp_payld_len(tcp_payld_len[15:0]),
1430 .l2_hdr_len(l2_hdr_len[9:0]),
1431 .l3_hdr_len(l3_hdr_len[9:0]),
1432 .header_len(header_len[9:0]),
1433 .tt_ok_reg(tt_ok_reg7),
1434 .buf_req_ok(buf_req_ok),
1435 // MCP debug
1436 .TL(TL[`XPAN_TCP_SEQ_SPACE]), // MCP debug
1437 .S(S[`XPAN_TCP_SEQ_SPACE]), // MCP debug
1438 .payload_len(payload_len[`PKT_LEN_R]), // MCP debug
1439 .header_delta(header_delta[`PKT_LEN_R]), // MCP debug
1440 .UE(UE[`XPAN_TCP_SEQ_SPACE]), // MCP debug
1441 .TL_bt_UE(TL_bt_UE), // MCP debug
1442 .TL_eq_UE(TL_eq_UE), // MCP debug
1443 .qual_ulp_end_fail_reg(qual_ulp_end_fail_reg), // MCP debug
1444 .running_anchor_seq(running_anchor_seq[`TCP_SEQ_SPACE] ),// MCP debug
1445 .first_byte_buf(first_byte_buf[5:0]), // MCP debug
1446 .last_byte_buf(last_byte_buf[20:0]), // MCP debug
1447 .index0(index0[5:0]), // MCP debug
1448 .index1(index1[5:0]), // MCP debug
1449 .index2(index2[5:0]), // MCP debug
1450 .index3(index3[5:0]), // MCP debug
1451 .win_ok(win_ok), // MCP debug
1452 .ulp_end_fail(ulp_end_fail), // MCP debug
1453 .mapped_in_fail(mapped_in_fail), // MCP debug
1454 .dmaw_threshold_fail(dmaw_threshold_fail), // MCP debug
1455 .unmap_on_left_oc(unmap_on_left_oc), // MCP debug
1456 /* ----- req_intf module ----- */
1457 .latch_rspfifo_dout(latch_rspfifo_dout),
1458 .zcp_arb1_req(zcp_arb1_req),
1459 .zcp_arb1_req_cmd(zcp_arb1_req_cmd[7:0]),
1460 .zcp_arb1_req_address(zcp_arb1_req_address[63:0]),
1461 .zcp_arb1_req_length(zcp_arb1_req_length[13:0]),
1462 .zcp_arb1_req_port_num(zcp_arb1_req_port_num[1:0]),
1463 .zcp_arb1_req_dma_num(zcp_arb1_req_dma_num[4:0]),
1464 .arb1_zcp_req_accept(arb1_zcp_req_accept),
1465 /* ----- rsp_intf module ----- */
1466 .rsp_accepted(rsp_accepted),
1467 .rsp_request(rsp_request),
1468 .rsp_ram_wr_en2(rsp_ram_wr_en2),
1469 .rsp_ram_wr_data(rsp_ram_wr_data[127:0]),
1470 .rsp_tt_index(rsp_tt_index[11:0]),
1471 .rsp_ram_mapped_in(rsp_ram_mapped_in[31:0]),
1472 // req intf
1473 .rspfifo_ren3(rspfifo_ren3),
1474 .rspfifo_rp(rspfifo_rp[`VAFIFO_A_PTR]),
1475 .reqfifo_wp(reqfifo_wp[`VAFIFO_A_PTR]),
1476 .rrfifo_rd_data(rrfifo_rd_data[`RRFIFO_W_R]),
1477 // META RESPONSE control info
1478 .meta_zcp_resp_ready(meta_zcp_resp_ready), // Resp Command Request
1479 .meta_zcp_resp_cmd(meta_zcp_resp_cmd[7:0]), // cmd
1480 .meta_zcp_resp_cmd_status(meta_zcp_resp_cmd_status[3:0]), // cmd
1481 .meta_zcp_resp_length(meta_zcp_resp_length[11:0]), // Packet Length
1482 .meta_zcp_resp_dma_num(meta_zcp_resp_dma_num[4:0]), // Channel Number
1483 .meta_zcp_resp_client(meta_zcp_resp_client), // bit 0
1484 .zcp_meta_resp_accept(zcp_meta_resp_accept), // bitwise client accept
1485 // META RESPONSE data
1486 .meta_zcp_data(meta_zcp_data[127:0]), // Transfer Data
1487 .meta_zcp_resp_byteenable(meta_zcp_resp_byteenable[15:0]),// First/Last BE
1488 .meta_zcp_data_status(meta_zcp_data_status[3:0]), // Transfer Data Status
1489 .meta_zcp_data_valid(meta_zcp_data_valid), // Transfer Data Ack
1490 .meta_zcp_resp_complete(meta_zcp_resp_complete), // bitwise ZCP_CLIENT[0]
1491 .meta_zcp_resp_transfer_cmpl(meta_zcp_resp_transfer_cmpl),// bitwise ZCP_CLIENT[0]
1492 /* ----- va ram module ----- */
1493 .va_dout(va_dout[127:0]),
1494 .va_ram_ren0(va_ram_ren0),
1495 .va_ram_wen0(va_ram_wen0),
1496 .va_ram_ren1(va_ram_ren1),
1497 .va_ram_wen1(va_ram_wen1),
1498 .va_ram_ren2(va_ram_ren2),
1499 .va_ram_wen2(va_ram_wen2),
1500 .va_ram_ren3(va_ram_ren3),
1501 .va_ram_wen3(va_ram_wen3),
1502 .va_ram_ren4(va_ram_ren4),
1503 .va_ram_wen4(va_ram_wen4),
1504 .va_ram_ren5(va_ram_ren5),
1505 .va_ram_wen5(va_ram_wen5),
1506 .va_ram_ren6(va_ram_ren6),
1507 .va_ram_wen6(va_ram_wen6),
1508 .va_ram_ren7(va_ram_ren7),
1509 .va_ram_wen7(va_ram_wen7),
1510 /* ----- dn ram module ----- */
1511 // tt r/w
1512 .dn_dout(dn_dout[`DN_R]),
1513 // slv r/w
1514 .dn_ram_wen(dn_ram_wen),
1515 .dn_ram_ren(dn_ram_ren),
1516 /* ----- st ram module ----- */
1517 .st_dout(st_dout[`ST_R]),
1518 .st_ram_wen(st_ram_wen),
1519 .st_ram_ren(st_ram_ren),
1520`else // N2
1521`endif // !ifdef NEPTUNE
1522 // shared section
1523 .kickoff_tt_reg(kickoff_tt_reg),
1524 .ififo_state(ififo_state[2:0]),
1525 .tt_state(tt_state[3:0]),
1526 .req_load_state(req_load_state),
1527 .req_unload_state(req_unload_state),
1528 .rsp_load_state(rsp_load_state),
1529 .rsp_unload_state(rsp_unload_state),
1530 .ram_access_state(ram_access_state[2:0]),
1531 // fflp wr intf
1532 .wr_data(wr_data),
1533 .wr_en0(wr_en0),
1534 .wr_en1(wr_en1),
1535 .wr_en2(wr_en2),
1536 .wr_en3(wr_en3),
1537 .default_rdc(default_rdc[4:0]),
1538 .table_rdc(table_rdc[4:0]),
1539 .zc_rdc(zc_rdc[4:0]),
1540 .fflp_data(fflp_data[`IFIFO_W_R]),
1541 .zcp_debug_sel(zcp_debug_sel[7:0]),
1542 .training_vector(training_vector[31:0]),
1543 .clk(clk),
1544 .reset(reset),
1545 .zcp_debug_port(zcp_debug_port[31:0])
1546);
1547
1548/* --------------- spare gates --------------- */
1549`ifdef NEPTUNE
1550wire [3:0] do_nad;
1551wire [3:0] do_nor;
1552wire [3:0] do_inv;
1553wire [3:0] do_mux;
1554wire [3:0] do_q;
1555wire so;
1556
1557 zcp_spare_gates zcp_top_spare_gates (
1558 .di_nd3 ({1'h1, 1'h1, do_q[3]}),
1559 .di_nd2 ({1'h1, 1'h1, do_q[2]}),
1560 .di_nd1 ({1'h1, 1'h1, do_q[1]}),
1561 .di_nd0 ({1'h1, 1'h1, do_q[0]}),
1562 .di_nr3 ({1'h0, 1'h0}),
1563 .di_nr2 ({1'h0, 1'h0}),
1564 .di_nr1 ({1'h0, 1'h0}),
1565 .di_nr0 ({1'h0, 1'h0}),
1566 .di_inv (do_nad[3:0]),
1567 .di_mx3 ({1'h0, 1'h0}),
1568 .di_mx2 ({1'h0, 1'h0}),
1569 .di_mx1 ({1'h0, 1'h0}),
1570 .di_mx0 ({1'h0, 1'h0}),
1571 .mx_sel (do_nor[3:0]),
1572 .di_reg (do_inv[3:0]),
1573 .wt_ena (do_mux[3:0]),
1574 .rst ({reset,reset,reset,reset}),
1575 .si (1'h0),
1576 .se (1'h0),
1577 .clk (clk),
1578 .do_nad (do_nad[3:0]),
1579 .do_nor (do_nor[3:0]),
1580 .do_inv (do_inv[3:0]),
1581 .do_mux (do_mux[3:0]),
1582 .do_q (do_q[3:0]),
1583 .so (so)
1584 );
1585
1586`else
1587`endif
1588
1589
1590endmodule // niu_zcp
Full OpenSPARC design & verification tarball including full HDL.