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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / design / sys / iop / niu / rtl / niu_zcp_cfifo8KB.v
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AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: niu_zcp_cfifo8KB.v
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
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35/*%W% %G%*/
36
37/*************************************************************************
38 *
39 * File Name : niu_zcp_cfifo8KB.v
40 * Author Name : John Lo
41 * Description :
42 * Parent Module:
43 * Child Module:
44 * Interface Mod: many.
45 * Date Created : 3/25/2004
46 *
47 * Copyright (c) 2020, Sun Microsystems, Inc.
48 * Sun Proprietary and Confidential
49 *
50 * Modification :
51 *
52 * Synthesis Notes:
53 *
54 *************************************************************************/
55
56`include "niu_zcp.h"
57
58module niu_zcp_cfifo8KB (/*AUTOARG*/
59 // Outputs
60 zcp_dmc_ack, zcp_dmc_dat, zcp_dmc_dat_err, zcp_dmc_ful_pkt,
61 cfifo_slv_rdata, scan_out, sram_hdr_read_data, niu_tcu_mbist_fail,
62 niu_tcu_mbist_done, mb_scan_out, mb_dmo_dout,
63 // Inputs
64 clk, iol2clk, reset, wr_en, wr_data, dmc_zcp_req, double_bit_err,
65 single_bit_err, last_line_err, second_line_err, first_line_err,
66 last_line, second_line, first_line, ecc_chk_dis, chk_bit_data,
67 cfifo_ren, cfifo_wen, slv_ram_wdata, slv_ram_addr,
68 tcu_mbist_user_mode, tcu_aclk, tcu_bclk, tcu_se_scancollar_in,
69 tcu_se_scancollar_out, tcu_array_wr_inhibit, scan_in,
70 hdr_sram_rvalue, hdr_sram_rid, hdr_sram_wr_en, hdr_sram_red_clr,
71 l2clk_2x, mb_scan_in, tcu_niu_mbist_start, tcu_mbist_bisi_en,
72 tcu_scan_en
73 );
74 input clk;
75 input iol2clk; // for TI sram only
76 input reset;
77 // from niu_zcp_tt for write to cfifo
78 input wr_en;
79 input [`CFIFO_W_R] wr_data;
80 // dmc intf for read from cfifo
81 input dmc_zcp_req;
82 output zcp_dmc_ack;
83 output [`CFIFO_W_R] zcp_dmc_dat; // This is alos slave read data to niu_zcp_slv -loj
84 output zcp_dmc_dat_err;
85 output zcp_dmc_ful_pkt;
86 // slv intf
87 input double_bit_err;
88 input single_bit_err;
89 input last_line_err;
90 input second_line_err;
91 input first_line_err;
92 input last_line;
93 input second_line;
94 input first_line;
95 input ecc_chk_dis;
96 input [15:0] chk_bit_data;
97 input cfifo_ren; // from niu_zcp_ram_access_sm
98 output [`CFIFO_W_R] cfifo_slv_rdata;
99 input cfifo_wen; // from niu_zcp_ram_access_sm
100 input [`CFIFO_W_R] slv_ram_wdata;
101 input [8:0] slv_ram_addr; // slv ram read addr
102 // DFT signals
103 input tcu_mbist_user_mode;
104 input tcu_aclk;
105 input tcu_bclk;
106 input tcu_se_scancollar_in;
107 input tcu_se_scancollar_out;
108// input tcu_clk_stop;
109 input tcu_array_wr_inhibit;
110 input scan_in;
111 output scan_out;
112 input [6:0] hdr_sram_rvalue;
113 input [1:0] hdr_sram_rid;
114 input hdr_sram_wr_en;
115 input hdr_sram_red_clr;
116 output [6:0] sram_hdr_read_data;
117 input l2clk_2x;
118 //
119 output niu_tcu_mbist_fail;
120 output niu_tcu_mbist_done;
121 input mb_scan_in;
122 output mb_scan_out;
123 output [39:0] mb_dmo_dout;
124// input tcu_pce_ov;
125 input tcu_niu_mbist_start;
126 input tcu_mbist_bisi_en;
127 input tcu_scan_en;
128
129 wire [`CFIFO_W_R] cfifo_slv_rdata;
130 // Mar22.05 -loj
131 wire first_line_time;
132 wire second_line_time;
133 wire inject_first_line_err = first_line_err & first_line_time;
134 wire inject_second_line_err = second_line_err & second_line_time;
135 wire inject_last_line_err = last_line_err & last_line;
136 wire inject_first_line_err_1bit = inject_first_line_err & single_bit_err;
137 wire inject_first_line_err_2bit = inject_first_line_err & double_bit_err;
138 wire inject_second_line_err_1bit = inject_second_line_err & single_bit_err;
139 wire inject_second_line_err_2bit = inject_second_line_err & double_bit_err;
140 wire inject_last_line_err_1bit = inject_last_line_err & single_bit_err;
141 wire inject_last_line_err_2bit = inject_last_line_err & double_bit_err;
142 //
143 wire [6:0] hdr_sram_rvalue;
144 wire [1:0] hdr_sram_rid;
145 wire [6:0] sram_hdr_read_data;
146 wire uncorr_error0;
147 wire uncorr_error1;
148 wire [`CFIFO_A9_R] waddr;
149 wire [`CFIFO_A9_R] raddr;
150 wire [`CFIFO_W_R] wr_data;
151 wire [`CFIFO_W_R] ecc_gen_din;
152 wire [`CFIFO_W_ECC_R] wdata;
153 wire [`CFIFO_W_ECC_R] rdata;
154 wire [`CFIFO_W_ECC_R] ecc_chk_din;
155 wire [`CFIFO_W_R] zcp_dmc_dat;
156 wire full;
157 wire empty;
158 wire we,wen,wr_en;
159 wire ren,rd_en;
160 wire ren_d1;
161 wire ren_d2;
162 wire dat_err_oc;
163 wire err_oc;
164 // vlint flag_dangling_net_within_module off
165 // vlint flag_net_has_no_load off
166 wire [`CFIFO_W_ECC_R] ecc_chk_dout;
167 wire error0;
168 wire no_error0;
169 wire corr_error0;
170 wire error1;
171 wire no_error1;
172 wire corr_error1;
173 // vlint flag_dangling_net_within_module on
174 // vlint flag_net_has_no_load on
175
176/* ----- start of cfifo pointer management ------------------- */
177 /* ----- wr pointer ----- */
178 reg [`CFIFO_A9_PTR] nx_wptr;
179 wire [`CFIFO_A9_PTR] wptr;
180always @(wen or wptr)
181 if (wen)
182 nx_wptr = wptr + 1;
183 else
184 nx_wptr = wptr; // hold the value
185
186dffr #(`CFIFO_A9_ADD1) wptr_dffr(.clk(clk),.reset(reset),.d(nx_wptr),.q(wptr));
187
188 /* ----- rd pointer ----- */
189 reg [`CFIFO_A9_PTR] nx_rptr;
190 wire [`CFIFO_A9_PTR] rptr;
191always @(ren or rptr)
192 if (ren)
193 nx_rptr = rptr + 1;
194 else
195 nx_rptr = rptr; // hold the value
196
197dffr #(`CFIFO_A9_ADD1) rptr_dffr(.clk(clk),.reset(reset),.d(nx_rptr),.q(rptr));
198
199// vlint flag_dangling_net_within_module off
200// vlint flag_net_has_no_load off
201 wire [`CFIFO_A9_PTR] empty_space =
202 (wptr[`CFIFO_A9] == rptr[`CFIFO_A9]) ?
203`CFIFO_D512 - ({1'b0,wptr[`CFIFO_A9_R]} - {1'b0,rptr[`CFIFO_A9_R]}):
204 ({1'b0,rptr[`CFIFO_A9_R]} - {1'b0,wptr[`CFIFO_A9_R]}) ;
205
206 wire [`CFIFO_A9_PTR] full_space =
207 (wptr[`CFIFO_A9] == rptr[`CFIFO_A9]) ?
208 ({1'b0,wptr[`CFIFO_A9_R]} - {1'b0,rptr[`CFIFO_A9_R]}):
209`CFIFO_D512 - ({1'b0,rptr[`CFIFO_A9_R]} - {1'b0,wptr[`CFIFO_A9_R]}) ;
210// vlint flag_dangling_net_within_module on
211// vlint flag_net_has_no_load on
212
213
214 assign full = (wptr[`CFIFO_A9] ==
215 (!rptr[`CFIFO_A9])) &&
216 (wptr[`CFIFO_A9_R] ==
217 rptr[`CFIFO_A9_R]) ;
218
219 assign empty = (wptr[`CFIFO_A9_PTR] ==
220 rptr[`CFIFO_A9_PTR]);
221
222// vlint flag_dangling_net_within_module off
223// vlint flag_net_has_no_load off
224 wire overrun = full & wen;
225 wire underrun = empty & ren;
226// vlint flag_dangling_net_within_module on
227// vlint flag_net_has_no_load on
228
229/* ----- end of cfifo pointer management ------------------- */
230/* ----- start of glue logic ------------------------- */
231 // Use eop to increase the counter.
232 // Use sop to decrease the counter.
233 wire inc_cnt;
234 wire inc_cnt_p1;
235 wire inc_cnt_p2;
236 wire dec_cnt;
237
238 assign inc_cnt_p2 = we & ecc_gen_din[`CFIFO_W_SUB1]; // wr eop
239df1 #(1) inc_cnt_p1_df1(.clk(clk),.d(inc_cnt_p2),.q(inc_cnt_p1));
240df1 #(1) inc_cnt_df1 (.clk(clk),.d(inc_cnt_p1),.q(inc_cnt));
241
242 assign dec_cnt = ren_d1 & rdata[`CFIFO_W_ECC_SUB2];// rd sop
243
244 reg [`CFIFO_A11_PTR] pkt_cnt;
245
246always @(posedge clk)
247 if (reset)
248 pkt_cnt <= 0;
249 else
250 case ({inc_cnt,dec_cnt}) // synopsys full_case parallel_case
251 2'b00: pkt_cnt <= pkt_cnt;
252 2'b01: pkt_cnt <= pkt_cnt - 1;
253 2'b10: pkt_cnt <= pkt_cnt + 1;
254 2'b11: pkt_cnt <= pkt_cnt;
255 endcase // case({inc_cnt,dec_cnt})
256
257 reg zcp_dmc_ful_pkt;
258always @(posedge clk)
259 zcp_dmc_ful_pkt <= (|pkt_cnt) & (~dat_err_oc);
260
261
262/* ----- start of write path logic ------------------- */
263 assign wen = ~full & wr_en;
264
265 wire we_p1;
266 wire [`CFIFO_A9_R] waddr_p1;
267 wire [`CFIFO_W_R] ecc_gen_din_p1;
268df1 #(1) first_line_time_df1(.clk(clk),.d(first_line), .q(first_line_time));
269df1 #(1) second_line_time_df1(.clk(clk),.d(second_line), .q(second_line_time));
270df1 #(1) we_df1(.clk(clk),.d(wen), .q(we_p1));
271df1 #(`CFIFO_A9) waddr_df1(.clk(clk),.d(wptr[`CFIFO_A9_R]), .q(waddr_p1[`CFIFO_A9_R]));
272df1 #(130) ecc_gen_din_df1(.clk(clk),.d(wr_data[`CFIFO_W_R]),.q(ecc_gen_din_p1[`CFIFO_W_R]));
273
274 assign we = cfifo_wen ? 1'b1 : we_p1;
275 assign waddr = cfifo_wen ? slv_ram_addr : waddr_p1;
276 assign ecc_gen_din = cfifo_wen ? slv_ram_wdata : ecc_gen_din_p1;
277
278// Mar22.05 -loj
279 wire add_first_line_err_1bit = inject_first_line_err_1bit & single_bit_err;
280 wire add_first_line_err_2bit = inject_first_line_err_2bit & double_bit_err;
281 wire add_second_line_err_1bit = inject_second_line_err_1bit & single_bit_err;
282 wire add_second_line_err_2bit = inject_second_line_err_2bit & double_bit_err;
283 wire add_last_line_err_1bit = inject_last_line_err_1bit & single_bit_err;
284 wire add_last_line_err_2bit = inject_last_line_err_2bit & double_bit_err;
285
286 wire chk_bit0_data = chk_bit_data[0] |
287 add_first_line_err_1bit |
288 add_first_line_err_2bit |
289 add_second_line_err_1bit |
290 add_second_line_err_2bit |
291 add_last_line_err_1bit |
292 add_last_line_err_2bit ;
293
294 wire chk_bit1_data = chk_bit_data[1] |
295 add_first_line_err_2bit |
296 add_second_line_err_2bit |
297 add_last_line_err_2bit ;
298
299 wire [7:0] chk_bit_data_mod = {chk_bit_data[7:2],chk_bit1_data,chk_bit0_data};
300
301niu_65data_ecc_generate_w_err_injection niu_65data_ecc_generate_w_err_injection0(.chk_bit_data(chk_bit_data_mod[7:0]),.din(ecc_gen_din[64:0]), .dout(wdata[72:0]));
302niu_65data_ecc_generate_w_err_injection niu_65data_ecc_generate_w_err_injection1(.chk_bit_data(chk_bit_data[15:8]),.din(ecc_gen_din[129:65]),.dout(wdata[145:73]));
303
304/* ----- start of read path logic ------------------- */
305df1 #(1) rd_en_df1(.clk(clk),.d(dmc_zcp_req),.q(rd_en));
306 assign ren = ~empty & rd_en;
307
308df1 #(1) ren_d1_df1(.clk(clk),.d(ren), .q(ren_d1));
309df1 #(1) ren_d2_df1(.clk(clk),.d(ren_d1),.q(ren_d2));
310df1 #(1) zcp_dmc_ack_df1(.clk(clk),.d(ren_d2),.q(zcp_dmc_ack));
311
312df1 #(`CFIFO_W_ECC) ecc_chk_din_df1 (.clk(clk),
313 .d(rdata[`CFIFO_W_ECC_R]),
314 .q(ecc_chk_din[`CFIFO_W_ECC_R]));
315
316 assign cfifo_slv_rdata = {ecc_chk_din[145:81],ecc_chk_din[72:8]}; // 6-8-05
317
318// dout [72:0] refers to {data bits[64:0], check bits[7:0]}
319niu_65data_ecc_correct niu_65data_ecc_correct0(
320.ecc_chk_dis(ecc_chk_dis),
321.din(ecc_chk_din[72:0]), // 73b
322.dout(ecc_chk_dout[72:0]), // 73b
323.no_error(no_error0),
324.error(error0),
325.corr_error(corr_error0),
326.uncorr_error(uncorr_error0));
327
328niu_65data_ecc_correct niu_65data_ecc_correct1(
329.ecc_chk_dis(ecc_chk_dis),
330.din(ecc_chk_din[145:73]), // 73b
331.dout(ecc_chk_dout[145:73]), // 73b
332.no_error(no_error1),
333.error(error1),
334.corr_error(corr_error1),
335.uncorr_error(uncorr_error1));
336
337df1 #(130) zcp_dmc_dat_df1(.clk(clk),.d({ecc_chk_dout[145:81],ecc_chk_dout[72:8]}),.q(zcp_dmc_dat[129:0]));
338
339 // use ren_d2 to qualify err so that the control signal won't be affect by "x" coming from SRAM.
340 wire err_flow_through = (uncorr_error0 | uncorr_error1) & (~ecc_chk_dis);
341 wire err = ren_d2 & err_flow_through;
342df1 #(1) zcp_dmc_dat_err_df1(.clk(clk),.d(err_flow_through),.q(zcp_dmc_dat_err));
343zcp_SRFF dat_err_oc_SRFF (.clk(clk),.reset(reset),.set(err),.rst(reset),.q(err_oc));
344 assign dat_err_oc = err | err_oc;
345
346assign raddr[`CFIFO_A9_R] = cfifo_ren ? slv_ram_addr[`CFIFO_A9_R] : rptr[`CFIFO_A9_R];
347
348/* ----- start of TI memory instantiation ---------------- */
349 wire [7:0] mb_wdata;
350 wire [8:0] mbi_adr;
351 wire mbi_wr_en;
352 wire mbi_rd_en;
353 wire mbi_run;
354// TI SRAM
355niu_ram_512_146 cfifo8KB (
356.tcu_aclk(tcu_aclk),
357.tcu_bclk(tcu_bclk),
358.tcu_scan_en(tcu_scan_en),
359.tcu_se_scancollar_in(tcu_se_scancollar_in),
360.tcu_se_scancollar_out(tcu_se_scancollar_out),
361//.tcu_clk_stop(tcu_clk_stop),
362.tcu_array_wr_inhibit(tcu_array_wr_inhibit),
363.scan_in(scan_in), // from top
364.scan_out(scan_out), // to top
365.hdr_sram_rvalue(hdr_sram_rvalue[6:0]),
366.hdr_sram_rid(hdr_sram_rid[1:0]),
367.hdr_sram_wr_en(hdr_sram_wr_en),
368.hdr_sram_red_clr(hdr_sram_red_clr),
369.sram_hdr_read_data(sram_hdr_read_data[6:0]),
370.l2clk_2x(l2clk_2x), // 750Mhz
371.reset(reset),
372.mbi_wdata({mb_wdata[1:0],{18{mb_wdata[7:0]}}}),
373.mbi_rd_adr(mbi_adr[8:0]),
374.mbi_wr_adr(mbi_adr[8:0]),
375.mbi_wr_en(mbi_wr_en),
376.mbi_rd_en(mbi_rd_en),
377.mbi_run(mbi_run),
378// functional ports
379.data_inp(wdata[`CFIFO_W_ECC_R]),
380.addr_rd(raddr[`CFIFO_A9_R]),
381.addr_wt(waddr[`CFIFO_A9_R]),
382.wt_enable(we),
383.cs_rd(1'b1),
384.clk(iol2clk),
385.data_out(rdata[`CFIFO_W_ECC_R])
386);
387
388
389
390/* ----- start of mbist instantiation ------------------ */
391niu_mb7 zcp_mb
392 (
393 // Outputs
394 .niu_mb7_cntrl_fifo_zcp_rd_en (mbi_rd_en),
395 .niu_mb7_cntrl_fifo_zcp_wr_en (mbi_wr_en),
396 .niu_mb7_addr (mbi_adr[8:0]),
397 .niu_mb7_wdata (mb_wdata[7:0]),
398 .niu_mb7_run (mbi_run),
399 .niu_tcu_mbist_fail_7 (niu_tcu_mbist_fail),
400 .niu_tcu_mbist_done_7 (niu_tcu_mbist_done),
401 .mb7_scan_out (mb_scan_out),
402 .mb7_dmo_dout (mb_dmo_dout[39:0]),
403 // Inputs
404 .mb7_scan_in (mb_scan_in),
405 .l1clk (clk),
406 .rst (reset),
407 .tcu_mbist_user_mode (tcu_mbist_user_mode),
408// .tcu_pce_ov (tcu_pce_ov),
409// .tcu_clk_stop (tcu_clk_stop),
410 .tcu_aclk (tcu_aclk),
411 .tcu_bclk (tcu_bclk),
412 .tcu_niu_mbist_start_7 (tcu_niu_mbist_start),
413 .tcu_mbist_bisi_en (tcu_mbist_bisi_en),
414 .niu_mb7_cntrl_fifo_zcp_data_out (rdata[`CFIFO_W_ECC_R])
415);
416
417/* ----- end of mbist instantiation -------------------- */
418
419
420endmodule // niu_zcp_cfifo8KB
421
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