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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / design / sys / iop / niu / rtl / niu_zcp_debug.v
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AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: niu_zcp_debug.v
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35/*%W% %G%*/
36
37/*************************************************************************
38 *
39 * File Name : niu_zcp_debug.v
40 * Author Name : John Lo
41 * Description : neptune debug port
42 * Parent Module:
43 * Child Module:
44 * Interface Mod:
45 * Date Created : 12/17/2004
46 *
47 * Design Notes :
48 *
49 * Copyright (c) 2020, Sun Microsystems, Inc.
50 * Sun Proprietary and Confidential
51 *
52 * Modification :
53 *
54 * Synthesis Notes:
55 *
56 *************************************************************************/
57
58`include "niu_zcp.h"
59
60module niu_zcp_debug (
61`ifdef NEPTUNE
62/* ----- tt module ----- */
63// error handling
64va_ram_perr,
65dn_ram_perr,
66st_ram_perr,
67// tt intf
68tt_index_4va,
69tt_index_4dn,
70tt_index_4st,
71// req ptr intf
72credit_ok,
73zcp_tt_index_err_lv,
74tt_index,
75buf_req,
76wptr_HoQ_reg,
77cross_q_end_reg,
78cross_4KB_reg,
79ring_size_reg,
80ring_base_addr_reg,
81reach_buf_end_reg,
82total_num_buf_requested_reg,
83// wb
84wb_dn_reg,
85wb_tt0,
86//
87tt_rd_en0,
88tt_active,
89// Zero copy specific
90tcp_payld_len,
91l2_hdr_len,
92l3_hdr_len,
93header_len,
94tt_ok_reg,
95buf_req_ok,
96// MCP debug
97TL, // MCP debug
98S, // MCP debug
99payload_len, // MCP debug
100header_delta, // MCP debug
101UE, // MCP debug
102TL_bt_UE, // MCP debug
103TL_eq_UE, // MCP debug
104qual_ulp_end_fail_reg, // MCP debug
105running_anchor_seq, // MCP debug
106first_byte_buf, // MCP debug
107last_byte_buf, // MCP debug
108index0, // MCP debug
109index1, // MCP debug
110index2, // MCP debug
111index3, // MCP debug
112win_ok, // MCP debug
113ulp_end_fail, // MCP debug
114mapped_in_fail, // MCP debug
115dmaw_threshold_fail, // MCP debug
116unmap_on_left_oc, // MCP debug
117/* ----- req_intf module ----- */
118latch_rspfifo_dout,
119zcp_arb1_req,
120zcp_arb1_req_cmd,
121zcp_arb1_req_address,
122zcp_arb1_req_length,
123zcp_arb1_req_port_num,
124zcp_arb1_req_dma_num,
125arb1_zcp_req_accept,
126/* ----- rsp_intf module ----- */
127rsp_accepted,
128rsp_request,
129rsp_ram_wr_en2,
130rsp_ram_wr_data, // from barrel shifter/rotater
131rsp_tt_index,
132rsp_ram_mapped_in,
133// req intf
134rspfifo_ren3,
135rspfifo_rp,
136reqfifo_wp,
137rrfifo_rd_data,
138// META RESPONSE control info
139meta_zcp_resp_ready, // Resp Command Request
140meta_zcp_resp_cmd, // cmd
141meta_zcp_resp_cmd_status, // cmd
142meta_zcp_resp_length, // Packet Length
143meta_zcp_resp_dma_num, // Channel Number
144meta_zcp_resp_client, // bit 0
145zcp_meta_resp_accept, // bitwise client accept
146// META RESPONSE data
147meta_zcp_data, // Transfer Data
148meta_zcp_resp_byteenable, // First/Last BE
149meta_zcp_data_status, // Transfer Data Status
150meta_zcp_data_valid, // Transfer Data Ack
151meta_zcp_resp_complete, // bitwise ZCP_CLIENT[0]
152meta_zcp_resp_transfer_cmpl,// bitwise ZCP_CLIENT[0]
153 /* ----- va ram module ----- */
154va_dout,
155va_ram_ren0,
156va_ram_wen0,
157va_ram_ren1,
158va_ram_wen1,
159va_ram_ren2,
160va_ram_wen2,
161va_ram_ren3,
162va_ram_wen3,
163va_ram_ren4,
164va_ram_wen4,
165va_ram_ren5,
166va_ram_wen5,
167va_ram_ren6,
168va_ram_wen6,
169va_ram_ren7,
170va_ram_wen7,
171 /* ----- dn ram module ----- */
172// tt r/w
173dn_dout,
174// slv r/w
175dn_ram_wen,
176dn_ram_ren,
177 /* ----- st ram module ----- */
178st_dout,
179st_ram_wen,
180st_ram_ren,
181`else // N2
182`endif // !ifdef NEPTUNE
183// shared section
184kickoff_tt_reg,
185ififo_state,
186tt_state,
187req_load_state,
188req_unload_state,
189rsp_load_state,
190rsp_unload_state,
191ram_access_state,
192// fflp wr intf
193wr_data,
194wr_en0,
195wr_en1,
196wr_en2,
197wr_en3,
198default_rdc,
199table_rdc,
200zc_rdc,
201fflp_data,
202zcp_debug_sel,
203training_vector,
204clk,
205reset,
206zcp_debug_port
207);
208
209
210`ifdef NEPTUNE
211 /* ----- tt module ----- */
212 // error handling
213 input va_ram_perr;
214 input dn_ram_perr;
215 input st_ram_perr;
216 // tt intf
217 input [11:0] tt_index_4va;
218 input [11:0] tt_index_4dn;
219 input [11:0] tt_index_4st;
220 // req ptr intf
221 input credit_ok;
222 input zcp_tt_index_err_lv;
223 input [11:0] tt_index ;
224 input buf_req ;
225 input [15:0] wptr_HoQ_reg ;
226 input cross_q_end_reg ;
227 input cross_4KB_reg ;
228 input [3:0] ring_size_reg ;
229 input [38:0] ring_base_addr_reg ;
230 input reach_buf_end_reg ;
231 input [5:0] total_num_buf_requested_reg;
232 // wb
233 input [`DN_R] wb_dn_reg;
234 input wb_tt0;
235 //
236 input tt_rd_en0;
237 input tt_active;
238 // Zero copy specific
239 input [15:0] tcp_payld_len;
240 input [9:0] l2_hdr_len;
241 input [9:0] l3_hdr_len;
242 input [9:0] header_len;
243 input tt_ok_reg;
244 input buf_req_ok;
245 // MCP debug
246 input [`XPAN_TCP_SEQ_SPACE]TL; // MCP debug
247 input [`XPAN_TCP_SEQ_SPACE]S; // MCP debug
248 input [`PKT_LEN_R] payload_len; // MCP debug
249 input [`PKT_LEN_R] header_delta; // MCP debug
250 input [`XPAN_TCP_SEQ_SPACE]UE; // MCP debug
251 input TL_bt_UE; // MCP debug
252 input TL_eq_UE; // MCP debug
253 input qual_ulp_end_fail_reg; // MCP debug
254 input [`TCP_SEQ_SPACE] running_anchor_seq; // MCP debug
255 input [5:0] first_byte_buf; // MCP debug
256 input [20:0] last_byte_buf; // MCP debug
257 input [5:0] index0; // MCP debug
258 input [5:0] index1; // MCP debug
259 input [5:0] index2; // MCP debug
260 input [5:0] index3; // MCP debug
261 input win_ok; // MCP debug
262 input ulp_end_fail; // MCP debug
263 input mapped_in_fail; // MCP debug
264 input dmaw_threshold_fail; // MCP debug
265 input unmap_on_left_oc; // MCP debug
266 /* ----- req_intf module ----- */
267 input latch_rspfifo_dout;
268 input zcp_arb1_req;
269 input [7:0] zcp_arb1_req_cmd;
270 input [63:0] zcp_arb1_req_address;
271 input [13:0] zcp_arb1_req_length;
272 input [1:0] zcp_arb1_req_port_num;
273 input [4:0] zcp_arb1_req_dma_num;
274 input arb1_zcp_req_accept;
275 /* ----- rsp_intf module ----- */
276 input rsp_accepted;
277 input rsp_request;
278 input rsp_ram_wr_en2;
279 input [127:0] rsp_ram_wr_data; // from barrel shifter/rotater
280 input [11:0] rsp_tt_index;
281 input [31:0] rsp_ram_mapped_in;
282 // req intf
283 input rspfifo_ren3;
284 input [`VAFIFO_A_PTR] rspfifo_rp;
285 input [`VAFIFO_A_PTR] reqfifo_wp;
286 input [`RRFIFO_W_R] rrfifo_rd_data;
287 // META RESPONSE control info
288 input meta_zcp_resp_ready; // Resp Command Request
289 input [7:0] meta_zcp_resp_cmd; // cmd
290 input [3:0] meta_zcp_resp_cmd_status; // cmd status
291 input [11:0] meta_zcp_resp_length; // Packet Length
292 input [4:0] meta_zcp_resp_dma_num; // Channel Number
293 input meta_zcp_resp_client; // bit 0
294 input zcp_meta_resp_accept; // bitwise client accept
295 // META RESPONSE data
296 input [127:0] meta_zcp_data; // Transfer Data
297 input [15:0] meta_zcp_resp_byteenable; // First/Last BE
298 input [3:0] meta_zcp_data_status; // Transfer Data Status
299 input meta_zcp_data_valid; // Transfer Data Ack
300 input meta_zcp_resp_complete; // bitwise ZCP_CLIENT[0]
301 input meta_zcp_resp_transfer_cmpl;// bitwise ZCP_CLIENT[0]
302 /* ----- va ram module ----- */
303 input [127:0] va_dout;
304 input va_ram_ren0;
305 input va_ram_wen0;
306 input va_ram_ren1;
307 input va_ram_wen1;
308 input va_ram_ren2;
309 input va_ram_wen2;
310 input va_ram_ren3;
311 input va_ram_wen3;
312 input va_ram_ren4;
313 input va_ram_wen4;
314 input va_ram_ren5;
315 input va_ram_wen5;
316 input va_ram_ren6;
317 input va_ram_wen6;
318 input va_ram_ren7;
319 input va_ram_wen7;
320 /* ----- dn ram module ----- */
321 // tt r/w
322 input [`DN_R] dn_dout;
323 // slv r/w
324 input dn_ram_wen;
325 input dn_ram_ren;
326 /* ----- st ram module ----- */
327 input [`ST_R] st_dout;
328 input st_ram_wen;
329 input st_ram_ren;
330`else // N2
331`endif // !ifdef NEPTUNE
332 // shared section
333 input kickoff_tt_reg;
334 input [2:0] ififo_state;
335 input [3:0] tt_state;
336 input [1:0] req_load_state;
337 input [1:0] req_unload_state;
338 input [3:0] rsp_load_state;
339 input [3:0] rsp_unload_state;
340 input [2:0] ram_access_state;
341 // fflp wr intf
342 input [`CFIFO_W_R] wr_data;
343 input wr_en0;
344 input wr_en1;
345 input wr_en2;
346 input wr_en3;
347 input [4:0] default_rdc;
348 input [4:0] table_rdc;
349 input [4:0] zc_rdc;
350 input [`IFIFO_W_R] fflp_data;
351 input [7:0] zcp_debug_sel;
352 input [31:0] training_vector;
353 input clk;
354 input reset;
355 output [`DBUG_R] zcp_debug_port;
356
357
358
359
360// debug
361 wire [7:0] zcp_debug_sel;
362 wire kickoff_tt_reg;
363
364
365
366////////////////////////////////////////////////////////////
367`ifdef NEPTUNE
368////////////////////////////////////////////////////////////
369/* ----- neptune specific area ----- */
370 /* ----- tt module ----- */
371 // error handling
372 wire va_ram_perr;
373 wire dn_ram_perr;
374 wire st_ram_perr;
375 // tt intf
376 wire [11:0] tt_index_4va;
377 wire [11:0] tt_index_4dn;
378 wire [11:0] tt_index_4st;
379 // req ptr intf
380 wire credit_ok;
381 wire zcp_tt_index_err_lv;
382 wire [11:0] tt_index ;
383 wire buf_req ;
384 wire [15:0] wptr_HoQ_reg ;
385 wire cross_q_end_reg ;
386 wire cross_4KB_reg ;
387 wire [3:0] ring_size_reg ;
388 wire [38:0] ring_base_addr_reg ;
389 wire reach_buf_end_reg ;
390 wire [5:0] total_num_buf_requested_reg;
391 // wb
392 wire [`DN_R] wb_dn_reg;
393 wire wb_tt0;
394 //
395 wire tt_rd_en0;
396 wire tt_active;
397 // Zero copy specific
398 wire [15:0] tcp_payld_len;
399 wire [9:0] l2_hdr_len;
400 wire [9:0] l3_hdr_len;
401 wire [9:0] header_len;
402 wire tt_ok_reg;
403 wire buf_req_ok;
404 // MCP debug
405 wire [`XPAN_TCP_SEQ_SPACE]TL; // MCP debug
406 wire [`XPAN_TCP_SEQ_SPACE]S; // MCP debug
407 wire [`PKT_LEN_R] payload_len; // MCP debug
408 wire [`PKT_LEN_R] header_delta; // MCP debug
409 wire [`XPAN_TCP_SEQ_SPACE]UE; // MCP debug
410 wire TL_bt_UE; // MCP debug
411 wire TL_eq_UE; // MCP debug
412 wire qual_ulp_end_fail_reg; // MCP debug
413 wire [`TCP_SEQ_SPACE] running_anchor_seq; // MCP debug
414 wire [5:0] first_byte_buf; // MCP debug
415 wire [20:0] last_byte_buf; // MCP debug
416 wire [5:0] index0; // MCP debug
417 wire [5:0] index1; // MCP debug
418 wire [5:0] index2; // MCP debug
419 wire [5:0] index3; // MCP debug
420 wire win_ok; // MCP debug
421 wire ulp_end_fail; // MCP debug
422 wire mapped_in_fail; // MCP debug
423 wire dmaw_threshold_fail; // MCP debug
424 wire unmap_on_left_oc; // MCP debug
425 /* ----- req_intf module ----- */
426 wire latch_rspfifo_dout;
427 wire zcp_arb1_req;
428 wire [7:0] zcp_arb1_req_cmd;
429 wire [63:0] zcp_arb1_req_address;
430 wire [13:0] zcp_arb1_req_length;
431 wire [1:0] zcp_arb1_req_port_num;
432 wire [4:0] zcp_arb1_req_dma_num;
433 wire arb1_zcp_req_accept;
434 /* ----- rsp_intf module ----- */
435 wire rsp_accepted;
436 wire rsp_request;
437 wire rsp_ram_wr_en2;
438 wire [127:0] rsp_ram_wr_data; // from barrel shifter/rotater
439 wire [11:0] rsp_tt_index;
440 wire [31:0] rsp_ram_mapped_in;
441 // req intf
442 wire rspfifo_ren3;
443 wire [`VAFIFO_A_PTR] rspfifo_rp;
444 wire [`VAFIFO_A_PTR] reqfifo_wp;
445 wire [`RRFIFO_W_R] rrfifo_rd_data;
446 // META RESPONSE control info
447 wire meta_zcp_resp_ready; // Resp Command Request
448 wire [7:0] meta_zcp_resp_cmd; // cmd
449 wire [3:0] meta_zcp_resp_cmd_status; // cmd status
450 wire [11:0] meta_zcp_resp_length; // Packet Length
451 wire [4:0] meta_zcp_resp_dma_num; // Channel Number
452 wire meta_zcp_resp_client; // bit 0
453 wire zcp_meta_resp_accept; // bitwise client accept
454 // META RESPONSE data
455 wire [127:0] meta_zcp_data; // Transfer Data
456 wire [15:0] meta_zcp_resp_byteenable; // First/Last BE
457 wire [3:0] meta_zcp_data_status; // Transfer Data Status
458 wire meta_zcp_data_valid; // Transfer Data Ack
459 wire meta_zcp_resp_complete; // bitwise ZCP_CLIENT[0]
460 wire meta_zcp_resp_transfer_cmpl;// bitwise ZCP_CLIENT[0]
461 /* ----- va ram module ----- */
462 wire [127:0] va_dout;
463 wire va_ram_ren0;
464 wire va_ram_wen0;
465 wire va_ram_ren1;
466 wire va_ram_wen1;
467 wire va_ram_ren2;
468 wire va_ram_wen2;
469 wire va_ram_ren3;
470 wire va_ram_wen3;
471 wire va_ram_ren4;
472 wire va_ram_wen4;
473 wire va_ram_ren5;
474 wire va_ram_wen5;
475 wire va_ram_ren6;
476 wire va_ram_wen6;
477 wire va_ram_ren7;
478 wire va_ram_wen7;
479 /* ----- dn ram module ----- */
480 // tt r/w
481 wire [`DN_R] dn_dout;
482 // slv r/w
483 wire dn_ram_wen;
484 wire dn_ram_ren;
485 /* ----- st ram module ----- */
486 wire [`ST_R] st_dout;
487 wire st_ram_wen;
488 wire st_ram_ren;
489
490// debug_bus0 is for mcp tt signals
491 reg [31:0] nx_debug_bus0;
492 wire [31:0] debug_bus0;
493 reg [4:0] debug_sel0;
494
495always @ (posedge clk)
496 debug_sel0[4:0] <= zcp_debug_sel[4:0];
497
498always @ (/*AUTOSENSE*/S or TL or TL_bt_UE or TL_eq_UE or UE
499 or buf_req_ok or debug_sel0 or dmaw_threshold_fail
500 or first_byte_buf or header_delta or index0 or index1
501 or index2 or index3 or last_byte_buf or mapped_in_fail
502 or payload_len or qual_ulp_end_fail_reg
503 or running_anchor_seq or tt_ok_reg or ulp_end_fail
504 or unmap_on_left_oc or win_ok)
505 case (debug_sel0[4:0]) // synopsys parallel_case full_case infer_mux
506 5'h0: nx_debug_bus0 = TL[31:0];
507 5'h1: nx_debug_bus0 = S[31:0];
508 5'h2: nx_debug_bus0 = {payload_len[15:0],header_delta[15:0]};
509 5'h3: nx_debug_bus0 = 32'hdead_beef;
510 5'h4: nx_debug_bus0 = UE[31:0];
511 5'h5: nx_debug_bus0 = running_anchor_seq[31:0];
512 5'h6: nx_debug_bus0 = {last_byte_buf[20:0],
513 TL[32],S[32],UE[32],TL_bt_UE,
514 TL_eq_UE,
515 qual_ulp_end_fail_reg,win_ok,
516 ulp_end_fail,mapped_in_fail,
517 dmaw_threshold_fail,
518 unmap_on_left_oc};
519 5'h7: nx_debug_bus0 = {buf_req_ok,tt_ok_reg,first_byte_buf[5:0],
520 index0[5:0],index1[5:0],
521 index2[5:0],index3[5:0]};
522 5'h8: nx_debug_bus0 = 32'hdead_beef;
523 default: nx_debug_bus0 = 32'hdead_beef;
524 endcase // case(debug_sel0[4:0])
525
526zcp_RegDff #(32) debug_bus0_RegDff(.din(nx_debug_bus0),.clk(clk),.qout(debug_bus0));
527
528// debug_bus1 is for non-mcp tt signals
529 reg [31:0] debug_bus1;
530 reg [4:0] debug_sel1;
531always @ (posedge clk)
532 debug_sel1[4:0] <= zcp_debug_sel[4:0];
533
534always @ (posedge clk)
535 case (debug_sel1[4:0]) // synopsys parallel_case full_case infer_mux
536 5'h0: debug_bus1 <= {ring_size_reg[3:0],
537 va_ram_perr,dn_ram_perr,st_ram_perr,
538 zcp_tt_index_err_lv,
539 tt_index_4dn[11:0],tt_index_4va[11:0]};
540
541 5'h1: debug_bus1 <= {5'b0,cross_4KB_reg,wb_tt0,
542 reach_buf_end_reg,
543 tt_index[11:0],tt_index_4st[11:0]};
544
545 5'h2: debug_bus1 <= {ring_base_addr_reg[38:32],
546 cross_q_end_reg,credit_ok,buf_req,
547 total_num_buf_requested_reg[5:0],
548 wptr_HoQ_reg[15:0]};
549
550 5'h3: debug_bus1 <= ring_base_addr_reg[31:0];
551 5'h4: debug_bus1 <= wb_dn_reg[`W32D0];
552 5'h5: debug_bus1 <= wb_dn_reg[`W32D1];
553 5'h6: debug_bus1 <= wb_dn_reg[`W32D2];
554 5'h7: debug_bus1 <= wb_dn_reg[`W32D3];
555 5'h8: debug_bus1 <= {wb_dn_reg[135:128], // 8b
556 tt_active,tt_rd_en0,wb_tt0,
557 kickoff_tt_reg,
558 l2_hdr_len[9:0],l3_hdr_len[9:0]
559 };
560
561 5'h9: debug_bus1 <= {6'b0,
562 header_len[9:0],
563 tcp_payld_len[15:0]};
564 5'ha: debug_bus1 <= 32'hdead_beef;
565 5'hb: debug_bus1 <= 32'hdead_beef;
566 5'hc: debug_bus1 <= va_dout[`W32D0];
567 5'hd: debug_bus1 <= va_dout[`W32D1];
568 5'he: debug_bus1 <= va_dout[`W32D2];
569 5'hf: debug_bus1 <= va_dout[`W32D3];
570 5'h10: debug_bus1 <= {12'b0,
571 dn_ram_wen,
572 dn_ram_ren,
573 st_ram_wen,
574 st_ram_ren,
575 va_ram_ren0,va_ram_wen0,
576 va_ram_ren1,va_ram_wen1,
577 va_ram_ren2,va_ram_wen2,
578 va_ram_ren3,va_ram_wen3,
579 va_ram_ren4,va_ram_wen4,
580 va_ram_ren5,va_ram_wen5,
581 va_ram_ren6,va_ram_wen6,
582 va_ram_ren7,va_ram_wen7
583 };
584 5'h11: debug_bus1 <= dn_dout[`W32D0];
585 5'h12: debug_bus1 <= dn_dout[`W32D1];
586 5'h13: debug_bus1 <= dn_dout[`W32D2];
587 5'h14: debug_bus1 <= dn_dout[`W32D3];
588 5'h15: debug_bus1 <= {8'b0,st_dout[111:96],dn_dout[135:128]};
589 5'h16: debug_bus1 <= st_dout[`W32D0];
590 5'h17: debug_bus1 <= st_dout[`W32D1];
591 5'h18: debug_bus1 <= st_dout[`W32D2];
592 default: debug_bus1 <= 32'hdead_beef;
593 endcase // case(debug_sel1[4:0])
594
595// debug_bus2 is for req and rsp interface signals
596 reg [31:0] debug_bus2;
597 reg [4:0] debug_sel2;
598always @ (posedge clk)
599 debug_sel2[4:0] <= zcp_debug_sel[4:0];
600
601always @ (posedge clk)
602 case (debug_sel2[4:0]) // synopsys parallel_case full_case infer_mux
603 5'h0: debug_bus2 <= {
604 latch_rspfifo_dout,zcp_arb1_req,
605 zcp_arb1_req_cmd[7:0],
606 zcp_arb1_req_length[13:0],
607 zcp_arb1_req_port_num[1:0],
608 zcp_arb1_req_dma_num[4:0],
609 arb1_zcp_req_accept
610 };
611 5'h1: debug_bus2 <= zcp_arb1_req_address[31:0];
612 5'h2: debug_bus2 <= zcp_arb1_req_address[63:32];
613 5'h3: debug_bus2 <= 32'hdead_beef;
614 5'h4: debug_bus2 <= 32'hdead_beef;
615 5'h5: debug_bus2 <= {6'b0,
616 rsp_accepted,rsp_request,
617 rsp_ram_wr_en2,
618 rsp_tt_index[11:0],
619 rspfifo_ren3,
620 rspfifo_rp[`VAFIFO_A_PTR],
621 reqfifo_wp[`VAFIFO_A_PTR]
622 };
623 5'h6: debug_bus2 <= rsp_ram_wr_data[`W32D0];
624 5'h7: debug_bus2 <= rsp_ram_wr_data[`W32D1];
625 5'h8: debug_bus2 <= rsp_ram_wr_data[`W32D2];
626 5'h9: debug_bus2 <= rsp_ram_wr_data[`W32D3];
627 5'ha: debug_bus2 <= rsp_ram_mapped_in[31:0];
628 5'hb: debug_bus2 <= {9'b0,rrfifo_rd_data[`RRFIFO_W_R]};
629 5'hc: debug_bus2 <= {meta_zcp_resp_ready,
630 meta_zcp_resp_cmd[7:0],
631 meta_zcp_resp_cmd_status[3:0],
632 meta_zcp_resp_length[11:0],
633 meta_zcp_resp_dma_num[4:0],
634 meta_zcp_resp_client,
635 zcp_meta_resp_accept
636 };
637 5'hd: debug_bus2 <= meta_zcp_data[`W32D0];
638 5'he: debug_bus2 <= meta_zcp_data[`W32D1];
639 5'hf: debug_bus2 <= meta_zcp_data[`W32D2];
640 5'h10: debug_bus2 <= meta_zcp_data[`W32D3];
641 5'h11: debug_bus2 <= {9'b0,
642 meta_zcp_data_valid,
643 meta_zcp_resp_byteenable[15:0],
644 meta_zcp_data_status[3:0],
645 meta_zcp_resp_complete,
646 meta_zcp_resp_transfer_cmpl
647 };
648 5'h1f: debug_bus2 <= 32'hdead_beef;
649 default: debug_bus2 <= 32'hdead_beef;
650 endcase // case(debug_sel2[4:0])
651
652
653////////////////////////////////////////////////////////////
654`else // N2
655`endif // !ifdef NEPTUNE
656////////////////////////////////////////////////////////////
657
658
659/* ----- common area ----- */
660 reg [31:0] debug_bus3;
661 reg [4:0] debug_sel3;
662always @ (posedge clk)
663 debug_sel3[4:0] <= zcp_debug_sel[4:0];
664
665always @ (posedge clk)
666 case (debug_sel3[4:0]) // synopsys parallel_case full_case infer_mux
667 5'h0: debug_bus3 <= {10'b0,
668 ififo_state[2:0],
669 ram_access_state[2:0], // 2b
670 rsp_unload_state[3:0], // 4b
671 rsp_load_state[3:0], // 4b
672 req_unload_state[1:0], // 2b
673 req_load_state[1:0], // 2b
674 tt_state[3:0]}; // 4b
675 5'h1: debug_bus3 <= 32'hdead_beef; // reserved
676 5'h2: debug_bus3 <= {fflp_data[`W32D0]};
677 5'h3: debug_bus3 <= {fflp_data[`W32D1]};
678 5'h4: debug_bus3 <= {fflp_data[`W32D2]};
679 5'h5: debug_bus3 <= {fflp_data[`W32D3]};
680 5'h6: debug_bus3 <= {fflp_data[`W32D4]};
681 5'h7: debug_bus3 <= {fflp_data[`W32D5]};
682 5'h8: debug_bus3 <= {7'b0,kickoff_tt_reg,fflp_data[215:192]};
683 5'h9: debug_bus3 <= {17'b0,default_rdc[4:0],table_rdc[4:0],zc_rdc[4:0]};
684 5'ha: debug_bus3 <= 32'hdead_beef; // reserved
685 5'hb: debug_bus3 <= 32'hdead_beef; // reserved
686 5'he: debug_bus3 <= 32'hdead_beef; // reserved
687 5'hf: debug_bus3 <= {wr_data[`W32D0]}; // cfifo wr_data
688 5'h10: debug_bus3 <= {wr_data[`W32D1]};
689 5'h11: debug_bus3 <= {wr_data[`W32D2]};
690 5'h12: debug_bus3 <= {wr_data[`W32D3]};
691 5'h13: debug_bus3 <= {26'b0,
692 wr_data[129:128],
693 wr_en3,wr_en2,wr_en1,wr_en0};
694 5'h14: debug_bus3 <= 32'hdead_beef;
695 5'h15: debug_bus3 <= 32'hdead_beef;
696 5'h16: debug_bus3 <= 32'hdead_beef;
697 5'h17: debug_bus3 <= 32'hdead_beef;
698 5'h18: debug_bus3 <= 32'hdead_beef;
699 5'h19: debug_bus3 <= 32'hdead_beef;
700 5'h1a: debug_bus3 <= 32'hdead_beef;
701 5'h1b: debug_bus3 <= 32'hdead_beef;
702 5'h1c: debug_bus3 <= 32'hdead_beef;
703 5'h1d: debug_bus3 <= 32'hdead_beef;
704 5'h1e: debug_bus3 <= 32'hdead_beef;
705 5'h1f: debug_bus3 <= 32'hdead_beef; // reserved
706 default: debug_bus3 <= 32'hdead_beef;
707 endcase // case(debug_sel3[4:0])
708
709
710////////////////////////////////////////////////
711// Final Stage assembly
712////////////////////////////////////////////////
713
714 reg [31:0] zcp_debug_port;
715
716always @ (posedge clk)
717 if (reset)
718 zcp_debug_port <= 32'b0;
719 else
720 case (zcp_debug_sel[7:5]) // synopsys parallel_case full_case infer_mux
721 `ifdef NEPTUNE
722 3'h0: zcp_debug_port <= debug_bus0;
723 3'h1: zcp_debug_port <= debug_bus1;
724 3'h2: zcp_debug_port <= debug_bus2;
725 `else // !ifdef NEPTUNE
726 `endif
727 3'h3: zcp_debug_port <= debug_bus3;
728 3'h4: zcp_debug_port <= training_vector;
729 3'h5: zcp_debug_port <=~zcp_debug_port;
730 3'h6: zcp_debug_port <= 32'hdead_beef;
731 3'h7: zcp_debug_port <= 32'hdead_beef;
732 default: zcp_debug_port <= 32'hdead_beef;
733 endcase // casex(zcp_debug_sel)
734
735
736endmodule // niu_zcp_debug
737
738
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