projects / OpenSPARC-T2-DV / blame
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1 | // ========== Copyright Header Begin ========================================== |
| 2 | // | |
| 3 | // OpenSPARC T2 Processor File: pcs_rx_dpath.v | |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
| 6 | // | |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
| 8 | // | |
| 9 | // This program is free software; you can redistribute it and/or modify | |
| 10 | // it under the terms of the GNU General Public License as published by | |
| 11 | // the Free Software Foundation; version 2 of the License. | |
| 12 | // | |
| 13 | // This program is distributed in the hope that it will be useful, | |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 16 | // GNU General Public License for more details. | |
| 17 | // | |
| 18 | // You should have received a copy of the GNU General Public License | |
| 19 | // along with this program; if not, write to the Free Software | |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
| 21 | // | |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license | |
| 23 | // choice is available it will apply instead, Sun elects to use only | |
| 24 | // the General Public License version 2 (GPLv2) at this time for any | |
| 25 | // software where a choice of GPL license versions is made | |
| 26 | // available with the language indicating that GPLv2 or any later version | |
| 27 | // may be used, or where a choice of which version of the GPL is applied is | |
| 28 | // otherwise unspecified. | |
| 29 | // | |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
| 32 | // have any questions. | |
| 33 | // | |
| 34 | // ========== Copyright Header End ============================================ | |
| 35 | // @(#)pcs_rx_dpath.v 1.1G | |
| 36 | /**********************************************************************/ | |
| 37 | /* Project Name : CASSINI */ | |
| 38 | /* Module Name : PCS Rx Datapath */ | |
| 39 | /* Description : The PCS Rx datapath contains the four stage */ | |
| 40 | /* pipeline used to detect special sequences. It */ | |
| 41 | /* also contains the Decoder block and input */ | |
| 42 | /* register. A mux exists which selects among */ | |
| 43 | /* several special characters and encoded data to */ | |
| 44 | /* to be shipped over the GMII. */ | |
| 45 | /* */ | |
| 46 | /* Assumptions : none. */ | |
| 47 | /* */ | |
| 48 | /* Parent module : pcs.v */ | |
| 49 | /* Child modules : pcs_decoder.v */ | |
| 50 | /* Author Name : Linda Chen */ | |
| 51 | /* Date Created : 10/24/96 */ | |
| 52 | /* */ | |
| 53 | /* Copyright (c) 1994, Sun Microsystems, Inc. */ | |
| 54 | /* Sun Proprietary and Confidential */ | |
| 55 | /* */ | |
| 56 | /* Modifications : 12/9/98 : added output ports comma_p,k285_p for */ | |
| 57 | /* carrier detect generation and sync */ | |
| 58 | /* Synthesis Notes : none yet */ | |
| 59 | /**********************************************************************/ | |
| 60 | ||
| 61 | module pcs_rx_dpath (rxclk,reset_rx,enable_pci, // inputs | |
| 62 | rx_10bdata,rx_d_sel,link_up_rx, | |
| 63 | ||
| 64 | rxd, | |
| 65 | rx_8bdata,kchar,disp_err,dec_err, // outputs | |
| 66 | rx_8bdata_p,kchar_p,disp_err_p,dec_err_p, | |
| 67 | rx_8bdata_pp,kchar_pp, | |
| 68 | got_d_linkconf_p,comma_p,k285w1_p,enable_rx); | |
| 69 | ||
| 70 | input rxclk; // 125 MHz rx clock | |
| 71 | input reset_rx; // reset synchronized to rx clk | |
| 72 | input enable_pci; // PCS enable bit | |
| 73 | input [9:0] rx_10bdata; // incoming 10 bits from link | |
| 74 | input [2:0] rx_d_sel; // receive data mux to GMII select | |
| 75 | input link_up_rx; // link status sychronized to rx clock domain | |
| 76 | ||
| 77 | output [7:0] rxd; // data going onto GMII | |
| 78 | output [7:0] rx_8bdata, // data from decoder | |
| 79 | rx_8bdata_p, // data from decoder previous stage | |
| 80 | rx_8bdata_pp; | |
| 81 | output kchar, | |
| 82 | kchar_p, | |
| 83 | kchar_pp; | |
| 84 | output disp_err, // disparity error flag for rx_8bdata | |
| 85 | disp_err_p; | |
| 86 | output dec_err, // decoder error flag for rx_8bdata | |
| 87 | dec_err_p; | |
| 88 | output got_d_linkconf_p; | |
| 89 | output comma_p; | |
| 90 | output k285w1_p; | |
| 91 | output enable_rx; | |
| 92 | ||
| 93 | wire [9:0] rx_10bdec_in; // data bus input to encoder | |
| 94 | wire [7:0] nxt_rxd; // rx data bus to MAC | |
| 95 | wire enable_rx; // PCS enable synchronized | |
| 96 | wire clr; // clear pipeline | |
| 97 | wire disp_err_p; | |
| 98 | wire dec_err_p; | |
| 99 | ||
| 100 | wire dec_err_pp,disp_err_pp,got_d_linkconf_pp,comma_pp,k285w1_pp; | |
| 101 | ||
| 102 | assign clr = reset_rx | ~enable_rx | !link_up_rx; | |
| 103 | ||
| 104 | /* | |
| 105 | ** Pre Decoder Data Reg | |
| 106 | */ | |
| 107 | REG #(10) r_in_reg (.qout(rx_10bdec_in),.clk(rxclk),.din(rx_10bdata)); | |
| 108 | ||
| 109 | ||
| 110 | /* | |
| 111 | ** DECODER - takes whatever comes in and decodes it to an 8 bit value. | |
| 112 | ** Generates helpful flags for special data characters and k characters. | |
| 113 | ** Flags disparity and decode errors. | |
| 114 | */ | |
| 115 | // vlint flag_non_name_based_inst off | |
| 116 | pcs_decoder pcs_decoder(rx_10bdec_in,rxclk, // inputs | |
| 117 | ||
| 118 | rx_8bdata_pp,dec_err_pp,disp_err_pp, // outputs | |
| 119 | kchar_pp,got_d_linkconf_pp,comma_pp,k285w1_pp); | |
| 120 | // vlint flag_non_name_based_inst on | |
| 121 | ||
| 122 | /* | |
| 123 | ** Pipeline regs | |
| 124 | */ | |
| 125 | REG #(8) r_8bdata_p (.qout(rx_8bdata_p),.clk(rxclk),.din(rx_8bdata_pp)); | |
| 126 | REG #(8) r_8bdata (.qout(rx_8bdata),.clk(rxclk),.din(rx_8bdata_p)); | |
| 127 | ||
| 128 | REG #(1) r_kchar_p (.qout(kchar_p),.clk(rxclk),.din(kchar_pp)); | |
| 129 | REG #(1) r_kchar (.qout(kchar),.clk(rxclk),.din(kchar_p)); | |
| 130 | ||
| 131 | REG #(1) r_disp_err_p (.qout(disp_err_p),.clk(rxclk),.din(disp_err_pp)); | |
| 132 | REG #(1) r_disp_err (.qout(disp_err),.clk(rxclk),.din(disp_err_p)); | |
| 133 | ||
| 134 | REG #(1) r_dec_err_p (.qout(dec_err_p),.clk(rxclk),.din(dec_err_pp)); | |
| 135 | REG #(1) r_dec_err (.qout(dec_err),.clk(rxclk),.din(dec_err_p)); | |
| 136 | ||
| 137 | REG #(1) r_got_d_linkconf_p(.qout(got_d_linkconf_p),.clk(rxclk), | |
| 138 | .din(got_d_linkconf_pp)); | |
| 139 | REG #(1) r_comma_p(.qout(comma_p),.clk(rxclk), | |
| 140 | .din(comma_pp)); | |
| 141 | REG #(1) r_k285w1_p(.qout(k285w1_p),.clk(rxclk), | |
| 142 | .din(k285w1_pp)); | |
| 143 | ||
| 144 | SYNCREG r_enable_rx (enable_rx,rxclk,enable_pci); | |
| 145 | ||
| 146 | /* | |
| 147 | ** Output MUX for rx data out | |
| 148 | ** PCS_RXD_ZERO 3'h0 | |
| 149 | ** PCS_RXD_PREAMBLE 3'h1 | |
| 150 | ** PCS_RXD_FALSE_CARRIER 3'h2 | |
| 151 | ** PCS_RXD_CRS_EXT 3'h3 | |
| 152 | ** PCS_RXD_CRS_EXT_ER 3'h4 | |
| 153 | ** PCS_RXD_DECODER 3'h5 | |
| 154 | */ | |
| 155 | MUX6TO1 #(8) rxd_outmux (.dout(nxt_rxd),.sel(rx_d_sel),.D0(8'h0),.D1(8'h55), | |
| 156 | .D2(8'hE),.D3(8'hF),.D4(8'h1F),.D5(rx_8bdata)); | |
| 157 | ||
| 158 | /* | |
| 159 | ** Output RXD reg | |
| 160 | */ | |
| 161 | RREG #(8) r_rxd (.qout(rxd),.clk(rxclk),.rst(clr),.din(nxt_rxd)); | |
| 162 | ||
| 163 | endmodule | |
| 164 | ||
| 165 |