Initial commit of OpenSPARC T2 design and verification files.

[OpenSPARC-T2-DV] / design / sys / iop / niu / rtl / rx_xgmii_intf.v

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// OpenSPARC T2 Processor File: rx_xgmii_intf.v
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/*%W%	%G%*/

/*************************************************************************
 *
 * File Name    : rx_xgmii_intf
 * Author Name  : John Lo
 * Description  : This module if for rx xgmii interface.
 * Parent Module: 
 * Child  Module: 
 * Interface Mod: 
 * Date Created : 3/24/04
 *
 * Copyright (c) 2020, Sun Microsystems, Inc. 
 * Sun Proprietary and Confidential   
 *
 * Modification :
 * 
 * Synthesis Notes: 
 * 
 *************************************************************************/

module rx_xgmii_intf (
rx_clk,
// xgmii 32bit  interface
xgmii_rxc,
xgmii_rxd,
// xgmii 64bit  interfaceoutput
xgmii_rxc_8b,
xgmii_rxd_64b
		   );

   input           rx_clk;
                   // xgmii 32bit  interface
   input [3:0] 	   xgmii_rxc;
   input [31:0]    xgmii_rxd;
                   // xgmii 64bit  interfaceoutput
   output [7:0]    xgmii_rxc_8b;
   output [63:0]   xgmii_rxd_64b;
   
   wire 	   rx_clk;
   wire 	   rx_clk_n;
   wire [3:0] 	   xgmii_rxc_reg_n;
   wire [3:0] 	   xgmii_rxc_reg;
   wire [31:0] 	   xgmii_rxd_reg_n;
   wire [31:0] 	   xgmii_rxd_reg;
   wire [7:0] 	   xgmii_rxc_8  = {xgmii_rxc_reg_n,xgmii_rxc_reg};
   wire [63:0] 	   xgmii_rxd_64 = {xgmii_rxd_reg_n,xgmii_rxd_reg};
   wire [7:0] 	   xgmii_rxc_8b;
   wire [63:0] 	   xgmii_rxd_64b;
   	     

/* -------------------- negative clock definition ------------- */

`ifdef USE_XGMII_INTF
   assign 	   rx_clk_n = ~rx_clk;
`else // !ifdef USE_XGMII_INTF
   assign 	   rx_clk_n =  rx_clk;
`endif
/* ***************** normal data path ************************* */
/* ----------------- xgmii pre statge registers --------------- */
   RegDff   #(4)  xgmii_rxc_reg_n_RegDff (.din(xgmii_rxc),.clk(rx_clk_n),.qout(xgmii_rxc_reg_n));
   RegDff   #(4)  xgmii_rxc_reg_RegDff   (.din(xgmii_rxc),.clk(rx_clk  ),.qout(xgmii_rxc_reg  ));
   RegDff   #(32) xgmii_rxd_reg_n_RegDff (.din(xgmii_rxd),.clk(rx_clk_n),.qout(xgmii_rxd_reg_n));
   RegDff   #(32) xgmii_rxd_reg_RegDff   (.din(xgmii_rxd),.clk(rx_clk  ),.qout(xgmii_rxd_reg  ));
   // convert to positive edge pipeline

   RegDff   #(8)  xgmii_rxc_8b_RegDff(.din(xgmii_rxc_8), .clk(rx_clk  ),.qout(xgmii_rxc_8b));
   RegDff   #(64) xgmii_rxd_64b_RegDff(.din(xgmii_rxd_64),.clk(rx_clk  ),.qout(xgmii_rxd_64b));

endmodule // rx_xgmii_intf