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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: rxfifo_load.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | /*%W% %G%*/ | |
36 | ||
37 | /************************************************************************* | |
38 | * | |
39 | * File Name : rxfifo_load | |
40 | * Author Name : John Lo | |
41 | * Description : It contains physical rxmac fifo and associated control | |
42 | * logic (read/write pointers). | |
43 | * Parent Module: rx_xmac | |
44 | * Child Module: rxfifo_memory_model | |
45 | * Interface Mod: many. | |
46 | * Date Created : 5/9/00 | |
47 | * | |
48 | * Copyright (c) 2002, Sun Microsystems, Inc. | |
49 | * Sun Proprietary and Confidential | |
50 | * | |
51 | * Design Notes: Since 802.3ae says that RxMac should be able to handle | |
52 | * min IPG == 4 byte times, it is a good idea to have a | |
53 | * larger rxfifo to combat this temporary phenominum. | |
54 | * | |
55 | * Modification : | |
56 | * | |
57 | * Synthesis Notes: | |
58 | * | |
59 | *************************************************************************/ | |
60 | ||
61 | module rxfifo_load ( | |
62 | rx_clk, | |
63 | rx_reset, | |
64 | rxfifo_wen, // for rxfifo to generate wr_en | |
65 | rxfifo_g_rd_ptr_sync, | |
66 | rxfifo_rd_ptr_clk, | |
67 | rxfifo_din, | |
68 | // outputs | |
69 | rxfifo_dout, // {mac_own_da,tag,64bit data} | |
70 | rxfifo_g_wr_ptr_rxclk, // to xmac_sync.v | |
71 | rxfifo_full_rxclk, | |
72 | rxfifo_afull_rxclk, | |
73 | // for signal observation | |
74 | rxfifo_wr_ptr_rxclk, | |
75 | rxfifo_empty_rxclk, | |
76 | rxfifo_overrun_rxclk); | |
77 | ||
78 | ||
79 | input rx_clk; | |
80 | input rx_reset; | |
81 | input rxfifo_wen; // for rxfifo to generate wr_en | |
82 | input [4:0] rxfifo_g_rd_ptr_sync; | |
83 | input [3:0] rxfifo_rd_ptr_clk; | |
84 | input [65:0] rxfifo_din; | |
85 | // outputs | |
86 | output [65:0] rxfifo_dout; // {mac_own_da,tag,64bit data} | |
87 | output [4:0] rxfifo_g_wr_ptr_rxclk; // to xmac_sync.v | |
88 | output rxfifo_full_rxclk; | |
89 | output rxfifo_afull_rxclk; | |
90 | // for signal observation | |
91 | output [4:0] rxfifo_wr_ptr_rxclk; | |
92 | output rxfifo_empty_rxclk; | |
93 | output rxfifo_overrun_rxclk; | |
94 | ||
95 | // rxfifo signals | |
96 | wire [4:0] rxfifo_wr_ptr_rxclk; | |
97 | // wire [4:0] rxfifo_wr_ptr_plus1_rxclk; | |
98 | wire [4:0] rxfifo_g_wr_ptr_rxclk; | |
99 | wire [4:0] rxfifo_rd_ptr_rxclk; | |
100 | wire rxfifo_wen; | |
101 | wire rxfifo_wr_en = rxfifo_wen & (~rxfifo_full_rxclk); | |
102 | ||
103 | // Before the rxfifo overflow bug was found (9/26/00), the signal: | |
104 | // rxfifo_full_rxclk can not be used to stop rxfifo_wr_en. | |
105 | // Because it is necessary to let eop and status tag be written | |
106 | // so that IPP can discard this pkt. | |
107 | // But now the rxfifo effective depth is reduced to 15 and the | |
108 | // rxfifo_afull_rxclk is used to generate eop and write to | |
109 | // rxfifo (one last data entry left), so it is ok to use | |
110 | // rxfifo_full to block rxfifo_wr_en. -loj (9/27/00) | |
111 | // | |
112 | // In Feb. 10th, 2004, the rxfifo overflow bug shows up again. | |
113 | // It is caused by adding one more layer of pipeline register | |
114 | // to add the strip_crc function. | |
115 | // For this reason, the rxfifo_afull signal has to be extended 1 more. | |
116 | ||
117 | /* --------------- start rxfifo pointer Management ------------------ */ | |
118 | // Rxfifo read Pointer, rd_ptr from sysclk | |
119 | g2b_5bit rxfifo_g_rd_ptr_g2b_5bit(.g_cnt(rxfifo_g_rd_ptr_sync), | |
120 | .b_cnt(rxfifo_rd_ptr_rxclk)); | |
121 | ||
122 | // Rxfifo G Write Pointer, g_wr_ptr to sysclk | |
123 | g_cntr_5bit rxfifo_g_wr_ptr_rxclk_g_cntr_5bit( .reset(rx_reset), | |
124 | .clk(rx_clk), | |
125 | .ce(rxfifo_wr_en), | |
126 | .g_cnt(rxfifo_g_wr_ptr_rxclk)); | |
127 | ||
128 | // Rxfifo Write Pointer | |
129 | g2b_5bit rxfifo_g2b_5bit(.g_cnt(rxfifo_g_wr_ptr_rxclk), | |
130 | .b_cnt(rxfifo_wr_ptr_rxclk)); | |
131 | ||
132 | //assign rxfifo_wr_ptr_plus1_rxclk = rxfifo_wr_ptr_rxclk + 1; | |
133 | ||
134 | ||
135 | wire [4:0] rxfifo_empty_space = (rxfifo_wr_ptr_rxclk[4] == rxfifo_rd_ptr_rxclk[4]) ? | |
136 | 16 - ({1'b0,rxfifo_wr_ptr_rxclk[3:0]} - {1'b0,rxfifo_rd_ptr_rxclk[3:0]}): | |
137 | ({1'b0,rxfifo_rd_ptr_rxclk[3:0]} - {1'b0,rxfifo_wr_ptr_rxclk[3:0]}); | |
138 | ||
139 | //wire [4:0] rxfifo_full_space = (rxfifo_wr_ptr_rxclk[4] == rxfifo_rd_ptr_rxclk[4]) ? | |
140 | // ({1'b0,rxfifo_wr_ptr_rxclk[3:0]} - {1'b0,rxfifo_rd_ptr_rxclk[3:0]}): | |
141 | // 16 - ({1'b0,rxfifo_rd_ptr_rxclk[3:0]} - {1'b0,rxfifo_wr_ptr_rxclk[3:0]}); | |
142 | ||
143 | wire rxfifo_full_rxclk = (rxfifo_wr_ptr_rxclk[4] == (!rxfifo_rd_ptr_rxclk[4])) && | |
144 | (rxfifo_wr_ptr_rxclk[3:0] == rxfifo_rd_ptr_rxclk[3:0]); | |
145 | ||
146 | // almost full | |
147 | //wire rxfifo_afull_rxclk = (rxfifo_wr_ptr_plus1_rxclk[4] == (!rxfifo_rd_ptr_rxclk[4])) && | |
148 | // (rxfifo_wr_ptr_plus1_rxclk[3:0] == rxfifo_rd_ptr_rxclk[3:0]); | |
149 | ||
150 | wire rxfifo_afull_rxclk = rxfifo_empty_space < 3; // 2 empty space left | |
151 | ||
152 | wire rxfifo_empty_rxclk = (rxfifo_wr_ptr_rxclk[4:0] == rxfifo_rd_ptr_rxclk[4:0]); | |
153 | ||
154 | wire rxfifo_overrun_rxclk = rxfifo_afull_rxclk & rxfifo_wr_en; | |
155 | /* --------------- end of rxfifo pointer Management ----------------- */ | |
156 | ||
157 | //*********************************************** | |
158 | //***** Rxfifo and associated control logic ***** | |
159 | //*********************************************** | |
160 | ||
161 | rxfifo_memory_model rxfifo_memory_model( | |
162 | .rx_clk(rx_clk), | |
163 | .reset(rx_reset), | |
164 | .wp(rxfifo_wr_ptr_rxclk[3:0]), | |
165 | .rp(rxfifo_rd_ptr_clk[3:0]), | |
166 | .we(rxfifo_wr_en), | |
167 | .din(rxfifo_din[65:0]), | |
168 | .dout(rxfifo_dout[65:0])); | |
169 | ||
170 | ||
171 | endmodule // rxfifo_load | |
172 | ||
173 | ||
174 | ||
175 | module rxfifo_memory_model (rx_clk,reset,wp,rp,we,din,dout); | |
176 | input rx_clk,reset; | |
177 | input [3:0] wp,rp; | |
178 | input we; | |
179 | input [65:0] din; | |
180 | output [65:0] dout; | |
181 | ||
182 | ||
183 | reg [65:0] rxfifo_mem [0:15]; // 65 bit wide 16 deep | |
184 | ||
185 | always @ (posedge rx_clk) | |
186 | begin | |
187 | if (reset) | |
188 | begin | |
189 | rxfifo_mem[0] <= 0; | |
190 | rxfifo_mem[1] <= 0; | |
191 | rxfifo_mem[2] <= 0; | |
192 | rxfifo_mem[3] <= 0; | |
193 | rxfifo_mem[4] <= 0; | |
194 | rxfifo_mem[5] <= 0; | |
195 | rxfifo_mem[6] <= 0; | |
196 | rxfifo_mem[7] <= 0; | |
197 | rxfifo_mem[8] <= 0; | |
198 | rxfifo_mem[9] <= 0; | |
199 | rxfifo_mem[10] <= 0; | |
200 | rxfifo_mem[11] <= 0; | |
201 | rxfifo_mem[12] <= 0; | |
202 | rxfifo_mem[13] <= 0; | |
203 | rxfifo_mem[14] <= 0; | |
204 | rxfifo_mem[15] <= 0; | |
205 | end | |
206 | else | |
207 | begin | |
208 | case (we) // synopsys parallel_case full_case infer_mux | |
209 | 1'b1: rxfifo_mem[wp] <= din; | |
210 | 1'b0: rxfifo_mem[wp] <= rxfifo_mem[wp]; | |
211 | endcase // case(we) | |
212 | end | |
213 | end // always @ (posedge rx_clk) | |
214 | ||
215 | assign dout = rxfifo_mem[rp]; | |
216 | ||
217 | endmodule // rxfifo_memory_model | |
218 | ||
219 | ||
220 |