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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / design / sys / iop / niu / rtl / sphy_dpath2.v
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AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: sphy_dpath2.v
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35/*%W% %G%*/
36
37/*****************************************************************
38 *
39 * File Name : sphy_dpath2
40 * Author Name : John Lo
41 * Description : mac to serdes physical data path (sphy_dpath).
42 * TI recommended to use channel 1 tx clk for 10G.
43 * Due to atca_GE, channel 0 esr_mac_tclk_0,1 is used.
44 *
45 * This module is intended to be place right on top of
46 * XAUI serdes to help on closing timing when no source
47 * synchronous tx clock is available in 10G mode.
48 *
49 * sphy_dpath2 works closely with esr_ctl2, phy_clock_2ports.
50 * The phy_clock_2ports is clock path.
51 * The sphy_dpath2 is data path.
52 * The control path is esr_ctl2.
53 * When doing changes/modifications make sure
54 * phy_clock_2ports , sphy_dpath2 and esr_ctl2 are in sync.
55 *
56 * Parent Module: mac
57 * Child Module: none
58 * Interface Mod:
59 * Date Created : 10/04/01
60 *
61 * Copyright (c) 2020, Sun Microsystems, Inc.
62 * Sun Proprietary and Confidential
63 *
64 * Modification :
65 *
66 * Synthesis Notes:
67 *
68 *****************************************************************/
69
70`include "xmac.h"
71
72module sphy_dpath2(
73blunt_end_loopback,
74tcu_scan_en,
75// ---- port 0 serdes 0
76xgmii_mode0,
77// tx side signals
78tx_nbclk0,
79tx_clk_312mhz0,
80xtx_code_group0,
81tx_code_group0,
82mac_esr_txd0_0,
83mac_esr_txd1_0,
84mac_esr_txd2_0,
85mac_esr_txd3_0,
86// rx side signals
87rbc0_a0,
88rbc0_b0,
89rbc0_c0,
90rbc0_d0,
91rx_nbclk0,
92esr_mac_rxd0_0,
93esr_mac_rxd1_0,
94esr_mac_rxd2_0,
95esr_mac_rxd3_0,
96esr_mac_oddcg0_0,
97odd_rx0,
98xrx_code_group0,
99rx_code_group0,
100// ---- port 1 serdes 1
101xgmii_mode1,
102// tx side signals
103tx_nbclk1,
104tx_clk_312mhz1,
105xtx_code_group1,
106tx_code_group1,
107mac_esr_txd0_1,
108mac_esr_txd1_1,
109mac_esr_txd2_1,
110mac_esr_txd3_1,
111// rx side signals
112rbc0_a1,
113rbc0_b1,
114rbc0_c1,
115rbc0_d1,
116rx_nbclk1,
117esr_mac_rxd0_1,
118esr_mac_rxd1_1,
119esr_mac_rxd2_1,
120esr_mac_rxd3_1,
121esr_mac_oddcg0_1,
122odd_rx1,
123xrx_code_group1,
124rx_code_group1
125 );
126
127 input blunt_end_loopback;
128 input tcu_scan_en;
129 // ----- port 0 serdes 0
130 input xgmii_mode0;
131 // tx side signals
132 input tx_nbclk0;
133 input tx_clk_312mhz0;
134 input [39:0] xtx_code_group0;
135 input [9:0] tx_code_group0;
136 output [9:0] mac_esr_txd0_0;
137 output [9:0] mac_esr_txd1_0;
138 output [9:0] mac_esr_txd2_0;
139 output [9:0] mac_esr_txd3_0;
140 // rx side signals
141 input rbc0_a0;
142 input rbc0_b0;
143 input rbc0_c0;
144 input rbc0_d0;
145 input rx_nbclk0;
146 input [9:0] esr_mac_rxd0_0;
147 input [9:0] esr_mac_rxd1_0;
148 input [9:0] esr_mac_rxd2_0;
149 input [9:0] esr_mac_rxd3_0;
150 input esr_mac_oddcg0_0;
151 output odd_rx0;
152 output [39:0] xrx_code_group0;
153 output [9:0] rx_code_group0;
154 // ----- port 1 serdes 1
155 input xgmii_mode1;
156 // tx side signals
157 input tx_nbclk1;
158 input tx_clk_312mhz1;
159 input [39:0] xtx_code_group1;
160 input [9:0] tx_code_group1;
161 output [9:0] mac_esr_txd0_1;
162 output [9:0] mac_esr_txd1_1;
163 output [9:0] mac_esr_txd2_1;
164 output [9:0] mac_esr_txd3_1;
165 // rx side signals
166 input rbc0_a1;
167 input rbc0_b1;
168 input rbc0_c1;
169 input rbc0_d1;
170 input rx_nbclk1;
171 input [9:0] esr_mac_rxd0_1;
172 input [9:0] esr_mac_rxd1_1;
173 input [9:0] esr_mac_rxd2_1;
174 input [9:0] esr_mac_rxd3_1;
175 input esr_mac_oddcg0_1;
176 output odd_rx1;
177 output [39:0] xrx_code_group1;
178 output [9:0] rx_code_group1;
179
180 // ----- port 0 serdes 0
181 wire xgmii_mode0;
182 wire tx_clk_312mhz0;
183 // tx side signals
184 wire [39:0] xtx_code_group0;
185 wire [39:0] xtx_code_group_reg0;
186 wire [39:0] xtx_code_group_reg_latch0;
187 wire [9:0] tx_code_group_latch0;
188 wire [9:0] tx_code_group0;
189 wire [9:0] mac_esr_txd0_0;
190 wire [9:0] mac_esr_txd1_0;
191 wire [9:0] mac_esr_txd2_0;
192 wire [9:0] mac_esr_txd3_0;
193 wire [9:0] mac_esr_txd0_0_p1;
194 wire [9:0] mac_esr_txd1_0_p1;
195 wire [9:0] mac_esr_txd2_0_p1;
196 wire [9:0] mac_esr_txd3_0_p1;
197 // rx side signals
198 wire [9:0] esr_mac_rxd0_0;
199 wire [9:0] esr_mac_rxd1_0;
200 wire [9:0] esr_mac_rxd2_0;
201 wire [9:0] esr_mac_rxd3_0;
202 wire [9:0] esr_mac_rxd0_0_swap;
203 wire [9:0] esr_mac_rxd1_0_swap;
204 wire [9:0] esr_mac_rxd2_0_swap;
205 wire [9:0] esr_mac_rxd3_0_swap;
206 wire [9:0] esr_mac_rxd0_0_blunt;
207 wire [9:0] esr_mac_rxd1_0_blunt;
208 wire [9:0] esr_mac_rxd2_0_blunt;
209 wire [9:0] esr_mac_rxd3_0_blunt;
210 wire [39:0] xrx_code_group0;
211 wire [9:0] rx_code_group0;
212 // ----- port 1 serdes 1
213 wire xgmii_mode1;
214 wire tx_clk_312mhz1;
215 // tx side signals
216 wire [39:0] xtx_code_group1;
217 wire [39:0] xtx_code_group_reg1;
218 wire [39:0] xtx_code_group_reg_latch1;
219 wire [9:0] tx_code_group1;
220 wire [9:0] tx_code_group_latch1;
221 wire [9:0] mac_esr_txd0_1;
222 wire [9:0] mac_esr_txd1_1;
223 wire [9:0] mac_esr_txd2_1;
224 wire [9:0] mac_esr_txd3_1;
225 wire [9:0] mac_esr_txd0_1_p1;
226 wire [9:0] mac_esr_txd1_1_p1;
227 wire [9:0] mac_esr_txd2_1_p1;
228 wire [9:0] mac_esr_txd3_1_p1;
229 // rx side signals
230 wire [9:0] esr_mac_rxd0_1;
231 wire [9:0] esr_mac_rxd1_1;
232 wire [9:0] esr_mac_rxd2_1;
233 wire [9:0] esr_mac_rxd3_1;
234 wire [9:0] esr_mac_rxd0_1_swap;
235 wire [9:0] esr_mac_rxd1_1_swap;
236 wire [9:0] esr_mac_rxd2_1_swap;
237 wire [9:0] esr_mac_rxd3_1_swap;
238 wire [9:0] esr_mac_rxd0_1_blunt;
239 wire [9:0] esr_mac_rxd1_1_blunt;
240 wire [9:0] esr_mac_rxd2_1_blunt;
241 wire [9:0] esr_mac_rxd3_1_blunt;
242 wire [39:0] xrx_code_group1;
243 wire [9:0] rx_code_group1;
244
245/***********************************************
246 * port 0
247 ***********************************************/
248/* ------------ transmit path ------------- */
249RegDff #(40) xtx_code_group_reg0_RegDff (.din(xtx_code_group0[39:0]),.clk(tx_clk_312mhz0),.qout(xtx_code_group_reg0[39:0]));
250
251n2_txd_blatch port0_n2_txd_blatch
252 (
253 // Outputs
254 .xtx_code_group_reg_latch (xtx_code_group_reg_latch0[39:0]),
255 .tx_code_group_latch (tx_code_group_latch0[9:0]),
256 // Inputs
257 .tx_nbclk (tx_nbclk0),
258 .tx_clk_312mhz (tx_clk_312mhz0),
259 .xtx_code_group_reg (xtx_code_group_reg0[39:0]),
260 .tx_code_group (tx_code_group0[9:0]));
261
262 // 1G uses ch0 since mac_esr_tclk_0 is from ch0.
263xMUX_2to1 #(10) mac_esr_txd0_0_p1_xMUX_2to1(.din0(tx_code_group_latch0[9:0]),.din1(xtx_code_group_reg_latch0[9:0]),.sel(xgmii_mode0),.dout(mac_esr_txd0_0_p1));
264 assign mac_esr_txd1_0_p1 = xtx_code_group_reg_latch0[19:10];
265 assign mac_esr_txd2_0_p1 = xtx_code_group_reg_latch0[29:20];
266 assign mac_esr_txd3_0_p1 = xtx_code_group_reg_latch0[39:30];
267
268// Final txd assembly and swapping
269xMUX_2to1 #(10) mac_esr_txd0_0_xMUX (.din0(mac_esr_txd0_0_p1),
270 .din1(esr_mac_rxd0_0_blunt),
271 .sel(blunt_end_loopback),
272 .dout({mac_esr_txd0_0[0],
273 mac_esr_txd0_0[1],
274 mac_esr_txd0_0[2],
275 mac_esr_txd0_0[3],
276 mac_esr_txd0_0[4],
277 mac_esr_txd0_0[5],
278 mac_esr_txd0_0[6],
279 mac_esr_txd0_0[7],
280 mac_esr_txd0_0[8],
281 mac_esr_txd0_0[9]}));
282xMUX_2to1 #(10) mac_esr_txd1_0_xMUX (.din0(mac_esr_txd1_0_p1),
283 .din1(esr_mac_rxd1_0_blunt),
284 .sel(blunt_end_loopback),
285 .dout({mac_esr_txd1_0[0],
286 mac_esr_txd1_0[1],
287 mac_esr_txd1_0[2],
288 mac_esr_txd1_0[3],
289 mac_esr_txd1_0[4],
290 mac_esr_txd1_0[5],
291 mac_esr_txd1_0[6],
292 mac_esr_txd1_0[7],
293 mac_esr_txd1_0[8],
294 mac_esr_txd1_0[9]}));
295xMUX_2to1 #(10) mac_esr_txd2_0_xMUX (.din0(mac_esr_txd2_0_p1),
296 .din1(esr_mac_rxd2_0_blunt),
297 .sel(blunt_end_loopback),
298 .dout({mac_esr_txd2_0[0],
299 mac_esr_txd2_0[1],
300 mac_esr_txd2_0[2],
301 mac_esr_txd2_0[3],
302 mac_esr_txd2_0[4],
303 mac_esr_txd2_0[5],
304 mac_esr_txd2_0[6],
305 mac_esr_txd2_0[7],
306 mac_esr_txd2_0[8],
307 mac_esr_txd2_0[9]}));
308
309xMUX_2to1 #(10) mac_esr_txd3_0_xMUX (.din0(mac_esr_txd3_0_p1),
310 .din1(esr_mac_rxd3_0_blunt),
311 .sel(blunt_end_loopback),
312 .dout({mac_esr_txd3_0[0],
313 mac_esr_txd3_0[1],
314 mac_esr_txd3_0[2],
315 mac_esr_txd3_0[3],
316 mac_esr_txd3_0[4],
317 mac_esr_txd3_0[5],
318 mac_esr_txd3_0[6],
319 mac_esr_txd3_0[7],
320 mac_esr_txd3_0[8],
321 mac_esr_txd3_0[9]}));
322
323/* ------------ receive path ------------- */
324 /* ----- start swapping ----- */
325 assign esr_mac_rxd0_0_swap = {esr_mac_rxd0_0[0],
326 esr_mac_rxd0_0[1],
327 esr_mac_rxd0_0[2],
328 esr_mac_rxd0_0[3],
329 esr_mac_rxd0_0[4],
330 esr_mac_rxd0_0[5],
331 esr_mac_rxd0_0[6],
332 esr_mac_rxd0_0[7],
333 esr_mac_rxd0_0[8],
334 esr_mac_rxd0_0[9]};
335
336 assign esr_mac_rxd1_0_swap = {esr_mac_rxd1_0[0],
337 esr_mac_rxd1_0[1],
338 esr_mac_rxd1_0[2],
339 esr_mac_rxd1_0[3],
340 esr_mac_rxd1_0[4],
341 esr_mac_rxd1_0[5],
342 esr_mac_rxd1_0[6],
343 esr_mac_rxd1_0[7],
344 esr_mac_rxd1_0[8],
345 esr_mac_rxd1_0[9]};
346
347 assign esr_mac_rxd2_0_swap = {esr_mac_rxd2_0[0],
348 esr_mac_rxd2_0[1],
349 esr_mac_rxd2_0[2],
350 esr_mac_rxd2_0[3],
351 esr_mac_rxd2_0[4],
352 esr_mac_rxd2_0[5],
353 esr_mac_rxd2_0[6],
354 esr_mac_rxd2_0[7],
355 esr_mac_rxd2_0[8],
356 esr_mac_rxd2_0[9]};
357
358 assign esr_mac_rxd3_0_swap = {esr_mac_rxd3_0[0],
359 esr_mac_rxd3_0[1],
360 esr_mac_rxd3_0[2],
361 esr_mac_rxd3_0[3],
362 esr_mac_rxd3_0[4],
363 esr_mac_rxd3_0[5],
364 esr_mac_rxd3_0[6],
365 esr_mac_rxd3_0[7],
366 esr_mac_rxd3_0[8],
367 esr_mac_rxd3_0[9]};
368 /* ----- end of swapping ---- */
369
370
371// assign xrx_code_group0= {esr_mac_rxd3_0_swap[9:0], // 10G
372// esr_mac_rxd2_0_swap[9:0],
373// esr_mac_rxd1_0_swap[9:0],
374// esr_mac_rxd0_0_swap[9:0]};
375//
376// // ch0 is used for 1G
377// assign rx_code_group0 = esr_mac_rxd0_0_swap[9:0]; // 1G, ch0
378
379n2_rxd_alatch port0_n2_rxd_alatch
380 (
381 // Outputs
382 .xrx_code_group (xrx_code_group0[39:0]),
383 .rx_code_group (rx_code_group0[9:0]),
384 // Inputs
385 .tcu_scan_en (tcu_scan_en),
386 .rx_nbclk (rx_nbclk0),
387 .rbc0_d (rbc0_d0),
388 .rbc0_c (rbc0_c0),
389 .rbc0_b (rbc0_b0),
390 .rbc0_a (rbc0_a0),
391 .esr_mac_rxd ({esr_mac_rxd3_0_swap[9:0],
392 esr_mac_rxd2_0_swap[9:0],
393 esr_mac_rxd1_0_swap[9:0],
394 esr_mac_rxd0_0_swap[9:0]}));
395
396// per Carlos's and Jeff's request on fixing 1G hold time violation 6-12-06
397RegDff #(1) odd_rx0_RegDff (.din(esr_mac_oddcg0_0),.clk(~rx_nbclk0),.qout(odd_rx0));
398
399// 10G blunt loopback path
400RegDff #(10) esr_mac_rxd0_0_blunt_RegDff (.din(xrx_code_group0[9:0]), .clk(rbc0_a0),.qout(esr_mac_rxd0_0_blunt[9:0]));
401RegDff #(10) esr_mac_rxd1_0_blunt_RegDff (.din(xrx_code_group0[19:10]),.clk(rbc0_b0),.qout(esr_mac_rxd1_0_blunt[9:0]));
402RegDff #(10) esr_mac_rxd2_0_blunt_RegDff (.din(xrx_code_group0[29:20]),.clk(rbc0_c0),.qout(esr_mac_rxd2_0_blunt[9:0]));
403RegDff #(10) esr_mac_rxd3_0_blunt_RegDff (.din(xrx_code_group0[39:30]),.clk(rbc0_d0),.qout(esr_mac_rxd3_0_blunt[9:0]));
404
405/***********************************************
406 * port 1
407 ***********************************************/
408/* ------------ transmit path ------------- */
409RegDff #(40) xtx_code_group_reg1_RegDff (.din(xtx_code_group1[39:0]),.clk(tx_clk_312mhz1),.qout(xtx_code_group_reg1[39:0]));
410
411n2_txd_blatch port1_n2_txd_blatch
412 (
413 // Outputs
414 .xtx_code_group_reg_latch (xtx_code_group_reg_latch1[39:0]),
415 .tx_code_group_latch (tx_code_group_latch1[9:0]),
416 // Inputs
417 .tx_nbclk (tx_nbclk1),
418 .tx_clk_312mhz (tx_clk_312mhz1),
419 .xtx_code_group_reg (xtx_code_group_reg1[39:0]),
420 .tx_code_group (tx_code_group1[9:0]));
421
422 // 1G uses ch0 since mac_esr_tclk_0 is from ch0.
423xMUX_2to1 #(10) mac_esr_txd0_1_p1_xMUX_2to1(.din0(tx_code_group_latch1[9:0]),.din1(xtx_code_group_reg_latch1[9:0]),.sel(xgmii_mode1),.dout(mac_esr_txd0_1_p1));
424 assign mac_esr_txd1_1_p1 = xtx_code_group_reg_latch1[19:10];
425 assign mac_esr_txd2_1_p1 = xtx_code_group_reg_latch1[29:20];
426 assign mac_esr_txd3_1_p1 = xtx_code_group_reg_latch1[39:30];
427
428// Final txd assembly and swapping
429xMUX_2to1 #(10) mac_esr_txd0_1_xMUX (.din0(mac_esr_txd0_1_p1),
430 .din1(esr_mac_rxd0_1_blunt),
431 .sel(blunt_end_loopback),
432 .dout({mac_esr_txd0_1[0],
433 mac_esr_txd0_1[1],
434 mac_esr_txd0_1[2],
435 mac_esr_txd0_1[3],
436 mac_esr_txd0_1[4],
437 mac_esr_txd0_1[5],
438 mac_esr_txd0_1[6],
439 mac_esr_txd0_1[7],
440 mac_esr_txd0_1[8],
441 mac_esr_txd0_1[9]}));
442xMUX_2to1 #(10) mac_esr_txd1_1_xMUX (.din0(mac_esr_txd1_1_p1),
443 .din1(esr_mac_rxd1_1_blunt),
444 .sel(blunt_end_loopback),
445 .dout({mac_esr_txd1_1[0],
446 mac_esr_txd1_1[1],
447 mac_esr_txd1_1[2],
448 mac_esr_txd1_1[3],
449 mac_esr_txd1_1[4],
450 mac_esr_txd1_1[5],
451 mac_esr_txd1_1[6],
452 mac_esr_txd1_1[7],
453 mac_esr_txd1_1[8],
454 mac_esr_txd1_1[9]}));
455xMUX_2to1 #(10) mac_esr_txd2_1_xMUX (.din0(mac_esr_txd2_1_p1),
456 .din1(esr_mac_rxd2_1_blunt),
457 .sel(blunt_end_loopback),
458 .dout({mac_esr_txd2_1[0],
459 mac_esr_txd2_1[1],
460 mac_esr_txd2_1[2],
461 mac_esr_txd2_1[3],
462 mac_esr_txd2_1[4],
463 mac_esr_txd2_1[5],
464 mac_esr_txd2_1[6],
465 mac_esr_txd2_1[7],
466 mac_esr_txd2_1[8],
467 mac_esr_txd2_1[9]}));
468
469xMUX_2to1 #(10) mac_esr_txd3_1_xMUX (.din0(mac_esr_txd3_1_p1),
470 .din1(esr_mac_rxd3_1_blunt),
471 .sel(blunt_end_loopback),
472 .dout({mac_esr_txd3_1[0],
473 mac_esr_txd3_1[1],
474 mac_esr_txd3_1[2],
475 mac_esr_txd3_1[3],
476 mac_esr_txd3_1[4],
477 mac_esr_txd3_1[5],
478 mac_esr_txd3_1[6],
479 mac_esr_txd3_1[7],
480 mac_esr_txd3_1[8],
481 mac_esr_txd3_1[9]}));
482
483/* ------------ receive path ------------- */
484 /* ----- start swapping ----- */
485 assign esr_mac_rxd0_1_swap = {esr_mac_rxd0_1[0],
486 esr_mac_rxd0_1[1],
487 esr_mac_rxd0_1[2],
488 esr_mac_rxd0_1[3],
489 esr_mac_rxd0_1[4],
490 esr_mac_rxd0_1[5],
491 esr_mac_rxd0_1[6],
492 esr_mac_rxd0_1[7],
493 esr_mac_rxd0_1[8],
494 esr_mac_rxd0_1[9]};
495
496 assign esr_mac_rxd1_1_swap = {esr_mac_rxd1_1[0],
497 esr_mac_rxd1_1[1],
498 esr_mac_rxd1_1[2],
499 esr_mac_rxd1_1[3],
500 esr_mac_rxd1_1[4],
501 esr_mac_rxd1_1[5],
502 esr_mac_rxd1_1[6],
503 esr_mac_rxd1_1[7],
504 esr_mac_rxd1_1[8],
505 esr_mac_rxd1_1[9]};
506
507 assign esr_mac_rxd2_1_swap = {esr_mac_rxd2_1[0],
508 esr_mac_rxd2_1[1],
509 esr_mac_rxd2_1[2],
510 esr_mac_rxd2_1[3],
511 esr_mac_rxd2_1[4],
512 esr_mac_rxd2_1[5],
513 esr_mac_rxd2_1[6],
514 esr_mac_rxd2_1[7],
515 esr_mac_rxd2_1[8],
516 esr_mac_rxd2_1[9]};
517
518 assign esr_mac_rxd3_1_swap = {esr_mac_rxd3_1[0],
519 esr_mac_rxd3_1[1],
520 esr_mac_rxd3_1[2],
521 esr_mac_rxd3_1[3],
522 esr_mac_rxd3_1[4],
523 esr_mac_rxd3_1[5],
524 esr_mac_rxd3_1[6],
525 esr_mac_rxd3_1[7],
526 esr_mac_rxd3_1[8],
527 esr_mac_rxd3_1[9]};
528 /* ----- end of swapping ---- */
529
530
531// assign xrx_code_group1= {esr_mac_rxd3_1_swap[9:0], // 10G
532// esr_mac_rxd2_1_swap[9:0],
533// esr_mac_rxd1_1_swap[9:0],
534// esr_mac_rxd0_1_swap[9:0]};
535//
536// // ch1 is used for 1G
537// assign rx_code_group1 = esr_mac_rxd0_1_swap[9:0]; // 1G, ch0
538
539n2_rxd_alatch port1_n2_rxd_alatch
540 (
541 // Outputs
542 .xrx_code_group (xrx_code_group1[39:0]),
543 .rx_code_group (rx_code_group1[9:0]),
544 // Inputs
545 .tcu_scan_en (tcu_scan_en),
546 .rx_nbclk (rx_nbclk1),
547 .rbc0_d (rbc0_d1),
548 .rbc0_c (rbc0_c1),
549 .rbc0_b (rbc0_b1),
550 .rbc0_a (rbc0_a1),
551 .esr_mac_rxd ({esr_mac_rxd3_1_swap[9:0],
552 esr_mac_rxd2_1_swap[9:0],
553 esr_mac_rxd1_1_swap[9:0],
554 esr_mac_rxd0_1_swap[9:0]}));
555
556// per Carlos's and Jeff's request on fixing 1G hold time violation 6-12-06
557RegDff #(1) odd_rx1_RegDff (.din(esr_mac_oddcg0_1),.clk(~rx_nbclk1),.qout(odd_rx1));
558
559// 10G blunt loopback path
560RegDff #(10) esr_mac_rxd0_1_blunt_RegDff (.din(xrx_code_group1[9:0]), .clk(rbc0_a1),.qout(esr_mac_rxd0_1_blunt[9:0]));
561RegDff #(10) esr_mac_rxd1_1_blunt_RegDff (.din(xrx_code_group1[19:10]),.clk(rbc0_b1),.qout(esr_mac_rxd1_1_blunt[9:0]));
562RegDff #(10) esr_mac_rxd2_1_blunt_RegDff (.din(xrx_code_group1[29:20]),.clk(rbc0_c1),.qout(esr_mac_rxd2_1_blunt[9:0]));
563RegDff #(10) esr_mac_rxd3_1_blunt_RegDff (.din(xrx_code_group1[39:30]),.clk(rbc0_d1),.qout(esr_mac_rxd3_1_blunt[9:0]));
564
565endmodule // sphy_dpath2
566
Full OpenSPARC design & verification tarball including full HDL.