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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: txfifo_unload.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | /*%W% %G%*/ | |
36 | ||
37 | /************************************************************************* | |
38 | * | |
39 | * File Name : txfifo_unload.v | |
40 | * Author Name : John Lo | |
41 | * Description : It contains txmac read pointer management logic and | |
42 | * associated control logic. | |
43 | * Parent Module: tx_xmac | |
44 | * Child Module: | |
45 | * Interface Mod: | |
46 | * Date Created : | |
47 | * | |
48 | * Copyright (c) 2002, Sun Microsystems, Inc. | |
49 | * Sun Proprietary and Confidential | |
50 | * | |
51 | * Modification : | |
52 | * | |
53 | * Synthesis Notes: | |
54 | * | |
55 | *************************************************************************/ | |
56 | ||
57 | module txfifo_unload ( | |
58 | tx_clk, | |
59 | tx_reset, | |
60 | txfifo_g_wr_ptr_sync, | |
61 | txfifo_rd_en, | |
62 | stfifo_rd_en, // stfifo read enable | |
63 | stfifo_g_wr_ptr_sync, | |
64 | // outputs | |
65 | // txfifo stuff | |
66 | txfifo_unload_rdy, | |
67 | txfifo_g_rd_ptr_txclk, // to xmac_sync.v | |
68 | txfifo_rd_ptr_txclk, | |
69 | txfifo_empty_txclk, | |
70 | txfifo_full_txclk, | |
71 | // stfifo stuff | |
72 | stfifo_g_rd_ptr_txclk, | |
73 | stfifo_rd_ptr_txclk, | |
74 | stfifo_empty_txclk, | |
75 | stfifo_underrun_txclk | |
76 | ); | |
77 | ||
78 | ||
79 | input tx_clk; | |
80 | input tx_reset; | |
81 | input [4:0] txfifo_g_wr_ptr_sync; | |
82 | input txfifo_rd_en; | |
83 | input stfifo_rd_en; | |
84 | input [4:0] stfifo_g_wr_ptr_sync; | |
85 | // outputs | |
86 | output txfifo_unload_rdy; | |
87 | output [4:0] txfifo_g_rd_ptr_txclk; | |
88 | output [4:0] txfifo_rd_ptr_txclk; | |
89 | output txfifo_empty_txclk; | |
90 | output txfifo_full_txclk; | |
91 | // stfifo stuff | |
92 | output [4:0] stfifo_g_rd_ptr_txclk; | |
93 | output [4:0] stfifo_rd_ptr_txclk; | |
94 | output stfifo_empty_txclk; | |
95 | output stfifo_underrun_txclk; | |
96 | ||
97 | wire stfifo_empty_txclk,stfifo_underrun_txclk; | |
98 | ||
99 | ||
100 | /* --------------- start txfifo pointer Management ------------------ */ | |
101 | wire [4:0] txfifo_g_rd_ptr_txclk; | |
102 | wire [4:0] txfifo_rd_ptr_txclk; | |
103 | wire [4:0] txfifo_wr_ptr_txclk; | |
104 | ||
105 | // Txfifo G read Pointer, g_wr_ptr to sysclk | |
106 | g_cntr_5bit txfifo_g_rd_ptr_txclk_g_cntr_5bit( | |
107 | .reset(tx_reset), | |
108 | .clk(tx_clk), | |
109 | .ce(txfifo_rd_en), | |
110 | .g_cnt(txfifo_g_rd_ptr_txclk)); | |
111 | ||
112 | // Txfifo read Pointer | |
113 | counter_X5 txfifo_rd_ptr_txclk_counter_X5(.clk(tx_clk),.clr(tx_reset),.enable(txfifo_rd_en),.count(txfifo_rd_ptr_txclk)); | |
114 | ||
115 | // Txfifo write Pointer, wr_ptr from clk | |
116 | g2b_5bit txfifo_wr_ptr_txclk_g2b_5bit(.g_cnt(txfifo_g_wr_ptr_sync), | |
117 | .b_cnt(txfifo_wr_ptr_txclk)); | |
118 | ||
119 | ||
120 | wire txfifo_full_txclk = | |
121 | (txfifo_wr_ptr_txclk[4] == (!txfifo_rd_ptr_txclk[4])) && | |
122 | (txfifo_wr_ptr_txclk[3:0] == txfifo_rd_ptr_txclk[3:0]) ; | |
123 | ||
124 | wire txfifo_empty_txclk = | |
125 | (txfifo_wr_ptr_txclk[4:0] == txfifo_rd_ptr_txclk[4:0]); | |
126 | ||
127 | // The following condition will never happen since xtlm_sm will | |
128 | // not assert txfifo_rd_en when txfifo_empty_txclk == 1. | |
129 | // Instead the txfifo_underrun_txclk is generated by xtlm_sm. | |
130 | // wire txfifo_underrun_txclk = txfifo_rd_en & txfifo_empty_txclk; | |
131 | ||
132 | // vlint flag_net_has_no_load off | |
133 | // vlint flag_dangling_net_within_module off | |
134 | wire [4:0] txfifo_empty_space_txclk = | |
135 | (txfifo_wr_ptr_txclk[4] == txfifo_rd_ptr_txclk[4]) ? | |
136 | 16 - ({1'b0,txfifo_wr_ptr_txclk[3:0]} - {1'b0,txfifo_rd_ptr_txclk[3:0]}): | |
137 | ({1'b0,txfifo_rd_ptr_txclk[3:0]} - {1'b0,txfifo_wr_ptr_txclk[3:0]}); | |
138 | // vlint flag_dangling_net_within_module on | |
139 | // vlint flag_net_has_no_load on | |
140 | ||
141 | // wire [4:0] txfifo_full_space_txclk = 16 - txfifo_empty_space_txclk; | |
142 | wire [4:0] txfifo_full_space_txclk = | |
143 | (txfifo_wr_ptr_txclk[4] == txfifo_rd_ptr_txclk[4]) ? | |
144 | ({1'b0,txfifo_wr_ptr_txclk[3:0]} - {1'b0,txfifo_rd_ptr_txclk[3:0]}): | |
145 | 16 - ({1'b0,txfifo_rd_ptr_txclk[3:0]} - {1'b0,txfifo_wr_ptr_txclk[3:0]}); | |
146 | ||
147 | // It is necessary to have TXFIFO_UNLOAD_THRESHOLD value so that | |
148 | // txfifo won't pre-maturely dry out | |
149 | parameter TXFIFO_UNLOAD_THRESHOLD = 5'h02; | |
150 | wire txfifo_reach_threshold = | |
151 | txfifo_full_space_txclk > TXFIFO_UNLOAD_THRESHOLD; | |
152 | wire txfifo_unload_rdy = txfifo_reach_threshold | | |
153 | (~stfifo_empty_txclk); | |
154 | ||
155 | // wire txfifo_unload_rdy = ~txfifo_empty_txclk; | |
156 | ||
157 | /* --------------- end of txfifo pointer Management ----------------- */ | |
158 | ||
159 | /* --------------- start stfifo pointer Management ------------------ */ | |
160 | // stfifo G read Pointer g_rd_ptr to sysclk | |
161 | wire [4:0] stfifo_g_rd_ptr_txclk; | |
162 | wire [4:0] stfifo_rd_ptr_txclk; | |
163 | wire [4:0] stfifo_wr_ptr_txclk; | |
164 | ||
165 | g_cntr_5bit stfifo_g_rd_ptr_txclk_g_cntr_5bit( | |
166 | .reset(tx_reset), | |
167 | .clk(tx_clk), | |
168 | .ce(stfifo_rd_en), | |
169 | .g_cnt(stfifo_g_rd_ptr_txclk)); | |
170 | ||
171 | // stfifo Read Pointer | |
172 | counter_X5 stfifo_rd_ptr_txclk_counter_X5(.clk(tx_clk),.clr(tx_reset),.enable(stfifo_rd_en),.count(stfifo_rd_ptr_txclk)); | |
173 | ||
174 | // synopsys translate_off | |
175 | // diag | |
176 | wire [4:0] txfifo_rd_ptr_txclk_from_g2b; | |
177 | wire [4:0] stfifo_rd_ptr_txclk_from_g2b; | |
178 | reg txfifo_rd_ptr_err; | |
179 | reg stfifo_rd_ptr_err; | |
180 | ||
181 | g2b_5bit txfifo_g2b_5bit(.g_cnt(txfifo_g_rd_ptr_txclk),.b_cnt(txfifo_rd_ptr_txclk_from_g2b)); | |
182 | g2b_5bit stfifo_g2b_5bit(.g_cnt(stfifo_g_rd_ptr_txclk),.b_cnt(stfifo_rd_ptr_txclk_from_g2b)); | |
183 | always @ (posedge tx_clk) | |
184 | begin | |
185 | txfifo_rd_ptr_err <= txfifo_rd_ptr_txclk_from_g2b != txfifo_rd_ptr_txclk; | |
186 | stfifo_rd_ptr_err <= stfifo_rd_ptr_txclk_from_g2b != stfifo_rd_ptr_txclk; | |
187 | end | |
188 | ||
189 | always @ (txfifo_rd_ptr_err or stfifo_rd_ptr_err) | |
190 | if (~tx_reset) | |
191 | $display("\n (* ERROR: at sim time = %d,txfifo_rd_ptr_err = %b,stfifo_rd_ptr_err = %b *) \n",$time,txfifo_rd_ptr_err,stfifo_rd_ptr_err); | |
192 | else ; | |
193 | // synopsys translate_on | |
194 | ||
195 | ||
196 | // stfifo Write Pointer | |
197 | g2b_5bit stfifo_wr_ptr_txclk_g2b_5bit(.g_cnt(stfifo_g_wr_ptr_sync), | |
198 | .b_cnt(stfifo_wr_ptr_txclk)); | |
199 | ||
200 | assign stfifo_empty_txclk = | |
201 | (stfifo_wr_ptr_txclk[4:0] == stfifo_rd_ptr_txclk[4:0]); | |
202 | ||
203 | assign stfifo_underrun_txclk = stfifo_empty_txclk & stfifo_rd_en; | |
204 | ||
205 | /* --------------- end of stfifo pointer pointer Management --------- */ | |
206 | ||
207 | ||
208 | endmodule // txfifo_unload | |
209 | ||
210 | ||
211 | ||
212 | ||
213 | ||
214 | ||
215 | ||
216 |