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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / design / sys / iop / niu / rtl / xmac.v
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86530b38
AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: xmac.v
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
19// along with this program; if not, write to the Free Software
20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
23// choice is available it will apply instead, Sun elects to use only
24// the General Public License version 2 (GPLv2) at this time for any
25// software where a choice of GPL license versions is made
26// available with the language indicating that GPLv2 or any later version
27// may be used, or where a choice of which version of the GPL is applied is
28// otherwise unspecified.
29//
30// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
31// CA 95054 USA or visit www.sun.com if you need additional information or
32// have any questions.
33//
34// ========== Copyright Header End ============================================
35/*%W% %G%*/
36
37/***************************************************************
38 *
39 * File Name : xmac
40 * Author Name : John Lo
41 * Description : xmac main logic except xmac_clk_mux.
42 * Parent Module: xmac
43 * Child Module: many
44 * Interface Mod: many.
45 * Date Created : 5/9/00
46 *
47 * Copyright (c) 2008, Sun Microsystems, Inc.
48 * Sun Proprietary and Confidential
49 *
50 * Features:
51 * ================
52 * 1. This is a pre-802.3ae standard design.
53 * 2. The RxMac can handle min IPG == 4 byte time.
54 * 3. Supports both 32 bit xgmii interface and
55 * 64 bit xpcs interface.
56 * 4. xmac 64bit xpcs interface can swap the S_I, S_D, I_S, and
57 * D_S to correct value.
58 * 5. xmac is designed such that the slowest DMA interface
59 * clock frequency can be the same as xgmii interface clock
60 * frequency.
61 * 6. rx_xmac logs the pre-amble data which can be used for
62 * inter-mac communication channel.
63 *
64 *
65 * Configuration:
66 * ================
67 * Use two ifdef variable to config the xmac.
68 * (check with xmac.h for detail)
69 * 1. XGMII_ONLY (10G only xmac)
70 * 2. ALT_ADDR_AND_HASH_FUNC
71 *
72 * Synthesis Notes:
73 * ================
74 * 1. tx_mii_gmii.v: 1st stage reg: change clock domain
75 * 2. rx_mii_gmii.v: 2nd stage reg: change clock domain
76 * 3. txmac to rxmac loopback path.
77 * 4. Special attenetion to PCS clock doubler timing.
78 * 5. (removed 01/10/02)
79 * 6. Each mac_clk_mux should be layed out in a small
80 * compact area and should be next to the corresponding
81 * mac port.
82 * 7. timing critical path
83 *
84 * Minmimum setup requirements:
85 * ============================
86 * 1. xMac requires two hardware resets with the duration
87 * of 400ns high and 400ns low. The first hw_reset is
88 * to reset the entire xmac and the second one to reset
89 * tx_heart_beat_timer and rx_heart_beat_timer.
90 *
91 * |- 400ns -|- 400ns -|- 400ns -|- 400ns -|- 400ns
92 * pio_core_reset _________ _________
93 * (hw_reset)_________| |_________| |_______
94 *
95 * 2. Program mac config register.
96 * 3. Program xif config register to enable tx_output_en.
97 *
98 * Modification :
99 * ==============
100 *
101 ***************************************************************/
102
103`include "xmac.h"
104
105module xmac (
106/* ------------- xmac clocks --------------------------------- */
107 clk,
108 tx_clk,
109 tx_nbclk,
110 rx_clk,
111 rx_nbclk,
112 sys_clk_count,
113 tx_heart_beat_timer,
114 rx_heart_beat_timer,
115/* ------------- shared MII/GMII Interface ------------------ */
116 gmii_rxd,
117 gmii_rx_dv,
118 gmii_rx_err,
119 gmii_txd,
120 gmii_tx_en,
121 gmii_tx_err,
122/* ------------- XGMII Interface ----------------------------- */
123 xgmii_rxc,
124 xgmii_rxd,
125 xgmii_txc,
126 xgmii_txd,
127/* ------------- XPCS Interface ------------------------------ */
128 xpcs_rxd, // internal 64 bit receive signals// data going onto xGMII
129 xpcs_rxc, // receive data valid, GMII interface
130 xpcs_txd, // internal 64 bit transmit signals // byte from MAC over GMII
131 xpcs_txc, // GMII transmit enable from Mac
132/* ------------- pio Interface ------------------------------- */
133 pio_core_reset, // becomes hw_reset
134 pio_core_sel, // sel mac
135 pio_ack,
136 pio_rd, // r/w
137 pio_addr, // address
138 pio_wr_data, // wr_data
139 pio_rd_data, // rd_data
140 pio_err,
141 txmac_interrupt,
142 rxmac_interrupt,
143 xmac_fc_interrupt,
144/* ------------- Tx DMA Interface ---------------------------- */
145 txmac_opp_req,
146 opp_txmac_ack,
147 opp_txmac_tag,
148 opp_txmac_data,
149 opp_txmac_stat,
150 opp_txmac_abort,
151/* ------------- Rx DMA Interface ---------------------------- */
152 ipp_rxmac_req,
153 rxmac_ipp_ack,
154 rxmac_ipp_tag,
155 rxmac_ipp_data,
156 rxmac_ipp_ctrl,
157 rxmac_ipp_stat,
158/* ------------- xmac_xpcs_clk_mux control signals ----------- */
159 sel_clk_25mhz,
160 loopback,
161 sel_por_clk_src,
162 mii_mode,
163 gmii_mode,
164 xgmii_mode,
165 pcs_bypass,
166 xpcs_bypass,
167/* ------------- led signals --------------------------------- */
168 force_LED_on,
169 led_polarity,
170 activity_led,
171/* ------------- PMD signals --------------------------------- */
172 MDINT,
173/* ------------- debug Interface ----------------------------- */
174 xmac_debug,
175 mac_debug_sel
176 );
177
178/* ------------- xmac clocks --------------------------------- */
179 input clk;
180 input tx_clk;
181 input tx_nbclk;
182 input rx_clk;
183 input rx_nbclk;
184 output [2:0] sys_clk_count;
185 output [3:0] tx_heart_beat_timer;
186 output [3:0] rx_heart_beat_timer;
187/* ------------- shared MII/GMII Interface ------------------ */
188 input gmii_rx_dv;
189 input [`BYTE] gmii_rxd;
190 input gmii_rx_err;
191 output gmii_tx_en;
192 output [`BYTE] gmii_txd;
193 output gmii_tx_err;
194/* ------------- XGMII Interface ----------------------------- */
195 input [3:0] xgmii_rxc;
196 input [31:0] xgmii_rxd;
197 output [3:0] xgmii_txc;
198 output [31:0] xgmii_txd;
199/* ------------- XPCS Interface ------------------------------ */
200 input [7:0] xpcs_rxc;
201 input [63:0] xpcs_rxd;
202 output [7:0] xpcs_txc;
203 output [63:0] xpcs_txd;
204/* ------------- pio Interface ------------------------------- */
205 input pio_core_reset; // becomes hw_reset
206 input pio_core_sel; // sel
207 output pio_ack;
208 input pio_rd; // r/w
209 input [8:0] pio_addr; // address
210 input [31:0] pio_wr_data; // wr_data
211 output [31:0] pio_rd_data; // rd_data
212 output pio_err;
213 output txmac_interrupt;
214 output rxmac_interrupt;
215 output xmac_fc_interrupt;
216/* ------------- Tx DMA Interface ---------------------------- */
217 output txmac_opp_req;
218 input opp_txmac_ack;
219 input opp_txmac_tag;
220 input [63:0] opp_txmac_data;
221 input [3:0] opp_txmac_stat;
222 input opp_txmac_abort;
223/* ------------- Rx DMA Interface ---------------------------- */
224 input ipp_rxmac_req;
225 output rxmac_ipp_ack;
226 output rxmac_ipp_tag;
227 output [63:0] rxmac_ipp_data; // {64bit data}
228 output rxmac_ipp_ctrl;
229 output [`TBITS] rxmac_ipp_stat; // {23bit data}
230/* ------------- xmac_clk_mux control signals ---------------- */
231 output sel_clk_25mhz;
232 output loopback;
233 output sel_por_clk_src;
234 output mii_mode;
235 output gmii_mode;
236 output xgmii_mode;
237 output pcs_bypass;
238 output xpcs_bypass;
239/* ------------- led signals --------------------------------- */
240 output force_LED_on;
241 output led_polarity;
242 output activity_led;
243/* ------------- PMD signals --------------------------------- */
244 input MDINT;
245/* ------------- debug Interface ----------------------------- */
246 output [31:0] xmac_debug;
247 output [2:0] mac_debug_sel;
248
249/*AUTOWIRE*/
250// Beginning of automatic wires (for undeclared instantiated-module outputs)
251wire B_eop_reg; // From tx_xmac of tx_xmac.v
252wire D_S_reg; // From rx_xmac of rx_xmac.v
253wire END_PKT_ERR_detected_a_at_modified_pkt_reg;// From rx_xmac of rx_xmac.v
254wire END_PKT_ERR_detected_b_at_modified_pkt_reg;// From rx_xmac of rx_xmac.v
255wire I_S_reg; // From rx_xmac of rx_xmac.v
256wire S_D_reg; // From rx_xmac of rx_xmac.v
257wire S_I_reg; // From rx_xmac of rx_xmac.v
258wire S_detected_reg; // From rx_xmac of rx_xmac.v
259wire T_E_detected_at_modified_pkt_reg;// From rx_xmac of rx_xmac.v
260wire abort_bit_reg; // From rx_xmac of rx_xmac.v
261wire adjust2crc_full_case_last_byte_position_is_3_or_7_reg;// From tx_xmac of tx_xmac.v
262wire [2:0] adjust2crc_full_case_last_byte_position_reg;// From tx_xmac of tx_xmac.v
263wire [15:0] alt_addr_comp_en; // From xmac_slv of xmac_slv.v
264wire always_no_crc; // From xmac_slv of xmac_slv.v
265wire back2back_reg; // From tx_xmac of tx_xmac.v
266wire back2back_swap_reg1; // From tx_xmac of tx_xmac.v
267wire clr_rx_reset_clk; // From xmac_sync of xmac_sync.v
268wire clr_tx_reset_clk; // From xmac_sync of xmac_sync.v
269wire code_viol_chk_dis; // From xmac_slv of xmac_slv.v
270wire crc_chk_dis; // From xmac_slv of xmac_slv.v
271wire crc_error_reg; // From rx_xmac of rx_xmac.v
272wire eop_txclk_reg0; // From tx_xmac of tx_xmac.v
273wire eop_w_fcs_reg0; // From tx_xmac of tx_xmac.v
274wire eop_w_fcs_reg1; // From tx_xmac of tx_xmac.v
275wire err_chk_dis; // From xmac_slv of xmac_slv.v
276wire force_ipg_done_lead_reg;// From tx_xmac of tx_xmac.v
277wire [2:0] full_case_last_byte_position_reg;// From tx_xmac of tx_xmac.v
278wire hw_reset; // From xmac_slv of xmac_slv.v
279wire hw_reset_rxnbclk; // From xmac_sync of xmac_sync.v
280wire hw_reset_txnbclk; // From xmac_sync of xmac_sync.v
281wire inc_align_err_count_sync;// From xmac_sync of xmac_sync.v
282wire inc_bcast_count; // From rx_xmac of rx_xmac.v
283wire inc_bcast_count_sync; // From xmac_sync of xmac_sync.v
284wire inc_code_viol_count; // From rx_xmac of rx_xmac.v
285wire inc_code_viol_count_sync;// From xmac_sync of xmac_sync.v
286wire inc_crc_err_count; // From rx_xmac of rx_xmac.v
287wire inc_crc_err_count_sync; // From xmac_sync of xmac_sync.v
288wire inc_histo_cntr1; // From rxfifo_unload of rxfifo_unload.v
289wire inc_histo_cntr2; // From rxfifo_unload of rxfifo_unload.v
290wire inc_histo_cntr3; // From rxfifo_unload of rxfifo_unload.v
291wire inc_histo_cntr4; // From rxfifo_unload of rxfifo_unload.v
292wire inc_histo_cntr5; // From rxfifo_unload of rxfifo_unload.v
293wire inc_histo_cntr6; // From rxfifo_unload of rxfifo_unload.v
294wire inc_histo_cntr7; // From rxfifo_unload of rxfifo_unload.v
295wire inc_link_fault_count; // From rx_xmac of rx_xmac.v
296wire inc_link_fault_count_sync;// From xmac_sync of xmac_sync.v
297wire inc_max_pkt_err_count; // From rx_xmac of rx_xmac.v
298wire inc_max_pkt_err_count_sync;// From xmac_sync of xmac_sync.v
299wire inc_mcast_count; // From rx_xmac of rx_xmac.v
300wire inc_mcast_count_sync; // From xmac_sync of xmac_sync.v
301wire inc_min_pkt_err_count; // From rx_xmac of rx_xmac.v
302wire inc_min_pkt_err_count_sync;// From xmac_sync of xmac_sync.v
303wire ipg_done_lead_temp_reg; // From tx_xmac of tx_xmac.v
304wire ipg_done_reg; // From tx_xmac of tx_xmac.v
305wire ipg_done_trail_temp_reg;// From tx_xmac of tx_xmac.v
306wire [2:0] ipg_value; // From xmac_slv of xmac_slv.v
307wire [`BYTE] ipg_value1; // From xmac_slv of xmac_slv.v
308wire kill_crc_reg; // From rx_xmac of rx_xmac.v
309wire kill_data_ready_reg; // From rx_xmac of rx_xmac.v
310wire lfs_disable; // From xmac_slv of xmac_slv.v
311wire lfs_disable_rxclk; // From xmac_sync of xmac_sync.v
312wire local_fault_oc_reg; // From rx_xmac of rx_xmac.v
313wire local_fault_oc_sync; // From xmac_sync of xmac_sync.v
314wire local_fault_oc_txclk; // From xmac_sync of xmac_sync.v
315wire mii_or_gmii_mode; // From xmac_slv of xmac_slv.v
316wire minus_4bytes_reg; // From tx_xmac of tx_xmac.v
317wire no_crc; // From txfifo_load of txfifo_load.v
318wire no_rx_min_pkt_size_chk; // From xmac_slv of xmac_slv.v
319wire no_tx_min_pkt_size_chk; // From xmac_slv of xmac_slv.v
320wire no_wasted_BW_reg; // From tx_xmac of tx_xmac.v
321wire pass_fc; // From xmac_slv of xmac_slv.v
322wire paused_state; // From tx_xmac of tx_xmac.v
323wire paused_state_sync; // From xmac_sync of xmac_sync.v
324wire promisc_all; // From xmac_slv of xmac_slv.v
325wire promisc_group; // From xmac_slv of xmac_slv.v
326wire remote_fault_oc_reg; // From rx_xmac of rx_xmac.v
327wire remote_fault_oc_sync; // From xmac_sync of xmac_sync.v
328wire remote_fault_oc_txclk; // From xmac_sync of xmac_sync.v
329wire replace_txd_time_reg; // From tx_xmac of tx_xmac.v
330wire reserve_multicast; // From xmac_slv of xmac_slv.v
331wire restart_ipg_timer_reg; // From tx_xmac of tx_xmac.v
332wire rx_data_valid_gmux_reg; // From rx_xmac of rx_xmac.v
333wire rx_data_valid_gmux_reg_clk;// From xmac_sync of xmac_sync.v
334wire rx_enable; // From xmac_slv of xmac_slv.v
335wire rx_enable_nbclk; // From xmac_sync of xmac_sync.v
336wire rx_enable_rxclk; // From xmac_sync of xmac_sync.v
337wire rx_err_reg; // From rx_xmac of rx_xmac.v
338wire rx_fc_pkt_ok; // From rx_xmac of rx_xmac.v
339wire rx_fc_pkt_ok_clk; // From xmac_sync of xmac_sync.v
340wire rx_fc_pkt_ok_txclk; // From xmac_sync of xmac_sync.v
341wire rx_good_pkt; // From rx_xmac of rx_xmac.v
342wire rx_good_pkt_sync; // From xmac_sync of xmac_sync.v
343wire rx_pause_en; // From xmac_slv of xmac_slv.v
344wire rx_reset; // From xmac_sync of xmac_sync.v
345wire rx_reset_clk; // From xmac_slv of xmac_slv.v
346wire rx_reset_nbclk; // From xmac_sync of xmac_sync.v
347wire [1:0] rx_sel_reg; // From rx_xmac of rx_xmac.v
348wire rxfifo_empty_clk_reg; // From rxfifo_unload of rxfifo_unload.v
349wire rxfifo_full_clk_reg; // From rxfifo_unload of rxfifo_unload.v
350wire rxfifo_full_nbclk; // From xmac_sync of xmac_sync.v
351wire rxfifo_full_rxclk_reg; // From rx_xmac of rx_xmac.v
352wire rxfifo_overrun_rxclk; // From rx_xmac of rx_xmac.v
353wire rxfifo_overrun_sync; // From xmac_sync of xmac_sync.v
354wire [4:0] rxfifo_rd_ptr_clk; // From rxfifo_unload of rxfifo_unload.v
355wire rxfifo_underrun_clk; // From rxfifo_unload of rxfifo_unload.v
356wire [4:0] rxfifo_wr_ptr_clk; // From rxfifo_unload of rxfifo_unload.v
357wire set_back2back_reg; // From tx_xmac of tx_xmac.v
358wire set_tx_pkt_ok; // From tx_xmac of tx_xmac.v
359wire set_tx_pkt_ok_sync; // From xmac_sync of xmac_sync.v
360wire stretch_1_more_clk_reg; // From tx_xmac of tx_xmac.v
361wire [2:0] stretch_bytes_reg; // From tx_xmac of tx_xmac.v
362wire [`BYTE] stretch_clks_reg; // From tx_xmac of tx_xmac.v
363wire [3:0] stretch_full_case_last_byte_position_reg;// From tx_xmac of tx_xmac.v
364wire stretch_mode; // From xmac_slv of xmac_slv.v
365wire toggle_rx_bcount; // From rx_xmac of rx_xmac.v
366wire toggle_rx_bcount_sync; // From xmac_sync of xmac_sync.v
367wire toggle_tx_bcount; // From tx_xmac of tx_xmac.v
368wire toggle_tx_bcount_sync; // From xmac_sync of xmac_sync.v
369wire toggle_txframe_count; // From tx_xmac of tx_xmac.v
370wire toggle_txframe_count_sync;// From xmac_sync of xmac_sync.v
371wire tx_abort_reg0; // From tx_xmac of tx_xmac.v
372wire tx_abort_reg1; // From tx_xmac of tx_xmac.v
373wire [7:0] tx_byte0_reg0; // From tx_xmac of tx_xmac.v
374wire tx_data_valid; // From tx_xmac of tx_xmac.v
375wire tx_data_valid_clk; // From xmac_sync of xmac_sync.v
376wire tx_enable; // From xmac_slv of xmac_slv.v
377wire tx_enable_txclk; // From xmac_sync of xmac_sync.v
378wire tx_err_image; // From tx_xmac of tx_xmac.v
379wire tx_max_pkt_size_err; // From tx_xmac of tx_xmac.v
380wire tx_max_pkt_size_err_sync;// From xmac_sync of xmac_sync.v
381wire tx_on_half_reg; // From tx_xmac of tx_xmac.v
382wire tx_on_reg; // From tx_xmac of tx_xmac.v
383wire tx_output_en; // From xmac_slv of xmac_slv.v
384wire tx_output_en_nbclk; // From xmac_sync of xmac_sync.v
385wire tx_output_en_txclk; // From xmac_sync of xmac_sync.v
386wire tx_reset; // From xmac_sync of xmac_sync.v
387wire tx_reset_clk; // From xmac_slv of xmac_slv.v
388wire tx_reset_nbclk; // From xmac_sync of xmac_sync.v
389wire tx_swap_reg; // From tx_xmac of tx_xmac.v
390wire txfifo_empty_clk_reg; // From txfifo_load of txfifo_load.v
391wire txfifo_full_clk_reg; // From txfifo_load of txfifo_load.v
392wire txfifo_overrun_clk; // From txfifo_load of txfifo_load.v
393wire [4:0] txfifo_rd_ptr_clk; // From txfifo_load of txfifo_load.v
394wire txfifo_underrun_sync; // From xmac_sync of xmac_sync.v
395wire txfifo_underrun_txclk; // From tx_xmac of tx_xmac.v
396wire [4:0] txfifo_wr_ptr_clk; // From txfifo_load of txfifo_load.v
397wire txfifo_xfr_err; // From tx_xmac of tx_xmac.v
398wire txfifo_xfr_err_sync; // From xmac_sync of xmac_sync.v
399wire var_min_ipg_en; // From xmac_slv of xmac_slv.v
400wire warning_msg_en; // From xmac_slv of xmac_slv.v
401wire xrlm_state; // From rx_xmac of rx_xmac.v
402// End of automatics
403
404// rxfifo_unload output wires
405 wire [65:0] rxfifo_dout; // {mac_ctrl_word,tag,64bit data}
406 wire [15:0] pause_time; // signal crossing different clock domain.
407// xmac_slv output wires
408 wire [4:0] stretch_ratio;
409 wire [2:0] stretch_constant;
410 wire [`BYTE] slot_time;
411 wire [9:0] tx_min_pkt_size;
412 wire [9:0] rx_min_pkt_size;
413 wire [13:0] max_pkt_size;
414 wire [47:0] mac_unique_addr;
415// xmac_sync output wires
416 // rxfifo stuff
417 wire [4:0] rxfifo_g_rd_ptr_clk;
418 wire [4:0] rxfifo_g_rd_ptr_sync; // to rx_clk domain
419 wire [4:0] rxfifo_g_wr_ptr_rxclk;
420 wire [4:0] rxfifo_g_wr_ptr_sync; // to clk domain
421 // srfifo stuff
422 wire [4:0] srfifo_rd_ptr_clk;
423 wire [4:0] srfifo_g_wr_ptr_rxclk;
424 wire [4:0] srfifo_g_wr_ptr_sync;
425 // txfifo stuff
426 wire [4:0] txfifo_g_rd_ptr_txclk;// from tx_clk domain
427 wire [4:0] txfifo_g_wr_ptr_clk; // from clk domain
428 wire [4:0] txfifo_g_rd_ptr_sync; // to tx_clk domain
429 wire [4:0] txfifo_g_wr_ptr_sync; // to clk domain
430 // stfifo stuff
431 wire [4:0] stfifo_g_rd_ptr_txclk;// from tx_clk domain
432 wire [4:0] stfifo_g_wr_ptr_clk; // from clk domain
433 wire [4:0] stfifo_g_rd_ptr_sync; // to clk domain
434 wire [4:0] stfifo_g_wr_ptr_sync; // to tx_clk domain
435
436// xpcs
437 wire [7:0] xpcs_rxc;
438 wire [63:0] xpcs_rxd;
439 wire [7:0] xpcs_txc;
440 wire [63:0] xpcs_txd;
441// tx_xmac output wires
442 wire [7:0] txc_image; // loopback path
443 wire [63:0] txd_image; // loopback path
444
445// internal signals
446 wire [63:0] rx_pa_data;
447 wire [1:0] lfs_state;
448 wire sop_state;
449 wire [2:0] xtlm_state;
450 wire [2:0] last_byte_position;
451 wire [65:0] txfifo_dout;
452 wire [63:0] hold_rxd;
453 wire [7:0] hold_rx_dv;
454 wire hold_rx_err;
455 wire [`BYTE] mgmii_txd;
456 wire mgmii_tx_en;
457 wire mgmii_tx_err;
458 wire [31:0] pio_rd_data;
459 wire [3:0] rx_heart_beat_timer;
460 wire [3:0] tx_heart_beat_timer;
461 wire [3:0] rx_heart_beat_timer_reg;
462 wire [3:0] tx_heart_beat_timer_reg;
463 wire mgrlm_state;
464 wire inc_align_err_count_nbclk;
465 // clock observation point signals
466 wire tx_clk_div2;
467 wire rx_clk_div2;
468 wire tx_nbclk_div2;
469 wire rx_nbclk_div2;
470
471 // start of ALT_ADDR_AND_HASH_FUNC specific signals
472 wire strip_crc;
473 wire addr_filter_en;
474 wire hash_filter_en;
475 wire [47:0] mac_alt_addr0;
476 wire [47:0] mac_alt_addr1;
477 wire [47:0] mac_alt_addr2;
478 wire [47:0] mac_alt_addr3;
479 wire [47:0] mac_alt_addr4;
480 wire [47:0] mac_alt_addr5;
481 wire [47:0] mac_alt_addr6;
482 wire [47:0] mac_alt_addr7;
483 wire [47:0] mac_alt_addr8;
484 wire [47:0] mac_alt_addr9;
485 wire [47:0] mac_alt_addr10;
486 wire [47:0] mac_alt_addr11;
487 wire [47:0] mac_alt_addr12;
488 wire [47:0] mac_alt_addr13;
489 wire [47:0] mac_alt_addr14;
490 wire [47:0] mac_alt_addr15;
491 wire [47:0] addr_filter;
492 wire [7:0] addr_filter_mask_msb;
493 wire [15:0] addr_filter_mask_lsb;
494 wire [255:0] hash_table;
495 wire [`H_INFO] mac_host_info0 ;
496 wire [`H_INFO] mac_host_info1 ;
497 wire [`H_INFO] mac_host_info2 ;
498 wire [`H_INFO] mac_host_info3 ;
499 wire [`H_INFO] mac_host_info4 ;
500 wire [`H_INFO] mac_host_info5 ;
501 wire [`H_INFO] mac_host_info6 ;
502 wire [`H_INFO] mac_host_info7 ;
503 wire [`H_INFO] mac_host_info8 ;
504 wire [`H_INFO] mac_host_info9 ;
505 wire [`H_INFO] mac_host_info10;
506 wire [`H_INFO] mac_host_info11;
507 wire [`H_INFO] mac_host_info12;
508 wire [`H_INFO] mac_host_info13;
509 wire [`H_INFO] mac_host_info14;
510 wire [`H_INFO] mac_host_info15;
511 wire [`H_INFO] mac_host_info16;
512 wire [`H_INFO] mac_host_info17;
513 wire [`H_INFO] mac_host_info18;
514 wire [`H_INFO] mac_host_info19;
515 wire [`TBITS] srfifo_dout;
516 // end of ALT_ADDR_AND_HASH_FUNC specific signals
517
518 // vlint flag_dangling_net_within_module off
519 // vlint flag_net_has_no_load off
520 wire rac_pls;
521 wire wr_en;
522 wire rd_en;
523 wire [4:0] rxfifo_full_space_clk;
524 wire stfifo_empty_clk;
525 wire stfifo_full_clk;
526 wire [4:0] stfifo_rd_ptr_txclk;
527 wire [4:0] txfifo_rd_ptr_txclk;
528 wire link_fault;
529 wire tx_hb_byte0_time;
530 wire tx_hb_byte1_time;
531 wire tx_hb_byte2_time;
532 wire tx_hb_byte3_time;
533 wire tx_hb_byte4_time;
534 wire tx_hb_byte5_time;
535 wire tx_hb_byte6_time;
536 wire tx_hb_byte7_time;
537 wire stfifo_underrun_txclk;
538 wire [13:0] tx_byte_count;
539 wire eop_txclk;
540 wire stfifo_overrun_clk;
541 // vlint flag_net_has_no_load on
542 // vlint flag_dangling_net_within_module on
543
544
545/* ------- start of rxfifo_unload instantiation -------------- */
546rxfifo_unload rxfifo_unload
547(/*AUTOINST*/
548 // Outputs
549 .rxmac_ipp_ack (rxmac_ipp_ack),
550 .rxmac_ipp_tag (rxmac_ipp_tag),
551 .rxmac_ipp_data (rxmac_ipp_data[63:0]),
552 .rxmac_ipp_ctrl (rxmac_ipp_ctrl),
553 .rxmac_ipp_stat (rxmac_ipp_stat[`TBITS]),
554 .rxfifo_g_rd_ptr_clk (rxfifo_g_rd_ptr_clk[4:0]),
555 .rxfifo_rd_ptr_clk (rxfifo_rd_ptr_clk[4:0]),
556 .rxfifo_wr_ptr_clk (rxfifo_wr_ptr_clk[4:0]),
557 .rxfifo_underrun_clk (rxfifo_underrun_clk),
558 .srfifo_rd_ptr_clk (srfifo_rd_ptr_clk[4:0]),
559 .inc_histo_cntr1 (inc_histo_cntr1),
560 .inc_histo_cntr2 (inc_histo_cntr2),
561 .inc_histo_cntr3 (inc_histo_cntr3),
562 .inc_histo_cntr4 (inc_histo_cntr4),
563 .inc_histo_cntr5 (inc_histo_cntr5),
564 .inc_histo_cntr6 (inc_histo_cntr6),
565 .inc_histo_cntr7 (inc_histo_cntr7),
566 .rxfifo_full_clk_reg (rxfifo_full_clk_reg),
567 .rxfifo_empty_clk_reg (rxfifo_empty_clk_reg),
568 .rxfifo_full_space_clk (rxfifo_full_space_clk[4:0]),
569 // Inputs
570 .clk (clk),
571 .rx_reset_clk (rx_reset_clk),
572 .srfifo_g_wr_ptr_sync (srfifo_g_wr_ptr_sync[4:0]),
573 .rxfifo_g_wr_ptr_sync (rxfifo_g_wr_ptr_sync[4:0]),
574 .rxfifo_dout (rxfifo_dout[65:0]),
575 .ipp_rxmac_req (ipp_rxmac_req),
576 .srfifo_dout (srfifo_dout[`TBITS]));
577/* ------- end of rxfifo_unload instatiation ----------------- */
578
579/* ------- start of rx_xmac instatiation --------------------- */
580rx_xmac rx_xmac
581(/*AUTOINST*/
582 // Outputs
583 .rxfifo_dout (rxfifo_dout[65:0]),
584 .rxfifo_g_wr_ptr_rxclk (rxfifo_g_wr_ptr_rxclk[4:0]),
585 .rxfifo_full_rxclk_reg (rxfifo_full_rxclk_reg),
586 .rxfifo_overrun_rxclk (rxfifo_overrun_rxclk),
587 .srfifo_dout (srfifo_dout[`TBITS]),
588 .srfifo_g_wr_ptr_rxclk (srfifo_g_wr_ptr_rxclk[4:0]),
589 .rx_good_pkt (rx_good_pkt),
590 .rx_fc_pkt_ok (rx_fc_pkt_ok),
591 .pause_time (pause_time[15:0]),
592 .toggle_rx_bcount (toggle_rx_bcount),
593 .inc_bcast_count (inc_bcast_count),
594 .inc_mcast_count (inc_mcast_count),
595 .inc_code_viol_count (inc_code_viol_count),
596 .inc_crc_err_count (inc_crc_err_count),
597 .inc_min_pkt_err_count (inc_min_pkt_err_count),
598 .inc_max_pkt_err_count (inc_max_pkt_err_count),
599 .rx_data_valid_gmux_reg (rx_data_valid_gmux_reg),
600 .rx_pa_data (rx_pa_data[63:0]),
601 .link_fault (link_fault),
602 .inc_link_fault_count (inc_link_fault_count),
603 .remote_fault_oc_reg (remote_fault_oc_reg),
604 .local_fault_oc_reg (local_fault_oc_reg),
605 .lfs_state (lfs_state[1:0]),
606 .xrlm_state (xrlm_state),
607 .sop_state (sop_state),
608 .S_detected_reg (S_detected_reg),
609 .T_E_detected_at_modified_pkt_reg (T_E_detected_at_modified_pkt_reg),
610 .END_PKT_ERR_detected_a_at_modified_pkt_reg(END_PKT_ERR_detected_a_at_modified_pkt_reg),
611 .END_PKT_ERR_detected_b_at_modified_pkt_reg(END_PKT_ERR_detected_b_at_modified_pkt_reg),
612 .S_D_reg (S_D_reg),
613 .S_I_reg (S_I_reg),
614 .D_S_reg (D_S_reg),
615 .I_S_reg (I_S_reg),
616 .abort_bit_reg (abort_bit_reg),
617 .rx_err_reg (rx_err_reg),
618 .crc_error_reg (crc_error_reg),
619 .kill_data_ready_reg (kill_data_ready_reg),
620 .kill_crc_reg (kill_crc_reg),
621 .rx_sel_reg (rx_sel_reg[1:0]),
622 // Inputs
623 .rx_clk (rx_clk),
624 .rx_reset (rx_reset),
625 .warning_msg_en (warning_msg_en),
626 .xgmii_rxc (xgmii_rxc[3:0]),
627 .xgmii_rxd (xgmii_rxd[31:0]),
628 .xpcs_rxc (xpcs_rxc[7:0]),
629 .xpcs_rxd (xpcs_rxd[63:0]),
630 .txc_image (txc_image[7:0]),
631 .txd_image (txd_image[63:0]),
632 .hold_rxd (hold_rxd[63:0]),
633 .hold_rx_dv (hold_rx_dv[7:0]),
634 .hold_rx_err (hold_rx_err),
635 .xpcs_bypass (xpcs_bypass),
636 .mii_or_gmii_mode (mii_or_gmii_mode),
637 .loopback (loopback),
638 .rx_enable_rxclk (rx_enable_rxclk),
639 .code_viol_chk_dis (code_viol_chk_dis),
640 .crc_chk_dis (crc_chk_dis),
641 .promisc_all (promisc_all),
642 .promisc_group (promisc_group),
643 .err_chk_dis (err_chk_dis),
644 .rx_pause_en (rx_pause_en),
645 .pass_fc (pass_fc),
646 .reserve_multicast (reserve_multicast),
647 .mac_unique_addr (mac_unique_addr[47:0]),
648 .no_rx_min_pkt_size_chk (no_rx_min_pkt_size_chk),
649 .rx_min_pkt_size (rx_min_pkt_size[9:0]),
650 .max_pkt_size (max_pkt_size[13:0]),
651 .lfs_disable_rxclk (lfs_disable_rxclk),
652 .rxfifo_g_rd_ptr_sync (rxfifo_g_rd_ptr_sync[4:0]),
653 .rxfifo_rd_ptr_clk (rxfifo_rd_ptr_clk[3:0]),
654 .srfifo_rd_ptr_clk (srfifo_rd_ptr_clk[4:0]),
655 .strip_crc (strip_crc),
656 .addr_filter_en (addr_filter_en),
657 .hash_filter_en (hash_filter_en),
658 .alt_addr_comp_en (alt_addr_comp_en[15:0]),
659 .mac_alt_addr0 (mac_alt_addr0[47:0]),
660 .mac_alt_addr1 (mac_alt_addr1[47:0]),
661 .mac_alt_addr2 (mac_alt_addr2[47:0]),
662 .mac_alt_addr3 (mac_alt_addr3[47:0]),
663 .mac_alt_addr4 (mac_alt_addr4[47:0]),
664 .mac_alt_addr5 (mac_alt_addr5[47:0]),
665 .mac_alt_addr6 (mac_alt_addr6[47:0]),
666 .mac_alt_addr7 (mac_alt_addr7[47:0]),
667 .mac_alt_addr8 (mac_alt_addr8[47:0]),
668 .mac_alt_addr9 (mac_alt_addr9[47:0]),
669 .mac_alt_addr10 (mac_alt_addr10[47:0]),
670 .mac_alt_addr11 (mac_alt_addr11[47:0]),
671 .mac_alt_addr12 (mac_alt_addr12[47:0]),
672 .mac_alt_addr13 (mac_alt_addr13[47:0]),
673 .mac_alt_addr14 (mac_alt_addr14[47:0]),
674 .mac_alt_addr15 (mac_alt_addr15[47:0]),
675 .addr_filter (addr_filter[47:0]),
676 .addr_filter_mask_msb (addr_filter_mask_msb[7:0]),
677 .addr_filter_mask_lsb (addr_filter_mask_lsb[15:0]),
678 .hash_table (hash_table[255:0]),
679 .mac_host_info0 (mac_host_info0[`H_INFO]),
680 .mac_host_info1 (mac_host_info1[`H_INFO]),
681 .mac_host_info2 (mac_host_info2[`H_INFO]),
682 .mac_host_info3 (mac_host_info3[`H_INFO]),
683 .mac_host_info4 (mac_host_info4[`H_INFO]),
684 .mac_host_info5 (mac_host_info5[`H_INFO]),
685 .mac_host_info6 (mac_host_info6[`H_INFO]),
686 .mac_host_info7 (mac_host_info7[`H_INFO]),
687 .mac_host_info8 (mac_host_info8[`H_INFO]),
688 .mac_host_info9 (mac_host_info9[`H_INFO]),
689 .mac_host_info10 (mac_host_info10[`H_INFO]),
690 .mac_host_info11 (mac_host_info11[`H_INFO]),
691 .mac_host_info12 (mac_host_info12[`H_INFO]),
692 .mac_host_info13 (mac_host_info13[`H_INFO]),
693 .mac_host_info14 (mac_host_info14[`H_INFO]),
694 .mac_host_info15 (mac_host_info15[`H_INFO]),
695 .mac_host_info16 (mac_host_info16[`H_INFO]),
696 .mac_host_info17 (mac_host_info17[`H_INFO]),
697 .mac_host_info18 (mac_host_info18[`H_INFO]),
698 .mac_host_info19 (mac_host_info19[`H_INFO]));
699/* ------------- end of rx_xmac instantiation ---------------- */
700
701/* ------------- start of xmac_slv instantiation ------------- */
702xmac_slv xmac_slv
703(/*AUTOINST*/
704 // Outputs
705 .pio_ack (pio_ack),
706 .pio_rd_data (pio_rd_data[31:0]),
707 .pio_err (pio_err),
708 .xmac_debug (xmac_debug[31:0]),
709 .mac_debug_sel (mac_debug_sel[2:0]),
710 .strip_crc (strip_crc),
711 .addr_filter_en (addr_filter_en),
712 .hash_filter_en (hash_filter_en),
713 .alt_addr_comp_en (alt_addr_comp_en[15:0]),
714 .mac_alt_addr0 (mac_alt_addr0[47:0]),
715 .mac_alt_addr1 (mac_alt_addr1[47:0]),
716 .mac_alt_addr2 (mac_alt_addr2[47:0]),
717 .mac_alt_addr3 (mac_alt_addr3[47:0]),
718 .mac_alt_addr4 (mac_alt_addr4[47:0]),
719 .mac_alt_addr5 (mac_alt_addr5[47:0]),
720 .mac_alt_addr6 (mac_alt_addr6[47:0]),
721 .mac_alt_addr7 (mac_alt_addr7[47:0]),
722 .mac_alt_addr8 (mac_alt_addr8[47:0]),
723 .mac_alt_addr9 (mac_alt_addr9[47:0]),
724 .mac_alt_addr10 (mac_alt_addr10[47:0]),
725 .mac_alt_addr11 (mac_alt_addr11[47:0]),
726 .mac_alt_addr12 (mac_alt_addr12[47:0]),
727 .mac_alt_addr13 (mac_alt_addr13[47:0]),
728 .mac_alt_addr14 (mac_alt_addr14[47:0]),
729 .mac_alt_addr15 (mac_alt_addr15[47:0]),
730 .addr_filter (addr_filter[47:0]),
731 .addr_filter_mask_msb (addr_filter_mask_msb[7:0]),
732 .addr_filter_mask_lsb (addr_filter_mask_lsb[15:0]),
733 .hash_table (hash_table[255:0]),
734 .mac_host_info0 (mac_host_info0[`H_INFO]),
735 .mac_host_info1 (mac_host_info1[`H_INFO]),
736 .mac_host_info2 (mac_host_info2[`H_INFO]),
737 .mac_host_info3 (mac_host_info3[`H_INFO]),
738 .mac_host_info4 (mac_host_info4[`H_INFO]),
739 .mac_host_info5 (mac_host_info5[`H_INFO]),
740 .mac_host_info6 (mac_host_info6[`H_INFO]),
741 .mac_host_info7 (mac_host_info7[`H_INFO]),
742 .mac_host_info8 (mac_host_info8[`H_INFO]),
743 .mac_host_info9 (mac_host_info9[`H_INFO]),
744 .mac_host_info10 (mac_host_info10[`H_INFO]),
745 .mac_host_info11 (mac_host_info11[`H_INFO]),
746 .mac_host_info12 (mac_host_info12[`H_INFO]),
747 .mac_host_info13 (mac_host_info13[`H_INFO]),
748 .mac_host_info14 (mac_host_info14[`H_INFO]),
749 .mac_host_info15 (mac_host_info15[`H_INFO]),
750 .mac_host_info16 (mac_host_info16[`H_INFO]),
751 .mac_host_info17 (mac_host_info17[`H_INFO]),
752 .mac_host_info18 (mac_host_info18[`H_INFO]),
753 .mac_host_info19 (mac_host_info19[`H_INFO]),
754 .pcs_bypass (pcs_bypass),
755 .xpcs_bypass (xpcs_bypass),
756 .force_LED_on (force_LED_on),
757 .led_polarity (led_polarity),
758 .activity_led (activity_led),
759 .hw_reset (hw_reset),
760 .rx_reset_clk (rx_reset_clk),
761 .tx_reset_clk (tx_reset_clk),
762 .sys_clk_count (sys_clk_count[2:0]),
763 .txmac_interrupt (txmac_interrupt),
764 .rxmac_interrupt (rxmac_interrupt),
765 .xmac_fc_interrupt (xmac_fc_interrupt),
766 .no_tx_min_pkt_size_chk (no_tx_min_pkt_size_chk),
767 .no_rx_min_pkt_size_chk (no_rx_min_pkt_size_chk),
768 .always_no_crc (always_no_crc),
769 .var_min_ipg_en (var_min_ipg_en),
770 .tx_enable (tx_enable),
771 .rx_enable (rx_enable),
772 .promisc_all (promisc_all),
773 .err_chk_dis (err_chk_dis),
774 .crc_chk_dis (crc_chk_dis),
775 .code_viol_chk_dis (code_viol_chk_dis),
776 .promisc_group (promisc_group),
777 .reserve_multicast (reserve_multicast),
778 .rx_pause_en (rx_pause_en),
779 .pass_fc (pass_fc),
780 .tx_output_en (tx_output_en),
781 .loopback (loopback),
782 .sel_por_clk_src (sel_por_clk_src),
783 .sel_clk_25mhz (sel_clk_25mhz),
784 .mii_mode (mii_mode),
785 .gmii_mode (gmii_mode),
786 .xgmii_mode (xgmii_mode),
787 .mii_or_gmii_mode (mii_or_gmii_mode),
788 .lfs_disable (lfs_disable),
789 .warning_msg_en (warning_msg_en),
790 .ipg_value (ipg_value[2:0]),
791 .ipg_value1 (ipg_value1[`BYTE]),
792 .stretch_ratio (stretch_ratio[4:0]),
793 .stretch_constant (stretch_constant[2:0]),
794 .stretch_mode (stretch_mode),
795 .slot_time (slot_time[`BYTE]),
796 .tx_min_pkt_size (tx_min_pkt_size[9:0]),
797 .rx_min_pkt_size (rx_min_pkt_size[9:0]),
798 .max_pkt_size (max_pkt_size[13:0]),
799 .mac_unique_addr (mac_unique_addr[47:0]),
800 .wr_en (wr_en),
801 .rd_en (rd_en),
802 .rac_pls (rac_pls),
803 // Inputs
804 .clk (clk),
805 .clr_rx_reset_clk (clr_rx_reset_clk),
806 .clr_tx_reset_clk (clr_tx_reset_clk),
807 .pio_core_reset (pio_core_reset),
808 .pio_core_sel (pio_core_sel),
809 .pio_rd (pio_rd),
810 .pio_addr (pio_addr[8:0]),
811 .pio_wr_data (pio_wr_data[31:0]),
812 .pause_time (pause_time[15:0]),
813 .rxfifo_underrun_clk (rxfifo_underrun_clk),
814 .rxfifo_overrun_sync (rxfifo_overrun_sync),
815 .rx_good_pkt_sync (rx_good_pkt_sync),
816 .rx_fc_pkt_ok_clk (rx_fc_pkt_ok_clk),
817 .inc_max_pkt_err_count_sync (inc_max_pkt_err_count_sync),
818 .inc_min_pkt_err_count_sync (inc_min_pkt_err_count_sync),
819 .inc_code_viol_count_sync (inc_code_viol_count_sync),
820 .inc_align_err_count_sync (inc_align_err_count_sync),
821 .inc_crc_err_count_sync (inc_crc_err_count_sync),
822 .toggle_rx_bcount_sync (toggle_rx_bcount_sync),
823 .inc_bcast_count_sync (inc_bcast_count_sync),
824 .inc_mcast_count_sync (inc_mcast_count_sync),
825 .inc_histo_cntr1 (inc_histo_cntr1),
826 .inc_histo_cntr2 (inc_histo_cntr2),
827 .inc_histo_cntr3 (inc_histo_cntr3),
828 .inc_histo_cntr4 (inc_histo_cntr4),
829 .inc_histo_cntr5 (inc_histo_cntr5),
830 .inc_histo_cntr6 (inc_histo_cntr6),
831 .inc_histo_cntr7 (inc_histo_cntr7),
832 .rx_data_valid_gmux_reg_clk (rx_data_valid_gmux_reg_clk),
833 .rx_pa_data (rx_pa_data[63:0]),
834 .set_tx_pkt_ok_sync (set_tx_pkt_ok_sync),
835 .paused_state_sync (paused_state_sync),
836 .txfifo_underrun_sync (txfifo_underrun_sync),
837 .txfifo_xfr_err_sync (txfifo_xfr_err_sync),
838 .tx_max_pkt_size_err_sync (tx_max_pkt_size_err_sync),
839 .txfifo_overrun_clk (txfifo_overrun_clk),
840 .toggle_tx_bcount_sync (toggle_tx_bcount_sync),
841 .toggle_txframe_count_sync (toggle_txframe_count_sync),
842 .tx_data_valid_clk (tx_data_valid_clk),
843 .inc_link_fault_count_sync (inc_link_fault_count_sync),
844 .remote_fault_oc_sync (remote_fault_oc_sync),
845 .local_fault_oc_sync (local_fault_oc_sync),
846 .ipp_rxmac_req (ipp_rxmac_req),
847 .rxmac_ipp_ack (rxmac_ipp_ack),
848 .rxmac_ipp_tag (rxmac_ipp_tag),
849 .rxmac_ipp_ctrl (rxmac_ipp_ctrl),
850 .rxmac_ipp_stat (rxmac_ipp_stat[`TBITS]),
851 .txmac_opp_req (txmac_opp_req),
852 .opp_txmac_ack (opp_txmac_ack),
853 .opp_txmac_tag (opp_txmac_tag),
854 .opp_txmac_stat (opp_txmac_stat[3:0]),
855 .opp_txmac_abort (opp_txmac_abort),
856 .rxfifo_full_clk_reg (rxfifo_full_clk_reg),
857 .rxfifo_empty_clk_reg (rxfifo_empty_clk_reg),
858 .rxfifo_rd_ptr_clk (rxfifo_rd_ptr_clk[4:0]),
859 .rxfifo_wr_ptr_clk (rxfifo_wr_ptr_clk[4:0]),
860 .S_detected_reg (S_detected_reg),
861 .T_E_detected_at_modified_pkt_reg (T_E_detected_at_modified_pkt_reg),
862 .END_PKT_ERR_detected_a_at_modified_pkt_reg(END_PKT_ERR_detected_a_at_modified_pkt_reg),
863 .END_PKT_ERR_detected_b_at_modified_pkt_reg(END_PKT_ERR_detected_b_at_modified_pkt_reg),
864 .S_D_reg (S_D_reg),
865 .S_I_reg (S_I_reg),
866 .D_S_reg (D_S_reg),
867 .I_S_reg (I_S_reg),
868 .abort_bit_reg (abort_bit_reg),
869 .rx_err_reg (rx_err_reg),
870 .crc_error_reg (crc_error_reg),
871 .kill_data_ready_reg (kill_data_ready_reg),
872 .kill_crc_reg (kill_crc_reg),
873 .rx_sel_reg (rx_sel_reg[1:0]),
874 .txfifo_full_clk_reg (txfifo_full_clk_reg),
875 .txfifo_empty_clk_reg (txfifo_empty_clk_reg),
876 .tx_swap_reg (tx_swap_reg),
877 .tx_on_reg (tx_on_reg),
878 .tx_on_half_reg (tx_on_half_reg),
879 .back2back_swap_reg1 (back2back_swap_reg1),
880 .replace_txd_time_reg (replace_txd_time_reg),
881 .adjust2crc_full_case_last_byte_position_reg(adjust2crc_full_case_last_byte_position_reg[2:0]),
882 .adjust2crc_full_case_last_byte_position_is_3_or_7_reg(adjust2crc_full_case_last_byte_position_is_3_or_7_reg),
883 .stretch_clks_reg (stretch_clks_reg[`BYTE]),
884 .full_case_last_byte_position_reg (full_case_last_byte_position_reg[2:0]),
885 .stretch_full_case_last_byte_position_reg(stretch_full_case_last_byte_position_reg[3:0]),
886 .stretch_bytes_reg (stretch_bytes_reg[2:0]),
887 .minus_4bytes_reg (minus_4bytes_reg),
888 .B_eop_reg (B_eop_reg),
889 .stretch_1_more_clk_reg (stretch_1_more_clk_reg),
890 .no_wasted_BW_reg (no_wasted_BW_reg),
891 .ipg_done_trail_temp_reg (ipg_done_trail_temp_reg),
892 .tx_byte0_reg0 (tx_byte0_reg0[7:0]),
893 .restart_ipg_timer_reg (restart_ipg_timer_reg),
894 .eop_txclk_reg0 (eop_txclk_reg0),
895 .eop_w_fcs_reg0 (eop_w_fcs_reg0),
896 .tx_abort_reg0 (tx_abort_reg0),
897 .eop_w_fcs_reg1 (eop_w_fcs_reg1),
898 .tx_abort_reg1 (tx_abort_reg1),
899 .ipg_done_reg (ipg_done_reg),
900 .ipg_done_lead_temp_reg (ipg_done_lead_temp_reg),
901 .force_ipg_done_lead_reg (force_ipg_done_lead_reg),
902 .set_back2back_reg (set_back2back_reg),
903 .back2back_reg (back2back_reg),
904 .txfifo_rd_ptr_clk (txfifo_rd_ptr_clk[4:0]),
905 .txfifo_wr_ptr_clk (txfifo_wr_ptr_clk[4:0]),
906 .last_byte_position (last_byte_position[2:0]),
907 .mgrlm_state (mgrlm_state),
908 .xrlm_state (xrlm_state),
909 .sop_state (sop_state),
910 .xtlm_state (xtlm_state[2:0]),
911 .lfs_state (lfs_state[1:0]),
912 .xpcs_rxc (xpcs_rxc[7:0]),
913 .xpcs_rxd (xpcs_rxd[63:0]),
914 .xpcs_txc (xpcs_txc[7:0]),
915 .xpcs_txd (xpcs_txd[63:0]),
916 .rx_heart_beat_timer_reg (rx_heart_beat_timer_reg[3:0]),
917 .tx_heart_beat_timer_reg (tx_heart_beat_timer_reg[3:0]),
918 .tx_clk_div2 (tx_clk_div2),
919 .rx_clk_div2 (rx_clk_div2),
920 .tx_nbclk_div2 (tx_nbclk_div2),
921 .rx_nbclk_div2 (rx_nbclk_div2),
922 .MDINT (MDINT));
923/* ------------- end of xmac_slv instantiation --------------- */
924
925/* ------------- start of xmac_sync instantiation ------------ */
926xmac_sync xmac_sync
927(/*AUTOINST*/
928 // Outputs
929 .rx_reset (rx_reset),
930 .tx_reset (tx_reset),
931 .clr_rx_reset_clk (clr_rx_reset_clk),
932 .clr_tx_reset_clk (clr_tx_reset_clk),
933 .hw_reset_rxnbclk (hw_reset_rxnbclk),
934 .hw_reset_txnbclk (hw_reset_txnbclk),
935 .rx_reset_nbclk (rx_reset_nbclk),
936 .tx_reset_nbclk (tx_reset_nbclk),
937 .rxfifo_g_rd_ptr_sync (rxfifo_g_rd_ptr_sync[4:0]),
938 .rxfifo_g_wr_ptr_sync (rxfifo_g_wr_ptr_sync[4:0]),
939 .rxfifo_overrun_sync (rxfifo_overrun_sync),
940 .txfifo_g_rd_ptr_sync (txfifo_g_rd_ptr_sync[4:0]),
941 .txfifo_g_wr_ptr_sync (txfifo_g_wr_ptr_sync[4:0]),
942 .txfifo_underrun_sync (txfifo_underrun_sync),
943 .stfifo_g_rd_ptr_sync (stfifo_g_rd_ptr_sync[4:0]),
944 .stfifo_g_wr_ptr_sync (stfifo_g_wr_ptr_sync[4:0]),
945 .srfifo_g_wr_ptr_sync (srfifo_g_wr_ptr_sync[4:0]),
946 .rx_good_pkt_sync (rx_good_pkt_sync),
947 .rx_fc_pkt_ok_txclk (rx_fc_pkt_ok_txclk),
948 .rx_fc_pkt_ok_clk (rx_fc_pkt_ok_clk),
949 .inc_max_pkt_err_count_sync (inc_max_pkt_err_count_sync),
950 .inc_min_pkt_err_count_sync (inc_min_pkt_err_count_sync),
951 .inc_code_viol_count_sync (inc_code_viol_count_sync),
952 .inc_align_err_count_sync (inc_align_err_count_sync),
953 .inc_crc_err_count_sync (inc_crc_err_count_sync),
954 .toggle_rx_bcount_sync (toggle_rx_bcount_sync),
955 .inc_bcast_count_sync (inc_bcast_count_sync),
956 .inc_mcast_count_sync (inc_mcast_count_sync),
957 .rx_enable_rxclk (rx_enable_rxclk),
958 .rx_enable_nbclk (rx_enable_nbclk),
959 .rxfifo_full_nbclk (rxfifo_full_nbclk),
960 .rx_data_valid_gmux_reg_clk (rx_data_valid_gmux_reg_clk),
961 .paused_state_sync (paused_state_sync),
962 .set_tx_pkt_ok_sync (set_tx_pkt_ok_sync),
963 .txfifo_xfr_err_sync (txfifo_xfr_err_sync),
964 .tx_max_pkt_size_err_sync (tx_max_pkt_size_err_sync),
965 .toggle_tx_bcount_sync (toggle_tx_bcount_sync),
966 .toggle_txframe_count_sync (toggle_txframe_count_sync),
967 .tx_enable_txclk (tx_enable_txclk),
968 .tx_output_en_txclk (tx_output_en_txclk),
969 .tx_output_en_nbclk (tx_output_en_nbclk),
970 .tx_data_valid_clk (tx_data_valid_clk),
971 .lfs_disable_rxclk (lfs_disable_rxclk),
972 .inc_link_fault_count_sync (inc_link_fault_count_sync),
973 .remote_fault_oc_sync (remote_fault_oc_sync),
974 .local_fault_oc_sync (local_fault_oc_sync),
975 .remote_fault_oc_txclk (remote_fault_oc_txclk),
976 .local_fault_oc_txclk (local_fault_oc_txclk),
977 // Inputs
978 .clk (clk),
979 .rx_clk (rx_clk),
980 .rx_nbclk (rx_nbclk),
981 .tx_clk (tx_clk),
982 .tx_nbclk (tx_nbclk),
983 .rx_reset_clk (rx_reset_clk),
984 .tx_reset_clk (tx_reset_clk),
985 .hw_reset (hw_reset),
986 .rxfifo_g_rd_ptr_clk (rxfifo_g_rd_ptr_clk[4:0]),
987 .rxfifo_g_wr_ptr_rxclk (rxfifo_g_wr_ptr_rxclk[4:0]),
988 .rxfifo_overrun_rxclk (rxfifo_overrun_rxclk),
989 .txfifo_g_rd_ptr_txclk (txfifo_g_rd_ptr_txclk[4:0]),
990 .txfifo_g_wr_ptr_clk (txfifo_g_wr_ptr_clk[4:0]),
991 .txfifo_underrun_txclk (txfifo_underrun_txclk),
992 .stfifo_g_rd_ptr_txclk (stfifo_g_rd_ptr_txclk[4:0]),
993 .stfifo_g_wr_ptr_clk (stfifo_g_wr_ptr_clk[4:0]),
994 .srfifo_g_wr_ptr_rxclk (srfifo_g_wr_ptr_rxclk[4:0]),
995 .rx_good_pkt (rx_good_pkt),
996 .rx_fc_pkt_ok (rx_fc_pkt_ok),
997 .inc_max_pkt_err_count (inc_max_pkt_err_count),
998 .inc_min_pkt_err_count (inc_min_pkt_err_count),
999 .inc_code_viol_count (inc_code_viol_count),
1000 .inc_align_err_count_nbclk (inc_align_err_count_nbclk),
1001 .inc_crc_err_count (inc_crc_err_count),
1002 .toggle_rx_bcount (toggle_rx_bcount),
1003 .inc_bcast_count (inc_bcast_count),
1004 .inc_mcast_count (inc_mcast_count),
1005 .rx_enable (rx_enable),
1006 .rxfifo_full_rxclk_reg (rxfifo_full_rxclk_reg),
1007 .rx_data_valid_gmux_reg (rx_data_valid_gmux_reg),
1008 .paused_state (paused_state),
1009 .set_tx_pkt_ok (set_tx_pkt_ok),
1010 .txfifo_xfr_err (txfifo_xfr_err),
1011 .tx_max_pkt_size_err (tx_max_pkt_size_err),
1012 .toggle_tx_bcount (toggle_tx_bcount),
1013 .toggle_txframe_count (toggle_txframe_count),
1014 .tx_enable (tx_enable),
1015 .tx_output_en (tx_output_en),
1016 .tx_data_valid (tx_data_valid),
1017 .lfs_disable (lfs_disable),
1018 .inc_link_fault_count (inc_link_fault_count),
1019 .remote_fault_oc_reg (remote_fault_oc_reg),
1020 .local_fault_oc_reg (local_fault_oc_reg));
1021/* ------------- end of xmac_sync instantiation -------------- */
1022
1023/* ------------- start of txfifo_load instantiation ---------- */
1024txfifo_load txfifo_load
1025(/*AUTOINST*/
1026 // Outputs
1027 .txmac_opp_req (txmac_opp_req),
1028 .txfifo_full_clk_reg (txfifo_full_clk_reg),
1029 .txfifo_empty_clk_reg (txfifo_empty_clk_reg),
1030 .txfifo_overrun_clk (txfifo_overrun_clk),
1031 .txfifo_g_wr_ptr_clk (txfifo_g_wr_ptr_clk[4:0]),
1032 .txfifo_wr_ptr_clk (txfifo_wr_ptr_clk[4:0]),
1033 .txfifo_rd_ptr_clk (txfifo_rd_ptr_clk[4:0]),
1034 .stfifo_full_clk (stfifo_full_clk),
1035 .stfifo_empty_clk (stfifo_empty_clk),
1036 .stfifo_overrun_clk (stfifo_overrun_clk),
1037 .stfifo_g_wr_ptr_clk (stfifo_g_wr_ptr_clk[4:0]),
1038 .no_crc (no_crc),
1039 .last_byte_position (last_byte_position[2:0]),
1040 .txfifo_dout (txfifo_dout[65:0]),
1041 // Inputs
1042 .clk (clk),
1043 .tx_reset_clk (tx_reset_clk),
1044 .opp_txmac_data (opp_txmac_data[63:0]),
1045 .opp_txmac_ack (opp_txmac_ack),
1046 .opp_txmac_tag (opp_txmac_tag),
1047 .opp_txmac_stat (opp_txmac_stat[3:0]),
1048 .opp_txmac_abort (opp_txmac_abort),
1049 .txfifo_g_rd_ptr_sync (txfifo_g_rd_ptr_sync[4:0]),
1050 .txfifo_rd_ptr_txclk (txfifo_rd_ptr_txclk[3:0]),
1051 .stfifo_g_rd_ptr_sync (stfifo_g_rd_ptr_sync[4:0]),
1052 .stfifo_rd_ptr_txclk (stfifo_rd_ptr_txclk[3:0]));
1053/* ------------- end of txfifo_load instantiation ------------ */
1054
1055/* ------------- start of tx_xmac instantiation -------------- */
1056tx_xmac tx_xmac
1057(/*AUTOINST*/
1058 // Outputs
1059 .xgmii_txc (xgmii_txc[3:0]),
1060 .xgmii_txd (xgmii_txd[31:0]),
1061 .xpcs_txc (xpcs_txc[7:0]),
1062 .xpcs_txd (xpcs_txd[63:0]),
1063 .txc_image (txc_image[7:0]),
1064 .txd_image (txd_image[63:0]),
1065 .tx_err_image (tx_err_image),
1066 .tx_byte_count (tx_byte_count[13:0]),
1067 .paused_state (paused_state),
1068 .txfifo_xfr_err (txfifo_xfr_err),
1069 .tx_max_pkt_size_err (tx_max_pkt_size_err),
1070 .set_tx_pkt_ok (set_tx_pkt_ok),
1071 .toggle_txframe_count (toggle_txframe_count),
1072 .toggle_tx_bcount (toggle_tx_bcount),
1073 .txfifo_g_rd_ptr_txclk (txfifo_g_rd_ptr_txclk[4:0]),
1074 .txfifo_rd_ptr_txclk (txfifo_rd_ptr_txclk[4:0]),
1075 .txfifo_underrun_txclk (txfifo_underrun_txclk),
1076 .eop_txclk (eop_txclk),
1077 .tx_data_valid (tx_data_valid),
1078 .stfifo_g_rd_ptr_txclk (stfifo_g_rd_ptr_txclk[4:0]),
1079 .stfifo_rd_ptr_txclk (stfifo_rd_ptr_txclk[4:0]),
1080 .stfifo_underrun_txclk (stfifo_underrun_txclk),
1081 .tx_swap_reg (tx_swap_reg),
1082 .tx_on_reg (tx_on_reg),
1083 .tx_on_half_reg (tx_on_half_reg),
1084 .back2back_swap_reg1 (back2back_swap_reg1),
1085 .replace_txd_time_reg (replace_txd_time_reg),
1086 .adjust2crc_full_case_last_byte_position_reg(adjust2crc_full_case_last_byte_position_reg[2:0]),
1087 .adjust2crc_full_case_last_byte_position_is_3_or_7_reg(adjust2crc_full_case_last_byte_position_is_3_or_7_reg),
1088 .stretch_clks_reg (stretch_clks_reg[`BYTE]),
1089 .full_case_last_byte_position_reg (full_case_last_byte_position_reg[2:0]),
1090 .stretch_full_case_last_byte_position_reg(stretch_full_case_last_byte_position_reg[3:0]),
1091 .stretch_bytes_reg (stretch_bytes_reg[2:0]),
1092 .minus_4bytes_reg (minus_4bytes_reg),
1093 .B_eop_reg (B_eop_reg),
1094 .stretch_1_more_clk_reg (stretch_1_more_clk_reg),
1095 .no_wasted_BW_reg (no_wasted_BW_reg),
1096 .ipg_done_trail_temp_reg (ipg_done_trail_temp_reg),
1097 .tx_byte0_reg0 (tx_byte0_reg0[7:0]),
1098 .restart_ipg_timer_reg (restart_ipg_timer_reg),
1099 .eop_txclk_reg0 (eop_txclk_reg0),
1100 .eop_w_fcs_reg0 (eop_w_fcs_reg0),
1101 .tx_abort_reg0 (tx_abort_reg0),
1102 .eop_w_fcs_reg1 (eop_w_fcs_reg1),
1103 .tx_abort_reg1 (tx_abort_reg1),
1104 .ipg_done_reg (ipg_done_reg),
1105 .ipg_done_lead_temp_reg (ipg_done_lead_temp_reg),
1106 .force_ipg_done_lead_reg (force_ipg_done_lead_reg),
1107 .set_back2back_reg (set_back2back_reg),
1108 .back2back_reg (back2back_reg),
1109 .xtlm_state (xtlm_state[2:0]),
1110 // Inputs
1111 .tx_clk (tx_clk),
1112 .tx_reset (tx_reset),
1113 .xgmii_mode (xgmii_mode),
1114 .txfifo_dout (txfifo_dout[65:0]),
1115 .no_crc (no_crc),
1116 .last_byte_position (last_byte_position[2:0]),
1117 .max_pkt_size (max_pkt_size[13:0]),
1118 .tx_min_pkt_size (tx_min_pkt_size[9:0]),
1119 .no_tx_min_pkt_size_chk (no_tx_min_pkt_size_chk),
1120 .mac_unique_addr (mac_unique_addr[47:0]),
1121 .ipg_value (ipg_value[2:0]),
1122 .stretch_ratio (stretch_ratio[4:0]),
1123 .stretch_constant (stretch_constant[2:0]),
1124 .stretch_mode (stretch_mode),
1125 .rx_fc_pkt_ok_txclk (rx_fc_pkt_ok_txclk),
1126 .pause_time (pause_time[15:0]),
1127 .slot_time (slot_time[`BYTE]),
1128 .txfifo_g_wr_ptr_sync (txfifo_g_wr_ptr_sync[4:0]),
1129 .stfifo_g_wr_ptr_sync (stfifo_g_wr_ptr_sync[4:0]),
1130 .tx_enable_txclk (tx_enable_txclk),
1131 .always_no_crc (always_no_crc),
1132 .tx_output_en_txclk (tx_output_en_txclk),
1133 .var_min_ipg_en (var_min_ipg_en),
1134 .mii_mode (mii_mode),
1135 .gmii_mode (gmii_mode),
1136 .warning_msg_en (warning_msg_en),
1137 .remote_fault_oc_txclk (remote_fault_oc_txclk),
1138 .local_fault_oc_txclk (local_fault_oc_txclk));
1139/* ------------- end of tx_xmac instantiation ---------------- */
1140
1141`ifdef XGMII_ONLY
1142// outputs of rx_mii_gmii
1143 assign inc_align_err_count_nbclk = 0;
1144 assign rx_heart_beat_timer = 0;
1145 assign rx_heart_beat_timer_reg = 0;
1146 assign hold_rxd = 0;
1147 assign hold_rx_dv = 0;
1148 assign hold_rx_err = 0;
1149 assign mgrlm_state = 0;
1150// outputs of tx_mii_gmii
1151 assign tx_heart_beat_timer = 0;
1152 assign tx_heart_beat_timer_reg = 0;
1153 // mii outputs
1154 assign mii_txd = 0;
1155 assign mii_tx_en = 0;
1156 assign mii_tx_err = 0;
1157 // gmii outputs
1158 assign gmii_txd = 0;
1159 assign gmii_tx_en = 0;
1160 assign gmii_tx_err = 0;
1161 // loopback path
1162 assign mgmii_txd = 0;
1163 assign mgmii_tx_en = 0;
1164 assign mgmii_tx_err= 0;
1165`else // quad speed
1166/* ------------- start of rx_mii_gmii instantiation ---------- */
1167rx_mii_gmii rx_mii_gmii
1168(/*AUTOINST*/
1169 // Outputs
1170 .inc_align_err_count_nbclk (inc_align_err_count_nbclk),
1171 .rx_heart_beat_timer (rx_heart_beat_timer[3:0]),
1172 .rx_heart_beat_timer_reg (rx_heart_beat_timer_reg[3:0]),
1173 .hold_rxd (hold_rxd[63:0]),
1174 .hold_rx_dv (hold_rx_dv[7:0]),
1175 .hold_rx_err (hold_rx_err),
1176 .mgrlm_state (mgrlm_state),
1177 // Inputs
1178 .rx_nbclk (rx_nbclk),
1179 .rx_reset_nbclk (rx_reset_nbclk),
1180 .hw_reset_rxnbclk (hw_reset_rxnbclk),
1181 .rxfifo_full_nbclk (rxfifo_full_nbclk),
1182 .rx_enable_nbclk (rx_enable_nbclk),
1183 .mgmii_txd (mgmii_txd[`BYTE]),
1184 .mgmii_tx_en (mgmii_tx_en),
1185 .mgmii_tx_err (mgmii_tx_err),
1186 .mii_mode (mii_mode),
1187 .gmii_mode (gmii_mode),
1188 .mii_or_gmii_mode (mii_or_gmii_mode),
1189 .loopback (loopback),
1190 .gmii_rxd (gmii_rxd[`BYTE]),
1191 .gmii_rx_dv (gmii_rx_dv),
1192 .gmii_rx_err (gmii_rx_err));
1193/* ------------- end of rx_mii_gmii instantiation ----------- */
1194
1195/* ------------- start of tx_mii_gmii instantiation ---------- */
1196tx_mii_gmii tx_mii_gmii
1197(/*AUTOINST*/
1198 // Outputs
1199 .tx_heart_beat_timer (tx_heart_beat_timer[3:0]),
1200 .tx_heart_beat_timer_reg (tx_heart_beat_timer_reg[3:0]),
1201 .gmii_txd (gmii_txd[`BYTE]),
1202 .gmii_tx_en (gmii_tx_en),
1203 .gmii_tx_err (gmii_tx_err),
1204 .mgmii_txd (mgmii_txd[`BYTE]),
1205 .mgmii_tx_en (mgmii_tx_en),
1206 .mgmii_tx_err (mgmii_tx_err),
1207 .tx_hb_byte0_time (tx_hb_byte0_time),
1208 .tx_hb_byte1_time (tx_hb_byte1_time),
1209 .tx_hb_byte2_time (tx_hb_byte2_time),
1210 .tx_hb_byte3_time (tx_hb_byte3_time),
1211 .tx_hb_byte4_time (tx_hb_byte4_time),
1212 .tx_hb_byte5_time (tx_hb_byte5_time),
1213 .tx_hb_byte6_time (tx_hb_byte6_time),
1214 .tx_hb_byte7_time (tx_hb_byte7_time),
1215 // Inputs
1216 .tx_nbclk (tx_nbclk),
1217 .tx_reset_nbclk (tx_reset_nbclk),
1218 .hw_reset_txnbclk (hw_reset_txnbclk),
1219 .tx_output_en_nbclk (tx_output_en_nbclk),
1220 .mii_mode (mii_mode),
1221 .gmii_mode (gmii_mode),
1222 .mii_or_gmii_mode (mii_or_gmii_mode),
1223 .txd_image (txd_image[63:0]),
1224 .txc_image (txc_image[7:0]),
1225 .tx_err_image (tx_err_image),
1226 .ipg_value1 (ipg_value1[`BYTE]));
1227/* ------------- end of tx_mii_gmii instantiation ----------- */
1228`endif // !ifdef XGMII_ONLY
1229
1230
1231/* ------------- clock observation point logic --------------- */
1232
1233 DIV2_CLK tx_clk_DIV2_CLK (.reset(tx_reset),.clk(tx_clk),.clk2(tx_clk_div2));
1234 DIV2_CLK rx_clk_DIV2_CLK (.reset(rx_reset),.clk(rx_clk),.clk2(rx_clk_div2));
1235 DIV2_CLK tx_nbclk_DIV2_CLK(.reset(tx_reset_nbclk),.clk(tx_nbclk),.clk2(tx_nbclk_div2));
1236 DIV2_CLK rx_nbclk_DIV2_CLK(.reset(rx_reset_nbclk),.clk(rx_nbclk),.clk2(rx_nbclk_div2));
1237
1238endmodule // xmac
1239
1240
Full OpenSPARC design & verification tarball including full HDL.