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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / design / sys / iop / niu / rtl / xmac_fcs.v
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AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: xmac_fcs.v
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
19// along with this program; if not, write to the Free Software
20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
23// choice is available it will apply instead, Sun elects to use only
24// the General Public License version 2 (GPLv2) at this time for any
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32// have any questions.
33//
34// ========== Copyright Header End ============================================
35/*%W% %G%*/
36
37/*************************************************************************
38 *
39 * File Name : xmac_fcs.v
40 * Author Name : John Lo
41 * Description : xmac frame check sequence logic.
42 * Parent Module: rx_xmac or tx_xmac
43 * Child Module: crc_gen_xmii
44 * Interface Mod: many.
45 * Date Created : 6/1/00
46 *
47 * Copyright (c) 2002, Sun Microsystems, Inc.
48 * Sun Proprietary and Confidential
49 *
50 * Modification :
51 *
52 * Synthesis Notes: This module is very timing critical. Need custom layout.
53 *
54 *************************************************************************/
55
56module xmac_fcs (clk,initialize_crc,compute_en,
57 crc_chk_dis,data_valid,dv_8bit,
58 data_64bit,new_crc5_result,crc_result,crc_error);
59
60 input clk;
61 input initialize_crc;
62 input compute_en;
63 input crc_chk_dis;
64 input data_valid;
65 input [7:0] dv_8bit;
66 input [63:0] data_64bit;
67// outputs
68 output [31:0] new_crc5_result;
69 output [31:0] crc_result;
70 output crc_error;
71
72 // The 32 bits of the CRC value are placed in the frame check seqeunce
73 // field so that the x31 term is the left-most bit of the first octet,
74 // and the x0 term is the right most bit of the last octet.
75 // The bits of the CRC are thus transmitted in the order X31,x30,...,x1,x0.
76 // 802.3 3.3 pp-15: Each octec of the MAC frame, with the exception of
77 // the FCS, is transmitted low_order bit first.
78 // bit0 has to come into crc logic first.
79
80 wire initialize_crc,compute_en,crc_compute_error;
81 wire [7:0] swap_byte0 = {data_64bit[0],
82 data_64bit[1],
83 data_64bit[2],
84 data_64bit[3],
85 data_64bit[4],
86 data_64bit[5],
87 data_64bit[6],
88 data_64bit[7]};
89 wire [7:0] swap_byte1 = {data_64bit[8],
90 data_64bit[9],
91 data_64bit[10],
92 data_64bit[11],
93 data_64bit[12],
94 data_64bit[13],
95 data_64bit[14],
96 data_64bit[15]};
97 wire [7:0] swap_byte2 = {data_64bit[16],
98 data_64bit[17],
99 data_64bit[18],
100 data_64bit[19],
101 data_64bit[20],
102 data_64bit[21],
103 data_64bit[22],
104 data_64bit[23]};
105 wire [7:0] swap_byte3 = {data_64bit[24],
106 data_64bit[25],
107 data_64bit[26],
108 data_64bit[27],
109 data_64bit[28],
110 data_64bit[29],
111 data_64bit[30],
112 data_64bit[31]};
113 wire [7:0] swap_byte4 = {data_64bit[32],
114 data_64bit[33],
115 data_64bit[34],
116 data_64bit[35],
117 data_64bit[36],
118 data_64bit[37],
119 data_64bit[38],
120 data_64bit[39]};
121 wire [7:0] swap_byte5 = {data_64bit[40],
122 data_64bit[41],
123 data_64bit[42],
124 data_64bit[43],
125 data_64bit[44],
126 data_64bit[45],
127 data_64bit[46],
128 data_64bit[47]};
129 wire [7:0] swap_byte6 = {data_64bit[48],
130 data_64bit[49],
131 data_64bit[50],
132 data_64bit[51],
133 data_64bit[52],
134 data_64bit[53],
135 data_64bit[54],
136 data_64bit[55]};
137 wire [7:0] swap_byte7 = {data_64bit[56],
138 data_64bit[57],
139 data_64bit[58],
140 data_64bit[59],
141 data_64bit[60],
142 data_64bit[61],
143 data_64bit[62],
144 data_64bit[63]};
145
146 wire [31:0] new_crc5_result;
147 wire [31:0] crc_result;
148
149 crc_gen_xmii crc_gen_xmii (.clk(clk),.initialize_crc(initialize_crc),
150 .compute_en(compute_en),
151 .data_valid(data_valid),
152 .dv_8bit(dv_8bit),
153 .input_byte0(swap_byte0),.input_byte1(swap_byte1),
154 .input_byte2(swap_byte2),.input_byte3(swap_byte3),
155 .input_byte4(swap_byte4),.input_byte5(swap_byte5),
156 .input_byte6(swap_byte6),.input_byte7(swap_byte7),
157 .new_crc5_result(new_crc5_result),
158 .crc_result(crc_result));
159
160
161 assign crc_compute_error = (crc_result != 32'h38FB2284);
162
163 assign crc_error = crc_compute_error & !crc_chk_dis;
164
165
166endmodule // xmac_fcs
167
Full OpenSPARC design & verification tarball including full HDL.