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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / design / sys / iop / niu / rtl / xmac_sync.v
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AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: xmac_sync.v
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
19// along with this program; if not, write to the Free Software
20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
23// choice is available it will apply instead, Sun elects to use only
24// the General Public License version 2 (GPLv2) at this time for any
25// software where a choice of GPL license versions is made
26// available with the language indicating that GPLv2 or any later version
27// may be used, or where a choice of which version of the GPL is applied is
28// otherwise unspecified.
29//
30// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
31// CA 95054 USA or visit www.sun.com if you need additional information or
32// have any questions.
33//
34// ========== Copyright Header End ============================================
35/*%W% %G%*/
36
37/*************************************************************************
38 *
39 * File Name : xmac_sync.v
40 * Author Name : John Lo
41 * Description : It contains control signals crossing different clk domain.
42 * Parent Module: xmac_core
43 * Child Module:
44 * Interface Mod: many.
45 * Date Created : 5/9/00
46 *
47 * Copyright (c) 2002, Sun Microsystems, Inc.
48 * Sun Proprietary and Confidential
49 *
50 * Modification :
51 *
52 * Synthesis Notes:
53 *
54 *************************************************************************/
55
56module xmac_sync (
57 clk,
58 rx_clk,
59 rx_nbclk,
60 tx_clk,
61 tx_nbclk,
62 rx_reset_clk, // sys_clk domain
63 tx_reset_clk,
64 hw_reset,
65 // fifo related input signal
66 rxfifo_g_rd_ptr_clk, // from clk domain
67 rxfifo_g_wr_ptr_rxclk, // from rx_clk domain
68 rxfifo_overrun_rxclk, // from rx_clk domain
69 txfifo_g_rd_ptr_txclk, // from tx_clk domain
70 txfifo_g_wr_ptr_clk, // from clk domain
71 txfifo_underrun_txclk, // from tx_clk domain
72 stfifo_g_rd_ptr_txclk, // from tx_clk domain
73 stfifo_g_wr_ptr_clk, // from clk domain
74 srfifo_g_wr_ptr_rxclk, // from rx_clk domain
75 // RxMac related input signals
76 rx_good_pkt,
77 rx_fc_pkt_ok, // from rx_clk domain
78 inc_max_pkt_err_count,
79 inc_min_pkt_err_count,
80 inc_code_viol_count,
81 inc_align_err_count_nbclk, // mii_mode
82 inc_crc_err_count,
83 toggle_rx_bcount,
84 inc_bcast_count,
85 inc_mcast_count,
86 rx_enable,
87 rxfifo_full_rxclk_reg,
88 rx_data_valid_gmux_reg,
89 // TxMac related input signlas
90 paused_state,
91 set_tx_pkt_ok,
92 txfifo_xfr_err,
93 tx_max_pkt_size_err,
94 toggle_tx_bcount,
95 toggle_txframe_count,
96 tx_enable,
97 tx_output_en,
98 tx_data_valid,
99 // lfs related input signals
100 lfs_disable,
101 inc_link_fault_count,
102 remote_fault_oc_reg,
103 local_fault_oc_reg,
104// outputs
105 rx_reset, // to rx_clk domain
106 tx_reset, // to tx_clk domain
107 clr_rx_reset_clk, // to clk domain
108 clr_tx_reset_clk, // to clk domain
109 hw_reset_rxnbclk, // to rx_nbclk domain
110 hw_reset_txnbclk, // to tx_nbclk domain
111 rx_reset_nbclk, // to rx_nbclk domain
112 tx_reset_nbclk, // to tx_nbclk domain
113 // fifo related output signals
114 rxfifo_g_rd_ptr_sync, // to rx_clk domain
115 rxfifo_g_wr_ptr_sync, // to clk domain
116 rxfifo_overrun_sync, // to clk domain
117 txfifo_g_rd_ptr_sync, // to clk domain
118 txfifo_g_wr_ptr_sync, // to tx_clk domain
119 txfifo_underrun_sync, // to clk domain
120 stfifo_g_rd_ptr_sync, // to clk domain
121 stfifo_g_wr_ptr_sync, // to tx_clk domain
122 srfifo_g_wr_ptr_sync, // to clk domain
123 // RxMac related output signals
124 rx_good_pkt_sync, // to xmac_slv.
125 rx_fc_pkt_ok_txclk, // to tx_xmac.
126 rx_fc_pkt_ok_clk, // to xmac_slv.
127 inc_max_pkt_err_count_sync,
128 inc_min_pkt_err_count_sync,
129 inc_code_viol_count_sync,
130 inc_align_err_count_sync,
131 inc_crc_err_count_sync,
132 toggle_rx_bcount_sync,
133 inc_bcast_count_sync,
134 inc_mcast_count_sync,
135 rx_enable_rxclk,
136 rx_enable_nbclk,
137 rxfifo_full_nbclk,
138 rx_data_valid_gmux_reg_clk,
139 // TxMac related output signals
140 paused_state_sync,
141 set_tx_pkt_ok_sync,
142 txfifo_xfr_err_sync,
143 tx_max_pkt_size_err_sync,
144 toggle_tx_bcount_sync,
145 toggle_txframe_count_sync,
146 tx_enable_txclk,
147 tx_output_en_txclk,
148 tx_output_en_nbclk,
149 tx_data_valid_clk,
150 // lfs related output signals
151 lfs_disable_rxclk,
152 inc_link_fault_count_sync,
153 remote_fault_oc_sync,
154 local_fault_oc_sync,
155 remote_fault_oc_txclk,
156 local_fault_oc_txclk
157 );
158
159 input clk;
160 input rx_clk;
161 input rx_nbclk;
162 input tx_clk;
163 input tx_nbclk;
164 input rx_reset_clk;
165 input tx_reset_clk;
166 input hw_reset;
167 // fifo related input signals
168 input [4:0] rxfifo_g_rd_ptr_clk; // from clk domain
169 input [4:0] rxfifo_g_wr_ptr_rxclk; // from rx_clk domain
170 input rxfifo_overrun_rxclk; // from rx_clk domain
171 input [4:0] txfifo_g_rd_ptr_txclk; // from tx_clk domain
172 input [4:0] txfifo_g_wr_ptr_clk; // from clk domain
173 input txfifo_underrun_txclk; // from tx_clk domain
174 input [4:0] stfifo_g_rd_ptr_txclk; // from tx_clk domain
175 input [4:0] stfifo_g_wr_ptr_clk; // from clk domain
176 input [4:0] srfifo_g_wr_ptr_rxclk; // from rx_clk domain
177 // RxMac related input signals
178 input rx_good_pkt;
179 input rx_fc_pkt_ok; // from rx_clk domain
180 input inc_max_pkt_err_count;
181 input inc_min_pkt_err_count;
182 input inc_code_viol_count;
183 input inc_align_err_count_nbclk;
184 input inc_crc_err_count;
185 input toggle_rx_bcount;
186 input inc_bcast_count;
187 input inc_mcast_count;
188 input rx_enable;
189 input rxfifo_full_rxclk_reg;
190 input rx_data_valid_gmux_reg;
191 // TxMac related input signlas
192 input paused_state;
193 input set_tx_pkt_ok;
194 input txfifo_xfr_err;
195 input tx_max_pkt_size_err;
196 input toggle_tx_bcount;
197 input toggle_txframe_count;
198 input tx_enable;
199 input tx_output_en;
200 input tx_data_valid;
201 // lfs related input signals
202 input lfs_disable;
203 input inc_link_fault_count;
204 input remote_fault_oc_reg;
205 input local_fault_oc_reg;
206// outputs
207 output rx_reset; // to rx_clk domain
208 output tx_reset; // to tx_clk domain
209 output clr_rx_reset_clk; // to clk domain
210 output clr_tx_reset_clk; // to clk domain
211 output hw_reset_rxnbclk; // to rx_nbclk domain
212 output hw_reset_txnbclk; // to tx_nbclk domain
213 output rx_reset_nbclk; // to rx_nbclk domain
214 output tx_reset_nbclk; // to tx_nbclk domain
215 // fifo related output signals
216 output [4:0] rxfifo_g_rd_ptr_sync; // to rx_clk domain
217 output [4:0] rxfifo_g_wr_ptr_sync; // to clk domain
218 output rxfifo_overrun_sync; // to clk domain
219 output [4:0] txfifo_g_rd_ptr_sync; // to clk domain
220 output [4:0] txfifo_g_wr_ptr_sync; // to tx_clk domain
221 output txfifo_underrun_sync; // to clk domain
222 output [4:0] stfifo_g_rd_ptr_sync; // to clk domain
223 output [4:0] stfifo_g_wr_ptr_sync; // to tx_clk domain
224 output [4:0] srfifo_g_wr_ptr_sync; // to clk domain
225 // RxMac related output signals
226 output rx_good_pkt_sync; // to xmac_slv.v
227 output rx_fc_pkt_ok_txclk; // to tx_xmac.v
228 output rx_fc_pkt_ok_clk; // to xmac_slv.v
229 output inc_max_pkt_err_count_sync;
230 output inc_min_pkt_err_count_sync;
231 output inc_code_viol_count_sync;
232 output inc_align_err_count_sync;
233 output inc_crc_err_count_sync;
234 output toggle_rx_bcount_sync;
235 output inc_bcast_count_sync;
236 output inc_mcast_count_sync;
237 output rx_enable_rxclk;
238 output rx_enable_nbclk;
239 output rxfifo_full_nbclk;
240 output rx_data_valid_gmux_reg_clk;
241 // TxMac related output signals
242 output paused_state_sync;
243 output set_tx_pkt_ok_sync;
244 output txfifo_xfr_err_sync;
245 output tx_max_pkt_size_err_sync;
246 output toggle_tx_bcount_sync;
247 output toggle_txframe_count_sync;
248 output tx_enable_txclk;
249 output tx_output_en_txclk;
250 output tx_output_en_nbclk;
251 output tx_data_valid_clk;
252 // lfs related input signals
253 output lfs_disable_rxclk;
254 output inc_link_fault_count_sync;
255 output remote_fault_oc_sync;
256 output local_fault_oc_sync;
257 output remote_fault_oc_txclk; // to tx_xmac to generate idle
258 output local_fault_oc_txclk; // to tx_xmac to generate RF
259
260 //
261 wire rx_reset;
262 wire hw_reset_rxnbclk;
263 wire rx_reset_nbclk;
264 wire tx_reset;
265 wire hw_reset_txnbclk;
266 wire tx_reset_nbclk;
267 wire clr_rx_reset_rxclk;
268 wire clr_tx_reset_txclk;
269
270/**********************************************************************
271 * RXMAC fifo section
272 *********************************************************************/
273
274 /* ---------------- from clk to rx_clk -------------------------- */
275
276 // start 5bit rxfifo_g_rd_ptr_sync
277SYNC_5bit rxfifo_g_rd_ptr_sync_SYNC_5bit (
278 .din(rxfifo_g_rd_ptr_clk),
279 .clk(rx_clk),
280 .qout(rxfifo_g_rd_ptr_sync));
281
282 /* ---------------- from rx_clk to clk --------------------------- */
283
284 // start 5-bit rxfifo_g_wr_ptr_sync
285SYNC_5bit rxfifo_g_wr_ptr_sync_SYNC_5bit (
286 .din(rxfifo_g_wr_ptr_rxclk),
287 .clk(clk),
288 .qout(rxfifo_g_wr_ptr_sync));
289
290SYNC_5bit srfifo_g_wr_ptr_sync_SYNC_5bit (
291 .din(srfifo_g_wr_ptr_rxclk),
292 .clk(clk),
293 .qout(srfifo_g_wr_ptr_sync));
294
295/**********************************************************************
296 * TXMAC fifo section
297 *********************************************************************/
298
299 /* ---------------- from tx_clk to clk --------------------------- */
300 // start 5-bit txfifo_g_rd_ptr_sync
301
302SYNC_5bit txfifo_g_rd_ptr_sync_SYNC_5bit (
303 .din(txfifo_g_rd_ptr_txclk[4:0]),
304 .clk(clk),
305 .qout(txfifo_g_rd_ptr_sync[4:0]));
306
307
308 /* ---------------- from clk to tx_clk --------------------------- */
309
310 // start 5-bit txfifo_g_wr_ptr_sync
311SYNC_5bit txfifo_g_wr_ptr_sync_SYNC_5bit (
312 .din(txfifo_g_wr_ptr_clk[4:0]),
313 .clk(tx_clk),
314 .qout(txfifo_g_wr_ptr_sync[4:0]));
315
316 /* ---------------- from tx_clk to clk --------------------------- */
317 // start 5-bit stfifo_g_rd_ptr_sync
318
319SYNC_5bit stfifo_g_rd_ptr_sync_SYNC_5bit (
320 .din(stfifo_g_rd_ptr_txclk[4:0]),
321 .clk(clk),
322 .qout(stfifo_g_rd_ptr_sync[4:0]));
323
324 /* ---------------- from clk to tx_clk --------------------------- */
325
326 // start 5-bit stfifo_g_wr_ptr_sync
327SYNC_5bit stfifo_g_wr_ptr_sync_SYNC_5bit (
328 .din(stfifo_g_wr_ptr_clk[4:0]),
329 .clk(tx_clk),
330 .qout(stfifo_g_wr_ptr_sync[4:0]));
331
332
333 /* --------------------------- rx_clk to clk --------------------- */
334 SYNC_PLS rx_good_pkt_sync_SYNC_PLS(.src_pls(rx_good_pkt),
335 .src_clk(rx_clk),
336 .src_reset(rx_reset),
337 .des_clk(clk),
338 .out_pls(rx_good_pkt_sync));
339
340 SYNC_PLS rx_fc_pkt_ok_clk_SYNC_PLS(.src_pls(rx_fc_pkt_ok),
341 .src_clk(rx_clk),
342 .src_reset(rx_reset),
343 .des_clk(clk),
344 .out_pls(rx_fc_pkt_ok_clk));
345
346 SYNC_PLS inc_max_pkt_err_count_sync_SYNC_PLS(.src_pls(inc_max_pkt_err_count),
347 .src_clk(rx_clk),
348 .src_reset(rx_reset),
349 .des_clk(clk),
350 .out_pls(inc_max_pkt_err_count_sync));
351
352 SYNC_PLS inc_min_pkt_err_count_sync_SYNC_PLS(.src_pls(inc_min_pkt_err_count),
353 .src_clk(rx_clk),
354 .src_reset(rx_reset),
355 .des_clk(clk),
356 .out_pls(inc_min_pkt_err_count_sync));
357
358 SYNC_PLS inc_code_viol_count_sync_SYNC_PLS(.src_pls(inc_code_viol_count),
359 .src_clk(rx_clk),
360 .src_reset(rx_reset),
361 .des_clk(clk),
362 .out_pls(inc_code_viol_count_sync));
363
364 SYNC_PLS inc_align_err_count_sync_SYNC_PLS(.src_pls(inc_align_err_count_nbclk),
365 .src_clk(rx_clk),
366 .src_reset(rx_reset),
367 .des_clk(clk),
368 .out_pls(inc_align_err_count_sync));
369
370 SYNC_PLS rxfifo_overrun_sync_SYNC_PLS(.src_pls(rxfifo_overrun_rxclk),
371 .src_clk(rx_clk),
372 .src_reset(rx_reset),
373 .des_clk(clk),
374 .out_pls(rxfifo_overrun_sync));
375
376 SYNC_PLS inc_crc_err_count_SYNC_PLS(.src_pls(inc_crc_err_count),
377 .src_clk(rx_clk),
378 .src_reset(rx_reset),
379 .des_clk(clk),
380 .out_pls(inc_crc_err_count_sync));
381
382 SYNC_CELL TOG_RX_BCNT_SYNC(.D(toggle_rx_bcount),.CP(clk),
383 .Q(toggle_rx_bcount_sync));
384
385 SYNC_PLS inc_bcast_count_sync_SYNC_PLS(.src_pls(inc_bcast_count),
386 .src_clk(rx_clk),
387 .src_reset(rx_reset),
388 .des_clk(clk),
389 .out_pls(inc_bcast_count_sync));
390
391 SYNC_PLS inc_mcast_count_sync_SYNC_PLS(.src_pls(inc_mcast_count),
392 .src_clk(rx_clk),
393 .src_reset(rx_reset),
394 .des_clk(clk),
395 .out_pls(inc_mcast_count_sync));
396
397 SYNC_CELL rx_data_valid_gmux_reg_clk_SYNC(
398 .D(rx_data_valid_gmux_reg),.CP(clk),
399 .Q(rx_data_valid_gmux_reg_clk));
400
401
402 // lfs related input signals
403 SYNC_PLS inc_link_fault_count_sync_SYNC_PLS(.src_pls(inc_link_fault_count),
404 .src_clk(rx_clk),
405 .src_reset(rx_reset),
406 .des_clk(clk),
407 .out_pls(inc_link_fault_count_sync));
408
409 SYNC_CELL remote_fault_oc_sync_SYNC(.D(remote_fault_oc_reg),.CP(clk),
410 .Q(remote_fault_oc_sync));
411
412 SYNC_CELL local_fault_oc_sync_SYNC(.D(local_fault_oc_reg),.CP(clk),
413 .Q(local_fault_oc_sync));
414
415 /* ---------------------- rx_clk to rx_nbclk --------------------- */
416 SYNC_CELL rxfifo_full_nbclk_SYNC_CELL (.D(rxfifo_full_rxclk_reg),
417 .CP(rx_nbclk),
418 .Q(rxfifo_full_nbclk));
419
420 /* -------------------------- clk to rx_clk ---------------------- */
421 SYNC_CELL SYNC_RX_RESET(.D(rx_reset_clk),.CP(rx_clk),
422 .Q(rx_reset));
423
424// logic vision complains the back to back NEC synchronizer
425// cell connection.
426// SYNC_CELL clr_rx_reset_rxclk_SYNC(.D(rx_reset),
427// .CP(rx_clk),
428// .Q(clr_rx_reset_rxclk));
429// the following DFF is for delaying one tx_clk purpose.
430 FD1 clr_rx_reset_rxclk_FD1(.CP(rx_clk),.D(rx_reset),
431 .Q(clr_rx_reset_rxclk));
432
433 SYNC_CELL SYNC_CLR_RX_RESET(.D(clr_rx_reset_rxclk),
434 .CP(clk),
435 .Q(clr_rx_reset_clk));
436
437 SYNC_CELL rx_enable_rxclk_SYNC(.D(rx_enable),.CP(rx_clk),
438 .Q(rx_enable_rxclk));
439
440 SYNC_CELL lfs_disable_rxclk_SYNC(.D(lfs_disable),
441 .CP(rx_clk),
442 .Q(lfs_disable_rxclk));
443
444 /* -------------------------- clk to rx_nbclk --------------------- */
445 SYNC_CELL hw_reset_rxnbclk_SYNC(.D(hw_reset),
446 .CP(rx_nbclk),
447 .Q(hw_reset_rxnbclk));
448
449 SYNC_CELL rx_reset_nbclk_SYNC(.D(rx_reset_clk),
450 .CP(rx_nbclk),
451 .Q(rx_reset_nbclk));
452
453 SYNC_CELL rx_enable_nbclk_SYNC(.D(rx_enable),
454 .CP(rx_nbclk),
455 .Q(rx_enable_nbclk));
456
457 /* ---------------------- rx_clk to tx_clk ----------------------- */
458 SYNC_PLS rx_fc_pkt_ok_txclk_SYNC_PLS(.src_pls(rx_fc_pkt_ok),
459 .src_clk(rx_clk),
460 .src_reset(rx_reset),
461 .des_clk(tx_clk),
462 .out_pls(rx_fc_pkt_ok_txclk));
463// to tx_xmac to generate IDLE
464 SYNC_CELL remote_fault_oc_txclk_SYNC(.D(remote_fault_oc_reg),.CP(tx_clk),
465 .Q(remote_fault_oc_txclk));
466// to tx_xmac to generate RF
467 SYNC_CELL local_fault_oc_txclk_SYNC(.D(local_fault_oc_reg),.CP(tx_clk),
468 .Q(local_fault_oc_txclk));
469
470 /* --------------------------- tx_clk to clk --------------------- */
471 SYNC_CELL PAUSED_SNC(.D(paused_state),.CP(clk),.Q(paused_state_sync));
472
473 SYNC_PLS TX_PKT_OK_SYNC_PLS(.src_pls(set_tx_pkt_ok),
474 .src_clk(tx_clk),
475 .src_reset(tx_reset),
476 .des_clk(clk),
477 .out_pls(set_tx_pkt_ok_sync));
478
479 SYNC_PLS txfifo_underrun_sync_SYNC_PLS(.src_pls(txfifo_underrun_txclk),
480 .src_clk(tx_clk),
481 .src_reset(tx_reset),
482 .des_clk(clk),
483 .out_pls(txfifo_underrun_sync));
484
485 SYNC_PLS txfifo_xfr_err_syn_SYNC_PLS(.src_pls(txfifo_xfr_err),
486 .src_clk(tx_clk),
487 .src_reset(tx_reset),
488 .des_clk(clk),
489 .out_pls(txfifo_xfr_err_sync));
490
491 SYNC_PLS tx_max_pkt_size_err_syn_SYNC_PLS(.src_pls(tx_max_pkt_size_err),
492 .src_clk(tx_clk),
493 .src_reset(tx_reset),
494 .des_clk(clk),
495 .out_pls(tx_max_pkt_size_err_sync));
496
497 SYNC_CELL TOG_TX_BCNT_SYNC(.D(toggle_tx_bcount),.CP(clk),
498 .Q(toggle_tx_bcount_sync));
499
500 SYNC_CELL TOG_TX_FRAME_SYNC(.D(toggle_txframe_count),.CP(clk),
501 .Q(toggle_txframe_count_sync));
502
503 SYNC_CELL tx_data_valid_clk_SYNC(.D(tx_data_valid),.CP(clk),
504 .Q(tx_data_valid_clk));
505
506 /* -------------------------- clk to tx_clk ---------------------- */
507 SYNC_CELL TX_CLK_RESET_SYNC(.D(tx_reset_clk),.CP(tx_clk),.Q(tx_reset));
508
509// logic vision complains the back to back NEC synchronizer
510// cell connection.
511// SYNC_CELL clr_tx_reset_txclk_SYNC(.D(tx_reset),
512// .CP(tx_clk),
513// .Q(clr_tx_reset_txclk));
514// the following DFF is for delaying one tx_clk purpose.
515 FD1 clr_rx_reset_txclk_FD1(.CP(tx_clk), .D(tx_reset), .Q(clr_tx_reset_txclk));
516
517 SYNC_CELL SYNC_CLR_TX_RESET(.D(clr_tx_reset_txclk),
518 .CP(clk),
519 .Q(clr_tx_reset_clk));
520
521 SYNC_CELL tx_enable_txclk_SYNC(.D(tx_enable),
522 .CP(tx_clk),
523 .Q(tx_enable_txclk));
524
525 SYNC_CELL tx_output_en_txclk_SYNC(.D(tx_output_en),
526 .CP(tx_clk),
527 .Q(tx_output_en_txclk));
528
529 /* -------------------------- clk to tx_nbclk --------------------- */
530 SYNC_CELL hw_reset_txnbclk_SYNC(.D(hw_reset),
531 .CP(tx_nbclk),
532 .Q(hw_reset_txnbclk));
533
534 SYNC_CELL tx_reset_nbclk_SYNC(.D(tx_reset_clk),
535 .CP(tx_nbclk),
536 .Q(tx_reset_nbclk));
537
538 SYNC_CELL tx_output_en_nbclk_SYNC(.D(tx_output_en),
539 .CP(tx_nbclk),
540 .Q(tx_output_en_nbclk));
541
542 /* -------------------------- tx_nbclk to clk --------------------- */
543 /* ---------------------------------------------------------------- */
544 /* -------------------------- clk to tx_nbclk --------------------- */
545 /* -------------------------- tx_clk to rx_clk -------------------- */
546
547endmodule // xmac_sync
548
Full OpenSPARC design & verification tarball including full HDL.