Initial commit of OpenSPARC T2 design and verification files.

[OpenSPARC-T2-DV] / design / sys / iop / niu / rtl / xpcs_dbg.v

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// 
// OpenSPARC T2 Processor File: xpcs_dbg.v
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module xpcs_dbg (csr_vendor_debug_sel,
                 training_vector,
                 rx0_debug,
                 rx1_debug,
                 rx2_debug,
                 rx3_debug,
                 tx0_debug,
                 tx1_debug,
                 tx2_debug,
                 tx3_debug,
                 xpcs_debug);

input  [3:0]  csr_vendor_debug_sel;
input  [31:0] training_vector;
input  [31:0] rx0_debug;
input  [31:0] rx1_debug;
input  [31:0] rx2_debug;
input  [31:0] rx3_debug;

input  [31:0] tx0_debug;
input  [31:0] tx1_debug;
input  [31:0] tx2_debug;
input  [31:0] tx3_debug;

output [31:0] xpcs_debug;

reg [31:0] xpcs_debug;

always @ (csr_vendor_debug_sel or rx0_debug or rx1_debug or rx2_debug or
          rx3_debug or tx0_debug or tx1_debug or tx2_debug or tx3_debug or
          training_vector)
    case (csr_vendor_debug_sel[3:0]) // synopsys parallel_case infer_mux
     4'h0 : xpcs_debug = rx0_debug; 
     4'h1 : xpcs_debug = rx1_debug;
     4'h2 : xpcs_debug = rx2_debug;
     4'h3 : xpcs_debug = rx3_debug;
     4'h4 : xpcs_debug = tx0_debug;
     4'h5 : xpcs_debug = tx1_debug;
     4'h6 : xpcs_debug = tx2_debug;
     4'h7 : xpcs_debug = tx3_debug;
     `SEL_xpcs_training_vector: xpcs_debug = training_vector;
   default: xpcs_debug = rx0_debug;

   endcase

endmodule