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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / design / sys / iop / niu / rtl / xpcs_rxio.v
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AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: xpcs_rxio.v
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
19// along with this program; if not, write to the Free Software
20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
23// choice is available it will apply instead, Sun elects to use only
24// the General Public License version 2 (GPLv2) at this time for any
25// software where a choice of GPL license versions is made
26// available with the language indicating that GPLv2 or any later version
27// may be used, or where a choice of which version of the GPL is applied is
28// otherwise unspecified.
29//
30// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
31// CA 95054 USA or visit www.sun.com if you need additional information or
32// have any questions.
33//
34// ========== Copyright Header End ============================================
35// ****************************************************************
36//
37// Sun Proprietary/Confidential: Internal Use Only
38//
39// ****************************************************************
40// Design: XPCS PMA Interface Core
41// Block: XPCS PMA Interface Core Top Level
42// Author: Carlos Castil
43//
44// Module: xpcs_rxio
45// File: xpcs_rxio.v
46//
47// Description: This block contains an X4 receive physical
48// interface.
49//
50// Revision History
51// ------------------------------------------------------------
52// Ver Date Comments
53// ------------------------------------------------------------
54// 1.0 09/20/02 Created
55//
56// ****************************************************************
57
58module xpcs_rxio (
59
60 core_clk,
61
62 reset_rxclk,
63
64 rx_signal_detect,
65
66 rx_byte_0,
67 rx_byte_1,
68 rx_byte_2,
69 rx_byte_3,
70
71 rx_special_0,
72 rx_special_1,
73 rx_special_2,
74 rx_special_3,
75
76 rx_error_0,
77 rx_error_1,
78 rx_error_2,
79 rx_error_3,
80
81 rx_wclk_a,
82 rx_symbol_a,
83
84 rx_wclk_b,
85 rx_symbol_b,
86
87 rx_wclk_c,
88 rx_symbol_c,
89
90 rx_wclk_d,
91 rx_symbol_d,
92
93 csr_lane_sync_status,
94
95 csr_lane_sync_state0,
96 csr_lane_sync_state1,
97 csr_lane_sync_state2,
98 csr_lane_sync_state3,
99
100 csr_link_status,
101 csr_link_status_rx,
102 csr_pulse_deskew_error,
103 csr_ebuffer_state
104
105 );
106
107input reset_rxclk;
108
109input core_clk;
110
111input [3:0] rx_signal_detect;
112
113output [7:0] rx_byte_0;
114output [7:0] rx_byte_1;
115output [7:0] rx_byte_2;
116output [7:0] rx_byte_3;
117
118output rx_special_0;
119output rx_special_1;
120output rx_special_2;
121output rx_special_3;
122
123output rx_error_0;
124output rx_error_1;
125output rx_error_2;
126output rx_error_3;
127
128input rx_wclk_a;
129input [9:0] rx_symbol_a;
130
131input rx_wclk_b;
132input [9:0] rx_symbol_b;
133
134input rx_wclk_c;
135input [9:0] rx_symbol_c;
136
137input rx_wclk_d;
138input [9:0] rx_symbol_d;
139
140output csr_link_status;
141output csr_link_status_rx;
142output [3:0] csr_lane_sync_status;
143
144output csr_pulse_deskew_error;
145output [7:0] csr_ebuffer_state;
146
147output [3:0] csr_lane_sync_state0;
148output [3:0] csr_lane_sync_state1;
149output [3:0] csr_lane_sync_state2;
150output [3:0] csr_lane_sync_state3;
151
152
153wire rx_wclk_a;
154wire rx_wclk_b;
155wire rx_wclk_c;
156wire rx_wclk_d;
157
158wire [7:0] w_byte_0;
159wire [7:0] w_byte_1;
160wire [7:0] w_byte_2;
161wire [7:0] w_byte_3;
162
163wire w_special_0;
164wire w_special_1;
165wire w_special_2;
166wire w_special_3;
167
168wire w_error_0;
169wire w_error_1;
170wire w_error_2;
171wire w_error_3;
172
173wire flush;
174
175wire w_hold_0;
176wire w_hold_1;
177wire w_hold_2;
178wire w_hold_3;
179
180wire sync_status;
181
182wire reset_rxclk_0;
183wire reset_rxclk_1;
184wire reset_rxclk_2;
185wire reset_rxclk_3;
186
187wire signal_detect_0;
188wire signal_detect_1;
189wire signal_detect_2;
190wire signal_detect_3;
191
192wire rx_clk;
193
194wire csr_lane_sync_status_lane0;
195wire csr_lane_sync_status_lane1;
196wire csr_lane_sync_status_lane2;
197wire csr_lane_sync_status_lane3;
198
199wire [3:0] lane_sync_status;
200
201assign rx_clk = rx_wclk_a;
202
203// **********************************************
204// synchronize each rx lane sync status to rx_clk
205// **********************************************
206
207SYNC_CELL u_sync_rx_status_lane0 (
208 .D (csr_lane_sync_status_lane0), // unsynchronized sync_status
209 .CP (rx_clk),
210 .Q (lane_sync_status[0])); // synchronized sync_status
211
212SYNC_CELL u_sync_rx_status_lane1 (
213 .D (csr_lane_sync_status_lane1), // unsynchronized sync_status
214 .CP (rx_clk),
215 .Q (lane_sync_status[1])); // synchronized sync_status
216
217SYNC_CELL u_sync_rx_status_lane2 (
218 .D (csr_lane_sync_status_lane2), // unsynchronized sync_status
219 .CP (rx_clk),
220 .Q (lane_sync_status[2])); // synchronized sync_status
221
222SYNC_CELL u_sync_rx_status_lane3 (
223 .D (csr_lane_sync_status_lane3), // unsynchronized sync_status
224 .CP (rx_clk),
225 .Q (lane_sync_status[3])); // synchronized sync_status
226
227assign sync_status = lane_sync_status[0] & lane_sync_status[1] & lane_sync_status[2] & lane_sync_status[3];
228
229// ***************************************
230// synchronize rx sync_status to core_clk
231// ***************************************
232
233SYNC_CELL u_sync_core_status_lane0 (
234 .D (csr_lane_sync_status_lane0), // unsynchronized sync_status
235 .CP (core_clk),
236 .Q (csr_lane_sync_status[0])); // synchronized sync_status
237
238SYNC_CELL u_sync_core_status_lane1 (
239 .D (csr_lane_sync_status_lane1), // unsynchronized sync_status
240 .CP (core_clk),
241 .Q (csr_lane_sync_status[1])); // synchronized sync_status
242
243SYNC_CELL u_sync_core_status_lane2 (
244 .D (csr_lane_sync_status_lane2), // unsynchronized sync_status
245 .CP (core_clk),
246 .Q (csr_lane_sync_status[2])); // synchronized sync_status
247
248SYNC_CELL u_sync_core_status_lane3 (
249 .D (csr_lane_sync_status_lane3), // unsynchronized sync_status
250 .CP (core_clk),
251 .Q (csr_lane_sync_status[3])); // synchronized sync_status
252
253// ***************************************
254// synchronize link status to core_clk
255// ***************************************
256
257SYNC_CELL u_sync_link_status_core (
258 .D (csr_link_status_rx), // unsynchronized sync_status
259 .CP (core_clk),
260 .Q (csr_link_status)); // synchronized sync_status
261
262// ***************************************
263// synchronize signal_detect to rx clocks
264// ***************************************
265
266SYNC_CELL u_sync_signal_detect_lane0 (
267 .D (rx_signal_detect[0]), // unsynchronized sync_status
268 .CP (rx_wclk_a),
269 .Q (signal_detect_0)); // synchronized sync_status
270
271SYNC_CELL u_sync_signal_detect_lane1 (
272 .D (rx_signal_detect[1]), // unsynchronized sync_status
273 .CP (rx_wclk_b),
274 .Q (signal_detect_1)); // synchronized sync_status
275
276SYNC_CELL u_sync_signal_detect_lane2 (
277 .D (rx_signal_detect[2]), // unsynchronized sync_status
278 .CP (rx_wclk_c),
279 .Q (signal_detect_2)); // synchronized sync_status
280
281SYNC_CELL u_sync_signal_detect_lane3 (
282 .D (rx_signal_detect[3]), // unsynchronized sync_status
283 .CP (rx_wclk_d),
284 .Q (signal_detect_3)); // synchronized sync_status
285
286// ***************************************
287// synchronize reset_rxclk to lane domains
288// ***************************************
289
290SYNC_CELL u_sync_reset_0 (
291 .D (reset_rxclk), // unsynchronized
292 .CP (rx_wclk_a),
293 .Q (reset_rxclk_0) ); // synchronized
294
295SYNC_CELL u_sync_reset_1 (
296 .D (reset_rxclk), // unsynchronized
297 .CP (rx_wclk_b),
298 .Q (reset_rxclk_1) ); // synchronized
299
300SYNC_CELL u_sync_reset_2 (
301 .D (reset_rxclk), // unsynchronized
302 .CP (rx_wclk_c),
303 .Q (reset_rxclk_2) ); // synchronized
304
305SYNC_CELL u_sync_reset_3 (
306 .D (reset_rxclk), // unsynchronized
307 .CP (rx_wclk_d),
308 .Q (reset_rxclk_3) ); // synchronized
309
310
311// Elastic Buffer
312
313xpcs_rxio_ebuffer u_ebuffer (
314 .rx_clk (rx_clk),
315 .reset (reset_rxclk),
316
317 .csr_link_status (csr_link_status_rx),
318 .sync_status (sync_status),
319 .csr_pulse_deskew_error (csr_pulse_deskew_error),
320 .csr_ebuffer_state (csr_ebuffer_state),
321
322 .w_byte_0 (w_byte_0),
323 .w_byte_1 (w_byte_1),
324 .w_byte_2 (w_byte_2),
325 .w_byte_3 (w_byte_3),
326
327 .w_special_0 (w_special_0),
328 .w_special_1 (w_special_1),
329 .w_special_2 (w_special_2),
330 .w_special_3 (w_special_3),
331
332 .w_error_0 (w_error_0),
333 .w_error_1 (w_error_1),
334 .w_error_2 (w_error_2),
335 .w_error_3 (w_error_3),
336
337 .flush (flush),
338
339 .w_hold_0 (w_hold_0),
340 .w_hold_1 (w_hold_1),
341 .w_hold_2 (w_hold_2),
342 .w_hold_3 (w_hold_3),
343
344 .r_byte_0 (rx_byte_0),
345 .r_byte_1 (rx_byte_1),
346 .r_byte_2 (rx_byte_2),
347 .r_byte_3 (rx_byte_3),
348
349 .r_special_0 (rx_special_0),
350 .r_special_1 (rx_special_1),
351 .r_special_2 (rx_special_2),
352 .r_special_3 (rx_special_3),
353
354 .r_error_0 (rx_error_0),
355 .r_error_1 (rx_error_1),
356 .r_error_2 (rx_error_2),
357 .r_error_3 (rx_error_3) );
358
359// lane 0
360
361xpcs_rxio_sync rxio_sync_lane_0 (
362 .rx_clk (rx_clk),
363 .reset_rxclk (reset_rxclk),
364 .reset_rxclk_lane (reset_rxclk_0),
365
366 .flush (flush), // from DESKEW
367 .rx_signal_detect (signal_detect_0),
368
369 .hold (w_hold_0), // from DESKEW
370
371 .byte_out (w_byte_0), // from DESKEW
372 .special_out (w_special_0), // from DESKEW
373 .error_out (w_error_0), // from DESKEW
374
375 .csr_lane_sync_status (csr_lane_sync_status_lane0),
376 .csr_lane_sync_state (csr_lane_sync_state0),
377
378 .symbol_in (rx_symbol_a),
379
380 .rx_lane_clk (rx_wclk_a) );
381
382// lane 1 : Byte 1 and Byte 5
383
384xpcs_rxio_sync rxio_sync_lane_1 (
385 .rx_clk (rx_clk),
386 .reset_rxclk (reset_rxclk),
387 .reset_rxclk_lane (reset_rxclk_1),
388
389 .flush (flush), // from DESKEW
390 .rx_signal_detect (signal_detect_1),
391
392 .hold (w_hold_1), // from DESKEW
393
394 .byte_out (w_byte_1), // from DESKEW
395 .special_out (w_special_1), // from DESKEW
396 .error_out (w_error_1), // from DESKEW
397
398 .csr_lane_sync_status (csr_lane_sync_status_lane1),
399 .csr_lane_sync_state (csr_lane_sync_state1),
400
401
402 .symbol_in (rx_symbol_b),
403
404 .rx_lane_clk (rx_wclk_b) );
405
406// lane 2 : Byte 2 and Byte 6
407
408xpcs_rxio_sync rxio_sync_lane_2 (
409 .rx_clk (rx_clk),
410 .reset_rxclk (reset_rxclk),
411 .reset_rxclk_lane (reset_rxclk_2),
412
413
414 .flush (flush), // from DESKEW
415 .rx_signal_detect (signal_detect_2),
416
417 .hold (w_hold_2), // from DESKEW
418
419 .byte_out (w_byte_2), // from DESKEW
420 .special_out (w_special_2), // from DESKEW
421 .error_out (w_error_2), // from DESKEW
422
423 .csr_lane_sync_status (csr_lane_sync_status_lane2),
424 .csr_lane_sync_state (csr_lane_sync_state2),
425
426 .symbol_in (rx_symbol_c),
427
428 .rx_lane_clk (rx_wclk_c) );
429
430
431// lane 3 : Byte 3 and Byte 7
432
433xpcs_rxio_sync rxio_sync_lane_3 (
434 .rx_clk (rx_clk),
435 .reset_rxclk (reset_rxclk),
436 .reset_rxclk_lane (reset_rxclk_3),
437
438 .flush (flush), // from DESKEW
439 .rx_signal_detect (signal_detect_3),
440
441 .hold (w_hold_3), // from DESKEW
442
443 .byte_out (w_byte_3), // from DESKEW
444 .special_out (w_special_3), // from DESKEW
445 .error_out (w_error_3), // from DESKEW
446
447 .csr_lane_sync_status (csr_lane_sync_status_lane3),
448 .csr_lane_sync_state (csr_lane_sync_state3),
449
450 .symbol_in (rx_symbol_d),
451
452 .rx_lane_clk (rx_wclk_d) );
453
454endmodule
Full OpenSPARC design & verification tarball including full HDL.