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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / design / sys / iop / niu / rtl / xpcs_rxio_sync_decoder.v
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AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: xpcs_rxio_sync_decoder.v
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
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8//
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10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
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15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
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32// have any questions.
33//
34// ========== Copyright Header End ============================================
35// ****************************************************************
36//
37// Sun Proprietary/Confidential: Internal Use Only
38//
39// ****************************************************************
40// Design: IB Physical Interface Core
41// Block: IB 10b8b Decoder
42// Author: Carlos Castil
43//
44// Module: xpcs_rxio_sync_decoder
45// File: xpcs_rxio_sync_decoder.v
46//
47// Description: This block performs 10b8b decoding on incomming
48// symbols.
49//
50//
51// Revision History
52// ------------------------------------------------------------
53// Ver Date Comments
54// ------------------------------------------------------------
55// 1.0 9/24/02 Created
56// ****************************************************************
57
58
59
60module xpcs_rxio_sync_decoder (
61 rx_lane_clk,
62 rx_lane_reset,
63 rx_symbol,
64
65 byte,
66 special,
67 error);
68
69
70input rx_lane_clk; // rx_lane_clk, 250 MHz
71input rx_lane_reset;
72
73input [9:0] rx_symbol; // receive encoded 10 bit data
74
75output [7:0] byte; // decoded data byte
76output special; // decoded special characters
77output error; // decoded error
78
79// Wires and Regs which are not flops
80
81wire noneof6;
82wire oneof6;
83wire twoof6;
84wire threeof6;
85wire fourof6;
86wire fiveof6;
87wire sixof6; //no. of 1#s in data[9:4]
88wire noneof4;
89wire oneof4;
90wire twoof4;
91wire threeof4;
92wire fourof4; //no. of 1#s in data[3:0]
93wire pos_disp;
94wire newRD; // running disparity signals
95reg [7:0] deco1_fcn;
96reg [3:0] deco2_fcn;
97
98// Regs which are flops
99
100reg [9:0] symbol;
101reg RDreg; // running disparity register
102
103// Register symbol input
104
105always @ (posedge rx_lane_clk)
106 if (rx_lane_reset)
107 symbol <= 10'b0000000000;
108 else
109 symbol <= rx_symbol;
110
111// Register to hold running disparity
112
113always @ (posedge rx_lane_clk)
114 if (rx_lane_reset)
115 RDreg <= 1'b0;
116 else
117 RDreg <= pos_disp;
118
119
120// Instead just drive outputs
121
122assign byte = {deco2_fcn[3:1],deco1_fcn[7:3]};
123assign special = deco1_fcn[0];
124
125// Error Legend: Disparity | Decode | Decode
126assign error = (deco1_fcn[1] | deco2_fcn[0] | deco1_fcn[2]);
127
128// Running disparity calculator
129
130assign noneof4 = ~(symbol[0] | symbol[1] | symbol[2] | symbol[3]);
131
132assign fourof4 = (symbol[0] & symbol[1] & symbol[2] & symbol[3]);
133
134assign threeof4 = ((symbol[0]^symbol[1]) & (~(symbol[2]^symbol[3]) &
135 (symbol[2]&symbol[3]))) | ((symbol[2]^symbol[3]) &
136 (~(symbol[0]^symbol[1]) & (symbol[0]&symbol[1])));
137
138assign oneof4 = ((~symbol[0]^~symbol[1]) & (~(~symbol[2]^~symbol[3]) &
139 (~symbol[2]&~symbol[3]))) | ((~symbol[2]^~symbol[3]) &
140 (~(~symbol[0]^~symbol[1]) & (~symbol[0]&~symbol[1])));
141
142assign twoof4 = ((symbol[0]^symbol[1]) & (symbol[2]^symbol[3])) | ((symbol[0]&symbol[1]) ^ (symbol[2]&symbol[3]));
143
144assign noneof6 = ~(symbol[4] | symbol[5] | symbol[6] | symbol[7] | symbol[8] | symbol[9]);
145
146assign sixof6 = (symbol[4] & symbol[5] & symbol[6] & symbol[7] & symbol[8] & symbol[9]);
147
148assign fiveof6 = ( (((symbol[4]^symbol[5]) & (~(symbol[6]^symbol[7]) &
149 (symbol[6]&symbol[7]))) | ((symbol[6]^symbol[7]) &
150 (~(symbol[4]^symbol[5]) & (symbol[4]&symbol[5])))) &
151 (symbol[8] & symbol[9]) ) | ((symbol[4] & symbol[5] &
152 symbol[6] & symbol[7]) & (symbol[8] ^ symbol[9]));
153
154assign oneof6 = ( (((~symbol[4]^~symbol[5]) & (~(~symbol[6]^~symbol[7]) &
155 (~symbol[6]&~symbol[7]))) | ((~symbol[6]^~symbol[7]) &
156 (~(~symbol[4]^~symbol[5]) & (~symbol[4]&~symbol[5])))) &
157 (~symbol[8] & ~symbol[9]) ) |
158 ((~symbol[4] & ~symbol[5] & ~symbol[6] & ~symbol[7]) & (~symbol[8] ^ ~symbol[9]));
159
160assign fourof6 = ( (((symbol[4]^symbol[5]) & (symbol[6]^symbol[7])) |
161 ((symbol[4]&symbol[5]) ^ (symbol[6]&symbol[7]))) &
162 (symbol[8] & symbol[9]) ) | ( (((symbol[4]^symbol[5]) &
163 (~(symbol[6]^symbol[7]) & (symbol[6]&symbol[7]))) |
164 ((symbol[6]^symbol[7]) & (~(symbol[4]^symbol[5]) &
165 (symbol[4]&symbol[5])))) & (symbol[8] ^ symbol[9]) ) |
166 ( (symbol[4] & symbol[5] & symbol[6] & symbol[7]) &
167 (~(symbol[8]|symbol[9])) );
168
169assign twoof6 = ( (((~symbol[4]^~symbol[5]) & (~symbol[6]^~symbol[7])) |
170 ((~symbol[4]&~symbol[5]) ^ (~symbol[6]&~symbol[7]))) &
171 (~symbol[8] & ~symbol[9]) ) | ( (((~symbol[4]^~symbol[5]) &
172 (~(~symbol[6]^~symbol[7]) & (~symbol[6]&~symbol[7])))
173 | ((~symbol[6]^~symbol[7]) & (~(~symbol[4]^~symbol[5]) &
174 (~symbol[4]&~symbol[5])))) & (~symbol[8] ^ ~symbol[9]) ) |
175 ( (~symbol[4] & ~symbol[5] & ~symbol[6] & ~symbol[7]) &
176 (~(~symbol[8]|~symbol[9])) );
177
178assign threeof6 = ( (((~symbol[4]^~symbol[5]) & (~(~symbol[6]^~symbol[7]) &
179 (~symbol[6]&~symbol[7]))) | ((~symbol[6]^~symbol[7]) &
180 (~(~symbol[4]^~symbol[5]) & (~symbol[4]&~symbol[5])))) &
181 (symbol[8] & symbol[9]) ) | ( (((symbol[4]^symbol[5]) &
182 (symbol[6]^symbol[7])) |
183 ((symbol[4]&symbol[5]) ^ (symbol[6]&symbol[7]))) &
184 (symbol[8] ^ symbol[9]) ) | ( (((symbol[4]^symbol[5]) &
185 (~(symbol[6]^symbol[7]) & (symbol[6]&symbol[7])))
186 | ((symbol[6]^symbol[7]) & (~(symbol[4]^symbol[5]) &
187 (symbol[6]&symbol[7])))) & ( ~(symbol[8] | symbol[9])) );
188
189assign newRD = ((noneof6 | oneof6 | twoof6) |
190 (threeof6 & (symbol[9:4]==6'b111000))) ? 1'b0 :
191 ((fourof6 | fiveof6 | sixof6) | (threeof6 &
192 (symbol[9:4]==6'b000111))) ? 1'b1 : RDreg;
193
194assign pos_disp = ((noneof4 | oneof4) | (twoof4 &
195 (symbol[3:0]==4'b1100))) ? 1'b0 : ((threeof4 | fourof4)
196 | (twoof4 & (symbol[3:0]==4'b0011))) ? 1'b1 : newRD;
197
198// 6b5b decode on most significant bits of rx_10bdata
199// ~RDreg means that you can only get this code if the beginning
200// running disparity is one. So if zero, error is flagged.
201// RDreg means that you can only get this code if the beginning
202// running disparity is zero. So if one, error is flagged.
203// 1'b0 means that this code can be received whether the
204// running disparity is zero or one. So no check is done.
205//
206// The function output is:
207// deco1_fcn = {decodata[4:0], dec_err1, rderr, Kchar}
208
209always @ (symbol or RDreg)
210 case (symbol[9:4]) //synopsys parallel_case full_case
211 /* D0 + */ 6'b011000: deco1_fcn = {5'b00000, 1'b0, !RDreg, 1'b0};
212 /* D0 - */ 6'b100111: deco1_fcn = {5'b00000, 1'b0, RDreg, 1'b0};
213 /* D1 + */ 6'b100010: deco1_fcn = {5'b00001, 1'b0, !RDreg, 1'b0};
214 /* D1 - */ 6'b011101: deco1_fcn = {5'b00001, 1'b0, RDreg, 1'b0};
215 /* D2 + */ 6'b010010: deco1_fcn = {5'b00010, 1'b0, !RDreg, 1'b0};
216 /* D2 - */ 6'b101101: deco1_fcn = {5'b00010, 1'b0, RDreg, 1'b0};
217 /* D3 0 */ 6'b110001: deco1_fcn = {5'b00011, 1'b0, 1'b0, 1'b0};
218 /* D4 + */ 6'b001010: deco1_fcn = {5'b00100, 1'b0, !RDreg, 1'b0};
219 /* D4 - */ 6'b110101: deco1_fcn = {5'b00100, 1'b0, RDreg, 1'b0};
220 /* D5 0 */ 6'b101001: deco1_fcn = {5'b00101, 1'b0, 1'b0, 1'b0};
221 /* D6 0 */ 6'b011001: deco1_fcn = {5'b00110, 1'b0, 1'b0, 1'b0};
222 /* D7 + */ 6'b000111: deco1_fcn = {5'b00111, 1'b0, !RDreg, 1'b0};
223 /* D7 - */ 6'b111000: deco1_fcn = {5'b00111, 1'b0, RDreg, 1'b0};
224 /* D8 + */ 6'b000110: deco1_fcn = {5'b01000, 1'b0, !RDreg, 1'b0};
225 /* D8 - */ 6'b111001: deco1_fcn = {5'b01000, 1'b0, RDreg, 1'b0};
226 /* D9 0 */ 6'b100101: deco1_fcn = {5'b01001, 1'b0, 1'b0, 1'b0};
227 /* D10 0 */ 6'b010101: deco1_fcn = {5'b01010, 1'b0, 1'b0, 1'b0};
228 /* D11 0 */ 6'b110100: deco1_fcn = {5'b01011, 1'b0, 1'b0, 1'b0};// Has Weird AX 7
229 /* D12 0 */ 6'b001101: deco1_fcn = {5'b01100, 1'b0, 1'b0, 1'b0};
230 /* D13 0 */ 6'b101100: deco1_fcn = {5'b01101, 1'b0, 1'b0, 1'b0};// Has Weird AX 7
231 /* D14 0 */ 6'b011100: deco1_fcn = {5'b01110, 1'b0, 1'b0, 1'b0};// Has Weird AX 7
232 /* D15 + */ 6'b101000: deco1_fcn = {5'b01111, 1'b0, !RDreg, 1'b0};
233 /* D15 - */ 6'b010111: deco1_fcn = {5'b01111, 1'b0, RDreg, 1'b0};
234 /* D16 + */ 6'b100100: deco1_fcn = {5'b10000, 1'b0, !RDreg, 1'b0};
235 /* D16 - */ 6'b011011: deco1_fcn = {5'b10000, 1'b0, RDreg, 1'b0};
236 /* D17 0 */ 6'b100011: deco1_fcn = {5'b10001, 1'b0, 1'b0, 1'b0};// Has Weird AX 7
237 /* D18 0 */ 6'b010011: deco1_fcn = {5'b10010, 1'b0, 1'b0, 1'b0};// Has Weird AX 7
238 /* D19 0 */ 6'b110010: deco1_fcn = {5'b10011, 1'b0, 1'b0, 1'b0};
239 /* D20 0 */ 6'b001011: deco1_fcn = {5'b10100, 1'b0, 1'b0, 1'b0};// Has Weird 7
240 /* D21 0 */ 6'b101010: deco1_fcn = {5'b10101, 1'b0, 1'b0, 1'b0};
241 /* D22 0 */ 6'b011010: deco1_fcn = {5'b10110, 1'b0, 1'b0, 1'b0};
242 /* D23 + */ 6'b000101: deco1_fcn = {5'b10111, 1'b0, !RDreg, (symbol[3:0]==4'b0111)};// PAD (23.7)
243 /* D23 - */ 6'b111010: deco1_fcn = {5'b10111, 1'b0, RDreg, (symbol[3:0]==4'b1000)};// PAD (23.7)
244 /* D24 + */ 6'b001100: deco1_fcn = {5'b11000, 1'b0, !RDreg, 1'b0};
245 /* D24 - */ 6'b110011: deco1_fcn = {5'b11000, 1'b0, RDreg, 1'b0};
246 /* D25 0 */ 6'b100110: deco1_fcn = {5'b11001, 1'b0, 1'b0, 1'b0};
247 /* D26 0 */ 6'b010110: deco1_fcn = {5'b11010, 1'b0, 1'b0, 1'b0};
248 /* D27 + */ 6'b001001: deco1_fcn = {5'b11011, 1'b0, !RDreg, (symbol[3:0]==4'b0111)};// SDP (27.7)
249 /* D27 - */ 6'b110110: deco1_fcn = {5'b11011, 1'b0, RDreg, (symbol[3:0]==4'b1000)};// SDP (27.7)
250
251 /* D28 0 */ 6'b001110: deco1_fcn = {5'b11100, 1'b0, 1'b0, 1'b0};
252
253 /* D29 + */ 6'b010001: deco1_fcn = {5'b11101, 1'b0, !RDreg, (symbol[3:0]==4'b0111)};// EGP (29.7)
254 /* D29 - */ 6'b101110: deco1_fcn = {5'b11101, 1'b0, RDreg, (symbol[3:0]==4'b1000)};// EGP (29.7)
255
256 /* D30 + */ 6'b100001: deco1_fcn = {5'b11110, 1'b0, !RDreg, (symbol[3:0]==4'b0111)};// EBP (30.7)
257 /* D30 - */ 6'b011110: deco1_fcn = {5'b11110, 1'b0, RDreg, (symbol[3:0]==4'b1000)};// EBP (30.7)
258
259 /* D31 + */ 6'b010100: deco1_fcn = {5'b11111, 1'b0, !RDreg, 1'b0};
260 /* D31 - */ 6'b101011: deco1_fcn = {5'b11111, 1'b0, RDreg, 1'b0};
261
262 // COM (28.5) SLP (28.2) ALG (28.3) SEQ (28.4) SKP (28.0) ALL OTHERS 1,6,7 are decode errors
263
264 /* K28 + */ 6'b110000: deco1_fcn = {5'b11100, 1'b0, !RDreg, 1'b1};
265
266 // COM (28.5) SLP (28.2) ALG (28.3) SEQ (28.4) SKP (28.0) ALL OTHERS 1,6,7 are decode errors
267
268 /* K28 - */ 6'b001111: deco1_fcn = {5'b11100, 1'b0, RDreg, 1'b1};
269
270 default: deco1_fcn = {5'b00000, 1'b1, 1'b0, 1'b0}; // dec_err1
271 endcase
272
273// 4b3b decode on least significant bits of rx_10bdata
274// deco2_fcn = {decodata[7:5], error }
275
276always @ (symbol or newRD or deco1_fcn)
277 case ({deco1_fcn[0],newRD,symbol[3:0]}) //synopsys parallel_case full_case
278
279 /* NS Dx.0 + */ 6'b010100: deco2_fcn = {3'b000, 1'b0};
280 /* NS Dx.0 - */ 6'b001011: deco2_fcn = {3'b000, 1'b0};
281 /* SS Dx.0 + */ 6'b110100: deco2_fcn = {3'b000, 1'b0}; // K28.0
282 /* SS Dx.0 - */ 6'b101011: deco2_fcn = {3'b000, 1'b0}; // K28.0
283
284 /* NS Dx.1 + */ 6'b011001: deco2_fcn = {3'b001, 1'b0};
285 /* NS Dx.1 - */ 6'b001001: deco2_fcn = {3'b001, 1'b0};
286 /* SS Dx.1 + */ 6'b111001: deco2_fcn = {3'b001, 1'b0}; // Reserved Symbol Link Error
287 /* SS Dx.1 - */ 6'b100110: deco2_fcn = {3'b001, 1'b0}; // Reserved Symbol Link Error
288
289 /* NS Dx.2 + */ 6'b010101: deco2_fcn = {3'b010, 1'b0};
290 /* NS Dx.2 - */ 6'b000101: deco2_fcn = {3'b010, 1'b0};
291 /* SS Dx.2 + */ 6'b110101: deco2_fcn = {3'b010, 1'b0}; // K28.2
292 /* SS Dx.2 - */ 6'b101010: deco2_fcn = {3'b010, 1'b0}; // K28.2
293
294 /* NS Dx.3 + */ 6'b010011: deco2_fcn = {3'b011, 1'b0};
295 /* NS Dx.3 - */ 6'b001100: deco2_fcn = {3'b011, 1'b0};
296 /* SS Dx.3 + */ 6'b110011: deco2_fcn = {3'b011, 1'b0}; // K28.3
297 /* SS Dx.3 - */ 6'b101100: deco2_fcn = {3'b011, 1'b0}; // K28.3
298
299 /* NS Dx.4 + */ 6'b010010: deco2_fcn = {3'b100, 1'b0};
300 /* NS Dx.4 - */ 6'b001101: deco2_fcn = {3'b100, 1'b0};
301 /* SS Dx.4 + */ 6'b110010: deco2_fcn = {3'b100, 1'b0}; // K28.4
302 /* SS Dx.4 - */ 6'b101101: deco2_fcn = {3'b100, 1'b0}; // K28.4
303
304 /* NS Dx.5 + */ 6'b011010: deco2_fcn = {3'b101, 1'b0};
305 /* NS Dx.5 - */ 6'b001010: deco2_fcn = {3'b101, 1'b0};
306 /* SS Dx.5 + */ 6'b111010: deco2_fcn = {3'b101, 1'b0}; // K28.5
307 /* SS Dx.5 - */ 6'b100101: deco2_fcn = {3'b101, 1'b0}; // K28.5
308
309 /* NS Dx.6 + */ 6'b010110: deco2_fcn = {3'b110, 1'b0};
310 /* NS Dx.6 - */ 6'b000110: deco2_fcn = {3'b110, 1'b0};
311 /* SS Dx.6 + */ 6'b110110: deco2_fcn = {3'b110, 1'b0}; // Reserved Symbol Link Error
312 /* SS Dx.6 - */ 6'b101001: deco2_fcn = {3'b110, 1'b0}; // Reserved Symbol Link Error
313
314 /* NS Dx.7 + */ 6'b010001: deco2_fcn = {3'b111, 1'b0};
315 /* NS Dx.7 - */ 6'b001110: deco2_fcn = {3'b111, 1'b0};
316 /* NS Ax.7 + */ 6'b011000: deco2_fcn = {3'b111, 1'b0};
317 /* NS Ax.7 - */ 6'b000111: deco2_fcn = {3'b111, 1'b0};
318 /* SS Ax.7 + */ 6'b111000: deco2_fcn = {3'b111, 1'b0}; // 23,27,29,30.7
319 /* SS Ax.7 - */ 6'b100111: deco2_fcn = {3'b111, 1'b0}; // 23,27,29,30.7
320
321 default: deco2_fcn = {3'b000, 1'b1}; // ERROR
322 endcase
323
324endmodule
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