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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: xpcs_rxio_sync_deskew_fifo.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | // **************************************************************** | |
36 | // | |
37 | // Sun Proprietary/Confidential: Internal Use Only | |
38 | // | |
39 | // **************************************************************** | |
40 | // Design: IB Phy Interface | |
41 | // Block: IB RX Phy Interface Controller | |
42 | // Author: Carlos Castil | |
43 | // | |
44 | // Module: xpcs_rxio_sync_deskew_fifo | |
45 | // File: xpcs_rxio_sync_deskew_fifo.v | |
46 | // | |
47 | // Description: This block contains a small fifo to allow | |
48 | // for clock deskewing. | |
49 | // | |
50 | // Revision History | |
51 | // ------------------------------------------------------------ | |
52 | // Ver Date Comments | |
53 | // ------------------------------------------------------------ | |
54 | // 1.0 10/13/02 Fifo size is 16 symbols to accomidate | |
55 | // IB spec. which allows for 24ns of | |
56 | // skew....for ieee 802.3ae we need ~14ns | |
57 | // | |
58 | // **************************************************************** | |
59 | ||
60 | ||
61 | ||
62 | module xpcs_rxio_sync_deskew_fifo ( | |
63 | w_clk, | |
64 | w_rst, | |
65 | w_byte, | |
66 | w_special, | |
67 | w_error, | |
68 | ||
69 | w_ptr, | |
70 | r_ptr, | |
71 | ||
72 | byte, | |
73 | special, | |
74 | error); | |
75 | ||
76 | ||
77 | input w_clk; // Received Clock With Data | |
78 | input w_rst; // Synchronous Active Low Reset | |
79 | input [7:0] w_byte; // Decode Data | |
80 | input w_special; // Decode Control | |
81 | input w_error; // Decode error | |
82 | ||
83 | input [2:0] r_ptr; | |
84 | input [2:0] w_ptr; | |
85 | ||
86 | output [7:0] byte; // output data | |
87 | output special; // output control | |
88 | output error; // output error | |
89 | ||
90 | reg [9:0] mem_0; | |
91 | reg [9:0] mem_1; | |
92 | reg [9:0] mem_2; | |
93 | reg [9:0] mem_3; | |
94 | reg [9:0] mem_4; | |
95 | reg [9:0] mem_5; | |
96 | reg [9:0] mem_6; | |
97 | reg [9:0] mem_7; | |
98 | ||
99 | reg [7:0] byte; | |
100 | reg special; | |
101 | reg error; | |
102 | ||
103 | // Memory Registers | |
104 | ||
105 | always @ (posedge w_clk) | |
106 | if (w_rst) | |
107 | begin | |
108 | mem_0 <= 10'b0000000000; | |
109 | mem_1 <= 10'b0000000000; | |
110 | mem_2 <= 10'b0000000000; | |
111 | mem_3 <= 10'b0000000000; | |
112 | mem_4 <= 10'b0000000000; | |
113 | mem_5 <= 10'b0000000000; | |
114 | mem_6 <= 10'b0000000000; | |
115 | mem_7 <= 10'b0000000000; | |
116 | end | |
117 | else | |
118 | begin | |
119 | mem_0 <= (w_ptr==3'b000) ? {w_error,w_special,w_byte} : mem_0; | |
120 | mem_1 <= (w_ptr==3'b001) ? {w_error,w_special,w_byte} : mem_1; | |
121 | mem_2 <= (w_ptr==3'b010) ? {w_error,w_special,w_byte} : mem_2; | |
122 | mem_3 <= (w_ptr==3'b011) ? {w_error,w_special,w_byte} : mem_3; | |
123 | mem_4 <= (w_ptr==3'b100) ? {w_error,w_special,w_byte} : mem_4; | |
124 | mem_5 <= (w_ptr==3'b101) ? {w_error,w_special,w_byte} : mem_5; | |
125 | mem_6 <= (w_ptr==3'b110) ? {w_error,w_special,w_byte} : mem_6; | |
126 | mem_7 <= (w_ptr==3'b111) ? {w_error,w_special,w_byte} : mem_7; | |
127 | end | |
128 | ||
129 | ||
130 | ||
131 | // Read Data Mux | |
132 | ||
133 | always @ (r_ptr or mem_0 or mem_1 or mem_2 or mem_3 or | |
134 | mem_4 or mem_5 or mem_6 or mem_7 ) | |
135 | case (r_ptr[2:0]) // synopsys parallel_case full_case infer_mux | |
136 | 3'b000 : {error,special,byte} = mem_0; | |
137 | 3'b001 : {error,special,byte} = mem_1; | |
138 | 3'b010 : {error,special,byte} = mem_2; | |
139 | 3'b011 : {error,special,byte} = mem_3; | |
140 | 3'b100 : {error,special,byte} = mem_4; | |
141 | 3'b101 : {error,special,byte} = mem_5; | |
142 | 3'b110 : {error,special,byte} = mem_6; | |
143 | 3'b111 : {error,special,byte} = mem_7; | |
144 | endcase | |
145 | ||
146 | ||
147 | endmodule |