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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: xpcs_rxio_sync_fifo_ptr.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | // **************************************************************** | |
36 | // | |
37 | // Sun Proprietary/Confidential: Internal Use Only | |
38 | // | |
39 | // **************************************************************** | |
40 | // Design: IB Phy Interface | |
41 | // Block: IB RX Phy Interface Controller | |
42 | // Author: Carlos Castil | |
43 | // | |
44 | // Module: xpcs_rxio_sync_fifo_ptr | |
45 | // File: xpcs_rxio_sync_fifo_ptr.v | |
46 | // | |
47 | // Description: This block contains a small fifo to allow | |
48 | // for clock deskewing. | |
49 | // | |
50 | // Revision History | |
51 | // ------------------------------------------------------------ | |
52 | // Ver Date Comments | |
53 | // ------------------------------------------------------------ | |
54 | // 1.0 8/11/03 Created this module to guarantee pointer | |
55 | // synchronization between hi/lo fifos of | |
56 | // the same lane. Lane to lane deskew | |
57 | // assumes fifos will be read at the same | |
58 | // time. | |
59 | // | |
60 | // **************************************************************** | |
61 | ||
62 | module xpcs_rxio_sync_fifo_ptr ( | |
63 | w_clk, | |
64 | w_rst, | |
65 | ||
66 | rx_clk, | |
67 | ||
68 | w_ptr, | |
69 | r_ptr, | |
70 | hold, | |
71 | ||
72 | rst, | |
73 | flush); | |
74 | ||
75 | ||
76 | input w_clk; // Received Clock With Data | |
77 | input w_rst; // Synchronous Active Low Reset | |
78 | input rx_clk; // Link Core Receive Clock (recovered clock from lane 0) | |
79 | input rst; // Synchronous Active Low Reset | |
80 | input flush; // strobed for one clock to flush fifo (sets the r_ptr = synchronized(w_ptr)) | |
81 | input hold; | |
82 | ||
83 | output [2:0] r_ptr; | |
84 | output [2:0] w_ptr; | |
85 | ||
86 | wire [2:0] w_ptr_sync; | |
87 | ||
88 | wire w_ptr_sync_0; | |
89 | wire w_ptr_sync_1; | |
90 | wire w_ptr_sync_2; | |
91 | wire w_ptr_sync_3; | |
92 | wire w_ptr_sync_4; | |
93 | wire w_ptr_sync_5; | |
94 | wire w_ptr_sync_6; | |
95 | wire w_ptr_sync_7; | |
96 | ||
97 | wire [2:0] n_w_ptr; | |
98 | reg [2:0] w_ptr; | |
99 | ||
100 | wire new_w_ptr_0; | |
101 | wire new_w_ptr_1; | |
102 | wire new_w_ptr_2; | |
103 | wire new_w_ptr_3; | |
104 | wire new_w_ptr_4; | |
105 | wire new_w_ptr_5; | |
106 | wire new_w_ptr_6; | |
107 | wire new_w_ptr_7; | |
108 | ||
109 | wire [2:0] n_r_ptr; | |
110 | ||
111 | reg [2:0] r_ptr; | |
112 | ||
113 | ||
114 | // Write Pointer | |
115 | ||
116 | // 4 bit gray code incrementer | |
117 | // 000,001,011,010,110,111,101,100 | |
118 | ||
119 | assign n_w_ptr[2] = (w_ptr[1] & !w_ptr[0]) | (w_ptr[2] & w_ptr[0]) | (w_ptr[2] & w_ptr[1]); | |
120 | ||
121 | assign n_w_ptr[1] = (w_ptr[1] & !w_ptr[2]) | (w_ptr[1] & !w_ptr[0]) | (w_ptr[0] & !w_ptr[2]); | |
122 | ||
123 | assign n_w_ptr[0] = ((!w_ptr[2]) & (!w_ptr[1])) | (w_ptr[2] & w_ptr[1]); | |
124 | ||
125 | ||
126 | // 2 bit gray code incrementer | |
127 | // 00,01,11,10 | |
128 | // assign n_w_ptr[1] = w_ptr[0]; | |
129 | // assign n_w_ptr[0] = !w_ptr[1]; | |
130 | ||
131 | ||
132 | always @ (posedge w_clk) | |
133 | if (w_rst) | |
134 | w_ptr <= 3'b000; | |
135 | else | |
136 | w_ptr <= n_w_ptr[2:0]; | |
137 | ||
138 | ||
139 | // Synchronize Write Pointer To rx_clk | |
140 | ||
141 | assign new_w_ptr_0 = rst ? 1'b0 : w_ptr == 3'b000; | |
142 | assign new_w_ptr_1 = rst ? 1'b0 : w_ptr == 3'b001; | |
143 | assign new_w_ptr_2 = rst ? 1'b0 : w_ptr == 3'b010; | |
144 | assign new_w_ptr_3 = rst ? 1'b0 : w_ptr == 3'b011; | |
145 | assign new_w_ptr_4 = rst ? 1'b0 : w_ptr == 3'b100; | |
146 | assign new_w_ptr_5 = rst ? 1'b0 : w_ptr == 3'b101; | |
147 | assign new_w_ptr_6 = rst ? 1'b0 : w_ptr == 3'b110; | |
148 | assign new_w_ptr_7 = rst ? 1'b0 : w_ptr == 3'b111; | |
149 | ||
150 | SYNC_CELL SYNC_W_PTR_0 (.D(new_w_ptr_0), .CP(rx_clk), .Q(w_ptr_sync_0) ); | |
151 | SYNC_CELL SYNC_W_PTR_1 (.D(new_w_ptr_1), .CP(rx_clk), .Q(w_ptr_sync_1) ); | |
152 | SYNC_CELL SYNC_W_PTR_2 (.D(new_w_ptr_2), .CP(rx_clk), .Q(w_ptr_sync_2) ); | |
153 | SYNC_CELL SYNC_W_PTR_3 (.D(new_w_ptr_3), .CP(rx_clk), .Q(w_ptr_sync_3) ); | |
154 | SYNC_CELL SYNC_W_PTR_4 (.D(new_w_ptr_4), .CP(rx_clk), .Q(w_ptr_sync_4) ); | |
155 | SYNC_CELL SYNC_W_PTR_5 (.D(new_w_ptr_5), .CP(rx_clk), .Q(w_ptr_sync_5) ); | |
156 | SYNC_CELL SYNC_W_PTR_6 (.D(new_w_ptr_6), .CP(rx_clk), .Q(w_ptr_sync_6) ); | |
157 | SYNC_CELL SYNC_W_PTR_7 (.D(new_w_ptr_7), .CP(rx_clk), .Q(w_ptr_sync_7) ); | |
158 | ||
159 | ||
160 | assign w_ptr_sync = w_ptr_sync_0 ? 3'b000 : | |
161 | w_ptr_sync_1 ? 3'b001 : | |
162 | w_ptr_sync_2 ? 3'b010 : | |
163 | w_ptr_sync_3 ? 3'b011 : | |
164 | w_ptr_sync_4 ? 3'b100 : | |
165 | w_ptr_sync_5 ? 3'b101 : | |
166 | w_ptr_sync_6 ? 3'b110 : | |
167 | w_ptr_sync_7 ? 3'b111 : | |
168 | 3'b000; | |
169 | ||
170 | // Read Pointer | |
171 | ||
172 | // 2 bit gray code incrementer | |
173 | // 00,01,11,10 | |
174 | // assign n_r_ptr[1] = r_ptr[0]; | |
175 | // assign n_r_ptr[0] = !r_ptr[1]; | |
176 | ||
177 | assign n_r_ptr[2] = (r_ptr[1] & !r_ptr[0]) | (r_ptr[2] & r_ptr[0]) | (r_ptr[2] & r_ptr[1]); | |
178 | ||
179 | assign n_r_ptr[1] = (r_ptr[1] & !r_ptr[2]) | (r_ptr[1] & !r_ptr[0]) | (r_ptr[0] & !r_ptr[2]); | |
180 | ||
181 | assign n_r_ptr[0] = ((!r_ptr[2]) & (!r_ptr[1])) | (r_ptr[2] & r_ptr[1]); | |
182 | ||
183 | ||
184 | always @ (posedge rx_clk) | |
185 | begin | |
186 | r_ptr <= rst ? 3'b000 : | |
187 | flush ? w_ptr_sync[2:0] : | |
188 | hold ? r_ptr[2:0] : | |
189 | n_r_ptr[2:0]; | |
190 | end | |
191 | ||
192 | ||
193 | //*********************************************** | |
194 | // Zero In Added Error Checks | |
195 | //*********************************************** | |
196 | ||
197 | // synopsys translate_off | |
198 | ||
199 | // START OF GREY CODE LOGIC CHECK FOR 0-in | |
200 | ||
201 | // 000,001,011,010,110,111,101,100 | |
202 | ||
203 | reg test_w_ptr_grey_code_inc; | |
204 | ||
205 | always @ (w_ptr or n_w_ptr) | |
206 | case (w_ptr) | |
207 | 3'b000 : test_w_ptr_grey_code_inc = (n_w_ptr != 3'b001); // 0 -> 1 | |
208 | 3'b001 : test_w_ptr_grey_code_inc = (n_w_ptr != 3'b011); // 1 -> 3 | |
209 | 3'b011 : test_w_ptr_grey_code_inc = (n_w_ptr != 3'b010); // 3 -> 2 | |
210 | 3'b010 : test_w_ptr_grey_code_inc = (n_w_ptr != 3'b110); // 2 -> 6 | |
211 | 3'b110 : test_w_ptr_grey_code_inc = (n_w_ptr != 3'b111); // 6 -> 7 | |
212 | 3'b111 : test_w_ptr_grey_code_inc = (n_w_ptr != 3'b101); // 7 -> 5 | |
213 | 3'b101 : test_w_ptr_grey_code_inc = (n_w_ptr != 3'b100); // 5 -> 4 | |
214 | 3'b100 : test_w_ptr_grey_code_inc = (n_w_ptr != 3'b000); // 4 -> 0 | |
215 | endcase | |
216 | ||
217 | // 0in custom -fire test_w_ptr_grey_code_inc -message "Deskew Fifo Grey Code Increment Failure On Write Pointer" | |
218 | ||
219 | reg test_r_ptr_grey_code_inc; | |
220 | ||
221 | always @ (r_ptr or n_r_ptr) | |
222 | case (r_ptr) | |
223 | 3'b000 : test_r_ptr_grey_code_inc = (n_r_ptr != 3'b001); // 0 -> 1 | |
224 | 3'b001 : test_r_ptr_grey_code_inc = (n_r_ptr != 3'b011); // 1 -> 3 | |
225 | 3'b011 : test_r_ptr_grey_code_inc = (n_r_ptr != 3'b010); // 3 -> 2 | |
226 | 3'b010 : test_r_ptr_grey_code_inc = (n_r_ptr != 3'b110); // 2 -> 6 | |
227 | 3'b110 : test_r_ptr_grey_code_inc = (n_r_ptr != 3'b111); // 6 -> 7 | |
228 | 3'b111 : test_r_ptr_grey_code_inc = (n_r_ptr != 3'b101); // 7 -> 5 | |
229 | 3'b101 : test_r_ptr_grey_code_inc = (n_r_ptr != 3'b100); // 5 -> 4 | |
230 | 3'b100 : test_r_ptr_grey_code_inc = (n_r_ptr != 3'b000); // 4 -> 0 | |
231 | endcase | |
232 | ||
233 | // 0in custom -fire test_r_ptr_grey_code_inc -message "Deskew Fifo Grey Code Increment Failure On Read Pointer" | |
234 | ||
235 | // END OF GREY CODE LOGIC CHECK FOR 0-in | |
236 | ||
237 | // synopsys translate_on | |
238 | ||
239 | ||
240 | ||
241 | endmodule | |
242 |