Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / design / sys / iop / niu / rtl / xpcs_rxio_sync_sm.v
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2//
3// OpenSPARC T2 Processor File: xpcs_rxio_sync_sm.v
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35// ****************************************************************
36//
37// Sun Proprietary/Confidential: Internal Use Only
38//
39// ****************************************************************
40// Design: XPCS RX IO Interface
41// Block: XPCS RX Sync state machine
42// Author: Carlos Castil
43//
44// Module: xpcs_rxio_sync_sm
45// File: xpcs_rxio_sync_sm.v
46//
47// Description: This block contains a comma detector compliant
48// to ieee 802.3ae clause 48 fig 48-7.
49//
50// Revision History
51// ------------------------------------------------------------
52// Ver Date Comments
53// ------------------------------------------------------------
54// 1.0 09/24/02 Created
55//
56// ****************************************************************
57
58
59
60module xpcs_rxio_sync_sm (
61 rx_lane_clk,
62 rx_lane_reset,
63 rx_signal_detect,
64
65 byte_deskew,
66 special_deskew,
67 error_deskew,
68
69 state,
70 csr_lane_sync_status);
71
72input rx_lane_clk;
73input rx_lane_reset;
74input rx_signal_detect;
75
76input [7:0] byte_deskew;
77input special_deskew;
78input error_deskew;
79
80output [3:0] state;
81output csr_lane_sync_status;
82
83// Wires and Regs which are not flops
84
85wire com_det;
86wire [3:0] nxt_state;
87
88// Regs which are flops
89
90reg csr_lane_sync_status;
91wire rx_lane_sync_loss;
92
93wire inc_comma_cnt;
94wire inc_symbol_cnt;
95
96wire [2:0] nxt_comma_cnt; // counter for number of good commas received
97wire [2:0] nxt_symbol_cnt; // counter for number of good symbol received
98
99reg [2:0] comma_cnt;
100reg [2:0] symbol_cnt;
101
102wire clr_comma_cnt;
103wire clr_symbol_cnt;
104
105wire comma_cnt_eq4;
106wire symbol_cnt_eq3;
107
108reg [3:0] state;
109
110wire com_k281_det;
111wire com_k285_det;
112wire com_k287_det;
113
114wire invalid;
115
116
117parameter LOSS_SYNC = 4'h0; // word synchronization state machine
118parameter IN_SYNC = 4'h1;
119parameter ONE_INVALID = 4'h2;
120parameter TWO_INVALID = 4'h4;
121parameter THREE_INVALID = 4'h8;
122
123
124// Decode
125/*
126XPCS_DEC_COM 10'h1BC // K28.5
127XPCS_DEC_281 10'h13C
128XPCS_DEC_285 10'h1BC
129XPCS_DEC_287 10'h1FC
130
131XPCS_DEC_SDP 10'h1FB
132XPCS_DEC_SLP 10'h15C
133XPCS_DEC_EGP 10'h1FD
134XPCS_DEC_EBP 10'h1FE
135XPCS_DEC_PAD 10'h1F7
136XPCS_DEC_SKP 10'h11C
137
138XPCS_DEC_LN0 10'h000
139XPCS_DEC_LN1 10'h001
140XPCS_DEC_LN2 10'h002
141XPCS_DEC_LN3 10'h004
142
143XPCS_DEC_LN4 10'h008
144XPCS_DEC_LN5 10'h00F
145XPCS_DEC_LN6 10'h010
146XPCS_DEC_LN7 10'h017
147XPCS_DEC_LN8 10'h018
148XPCS_DEC_LN9 10'h01B
149XPCS_DEC_LNA 10'h01D
150XPCS_DEC_LNB 10'h01E
151*/
152
153assign com_k281_det = ({error_deskew,special_deskew,byte_deskew[7:0]} == `XPCS_DEC_281);
154assign com_k285_det = ({error_deskew,special_deskew,byte_deskew[7:0]} == `XPCS_DEC_285);
155assign com_k287_det = ({error_deskew,special_deskew,byte_deskew[7:0]} == `XPCS_DEC_287);
156
157
158assign com_det = com_k281_det | com_k285_det | com_k287_det;
159
160assign invalid = error_deskew; // Disparity and decode errors
161
162
163/*
164** Synchronization COMMA counter
165*/
166
167always @ (posedge rx_lane_clk)
168 if (rx_lane_reset)
169 comma_cnt <= 3'b0;
170 else
171 comma_cnt <= nxt_comma_cnt;
172
173assign nxt_comma_cnt = (rx_lane_reset | clr_comma_cnt) ? 3'h0 :
174 (inc_comma_cnt) ? comma_cnt + 3'h1 :
175 comma_cnt;
176
177assign comma_cnt_eq4 = (comma_cnt >= 3'h4);
178
179/*
180** Synchronization SYMBOL counter
181*/
182
183always @ (posedge rx_lane_clk)
184 if (rx_lane_reset)
185 symbol_cnt <= 3'b0;
186 else
187 symbol_cnt <= nxt_symbol_cnt;
188
189assign nxt_symbol_cnt = (rx_lane_reset | clr_symbol_cnt) ? 3'h0 :
190 (inc_symbol_cnt) ? symbol_cnt + 3'h1 :
191 symbol_cnt;
192
193assign symbol_cnt_eq3 = (symbol_cnt >= 3'h3);
194
195/* ************************************************************* */
196
197always @ (posedge rx_lane_clk)
198 csr_lane_sync_status <= !rx_lane_sync_loss;
199
200/*
201** Call of function word synchronization
202*/
203
204assign {rx_lane_sync_loss,inc_symbol_cnt,clr_symbol_cnt,inc_comma_cnt,clr_comma_cnt,nxt_state}
205 = synchronization_fn(rx_lane_reset,
206 com_det,
207 invalid,
208 comma_cnt_eq4,
209 symbol_cnt_eq3,
210 state);
211
212
213/*
214** Word Synchronization state machine
215*/
216function [8:0] synchronization_fn;
217 input f_reset;
218 input f_com_det; // to determine if there is a comma
219 input f_invalid; // invalid transmission word detected
220 input f_comma_cnt_eq4;
221 input f_symbol_cnt_eq3; // found 3 commas with no errors
222 input [3:0] state;
223
224 reg f_loss_sync; // indicates word sync status
225 reg f_inc_comma_cnt; // increment word sync counter
226 reg f_clr_comma_cnt; // clear word sync counter
227 reg f_inc_symbol_cnt; // increment word sync counter
228 reg f_clr_symbol_cnt; // clear word sync counter
229 reg [3:0] n_state; // next state
230
231 begin
232 if (f_reset)
233 begin
234 f_loss_sync = 1'h1;
235 f_inc_comma_cnt = 1'h0;
236 f_clr_comma_cnt = 1'h1;
237 f_inc_symbol_cnt = 1'h0;
238 f_clr_symbol_cnt = 1'h1;
239 n_state = LOSS_SYNC;
240 end
241 else
242 begin
243 f_loss_sync = 1'h0;
244 f_inc_comma_cnt = 1'h0;
245 f_clr_comma_cnt = 1'h0;
246 f_inc_symbol_cnt = 1'h0;
247 f_clr_symbol_cnt = 1'h0;
248 n_state = LOSS_SYNC;
249
250 case (state) // synopsys parallel_case
251
252 LOSS_SYNC : // 0 // being in this state triggers link config
253 begin
254 f_loss_sync = 1'h1;
255 if (f_reset)
256 n_state = LOSS_SYNC;
257 else if (f_invalid)
258 begin
259 f_clr_comma_cnt = 1'h1;
260 f_clr_symbol_cnt = 1'h1;
261 n_state = LOSS_SYNC;
262 end
263 else if (f_comma_cnt_eq4) // got 3 good commas
264 n_state = IN_SYNC;
265 else if (f_com_det) // accum good
266 begin
267 f_clr_comma_cnt = 1'h0;
268 f_inc_comma_cnt = 1'h1;
269 n_state = LOSS_SYNC;
270 end
271 else
272 n_state = LOSS_SYNC;
273
274 end
275
276 IN_SYNC : // 1
277 if (f_invalid)
278 begin
279 f_clr_comma_cnt = 1'h1;
280 f_clr_symbol_cnt = 1'h1;
281 n_state = ONE_INVALID;
282 end
283 else
284 n_state = IN_SYNC;
285
286 ONE_INVALID : // 2
287 if (f_invalid)
288 begin
289 f_clr_symbol_cnt = 1'h1;
290 f_clr_comma_cnt = 1'h1;
291 n_state = TWO_INVALID;
292 end
293
294 else if (f_symbol_cnt_eq3) // got 3 good symbols
295 begin
296 f_clr_symbol_cnt = 1'h1;
297 f_clr_comma_cnt = 1'h1;
298 n_state = IN_SYNC; // go to sync state
299 end
300
301 else // inc good symbol count
302 begin
303 f_clr_symbol_cnt = 1'h0;
304 f_inc_symbol_cnt = 1'h1;
305 n_state = ONE_INVALID;
306 end
307
308
309 TWO_INVALID : // 4
310 if (f_invalid)
311 begin
312 f_clr_symbol_cnt = 1'h1;
313 f_clr_comma_cnt = 1'h1;
314 n_state = THREE_INVALID;
315 end
316
317 else if (f_symbol_cnt_eq3) // got 3 good symbols
318 begin
319 f_clr_symbol_cnt = 1'h1;
320 f_clr_comma_cnt = 1'h1;
321 n_state = ONE_INVALID; // Need to get 3 more good symbols
322 end
323
324 else // inc good symbol count
325 begin
326 f_clr_symbol_cnt = 1'h0;
327 f_inc_symbol_cnt = 1'h1;
328 n_state = TWO_INVALID;
329 end
330
331
332 THREE_INVALID : // 8
333 if (f_invalid)
334 begin
335 f_clr_symbol_cnt = 1'h1;
336 f_clr_comma_cnt = 1'h1;
337 n_state = LOSS_SYNC;
338 end
339
340 else if (f_symbol_cnt_eq3) // got 3 good symbols
341 begin
342 f_clr_symbol_cnt = 1'h1;
343 f_clr_comma_cnt = 1'h1;
344 n_state = TWO_INVALID; // Need to get 6 more good symbols
345 end
346
347 else // inc good symbol count
348 begin
349 f_clr_symbol_cnt = 1'h0;
350 f_inc_symbol_cnt = 1'h1;
351 n_state = THREE_INVALID;
352 end
353
354
355 endcase
356
357 end
358// {rx_lane_sync_loss, inc_symbol_cnt, clr_symbol_cnt, inc_comma_cnt, clr_comma_cnt,nxt_state}
359 synchronization_fn = {f_loss_sync,f_inc_symbol_cnt,f_clr_symbol_cnt,f_inc_comma_cnt,f_clr_comma_cnt,n_state};
360
361 end
362endfunction
363
364// ********************************
365// Receive State Machine Registers
366// ********************************
367
368always @(posedge rx_lane_clk)
369 if (rx_lane_reset | !rx_signal_detect)
370 begin
371 state <= 4'b0;
372 end
373 else
374 begin
375 state <= nxt_state;
376 end
377
378// 0in bits_on -var state -max 1 -clock rx_lane_clk
379
380// 0in state -var state -val LOSS_SYNC -next IN_SYNC -clock rx_lane_clk -reset (rx_lane_reset | !rx_signal_detect)
381// 0in state -var state -val IN_SYNC -next ONE_INVALID -clock rx_lane_clk -reset (rx_lane_reset | !rx_signal_detect)
382// 0in state -var state -val ONE_INVALID -next TWO_INVALID IN_SYNC -clock rx_lane_clk -reset (rx_lane_reset | !rx_signal_detect)
383// 0in state -var state -val TWO_INVALID -next THREE_INVALID ONE_INVALID -clock rx_lane_clk -reset (rx_lane_reset | !rx_signal_detect)
384// 0in state -var state -val THREE_INVALID -next LOSS_SYNC TWO_INVALID -clock rx_lane_clk -reset (rx_lane_reset | !rx_signal_detect)
385
386endmodule