[OpenSPARC-T2-DV] / design / sys / iop / niu / rtl / xpcs_tx.v

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// 
// OpenSPARC T2 Processor File: xpcs_tx.v
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/**********************************************************************/
/* Project Name  :  Vega                                              */
/* Module Name   :  xpcs_tx                                           */
/* Description   :  XPCS transmit top level.  Ranmomizer and tx state */
/*                  machine (clause 48.2.6.2.1 ieee802.3ae).          */
/*                                                                    */
/*                  Link protocol:                                    */
/*                                                                    */
/*                  When xpcs receiver asserts local fault to XGMII   */
/*                  due to link loss, the xpcs transmiter transmits   */
/*                  remote faults and idles.                          */
/*                                                                    */
/*                  When the receiver gets remote faults, the XPCS    */
/*                  passes it on to the XGMII. The MAC then generates */
/*                  idles for XPCS to transmit to assist the remote   */
/*                  node regain link. (clause 46.3.4 p285).           */
/*                                                                    */
/* Assumptions   : none.                                              */
/*                                                                    */
/* Parent module : xpcs_tx.v                                          */
/* Child modules : none.                                              */
/* Author Name   : Carlos Castil                                      */
/* Date Created  : 11/10/02                                           */
/*                                                                    */
/*              Copyright (c) 2002, Sun Microsystems, Inc.            */
/*                   Sun Proprietary and Confidential                 */
/*                                                                    */ 
/* Modifications :                                                    */
/**********************************************************************/

 
module xpcs_tx (           tx_clk, 
                           reset, 

                           csr_link_status,
                           csr_tx_test_enable,
                           csr_test_pattern_sel,
                           
                           tx_byte_0,
                           tx_byte_1,
                           tx_byte_2,
                           tx_byte_3,

                           tx_special_0,
                           tx_special_1,
                           tx_special_2,
                           tx_special_3,

                           tx_byte_0_enc,
                           tx_byte_1_enc,
                           tx_byte_2_enc,
                           tx_byte_3_enc,

                           tx_special_0_enc,
                           tx_special_1_enc,
                           tx_special_2_enc,
                           tx_special_3_enc,

                           csr_transmit_fault_ref,

                           inc_tx_pkt_count_ref,

                           
                           state       );

input       tx_clk;
input       reset;

input       csr_link_status;
input       csr_tx_test_enable;
input [1:0] csr_test_pattern_sel;

output      inc_tx_pkt_count_ref;
output      csr_transmit_fault_ref;

input [7:0] tx_byte_0;
input [7:0] tx_byte_1;
input [7:0] tx_byte_2;
input [7:0] tx_byte_3;

input       tx_special_0;
input       tx_special_1;
input       tx_special_2;
input       tx_special_3;

output [3:0] state;

output [7:0] tx_byte_0_enc;
output [7:0] tx_byte_1_enc;
output [7:0] tx_byte_2_enc;
output [7:0] tx_byte_3_enc;

output       tx_special_0_enc;
output       tx_special_1_enc;
output       tx_special_2_enc;
output       tx_special_3_enc;

parameter SEND_DATA       = 4'h0;
parameter SEND_SDP        = 4'h1;
parameter SEND_A          = 4'h2;
parameter SEND_K          = 4'h3;
parameter SEND_Q          = 4'h4;
parameter SEND_RANDOM_R   = 4'h5;
parameter SEND_RANDOM_A   = 4'h6;
parameter SEND_RANDOM_K   = 4'h7;
parameter SEND_RANDOM_Q   = 4'h8;
parameter UNDERRUN        = 4'h9;

reg [3:0] state;

wire [3:0] nxt_state;

reg [7:0] tx_byte_0_in;
reg [7:0] tx_byte_1_in;
reg [7:0] tx_byte_2_in;
reg [7:0] tx_byte_3_in;

reg      tx_special_0_in;
reg      tx_special_1_in;
reg      tx_special_2_in;
reg      tx_special_3_in;

reg [7:0] tx_byte_0_int;
reg [7:0] tx_byte_1_int;
reg [7:0] tx_byte_2_int;
reg [7:0] tx_byte_3_int;

reg      tx_special_0_int;
reg      tx_special_1_int;
reg      tx_special_2_int;
reg      tx_special_3_int;

wire [7:0] tx_byte_0_mux;
wire [7:0] tx_byte_1_mux;
wire [7:0] tx_byte_2_mux;
wire [7:0] tx_byte_3_mux;

wire      tx_special_0_mux;
wire      tx_special_1_mux;
wire      tx_special_2_mux;
wire      tx_special_3_mux;

reg [7:0] tx_byte_0_enc;
reg [7:0] tx_byte_1_enc;
reg [7:0] tx_byte_2_enc;
reg [7:0] tx_byte_3_enc;

reg       tx_special_0_enc;
reg       tx_special_1_enc;
reg       tx_special_2_enc;
reg       tx_special_3_enc;

wire     align_count_exp;
wire     code_sel_random;

wire     sel_d, sel_k, sel_a, sel_r, sel_q;
wire     sel_s;

wire     q_detect;

wire     term_det_0;
wire     term_det_1;
wire     term_det_2;
wire     term_det_3;

wire     idle_det_0;
wire     idle_det_1;
wire     idle_det_2;
wire     idle_det_3;

wire     i_detect;

wire     clr_a_cnt;

wire     clr_q_det;

wire     xgmii_s_detect;
wire     xgmii_d_detect;

wire     csr_transmit_fault_ref;

wire [7:0] test_byte;
wire       test_special;

wire       q_detect_local;
wire       q_detect_remote;

reg        q_det_local;
reg        q_det_remote;

wire       link_status_tx;
wire       tx_test_enable;

wire [1:0] test_pattern_sel;

/* ********************************************************** */
/*        Synchronize                                         */
/* ********************************************************** */

SYNC_CELL u_sync_link_status (
                        .D  (csr_link_status),  // unsynchronized
                        .CP (tx_clk),
                        .Q  (link_status_tx));    // synchronized

SYNC_CELL u_sync_test_enable (
                        .D  (csr_tx_test_enable),  // unsynchronized
                        .CP (tx_clk),
                        .Q  (tx_test_enable));    // synchronized

SYNC_CELL u_sync_test_pattern_sel_0 (
                        .D  (csr_test_pattern_sel[0]),  // unsynchronized
                        .CP (tx_clk),
                        .Q  (test_pattern_sel[0]));    // synchronized

SYNC_CELL u_sync_test_pattern_sel_1 (
                        .D  (csr_test_pattern_sel[1]),  // unsynchronized
                        .CP (tx_clk),
                        .Q  (test_pattern_sel[1]));    // synchronized

// *******************************************************
// q_det function per clause 48.2.6.1.4 ieee 802.3ae
// *******************************************************

assign q_detect_local = tx_special_0_in & (tx_byte_0_in == `XPCS_ENC_SEQ) & 
                                          (tx_byte_1_in == `XPCS_ENC_D00) &
                                          (tx_byte_2_in == `XPCS_ENC_D00) &
                                          (tx_byte_3_in == `XPCS_ENC_D10) ;

always @ (posedge tx_clk)
    if (reset)
      q_det_local <= 1'b0;
    else
      q_det_local <= (q_detect_local) ? 1'b1 : (clr_q_det) ? 1'b0 : q_det_local;
 

assign q_detect_remote = tx_special_0_in & (tx_byte_0_in == `XPCS_ENC_SEQ) &
                                           (tx_byte_1_in == `XPCS_ENC_D00) &
                                           (tx_byte_2_in == `XPCS_ENC_D00) &
                                           (tx_byte_3_in == `XPCS_ENC_D20) ; 

always @ (posedge tx_clk)
    if (reset)
      q_det_remote <= 1'b0;
    else
      q_det_remote <= ((!link_status_tx) | q_detect_remote) ? 1'b1 :         
                                                 (clr_q_det) ? 1'b0 : q_det_remote;


assign q_detect = q_det_local | q_det_remote;


assign csr_transmit_fault_ref = q_detect;

// *******************************************************
// sop detection logic
// *******************************************************

assign xgmii_s_detect = tx_special_0_in & (tx_byte_0_in == `XPCS_ENC_SDP);

// *******************************************************
// data detection logic
// *******************************************************

assign xgmii_d_detect = (!tx_special_0_in) |
                        (!tx_special_1_in) |
                        (!tx_special_2_in) |
                        (!tx_special_3_in) &
                        ( link_status_tx & !xgmii_s_detect );

// ***************************************************************
//  Terminate detection  
// ***************************************************************

assign term_det_0 = tx_special_0_mux & (tx_byte_0_mux == `XPCS_ENC_EGP) &
                    tx_special_1_mux & (tx_byte_1_mux == `XPCS_ENC_IDL) &
                    tx_special_2_mux & (tx_byte_2_mux == `XPCS_ENC_IDL) &
                    tx_special_3_mux & (tx_byte_3_mux == `XPCS_ENC_IDL);

assign term_det_1 = tx_special_1_mux & (tx_byte_1_mux == `XPCS_ENC_EGP) &
                    tx_special_2_mux & (tx_byte_2_mux == `XPCS_ENC_IDL) &
                    tx_special_3_mux & (tx_byte_3_mux == `XPCS_ENC_IDL);

assign term_det_2 = tx_special_2_mux & (tx_byte_2_mux == `XPCS_ENC_EGP) &
                    tx_special_3_mux & (tx_byte_3_mux == `XPCS_ENC_IDL);

assign term_det_3 = tx_special_3_mux & (tx_byte_3_mux == `XPCS_ENC_EGP);


assign inc_tx_pkt_count_ref = term_det_0 | term_det_1 | term_det_2 | term_det_3 ;


// ***************************************************************
//  Idle detection
// ***************************************************************

assign idle_det_0 = tx_special_0_in & (tx_byte_0_in == `XPCS_ENC_IDL);
assign idle_det_1 = tx_special_1_in & (tx_byte_1_in == `XPCS_ENC_IDL);
assign idle_det_2 = tx_special_2_in & (tx_byte_2_in == `XPCS_ENC_IDL);
assign idle_det_3 = tx_special_3_in & (tx_byte_3_in == `XPCS_ENC_IDL);

assign i_detect = idle_det_0 & idle_det_1 & idle_det_2 & idle_det_3;

// ***************************************************************
// State Machine 48.2.6.2.1 ieee 802.3ae
// ***************************************************************

/* *************************************************************************
                   {n_state, n_clr_a_cnt, n_clr_q_det, n_sel_s
                    n_sel_d, n_sel_r, n_sel_k, n_sel_a, n_sel_q};
** *************************************************************************/

assign {nxt_state, 
        clr_a_cnt, 
        clr_q_det, 
        sel_s,
        sel_d, 
        sel_r,
        sel_k,
        sel_a,
        sel_q}   = transmit_fn (reset, 
                                align_count_exp,
                                code_sel_random, 
                                q_detect,
                                i_detect,
                                xgmii_s_detect,
                                xgmii_d_detect,
                                state);

function [11:0]  transmit_fn;

 input        reset;
 input        a_cnt;
 input        code_sel;
 input        q_det;
 input        i_det;
 input        s_det;
 input        d_det;
 input [3:0]  state;

 reg   [3:0]  n_state;

 reg          n_clr_a_cnt;
 reg          n_clr_q_det;

 reg          n_sel_d;
 reg          n_sel_a;
 reg          n_sel_k;
 reg          n_sel_r;
 reg          n_sel_q;
 reg          n_sel_s;

 reg          nxt_ifg;

 begin

  if (reset)
     begin

       n_clr_a_cnt = 1'b0;
       n_clr_q_det = 1'b0;

       n_sel_d     = 1'b0;
       n_sel_r     = 1'b0;
       n_sel_k     = 1'b0;
       n_sel_a     = 1'b0;
       n_sel_q     = 1'b0;
       n_sel_s     = 1'b0;

       nxt_ifg     = 1'b0;

       n_state = SEND_K;  // send K
    
     end

  else

     begin

       n_state = SEND_K;

       n_clr_a_cnt = 1'b0;

       n_clr_q_det = 1'b0;

       n_sel_d       = 1'b0;
       n_sel_r       = 1'b0;
       n_sel_k       = 1'b0;
       n_sel_a       = 1'b0;
       n_sel_q       = 1'b0;
       n_sel_s       = 1'b0;

       case (state)

         SEND_DATA  :  // 0 
           begin 
             n_sel_d  = 1'b1;
           
             if (i_det | q_det)
               begin
                 if (nxt_ifg & a_cnt)
                   n_state =  SEND_A;

                 else if (!nxt_ifg | !a_cnt)
                   n_state =  SEND_K;
               end
             else
               n_state     = SEND_DATA;

           end


         SEND_SDP :  //  1
           begin
             n_sel_s       = 1'b1;

             if (d_det)
               n_state     = SEND_DATA;
             else
               n_state     = UNDERRUN;

           end


         SEND_A :   //  2
           begin
             n_clr_a_cnt = 1'b1;
             n_sel_a     = 1'b1;  
             nxt_ifg     = 1'b0;    // select K next instead of A    

             if (q_det)
               n_state     = SEND_Q;

             else if (s_det)
               n_state     = SEND_SDP;
              
             else  
               n_state     = SEND_RANDOM_R;

           end

         SEND_K :   // 3
           begin
             n_sel_k   = 1'b1;  
             nxt_ifg   = 1'b1;    // select A next instead of K

             if (s_det)
               n_state     = SEND_SDP;

             else
               n_state     = SEND_RANDOM_R;  

           end

         SEND_Q :  // 4
           begin
             n_sel_q     = 1'b1;
             n_clr_q_det = 1'b1;

            if (s_det)
               n_state     = SEND_SDP;

            else
               n_state     = SEND_RANDOM_R;

           end

         SEND_RANDOM_R :  // 5
           begin
             n_sel_r       = 1'b1;

             if (s_det)
               n_state     = SEND_SDP;

             else if (code_sel & !a_cnt)
               n_state     = SEND_RANDOM_R;

             else if ((!code_sel) & !a_cnt)
               n_state     = SEND_RANDOM_K;

             else if (a_cnt)
               n_state     = SEND_RANDOM_A;

           end

         SEND_RANDOM_A :  // 6
           begin
             n_sel_a     = 1'b1;
             n_clr_a_cnt = 1'b1;

             if (s_det)
               n_state     = SEND_SDP;

             else if (q_det)
               n_state     = SEND_RANDOM_Q;

             else if (code_sel & !q_det)
               n_state     = SEND_RANDOM_R;

             else if ((!code_sel) & !q_det)
               n_state     = SEND_RANDOM_K;

           end


         SEND_RANDOM_K :  // 7 
           begin
             n_sel_k     = 1'b1;

             if (s_det)
               n_state     = SEND_SDP;

             else if (a_cnt)
               n_state     = SEND_RANDOM_A;

             else if (code_sel & !a_cnt)
               n_state     = SEND_RANDOM_R;

             else if ((!code_sel) & !a_cnt)
               n_state     = SEND_RANDOM_K;


           end


         SEND_RANDOM_Q  :  // 8
           begin
             n_sel_q     = 1'b1;
             n_clr_q_det = 1'b1;

             if (s_det)
               n_state     = SEND_SDP;

             else if (code_sel)
               n_state     = SEND_RANDOM_R;

             else if (!code_sel)
               n_state     = SEND_RANDOM_K;

           end

         UNDERRUN :  // 9 
           begin
              n_state     = SEND_A;
           end


        endcase

      end

     transmit_fn = {n_state, n_clr_a_cnt, n_clr_q_det, n_sel_s,
                    n_sel_d, n_sel_r, n_sel_k, n_sel_a, n_sel_q}; 

  end

endfunction


// State machine register

always @ (posedge tx_clk)
   if (reset)
       state <=  4'h0;
   else
       state <=  nxt_state;

// *******************************************************
//                 Data Path Pipeline
// *******************************************************

always @ (posedge tx_clk)
  begin
   tx_byte_0_in <= tx_byte_0;
   tx_byte_1_in <= tx_byte_1;
   tx_byte_2_in <= tx_byte_2;
   tx_byte_3_in <= tx_byte_3;
 end

always @ (posedge tx_clk)
  begin
   tx_special_0_in <= tx_special_0;
   tx_special_1_in <= tx_special_1;
   tx_special_2_in <= tx_special_2;
   tx_special_3_in <= tx_special_3;
  end

always @ (posedge tx_clk)
  begin
   tx_byte_0_int <= tx_byte_0_in;
   tx_byte_1_int <= tx_byte_1_in;
   tx_byte_2_int <= tx_byte_2_in;
   tx_byte_3_int <= tx_byte_3_in;
 end

always @ (posedge tx_clk)
  begin
   tx_special_0_int <= tx_special_0_in;
   tx_special_1_int <= tx_special_1_in;
   tx_special_2_int <= tx_special_2_in;
   tx_special_3_int <= tx_special_3_in;
  end


// *******************************************************
//     Data Path MUX and output register to Decoder
// *******************************************************

assign {tx_special_0_mux} = (sel_r | sel_k | sel_a) ? 1'b1 :
                                             sel_q  ? 1'b1 : {tx_special_0_int}; 

assign {tx_special_1_mux} = (sel_r | sel_k | sel_a) ? 1'b1 :         
                                             sel_q  ? 1'b0 : {tx_special_1_int};

assign {tx_special_2_mux} = (sel_r | sel_k | sel_a) ? 1'b1 :         
                                             sel_q  ? 1'b0 : {tx_special_2_int};

assign {tx_special_3_mux} = (sel_r | sel_k | sel_a) ? 1'b1 :         
                                             sel_q  ? 1'b0 : {tx_special_3_int};

assign tx_byte_0_mux  =  sel_s ? `XPCS_ENC_SDP :

                         sel_d ? tx_byte_0_int :

                         sel_r ? `XPCS_ENC_SKP :
                         sel_k ? `XPCS_ENC_COM :
                         sel_a ? `XPCS_ENC_ALG :

                         sel_q ? `XPCS_ENC_SEQ :

                         tx_byte_0_int ;


assign tx_byte_1_mux  = sel_s ? tx_byte_1_int  :

                        sel_d ? tx_byte_1_int  :

                        sel_r ? `XPCS_ENC_SKP  :
                        sel_k ? `XPCS_ENC_COM  :
                        sel_a ? `XPCS_ENC_ALG  :

                        sel_q ? `XPCS_ENC_D00  :

                        tx_byte_1_int ;


assign tx_byte_2_mux  = sel_s ? tx_byte_2_int :
             
                        sel_d ? tx_byte_2_int :

                        sel_r ? `XPCS_ENC_SKP :
                        sel_k ? `XPCS_ENC_COM :
                        sel_a ? `XPCS_ENC_ALG :

                        sel_q ? `XPCS_ENC_D00  :

                        tx_byte_2_int ;

assign tx_byte_3_mux  = sel_s ? tx_byte_3_int :

                        sel_d ? tx_byte_3_int :

                        sel_r ? `XPCS_ENC_SKP :
                        sel_k ? `XPCS_ENC_COM :
                        sel_a ? `XPCS_ENC_ALG :

                        sel_q & q_det_remote ? `XPCS_ENC_D20  :
                        sel_q & q_det_local  ? `XPCS_ENC_D10  :

                        tx_byte_3_int ;


always @ (posedge tx_clk)
  begin
   tx_byte_0_enc <= tx_test_enable ? test_byte : term_det_0 ? `XPCS_ENC_EGP : tx_byte_0_mux ;

   tx_byte_1_enc <= tx_test_enable ? test_byte : term_det_0 ? `XPCS_ENC_COM : 
                                                     term_det_1 ? `XPCS_ENC_EGP : tx_byte_1_mux ;

   tx_byte_2_enc <= tx_test_enable ? test_byte : term_det_0 ? `XPCS_ENC_COM : 
                                                     term_det_1 ? `XPCS_ENC_COM : 
                                                     term_det_2 ? `XPCS_ENC_EGP : tx_byte_2_mux ;

   tx_byte_3_enc <= tx_test_enable ? test_byte : term_det_0 ? `XPCS_ENC_COM : 
                                                     term_det_1 ? `XPCS_ENC_COM : 
                                                     term_det_2 ? `XPCS_ENC_COM : 
                                                     term_det_3 ? `XPCS_ENC_EGP : tx_byte_3_mux ; 
  end

always @ (posedge tx_clk)
  begin
   tx_special_0_enc <= tx_test_enable ? test_special : (term_det_0) ? 1'b1 : tx_special_0_mux ; 

   tx_special_1_enc <= tx_test_enable ? test_special : (term_det_0 | term_det_1) ? 1'b1 : tx_special_1_mux;

   tx_special_2_enc <= tx_test_enable ? test_special : (term_det_0 | term_det_1 | term_det_2) ? 1'b1 : tx_special_2_mux;

   tx_special_3_enc <= tx_test_enable ? test_special : 
                             (term_det_0 | term_det_1 | term_det_2 | term_det_3) ? 1'b1 : tx_special_3_mux;

  end


// ***************************************************************
//                     Randomizers
// ***************************************************************

xpcs_tx_randomizer xpcs_tx_randomizer_l (.tx_clk(tx_clk), 
                                         .reset(reset), 
                                         .align_count_exp(align_count_exp), 
                                         .clr_align_count(clr_a_cnt), 
                                         .code_sel(code_sel_random) );


// ****************************************************************
//  Test mode logic high/low/mixed frequency patterns per Annex 48A
//   ieee 802.3 ae
//  00 high freq, 01 low freq, 10 mixed freq.
// ****************************************************************

assign test_byte    = (test_pattern_sel == 2'b00) ? `XPCS_ENC_TTH :
                      (test_pattern_sel == 2'b01) ? `XPCS_ENC_TTL :
                      (test_pattern_sel == 2'b10) ? `XPCS_ENC_COM : `XPCS_ENC_COM;

assign test_special = (test_pattern_sel == 2'b00) ?  1'b0 :         // D21.5
                      (test_pattern_sel == 2'b01) ?  1'b1 :         // K28.7
                      (test_pattern_sel == 2'b10) ?  1'b1 : 1'b1 ;  // K28.5


// 0in state -var state -val SEND_DATA -next SEND_A SEND_K -clock tx_clk -reset reset
// 0in state -var state -val SEND_SDP -next SEND_DATA UNDERRUN SEND_K -clock tx_clk -reset reset
// 0in state -var state -val SEND_A -next SEND_RANDOM_R SEND_Q SEND_SDP SEND_K -clock tx_clk -reset reset
// 0in state -var state -val SEND_K -next SEND_RANDOM_R SEND_SDP SEND_K -clock tx_clk -reset reset
// 0in state -var state -val SEND_Q -next SEND_RANDOM_R SEND_SDP SEND_K -clock tx_clk -reset reset
// 0in state -var state -val SEND_RANDOM_R -next SEND_RANDOM_A SEND_RANDOM_K SEND_SDP SEND_K -clock tx_clk -reset reset
// 0in state -var state -val SEND_RANDOM_K -next SEND_RANDOM_A SEND_RANDOM_R SEND_SDP SEND_K -clock tx_clk -reset reset
// 0in state -var state -val SEND_RANDOM_Q -next SEND_RANDOM_K SEND_RANDOM_R SEND_SDP SEND_K -clock tx_clk -reset reset
// 0in state -var state -val SEND_RANDOM_A -next SEND_RANDOM_Q SEND_RANDOM_R SEND_RANDOM_K SEND_SDP SEND_K -clock tx_clk -reset reset
// 0in state -var state -val UNDERRUN -next SEND_A SEND_K -clock tx_clk -reset reset


endmodule
Commit	Line	Data
86530b38 AT	1	// ========== Copyright Header Begin ==========================================
	2	//
	3	// OpenSPARC T2 Processor File: xpcs_tx.v
	4	// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
	5	// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
	6	//
	7	// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
	8	//
	9	// This program is free software; you can redistribute it and/or modify
	10	// it under the terms of the GNU General Public License as published by
	11	// the Free Software Foundation; version 2 of the License.
	12	//
	13	// This program is distributed in the hope that it will be useful,
	14	// but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	// GNU General Public License for more details.
	17	//
	18	// You should have received a copy of the GNU General Public License
	19	// along with this program; if not, write to the Free Software
	20	// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	21	//
	22	// For the avoidance of doubt, and except that if any non-GPL license
	23	// choice is available it will apply instead, Sun elects to use only
	24	// the General Public License version 2 (GPLv2) at this time for any
	25	// software where a choice of GPL license versions is made
	26	// available with the language indicating that GPLv2 or any later version
	27	// may be used, or where a choice of which version of the GPL is applied is
	28	// otherwise unspecified.
	29	//
	30	// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
	31	// CA 95054 USA or visit www.sun.com if you need additional information or
	32	// have any questions.
	33	//
	34	// ========== Copyright Header End ============================================
	35	/**********************************************************************/
	36	/* Project Name : Vega */
	37	/* Module Name : xpcs_tx */
	38	/* Description : XPCS transmit top level. Ranmomizer and tx state */
	39	/* machine (clause 48.2.6.2.1 ieee802.3ae). */
	40	/* */
	41	/* Link protocol: */
	42	/* */
	43	/* When xpcs receiver asserts local fault to XGMII */
	44	/* due to link loss, the xpcs transmiter transmits */
	45	/* remote faults and idles. */
	46	/* */
	47	/* When the receiver gets remote faults, the XPCS */
	48	/* passes it on to the XGMII. The MAC then generates */
	49	/* idles for XPCS to transmit to assist the remote */
	50	/* node regain link. (clause 46.3.4 p285). */
	51	/* */
	52	/* Assumptions : none. */
	53	/* */
	54	/* Parent module : xpcs_tx.v */
	55	/* Child modules : none. */
	56	/* Author Name : Carlos Castil */
	57	/* Date Created : 11/10/02 */
	58	/* */
	59	/* Copyright (c) 2002, Sun Microsystems, Inc. */
	60	/* Sun Proprietary and Confidential */
	61	/* */
	62	/* Modifications : */
	63	/**********************************************************************/
	64
65
66	module xpcs_tx ( tx_clk,
67	reset,
68
69	csr_link_status,
70	csr_tx_test_enable,
71	csr_test_pattern_sel,
72
73	tx_byte_0,
74	tx_byte_1,
75	tx_byte_2,
76	tx_byte_3,
77
78	tx_special_0,
79	tx_special_1,
80	tx_special_2,
81	tx_special_3,
82
83	tx_byte_0_enc,
84	tx_byte_1_enc,
85	tx_byte_2_enc,
86	tx_byte_3_enc,
87
88	tx_special_0_enc,
89	tx_special_1_enc,
90	tx_special_2_enc,
91	tx_special_3_enc,
92
93	csr_transmit_fault_ref,
94
95	inc_tx_pkt_count_ref,
96
97
98	state );
99
100	input tx_clk;
101	input reset;
102
103	input csr_link_status;
104	input csr_tx_test_enable;
105	input [1:0] csr_test_pattern_sel;
106
107	output inc_tx_pkt_count_ref;
108	output csr_transmit_fault_ref;
109
110	input [7:0] tx_byte_0;
111	input [7:0] tx_byte_1;
112	input [7:0] tx_byte_2;
113	input [7:0] tx_byte_3;
114
115	input tx_special_0;
116	input tx_special_1;
117	input tx_special_2;
118	input tx_special_3;
119
120	output [3:0] state;
121
122	output [7:0] tx_byte_0_enc;
123	output [7:0] tx_byte_1_enc;
124	output [7:0] tx_byte_2_enc;
125	output [7:0] tx_byte_3_enc;
126
127	output tx_special_0_enc;
128	output tx_special_1_enc;
129	output tx_special_2_enc;
130	output tx_special_3_enc;
131
132	parameter SEND_DATA = 4'h0;
133	parameter SEND_SDP = 4'h1;
134	parameter SEND_A = 4'h2;
135	parameter SEND_K = 4'h3;
136	parameter SEND_Q = 4'h4;
137	parameter SEND_RANDOM_R = 4'h5;
138	parameter SEND_RANDOM_A = 4'h6;
139	parameter SEND_RANDOM_K = 4'h7;
140	parameter SEND_RANDOM_Q = 4'h8;
141	parameter UNDERRUN = 4'h9;
142
143	reg [3:0] state;
144
145	wire [3:0] nxt_state;
146
147	reg [7:0] tx_byte_0_in;
148	reg [7:0] tx_byte_1_in;
149	reg [7:0] tx_byte_2_in;
150	reg [7:0] tx_byte_3_in;
151
152	reg tx_special_0_in;
153	reg tx_special_1_in;
154	reg tx_special_2_in;
155	reg tx_special_3_in;
156
157	reg [7:0] tx_byte_0_int;
158	reg [7:0] tx_byte_1_int;
159	reg [7:0] tx_byte_2_int;
160	reg [7:0] tx_byte_3_int;
161
162	reg tx_special_0_int;
163	reg tx_special_1_int;
164	reg tx_special_2_int;
165	reg tx_special_3_int;
166
167	wire [7:0] tx_byte_0_mux;
168	wire [7:0] tx_byte_1_mux;
169	wire [7:0] tx_byte_2_mux;
170	wire [7:0] tx_byte_3_mux;
171
172	wire tx_special_0_mux;
173	wire tx_special_1_mux;
174	wire tx_special_2_mux;
175	wire tx_special_3_mux;
176
177	reg [7:0] tx_byte_0_enc;
178	reg [7:0] tx_byte_1_enc;
179	reg [7:0] tx_byte_2_enc;
180	reg [7:0] tx_byte_3_enc;
181
182	reg tx_special_0_enc;
183	reg tx_special_1_enc;
184	reg tx_special_2_enc;
185	reg tx_special_3_enc;
186
187	wire align_count_exp;
188	wire code_sel_random;
189
190	wire sel_d, sel_k, sel_a, sel_r, sel_q;
191	wire sel_s;
192
193	wire q_detect;
194
195	wire term_det_0;
196	wire term_det_1;
197	wire term_det_2;
198	wire term_det_3;
199
200	wire idle_det_0;
201	wire idle_det_1;
202	wire idle_det_2;
203	wire idle_det_3;
204
205	wire i_detect;
206
207	wire clr_a_cnt;
208
209	wire clr_q_det;
210
211	wire xgmii_s_detect;
212	wire xgmii_d_detect;
213
214	wire csr_transmit_fault_ref;
215
216	wire [7:0] test_byte;
217	wire test_special;
218
219	wire q_detect_local;
220	wire q_detect_remote;
221
222	reg q_det_local;
223	reg q_det_remote;
224
225	wire link_status_tx;
226	wire tx_test_enable;
227
228	wire [1:0] test_pattern_sel;
229
230	/* ********************************************************** */
231	/* Synchronize */
232	/* ********************************************************** */
233
234	SYNC_CELL u_sync_link_status (
235	.D (csr_link_status), // unsynchronized
236	.CP (tx_clk),
237	.Q (link_status_tx)); // synchronized
238
239	SYNC_CELL u_sync_test_enable (
240	.D (csr_tx_test_enable), // unsynchronized
241	.CP (tx_clk),
242	.Q (tx_test_enable)); // synchronized
243
244	SYNC_CELL u_sync_test_pattern_sel_0 (
245	.D (csr_test_pattern_sel[0]), // unsynchronized
246	.CP (tx_clk),
247	.Q (test_pattern_sel[0])); // synchronized
248
249	SYNC_CELL u_sync_test_pattern_sel_1 (
250	.D (csr_test_pattern_sel[1]), // unsynchronized
251	.CP (tx_clk),
252	.Q (test_pattern_sel[1])); // synchronized
253
254	// *******************************************************
255	// q_det function per clause 48.2.6.1.4 ieee 802.3ae
256	// *******************************************************
257
258	assign q_detect_local = tx_special_0_in & (tx_byte_0_in == `XPCS_ENC_SEQ) &
259	(tx_byte_1_in == `XPCS_ENC_D00) &
260	(tx_byte_2_in == `XPCS_ENC_D00) &
261	(tx_byte_3_in == `XPCS_ENC_D10) ;
262
263	always @ (posedge tx_clk)
264	if (reset)
265	q_det_local <= 1'b0;
266	else
267	q_det_local <= (q_detect_local) ? 1'b1 : (clr_q_det) ? 1'b0 : q_det_local;
268
269
270	assign q_detect_remote = tx_special_0_in & (tx_byte_0_in == `XPCS_ENC_SEQ) &
271	(tx_byte_1_in == `XPCS_ENC_D00) &
272	(tx_byte_2_in == `XPCS_ENC_D00) &
273	(tx_byte_3_in == `XPCS_ENC_D20) ;
274
275	always @ (posedge tx_clk)
276	if (reset)
277	q_det_remote <= 1'b0;
278	else
279	q_det_remote <= ((!link_status_tx) \| q_detect_remote) ? 1'b1 :
280	(clr_q_det) ? 1'b0 : q_det_remote;
281
282
283	assign q_detect = q_det_local \| q_det_remote;
284
285
286	assign csr_transmit_fault_ref = q_detect;
287
288	// *******************************************************
289	// sop detection logic
290	// *******************************************************
291
292	assign xgmii_s_detect = tx_special_0_in & (tx_byte_0_in == `XPCS_ENC_SDP);
293
294	// *******************************************************
295	// data detection logic
296	// *******************************************************
297
298	assign xgmii_d_detect = (!tx_special_0_in) \|
299	(!tx_special_1_in) \|
300	(!tx_special_2_in) \|
301	(!tx_special_3_in) &
302	( link_status_tx & !xgmii_s_detect );
303
304	// ***************************************************************
305	// Terminate detection
306	// ***************************************************************
307
308	assign term_det_0 = tx_special_0_mux & (tx_byte_0_mux == `XPCS_ENC_EGP) &
309	tx_special_1_mux & (tx_byte_1_mux == `XPCS_ENC_IDL) &
310	tx_special_2_mux & (tx_byte_2_mux == `XPCS_ENC_IDL) &
311	tx_special_3_mux & (tx_byte_3_mux == `XPCS_ENC_IDL);
312
313	assign term_det_1 = tx_special_1_mux & (tx_byte_1_mux == `XPCS_ENC_EGP) &
314	tx_special_2_mux & (tx_byte_2_mux == `XPCS_ENC_IDL) &
315	tx_special_3_mux & (tx_byte_3_mux == `XPCS_ENC_IDL);
316
317	assign term_det_2 = tx_special_2_mux & (tx_byte_2_mux == `XPCS_ENC_EGP) &
318	tx_special_3_mux & (tx_byte_3_mux == `XPCS_ENC_IDL);
319
320	assign term_det_3 = tx_special_3_mux & (tx_byte_3_mux == `XPCS_ENC_EGP);
321
322
323	assign inc_tx_pkt_count_ref = term_det_0 \| term_det_1 \| term_det_2 \| term_det_3 ;
324
325
326	// ***************************************************************
327	// Idle detection
328	// ***************************************************************
329
330	assign idle_det_0 = tx_special_0_in & (tx_byte_0_in == `XPCS_ENC_IDL);
331	assign idle_det_1 = tx_special_1_in & (tx_byte_1_in == `XPCS_ENC_IDL);
332	assign idle_det_2 = tx_special_2_in & (tx_byte_2_in == `XPCS_ENC_IDL);
333	assign idle_det_3 = tx_special_3_in & (tx_byte_3_in == `XPCS_ENC_IDL);
334
335	assign i_detect = idle_det_0 & idle_det_1 & idle_det_2 & idle_det_3;
336
337	// ***************************************************************
338	// State Machine 48.2.6.2.1 ieee 802.3ae
339	// ***************************************************************
340
341	/* *************************************************************************
342	{n_state, n_clr_a_cnt, n_clr_q_det, n_sel_s
343	n_sel_d, n_sel_r, n_sel_k, n_sel_a, n_sel_q};
344	***********************************************************************/
345
346	assign {nxt_state,
347	clr_a_cnt,
348	clr_q_det,
349	sel_s,
350	sel_d,
351	sel_r,
352	sel_k,
353	sel_a,
354	sel_q} = transmit_fn (reset,
355	align_count_exp,
356	code_sel_random,
357	q_detect,
358	i_detect,
359	xgmii_s_detect,
360	xgmii_d_detect,
361	state);
362
363	function [11:0] transmit_fn;
364
365	input reset;
366	input a_cnt;
367	input code_sel;
368	input q_det;
369	input i_det;
370	input s_det;
371	input d_det;
372	input [3:0] state;
373
374	reg [3:0] n_state;
375
376	reg n_clr_a_cnt;
377	reg n_clr_q_det;
378
379	reg n_sel_d;
380	reg n_sel_a;
381	reg n_sel_k;
382	reg n_sel_r;
383	reg n_sel_q;
384	reg n_sel_s;
385
386	reg nxt_ifg;
387
388	begin
389
390	if (reset)
391	begin
392
393	n_clr_a_cnt = 1'b0;
394	n_clr_q_det = 1'b0;
395
396	n_sel_d = 1'b0;
397	n_sel_r = 1'b0;
398	n_sel_k = 1'b0;
399	n_sel_a = 1'b0;
400	n_sel_q = 1'b0;
401	n_sel_s = 1'b0;
402
403	nxt_ifg = 1'b0;
404
405	n_state = SEND_K; // send K
406
407	end
408
409	else
410
411	begin
412
413	n_state = SEND_K;
414
415	n_clr_a_cnt = 1'b0;
416
417	n_clr_q_det = 1'b0;
418
419	n_sel_d = 1'b0;
420	n_sel_r = 1'b0;
421	n_sel_k = 1'b0;
422	n_sel_a = 1'b0;
423	n_sel_q = 1'b0;
424	n_sel_s = 1'b0;
425
426	case (state)
427
428	SEND_DATA : // 0
429	begin
430	n_sel_d = 1'b1;
431
432	if (i_det \| q_det)
433	begin
434	if (nxt_ifg & a_cnt)
435	n_state = SEND_A;
436
437	else if (!nxt_ifg \| !a_cnt)
438	n_state = SEND_K;
439	end
440	else
441	n_state = SEND_DATA;
442
443	end
444
445
446	SEND_SDP : // 1
447	begin
448	n_sel_s = 1'b1;
449
450	if (d_det)
451	n_state = SEND_DATA;
452	else
453	n_state = UNDERRUN;
454
455	end
456
457
458	SEND_A : // 2
459	begin
460	n_clr_a_cnt = 1'b1;
461	n_sel_a = 1'b1;
462	nxt_ifg = 1'b0; // select K next instead of A
463
464	if (q_det)
465	n_state = SEND_Q;
466
467	else if (s_det)
468	n_state = SEND_SDP;
469
470	else
471	n_state = SEND_RANDOM_R;
472
473	end
474
475	SEND_K : // 3
476	begin
477	n_sel_k = 1'b1;
478	nxt_ifg = 1'b1; // select A next instead of K
479
480	if (s_det)
481	n_state = SEND_SDP;
482
483	else
484	n_state = SEND_RANDOM_R;
485
486	end
487
488	SEND_Q : // 4
489	begin
490	n_sel_q = 1'b1;
491	n_clr_q_det = 1'b1;
492
493	if (s_det)
494	n_state = SEND_SDP;
495
496	else
497	n_state = SEND_RANDOM_R;
498
499	end
500
501	SEND_RANDOM_R : // 5
502	begin
503	n_sel_r = 1'b1;
504
505	if (s_det)
506	n_state = SEND_SDP;
507
508	else if (code_sel & !a_cnt)
509	n_state = SEND_RANDOM_R;
510
511	else if ((!code_sel) & !a_cnt)
512	n_state = SEND_RANDOM_K;
513
514	else if (a_cnt)
515	n_state = SEND_RANDOM_A;
516
517	end
518
519	SEND_RANDOM_A : // 6
520	begin
521	n_sel_a = 1'b1;
522	n_clr_a_cnt = 1'b1;
523
524	if (s_det)
525	n_state = SEND_SDP;
526
527	else if (q_det)
528	n_state = SEND_RANDOM_Q;
529
530	else if (code_sel & !q_det)
531	n_state = SEND_RANDOM_R;
532
533	else if ((!code_sel) & !q_det)
534	n_state = SEND_RANDOM_K;
535
536	end
537
538
539	SEND_RANDOM_K : // 7
540	begin
541	n_sel_k = 1'b1;
542
543	if (s_det)
544	n_state = SEND_SDP;
545
546	else if (a_cnt)
547	n_state = SEND_RANDOM_A;
548
549	else if (code_sel & !a_cnt)
550	n_state = SEND_RANDOM_R;
551
552	else if ((!code_sel) & !a_cnt)
553	n_state = SEND_RANDOM_K;
554
555
556	end
557
558
559	SEND_RANDOM_Q : // 8
560	begin
561	n_sel_q = 1'b1;
562	n_clr_q_det = 1'b1;
563
564	if (s_det)
565	n_state = SEND_SDP;
566
567	else if (code_sel)
568	n_state = SEND_RANDOM_R;
569
570	else if (!code_sel)
571	n_state = SEND_RANDOM_K;
572
573	end
574
575	UNDERRUN : // 9
576	begin
577	n_state = SEND_A;
578	end
579
580
581	endcase
582
583	end
584
585	transmit_fn = {n_state, n_clr_a_cnt, n_clr_q_det, n_sel_s,
586	n_sel_d, n_sel_r, n_sel_k, n_sel_a, n_sel_q};
587
588	end
589
590	endfunction
591
592
593	// State machine register
594
595	always @ (posedge tx_clk)
596	if (reset)
597	state <= 4'h0;
598	else
599	state <= nxt_state;
600
601	// *******************************************************
602	// Data Path Pipeline
603	// *******************************************************
604
605	always @ (posedge tx_clk)
606	begin
607	tx_byte_0_in <= tx_byte_0;
608	tx_byte_1_in <= tx_byte_1;
609	tx_byte_2_in <= tx_byte_2;
610	tx_byte_3_in <= tx_byte_3;
611	end
612
613	always @ (posedge tx_clk)
614	begin
615	tx_special_0_in <= tx_special_0;
616	tx_special_1_in <= tx_special_1;
617	tx_special_2_in <= tx_special_2;
618	tx_special_3_in <= tx_special_3;
619	end
620
621	always @ (posedge tx_clk)
622	begin
623	tx_byte_0_int <= tx_byte_0_in;
624	tx_byte_1_int <= tx_byte_1_in;
625	tx_byte_2_int <= tx_byte_2_in;
626	tx_byte_3_int <= tx_byte_3_in;
627	end
628
629	always @ (posedge tx_clk)
630	begin
631	tx_special_0_int <= tx_special_0_in;
632	tx_special_1_int <= tx_special_1_in;
633	tx_special_2_int <= tx_special_2_in;
634	tx_special_3_int <= tx_special_3_in;
635	end
636
637
638	// *******************************************************
639	// Data Path MUX and output register to Decoder
640	// *******************************************************
641
642	assign {tx_special_0_mux} = (sel_r \| sel_k \| sel_a) ? 1'b1 :
643	sel_q ? 1'b1 : {tx_special_0_int};
644
645	assign {tx_special_1_mux} = (sel_r \| sel_k \| sel_a) ? 1'b1 :
646	sel_q ? 1'b0 : {tx_special_1_int};
647
648	assign {tx_special_2_mux} = (sel_r \| sel_k \| sel_a) ? 1'b1 :
649	sel_q ? 1'b0 : {tx_special_2_int};
650
651	assign {tx_special_3_mux} = (sel_r \| sel_k \| sel_a) ? 1'b1 :
652	sel_q ? 1'b0 : {tx_special_3_int};
653
654	assign tx_byte_0_mux = sel_s ? `XPCS_ENC_SDP :
655
656	sel_d ? tx_byte_0_int :
657
658	sel_r ? `XPCS_ENC_SKP :
659	sel_k ? `XPCS_ENC_COM :
660	sel_a ? `XPCS_ENC_ALG :
661
662	sel_q ? `XPCS_ENC_SEQ :
663
664	tx_byte_0_int ;
665
666
667	assign tx_byte_1_mux = sel_s ? tx_byte_1_int :
668
669	sel_d ? tx_byte_1_int :
670
671	sel_r ? `XPCS_ENC_SKP :
672	sel_k ? `XPCS_ENC_COM :
673	sel_a ? `XPCS_ENC_ALG :
674
675	sel_q ? `XPCS_ENC_D00 :
676
677	tx_byte_1_int ;
678
679
680	assign tx_byte_2_mux = sel_s ? tx_byte_2_int :
681
682	sel_d ? tx_byte_2_int :
683
684	sel_r ? `XPCS_ENC_SKP :
685	sel_k ? `XPCS_ENC_COM :
686	sel_a ? `XPCS_ENC_ALG :
687
688	sel_q ? `XPCS_ENC_D00 :
689
690	tx_byte_2_int ;
691
692	assign tx_byte_3_mux = sel_s ? tx_byte_3_int :
693
694	sel_d ? tx_byte_3_int :
695
696	sel_r ? `XPCS_ENC_SKP :
697	sel_k ? `XPCS_ENC_COM :
698	sel_a ? `XPCS_ENC_ALG :
699
700	sel_q & q_det_remote ? `XPCS_ENC_D20 :
701	sel_q & q_det_local ? `XPCS_ENC_D10 :
702
703	tx_byte_3_int ;
704
705
706	always @ (posedge tx_clk)
707	begin
708	tx_byte_0_enc <= tx_test_enable ? test_byte : term_det_0 ? `XPCS_ENC_EGP : tx_byte_0_mux ;
709
710	tx_byte_1_enc <= tx_test_enable ? test_byte : term_det_0 ? `XPCS_ENC_COM :
711	term_det_1 ? `XPCS_ENC_EGP : tx_byte_1_mux ;
712
713	tx_byte_2_enc <= tx_test_enable ? test_byte : term_det_0 ? `XPCS_ENC_COM :
714	term_det_1 ? `XPCS_ENC_COM :
715	term_det_2 ? `XPCS_ENC_EGP : tx_byte_2_mux ;
716
717	tx_byte_3_enc <= tx_test_enable ? test_byte : term_det_0 ? `XPCS_ENC_COM :
718	term_det_1 ? `XPCS_ENC_COM :
719	term_det_2 ? `XPCS_ENC_COM :
720	term_det_3 ? `XPCS_ENC_EGP : tx_byte_3_mux ;
721	end
722
723	always @ (posedge tx_clk)
724	begin
725	tx_special_0_enc <= tx_test_enable ? test_special : (term_det_0) ? 1'b1 : tx_special_0_mux ;
726
727	tx_special_1_enc <= tx_test_enable ? test_special : (term_det_0 \| term_det_1) ? 1'b1 : tx_special_1_mux;
728
729	tx_special_2_enc <= tx_test_enable ? test_special : (term_det_0 \| term_det_1 \| term_det_2) ? 1'b1 : tx_special_2_mux;
730
731	tx_special_3_enc <= tx_test_enable ? test_special :
732	(term_det_0 \| term_det_1 \| term_det_2 \| term_det_3) ? 1'b1 : tx_special_3_mux;
733
734	end
735
736
737
738
739	// ***************************************************************
740	// Randomizers
741	// ***************************************************************
742
743	xpcs_tx_randomizer xpcs_tx_randomizer_l (.tx_clk(tx_clk),
744	.reset(reset),
745	.align_count_exp(align_count_exp),
746	.clr_align_count(clr_a_cnt),
747	.code_sel(code_sel_random) );
748
749
750	// ****************************************************************
751	// Test mode logic high/low/mixed frequency patterns per Annex 48A
752	// ieee 802.3 ae
753	// 00 high freq, 01 low freq, 10 mixed freq.
754	// ****************************************************************
755
756	assign test_byte = (test_pattern_sel == 2'b00) ? `XPCS_ENC_TTH :
757	(test_pattern_sel == 2'b01) ? `XPCS_ENC_TTL :
758	(test_pattern_sel == 2'b10) ? `XPCS_ENC_COM : `XPCS_ENC_COM;
759
760	assign test_special = (test_pattern_sel == 2'b00) ? 1'b0 : // D21.5
761	(test_pattern_sel == 2'b01) ? 1'b1 : // K28.7
762	(test_pattern_sel == 2'b10) ? 1'b1 : 1'b1 ; // K28.5
763
764
765	// 0in state -var state -val SEND_DATA -next SEND_A SEND_K -clock tx_clk -reset reset
766	// 0in state -var state -val SEND_SDP -next SEND_DATA UNDERRUN SEND_K -clock tx_clk -reset reset
767	// 0in state -var state -val SEND_A -next SEND_RANDOM_R SEND_Q SEND_SDP SEND_K -clock tx_clk -reset reset
768	// 0in state -var state -val SEND_K -next SEND_RANDOM_R SEND_SDP SEND_K -clock tx_clk -reset reset
769	// 0in state -var state -val SEND_Q -next SEND_RANDOM_R SEND_SDP SEND_K -clock tx_clk -reset reset
770	// 0in state -var state -val SEND_RANDOM_R -next SEND_RANDOM_A SEND_RANDOM_K SEND_SDP SEND_K -clock tx_clk -reset reset
771	// 0in state -var state -val SEND_RANDOM_K -next SEND_RANDOM_A SEND_RANDOM_R SEND_SDP SEND_K -clock tx_clk -reset reset
772	// 0in state -var state -val SEND_RANDOM_Q -next SEND_RANDOM_K SEND_RANDOM_R SEND_SDP SEND_K -clock tx_clk -reset reset
773	// 0in state -var state -val SEND_RANDOM_A -next SEND_RANDOM_Q SEND_RANDOM_R SEND_RANDOM_K SEND_SDP SEND_K -clock tx_clk -reset reset
774	// 0in state -var state -val UNDERRUN -next SEND_A SEND_K -clock tx_clk -reset reset
775
776
777	endmodule