projects / OpenSPARC-T2-DV / blame
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1 | // ========== Copyright Header Begin ========================================== |
| 2 | // | |
| 3 | // OpenSPARC T2 Processor File: xpcs_txio.v | |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
| 6 | // | |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
| 8 | // | |
| 9 | // This program is free software; you can redistribute it and/or modify | |
| 10 | // it under the terms of the GNU General Public License as published by | |
| 11 | // the Free Software Foundation; version 2 of the License. | |
| 12 | // | |
| 13 | // This program is distributed in the hope that it will be useful, | |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 16 | // GNU General Public License for more details. | |
| 17 | // | |
| 18 | // You should have received a copy of the GNU General Public License | |
| 19 | // along with this program; if not, write to the Free Software | |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
| 21 | // | |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license | |
| 23 | // choice is available it will apply instead, Sun elects to use only | |
| 24 | // the General Public License version 2 (GPLv2) at this time for any | |
| 25 | // software where a choice of GPL license versions is made | |
| 26 | // available with the language indicating that GPLv2 or any later version | |
| 27 | // may be used, or where a choice of which version of the GPL is applied is | |
| 28 | // otherwise unspecified. | |
| 29 | // | |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
| 32 | // have any questions. | |
| 33 | // | |
| 34 | // ========== Copyright Header End ============================================ | |
| 35 | // **************************************************************** | |
| 36 | // | |
| 37 | // Sun Proprietary/Confidential: Internal Use Only | |
| 38 | // | |
| 39 | // **************************************************************** | |
| 40 | // Design: XPCS Phy Interface Core | |
| 41 | // Block: XPCS Phy Interface Core Top Level | |
| 42 | // Author: Carlos Castil | |
| 43 | // | |
| 44 | // Module: xpcs_txio | |
| 45 | // File: xpcs_txio.v | |
| 46 | // | |
| 47 | // Description: This block contains 8 channel transmit physical | |
| 48 | // interface to ieee 802.3 clause 48 xpcs. | |
| 49 | // | |
| 50 | // Revision History | |
| 51 | // ------------------------------------------------------------ | |
| 52 | // Ver Date Comments | |
| 53 | // ------------------------------------------------------------ | |
| 54 | // 1.0 11/12/02 Created | |
| 55 | // | |
| 56 | // **************************************************************** | |
| 57 | ||
| 58 | module xpcs_txio ( | |
| 59 | reset, | |
| 60 | tx_clk, | |
| 61 | ||
| 62 | tx_byte_0, | |
| 63 | tx_byte_1, | |
| 64 | tx_byte_2, | |
| 65 | tx_byte_3, | |
| 66 | ||
| 67 | tx_special_0, | |
| 68 | tx_special_1, | |
| 69 | tx_special_2, | |
| 70 | tx_special_3, | |
| 71 | ||
| 72 | tx_symbol_0, | |
| 73 | tx_symbol_1, | |
| 74 | tx_symbol_2, | |
| 75 | tx_symbol_3 | |
| 76 | ||
| 77 | ); | |
| 78 | ||
| 79 | // Interface | |
| 80 | input reset; | |
| 81 | input tx_clk; | |
| 82 | ||
| 83 | input [7:0] tx_byte_0; | |
| 84 | input [7:0] tx_byte_1; | |
| 85 | input [7:0] tx_byte_2; | |
| 86 | input [7:0] tx_byte_3; | |
| 87 | ||
| 88 | input tx_special_0; | |
| 89 | input tx_special_1; | |
| 90 | input tx_special_2; | |
| 91 | input tx_special_3; | |
| 92 | ||
| 93 | output [9:0] tx_symbol_0; | |
| 94 | output [9:0] tx_symbol_1; | |
| 95 | output [9:0] tx_symbol_2; | |
| 96 | output [9:0] tx_symbol_3; | |
| 97 | ||
| 98 | ||
| 99 | // lane 0 macro | |
| 100 | ||
| 101 | xpcs_txio_pcs u_lane_0 ( | |
| 102 | .reset (reset), | |
| 103 | .tx_clk (tx_clk), | |
| 104 | ||
| 105 | .tx_byte (tx_byte_0), | |
| 106 | .tx_special (tx_special_0), | |
| 107 | ||
| 108 | .tx_symbol (tx_symbol_0) ); | |
| 109 | ||
| 110 | // lane 1 macro | |
| 111 | ||
| 112 | xpcs_txio_pcs u_lane_1 ( | |
| 113 | .reset (reset), | |
| 114 | .tx_clk (tx_clk), | |
| 115 | ||
| 116 | .tx_byte (tx_byte_1), | |
| 117 | .tx_special (tx_special_1), | |
| 118 | ||
| 119 | .tx_symbol (tx_symbol_1) ); | |
| 120 | ||
| 121 | ||
| 122 | // lane 2 macro | |
| 123 | ||
| 124 | xpcs_txio_pcs u_lane_2 ( | |
| 125 | .reset (reset), | |
| 126 | .tx_clk (tx_clk), | |
| 127 | ||
| 128 | .tx_byte (tx_byte_2), | |
| 129 | .tx_special (tx_special_2), | |
| 130 | ||
| 131 | .tx_symbol (tx_symbol_2) ); | |
| 132 | ||
| 133 | // lane 3 macro | |
| 134 | ||
| 135 | xpcs_txio_pcs u_lane_3 ( | |
| 136 | .reset (reset), | |
| 137 | .tx_clk (tx_clk), | |
| 138 | ||
| 139 | .tx_byte (tx_byte_3), | |
| 140 | .tx_special (tx_special_3), | |
| 141 | ||
| 142 | .tx_symbol (tx_symbol_3) ); | |
| 143 | ||
| 144 | ||
| 145 | endmodule |