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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: xpcs_xgmii_dpath.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | /**********************************************************************/ | |
36 | /* Project Name : Vega */ | |
37 | /* Module Name : xpcs_xgmii_dpath */ | |
38 | /* Description : */ | |
39 | /* */ | |
40 | /* Assumptions : none. */ | |
41 | /* */ | |
42 | /* Parent module : xpcs_xgmii_dpath.v */ | |
43 | /* Child modules : none. */ | |
44 | /* Author Name : Carlos Castil */ | |
45 | /* Date Created : 8/17/03 */ | |
46 | /* */ | |
47 | /* Copyright (c) 2002, Sun Microsystems, Inc. */ | |
48 | /* Sun Proprietary and Confidential */ | |
49 | /* */ | |
50 | /* Modifications : */ | |
51 | /**********************************************************************/ | |
52 | ||
53 | ||
54 | ||
55 | module xpcs_xgmii_dpath ( | |
56 | ||
57 | reset_txclk, | |
58 | reset_rxclk, | |
59 | ||
60 | tx_clk, // 312 mhz tx clk | |
61 | ||
62 | rbc0_a, | |
63 | ||
64 | xpcs_rxd, // outputs to XMAC receive | |
65 | xpcs_rxc, | |
66 | ||
67 | xpcs_txd, // inputs from XMAC transmit | |
68 | xpcs_txc, | |
69 | ||
70 | // inputs from XPCS receive | |
71 | ||
72 | rx_xgmii_byte_0, | |
73 | rx_xgmii_byte_1, | |
74 | rx_xgmii_byte_2, | |
75 | rx_xgmii_byte_3, | |
76 | ||
77 | rx_xgmii_special_0, | |
78 | rx_xgmii_special_1, | |
79 | rx_xgmii_special_2, | |
80 | rx_xgmii_special_3, | |
81 | ||
82 | // outputs to XPCS transmit | |
83 | ||
84 | tx_xgmii_byte_0, | |
85 | tx_xgmii_byte_1, | |
86 | tx_xgmii_byte_2, | |
87 | tx_xgmii_byte_3, | |
88 | ||
89 | tx_xgmii_special_0, | |
90 | tx_xgmii_special_1, | |
91 | tx_xgmii_special_2, | |
92 | tx_xgmii_special_3 | |
93 | ||
94 | ); | |
95 | ||
96 | input reset_txclk; | |
97 | input reset_rxclk; | |
98 | ||
99 | input tx_clk; // 312 mhz tx clk | |
100 | input rbc0_a; | |
101 | ||
102 | output [63:0] xpcs_rxd; // outputs to XMAC receive | |
103 | output [7:0] xpcs_rxc; | |
104 | ||
105 | input [63:0] xpcs_txd; // inputs from XMAC transmit | |
106 | input [7:0] xpcs_txc; | |
107 | ||
108 | // inputs from XPCS receive | |
109 | ||
110 | input [7:0] rx_xgmii_byte_0; | |
111 | input [7:0] rx_xgmii_byte_1; | |
112 | input [7:0] rx_xgmii_byte_2; | |
113 | input [7:0] rx_xgmii_byte_3; | |
114 | ||
115 | input rx_xgmii_special_0; | |
116 | input rx_xgmii_special_1; | |
117 | input rx_xgmii_special_2; | |
118 | input rx_xgmii_special_3; | |
119 | ||
120 | // outputs to XPCS transmit | |
121 | ||
122 | output [7:0] tx_xgmii_byte_0; | |
123 | output [7:0] tx_xgmii_byte_1; | |
124 | output [7:0] tx_xgmii_byte_2; | |
125 | output [7:0] tx_xgmii_byte_3; | |
126 | ||
127 | output tx_xgmii_special_0; | |
128 | output tx_xgmii_special_1; | |
129 | output tx_xgmii_special_2; | |
130 | output tx_xgmii_special_3; | |
131 | ||
132 | reg [63:0] xpcs_rxd; | |
133 | reg load_rx_word; | |
134 | ||
135 | reg [7:0] xpcs_rxc; | |
136 | ||
137 | reg [7:0] tx_xgmii_byte_0; | |
138 | reg [7:0] tx_xgmii_byte_1; | |
139 | reg [7:0] tx_xgmii_byte_2; | |
140 | reg [7:0] tx_xgmii_byte_3; | |
141 | ||
142 | reg [7:0] shift_byte_0; | |
143 | reg [7:0] shift_byte_1; | |
144 | reg [7:0] shift_byte_2; | |
145 | reg [7:0] shift_byte_3; | |
146 | reg [7:0] shift_byte_4; | |
147 | reg [7:0] shift_byte_5; | |
148 | reg [7:0] shift_byte_6; | |
149 | reg [7:0] shift_byte_7; | |
150 | ||
151 | reg tx_xgmii_special_0; | |
152 | reg tx_xgmii_special_1; | |
153 | reg tx_xgmii_special_2; | |
154 | reg tx_xgmii_special_3; | |
155 | ||
156 | reg shift_special_0; | |
157 | reg shift_special_1; | |
158 | reg shift_special_2; | |
159 | reg shift_special_3; | |
160 | reg shift_special_4; | |
161 | reg shift_special_5; | |
162 | reg shift_special_6; | |
163 | reg shift_special_7; | |
164 | ||
165 | wire det_sop; | |
166 | wire pulse_det_sop; | |
167 | wire load_tx_hi; | |
168 | ||
169 | reg det_sop_d; | |
170 | reg load_tx_hi_r; | |
171 | ||
172 | // *********************************************** | |
173 | // Double byte XGMII RX at 156 Mhz | |
174 | // *********************************************** | |
175 | ||
176 | always @ (posedge rbc0_a) | |
177 | if (reset_rxclk) | |
178 | begin | |
179 | shift_byte_0 <= 8'h00; | |
180 | shift_byte_1 <= 8'h00; | |
181 | shift_byte_2 <= 8'h00; | |
182 | shift_byte_3 <= 8'h00; | |
183 | shift_byte_4 <= 8'h00; | |
184 | shift_byte_5 <= 8'h00; | |
185 | shift_byte_6 <= 8'h00; | |
186 | shift_byte_7 <= 8'h00; | |
187 | end | |
188 | else | |
189 | begin | |
190 | shift_byte_4 <= rx_xgmii_byte_0; | |
191 | shift_byte_0 <= shift_byte_4; | |
192 | ||
193 | shift_byte_5 <= rx_xgmii_byte_1; | |
194 | shift_byte_1 <= shift_byte_5; | |
195 | ||
196 | shift_byte_6 <= rx_xgmii_byte_2; | |
197 | shift_byte_2 <= shift_byte_6; | |
198 | ||
199 | shift_byte_7 <= rx_xgmii_byte_3; | |
200 | shift_byte_3 <= shift_byte_7; | |
201 | end | |
202 | ||
203 | always @ (posedge rbc0_a) | |
204 | if (reset_rxclk) | |
205 | begin | |
206 | shift_special_0 <= 1'b0; | |
207 | shift_special_1 <= 1'b0; | |
208 | shift_special_2 <= 1'b0; | |
209 | shift_special_3 <= 1'b0; | |
210 | shift_special_4 <= 1'b0; | |
211 | shift_special_5 <= 1'b0; | |
212 | shift_special_6 <= 1'b0; | |
213 | shift_special_7 <= 1'b0; | |
214 | end | |
215 | else | |
216 | begin | |
217 | shift_special_4 <= rx_xgmii_special_0; | |
218 | shift_special_0 <= shift_special_4; | |
219 | ||
220 | shift_special_5 <= rx_xgmii_special_1; | |
221 | shift_special_1 <= shift_special_5; | |
222 | ||
223 | shift_special_6 <= rx_xgmii_special_2; | |
224 | shift_special_2 <= shift_special_6; | |
225 | ||
226 | shift_special_7 <= rx_xgmii_special_3; | |
227 | shift_special_3 <= shift_special_7; | |
228 | end | |
229 | ||
230 | ||
231 | ||
232 | always @ (posedge rbc0_a) | |
233 | if (reset_rxclk) | |
234 | xpcs_rxd <= 64'h0100009C0100009C; | |
235 | else | |
236 | xpcs_rxd <= load_rx_word ? {shift_byte_7, shift_byte_6, shift_byte_5, shift_byte_4, | |
237 | shift_byte_3, shift_byte_2, shift_byte_1, shift_byte_0} : xpcs_rxd; | |
238 | ||
239 | always @ (posedge rbc0_a) | |
240 | if (reset_rxclk) | |
241 | xpcs_rxc <= 8'h11; | |
242 | else | |
243 | xpcs_rxc <= load_rx_word ? {shift_special_7, shift_special_6, shift_special_5, shift_special_4, | |
244 | shift_special_3, shift_special_2, shift_special_1, shift_special_0} : xpcs_rxc; | |
245 | ||
246 | ||
247 | always @ (posedge rbc0_a) | |
248 | if (reset_rxclk) | |
249 | load_rx_word <= 1'b0; | |
250 | else | |
251 | load_rx_word <= !load_rx_word; | |
252 | ||
253 | ||
254 | // *********************************************** | |
255 | // Double byte XGMII TX at 156 Mhz | |
256 | // *********************************************** | |
257 | ||
258 | assign det_sop = ({1'b0,xpcs_txc[0],xpcs_txd[7:0]} == `XPCS_DEC_SDP) | | |
259 | ({1'b0,xpcs_txc[4],xpcs_txd[39:32]} == `XPCS_DEC_SDP); | |
260 | ||
261 | always @ (posedge tx_clk) | |
262 | det_sop_d <= det_sop; | |
263 | ||
264 | assign pulse_det_sop = det_sop & !det_sop_d; | |
265 | ||
266 | always @ (posedge tx_clk) | |
267 | if (reset_txclk) | |
268 | load_tx_hi_r <= 1'b0; | |
269 | else | |
270 | load_tx_hi_r <= pulse_det_sop ? 1'b1 : !load_tx_hi_r; | |
271 | ||
272 | assign load_tx_hi = pulse_det_sop ? 1'b0 : load_tx_hi_r; | |
273 | ||
274 | ||
275 | always @ (posedge tx_clk) | |
276 | if (reset_txclk) | |
277 | begin | |
278 | tx_xgmii_byte_0 <= 8'h00; | |
279 | tx_xgmii_byte_1 <= 8'h00; | |
280 | tx_xgmii_byte_2 <= 8'h00; | |
281 | tx_xgmii_byte_3 <= 8'h00; | |
282 | end | |
283 | else | |
284 | begin | |
285 | tx_xgmii_byte_0 <= load_tx_hi ? xpcs_txd[39:32] : xpcs_txd[7:0]; | |
286 | tx_xgmii_byte_1 <= load_tx_hi ? xpcs_txd[47:40] : xpcs_txd[15:8]; | |
287 | tx_xgmii_byte_2 <= load_tx_hi ? xpcs_txd[55:48] : xpcs_txd[23:16]; | |
288 | tx_xgmii_byte_3 <= load_tx_hi ? xpcs_txd[63:56] : xpcs_txd[31:24]; | |
289 | end | |
290 | ||
291 | ||
292 | always @ (posedge tx_clk) | |
293 | if (reset_txclk) | |
294 | begin | |
295 | tx_xgmii_special_0 <= 1'b0; | |
296 | tx_xgmii_special_1 <= 1'b0; | |
297 | tx_xgmii_special_2 <= 1'b0; | |
298 | tx_xgmii_special_3 <= 1'b0; | |
299 | end | |
300 | else | |
301 | begin | |
302 | tx_xgmii_special_0 <= load_tx_hi ? xpcs_txc[4] : xpcs_txc[0]; | |
303 | tx_xgmii_special_1 <= load_tx_hi ? xpcs_txc[5] : xpcs_txc[1]; | |
304 | tx_xgmii_special_2 <= load_tx_hi ? xpcs_txc[6] : xpcs_txc[2]; | |
305 | tx_xgmii_special_3 <= load_tx_hi ? xpcs_txc[7] : xpcs_txc[3]; | |
306 | end | |
307 | ||
308 | ||
309 | ||
310 | endmodule |