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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / design / sys / iop / pcie_common / rtl / dmu_common_ccc.v
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AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: dmu_common_ccc.v
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
19// along with this program; if not, write to the Free Software
20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
23// choice is available it will apply instead, Sun elects to use only
24// the General Public License version 2 (GPLv2) at this time for any
25// software where a choice of GPL license versions is made
26// available with the language indicating that GPLv2 or any later version
27// may be used, or where a choice of which version of the GPL is applied is
28// otherwise unspecified.
29//
30// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
31// CA 95054 USA or visit www.sun.com if you need additional information or
32// have any questions.
33//
34// ========== Copyright Header End ============================================
35module dmu_common_ccc
36 (
37 csr_host_0_done,
38 csr_host_0_done_status,
39 csr_host_0_read_data,
40 csr_host_1_done,
41 csr_host_1_done_status,
42 csr_host_1_read_data,
43 csr_host_2_done,
44 csr_host_2_done_status,
45 csr_host_2_read_data,
46 csr_host_3_done,
47 csr_host_3_done_status,
48 csr_host_3_read_data,
49 csr_ring_out,
50 clk,
51 rst_l,
52 csr_ring_in,
53 csr_host_0_req,
54 csr_host_0_addr,
55 csr_host_0_data,
56 csr_host_0_wr,
57 csr_host_0_src_bus_id,
58 csr_host_1_req,
59 csr_host_1_addr,
60 csr_host_1_data,
61 csr_host_1_wr,
62 csr_host_1_src_bus_id,
63 csr_host_2_req,
64 csr_host_2_addr,
65 csr_host_2_data,
66 csr_host_2_wr,
67 csr_host_2_src_bus_id,
68 csr_host_3_req,
69 csr_host_3_addr,
70 csr_host_3_data,
71 csr_host_3_wr,
72 csr_host_3_src_bus_id,
73 csr_host_bit_check_mask,
74 done_timeout_value,
75 ccc_idle
76 );
77
78// ----------------------------------------------------------------------------
79// Parameters
80// ----------------------------------------------------------------------------
81
82// ----------------------------------------------------------------------------
83// Ports
84// ----------------------------------------------------------------------------
85 output csr_host_0_done;
86 output [`FIRE_CSR_STTS_BITS] csr_host_0_done_status;
87 output [`FIRE_CSR_DATA_BITS] csr_host_0_read_data;
88 output csr_host_1_done;
89 output [`FIRE_CSR_STTS_BITS] csr_host_1_done_status;
90 output [`FIRE_CSR_DATA_BITS] csr_host_1_read_data;
91 output csr_host_2_done;
92 output [`FIRE_CSR_STTS_BITS] csr_host_2_done_status;
93 output [`FIRE_CSR_DATA_BITS] csr_host_2_read_data;
94 output csr_host_3_done;
95 output [`FIRE_CSR_STTS_BITS] csr_host_3_done_status;
96 output [`FIRE_CSR_DATA_BITS] csr_host_3_read_data;
97 output [`FIRE_CSR_RING_BITS] csr_ring_out;
98 output ccc_idle;
99
100 input clk;
101 input rst_l;
102 input [`FIRE_CSR_RING_BITS] csr_ring_in;
103
104 input csr_host_0_req;
105 input [`FIRE_CSR_ADDR_BITS] csr_host_0_addr;
106 input [`FIRE_CSR_DATA_BITS] csr_host_0_data;
107 input csr_host_0_wr;
108 input [`FIRE_CSR_SRCB_BITS] csr_host_0_src_bus_id;
109
110 input csr_host_1_req;
111 input [`FIRE_CSR_ADDR_BITS] csr_host_1_addr;
112 input [`FIRE_CSR_DATA_BITS] csr_host_1_data;
113 input csr_host_1_wr;
114 input [`FIRE_CSR_SRCB_BITS] csr_host_1_src_bus_id;
115
116 input csr_host_2_req;
117 input [`FIRE_CSR_ADDR_BITS] csr_host_2_addr;
118 input [`FIRE_CSR_DATA_BITS] csr_host_2_data;
119 input csr_host_2_wr;
120 input [`FIRE_CSR_SRCB_BITS] csr_host_2_src_bus_id;
121
122 input csr_host_3_req;
123 input [`FIRE_CSR_ADDR_BITS] csr_host_3_addr;
124 input [`FIRE_CSR_DATA_BITS] csr_host_3_data;
125 input csr_host_3_wr;
126 input [`FIRE_CSR_SRCB_BITS] csr_host_3_src_bus_id;
127
128 input [`FIRE_CSR_ADDR_BITS] csr_host_bit_check_mask;
129
130 input [`FIRE_CSR_TOUT_BITS] done_timeout_value;
131
132// ----------------------------------------------------------------------------
133// Variables
134// ----------------------------------------------------------------------------
135 wire csr_host_0_done;
136 wire [`FIRE_CSR_STTS_BITS] csr_host_0_done_status;
137 wire [`FIRE_CSR_DATA_BITS] csr_host_0_read_data;
138 wire csr_host_1_done;
139 wire [`FIRE_CSR_STTS_BITS] csr_host_1_done_status;
140 wire [`FIRE_CSR_DATA_BITS] csr_host_1_read_data;
141 wire csr_host_2_done;
142 wire [`FIRE_CSR_STTS_BITS] csr_host_2_done_status;
143 wire [`FIRE_CSR_DATA_BITS] csr_host_2_read_data;
144 wire csr_host_3_done;
145 wire [`FIRE_CSR_STTS_BITS] csr_host_3_done_status;
146 wire [`FIRE_CSR_DATA_BITS] csr_host_3_read_data;
147 wire [`FIRE_CSR_RING_BITS] csr_ring_out;
148 wire ccc_idle;
149
150 wire [`FIRE_CSR_SRCB_BITS] arb2cdp_sel;
151 wire arb2fsm_valid;
152
153 wire cdp2fsm_error;
154 wire [`FIRE_CSR_ADDR_BITS] cdp2pkt_addr;
155 wire [`FIRE_CSR_DATA_BITS] cdp2pkt_data;
156 wire [`FIRE_CSR_SRCB_BITS] cdp2pkt_src_bus;
157 wire cdp2pkt_wr;
158
159 wire [`FIRE_CSR_DATA_BITS] dep2cdp_data;
160 wire dep2fsm_acc_vio;
161 wire dep2fsm_done;
162 wire dep2fsm_mapped;
163 wire dep2fsm_valid;
164
165 wire fsm2arb_done;
166 wire [`FIRE_CSR_STTS_BITS] fsm2cdp_stts;
167 wire fsm2pkt_valid;
168
169// ----------------------------------------------------------------------------
170// Instantiations
171// ----------------------------------------------------------------------------
172 dmu_common_ccc_arb arb
173 (
174 .clk (clk),
175 .rst_l (rst_l),
176 .csr_host_0_req (csr_host_0_req),
177 .csr_host_1_req (csr_host_1_req),
178 .csr_host_2_req (csr_host_2_req),
179 .csr_host_3_req (csr_host_3_req),
180 .fsm2arb_done (fsm2arb_done),
181 .csr_host_0_done (csr_host_0_done),
182 .csr_host_1_done (csr_host_1_done),
183 .csr_host_2_done (csr_host_2_done),
184 .csr_host_3_done (csr_host_3_done),
185 .arb2cdp_sel (arb2cdp_sel),
186 .arb2fsm_valid (arb2fsm_valid)
187 );
188
189 dmu_common_ccc_cdp cdp
190 (
191 .clk (clk),
192 .rst_l (rst_l),
193 .csr_host_0_addr (csr_host_0_addr),
194 .csr_host_0_data (csr_host_0_data),
195 .csr_host_0_src_bus_id (csr_host_0_src_bus_id),
196 .csr_host_0_wr (csr_host_0_wr),
197 .csr_host_1_addr (csr_host_1_addr),
198 .csr_host_1_data (csr_host_1_data),
199 .csr_host_1_src_bus_id (csr_host_1_src_bus_id),
200 .csr_host_1_wr (csr_host_1_wr),
201 .csr_host_2_addr (csr_host_2_addr),
202 .csr_host_2_data (csr_host_2_data),
203 .csr_host_2_src_bus_id (csr_host_2_src_bus_id),
204 .csr_host_2_wr (csr_host_2_wr),
205 .csr_host_3_addr (csr_host_3_addr),
206 .csr_host_3_data (csr_host_3_data),
207 .csr_host_3_src_bus_id (csr_host_3_src_bus_id),
208 .csr_host_3_wr (csr_host_3_wr),
209 .csr_host_bit_check_mask (csr_host_bit_check_mask),
210 .arb2cdp_sel (arb2cdp_sel),
211 .dep2cdp_data (dep2cdp_data),
212 .fsm2cdp_stts (fsm2cdp_stts),
213 .csr_host_0_done_status (csr_host_0_done_status),
214 .csr_host_0_read_data (csr_host_0_read_data),
215 .csr_host_1_done_status (csr_host_1_done_status),
216 .csr_host_1_read_data (csr_host_1_read_data),
217 .csr_host_2_done_status (csr_host_2_done_status),
218 .csr_host_2_read_data (csr_host_2_read_data),
219 .csr_host_3_done_status (csr_host_3_done_status),
220 .csr_host_3_read_data (csr_host_3_read_data),
221 .cdp2fsm_error (cdp2fsm_error),
222 .cdp2pkt_addr (cdp2pkt_addr),
223 .cdp2pkt_data (cdp2pkt_data),
224 .cdp2pkt_src_bus (cdp2pkt_src_bus),
225 .cdp2pkt_wr (cdp2pkt_wr)
226 );
227
228 dmu_common_ccc_dep dep
229 (
230 .clk (clk),
231 .rst_l (rst_l),
232 .csr_ring_in (csr_ring_in),
233 .dep2cdp_data (dep2cdp_data),
234 .dep2fsm_acc_vio (dep2fsm_acc_vio),
235 .dep2fsm_done (dep2fsm_done),
236 .dep2fsm_mapped (dep2fsm_mapped),
237 .dep2fsm_valid (dep2fsm_valid)
238 );
239
240 dmu_common_ccc_fsm fsm
241 (
242 .clk (clk),
243 .rst_l (rst_l),
244 .done_timeout_value (done_timeout_value),
245 .arb2fsm_valid (arb2fsm_valid),
246 .cdp2fsm_error (cdp2fsm_error),
247 .dep2fsm_acc_vio (dep2fsm_acc_vio),
248 .dep2fsm_done (dep2fsm_done),
249 .dep2fsm_mapped (dep2fsm_mapped),
250 .dep2fsm_valid (dep2fsm_valid),
251 .ccc_idle (ccc_idle),
252 .fsm2arb_done (fsm2arb_done),
253 .fsm2cdp_stts (fsm2cdp_stts),
254 .fsm2pkt_valid (fsm2pkt_valid)
255 );
256
257 dmu_common_ccc_pkt pkt
258 (
259 .clk (clk),
260 .rst_l (rst_l),
261 .cdp2pkt_addr (cdp2pkt_addr),
262 .cdp2pkt_data (cdp2pkt_data),
263 .cdp2pkt_src_bus (cdp2pkt_src_bus),
264 .cdp2pkt_wr (cdp2pkt_wr),
265 .fsm2pkt_valid (fsm2pkt_valid),
266 .csr_ring_out (csr_ring_out)
267 );
268
269endmodule // dmu_common_ccc
Full OpenSPARC design & verification tarball including full HDL.