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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / design / sys / iop / pcie_common / rtl / pcie.h
CommitLineData
86530b38
AT		 1/*
2* ========== Copyright Header Begin ==========================================
3*
4* OpenSPARC T2 Processor File: pcie.h
5* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
6* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
7*
8* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
9*
10* This program is free software; you can redistribute it and/or modify
11* it under the terms of the GNU General Public License as published by
12* the Free Software Foundation; version 2 of the License.
13*
14* This program is distributed in the hope that it will be useful,
15* but WITHOUT ANY WARRANTY; without even the implied warranty of
16* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17* GNU General Public License for more details.
18*
19* You should have received a copy of the GNU General Public License
20* along with this program; if not, write to the Free Software
21* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22*
23* For the avoidance of doubt, and except that if any non-GPL license
24* choice is available it will apply instead, Sun elects to use only
25* the General Public License version 2 (GPLv2) at this time for any
26* software where a choice of GPL license versions is made
27* available with the language indicating that GPLv2 or any later version
28* may be used, or where a choice of which version of the GPL is applied is
29* otherwise unspecified.
30*
31* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
32* CA 95054 USA or visit www.sun.com if you need additional information or
33* have any questions.
34*
35*
36* ========== Copyright Header End ============================================
37*/
38`define FIRE_PA_MSB 42 // Physical address MSB
39
40`define FIRE_DEBUG_WDTH 8 // Width of the Debug Ports
41`define FIRE_DBG_DATA_BITS 7:0 // Debug data bits
42
43`define FIRE_PRF_ADDR_BITS 7:0
44`define FIRE_PRF_DATA_BITS 63:0
45
46//-----------------------------------------------------------------------------
47//******************************** CSR INTERFACE ******************************
48//-----------------------------------------------------------------------------
49
50`define FIRE_CSR_ADDR_BITS 26:0
51`define FIRE_CSR_DATA_BITS 63:0
52`define FIRE_CSR_RDMS_BITS 63:32
53`define FIRE_CSR_RDLS_BITS 31:0
54
55`define FIRE_CSR_CMND_BITS 2:0
56`define FIRE_CSR_SRCB_BITS 1:0
57`define FIRE_CSR_STTS_BITS 2:0
58`define FIRE_CSR_TOUT_BITS 7:0
59
60`define FIRE_CSR_RING_WDTH 32
61`define FIRE_CSR_RING_BITS `FIRE_CSR_RING_WDTH-1:0
62
63`define FIRE_CSR_PCKT_WDTH 96
64`define FIRE_CSR_PCKT_BITS `FIRE_CSR_PCKT_WDTH-1:0
65
66`define FIRE_CSR_CMND_IDLE 3'b000
67`define FIRE_CSR_CMND_RSET 3'b001
68`define FIRE_CSR_CMND_RREQ 3'b010
69`define FIRE_CSR_CMND_WREQ 3'b011
70`define FIRE_CSR_CMND_RRSP 3'b100
71`define FIRE_CSR_CMND_WRSP 3'b101
72`define FIRE_CSR_CMND_RERR 3'b110
73`define FIRE_CSR_CMND_WERR 3'b111
74
75`define FIRE_CSR_PCKT_CMND_BITS 95:93
76`define FIRE_CSR_PCKT_ADDR_BITS 95:64
77`define FIRE_CSR_PCKT_RDMS_BITS 63:32
78`define FIRE_CSR_PCKT_RDLS_BITS 31:0
79
80`define FIRE_CSR_RING_CMND_BITS 31:29
81`define FIRE_CSR_RING_WRIT_BITS 29
82`define FIRE_CSR_RING_SRCB_BITS 28:27
83`define FIRE_CSR_RING_ADDR_BITS `FIRE_CSR_ADDR_BITS
84
85`define FIRE_CSR_SRCB_JTAG 2'b00
86`define FIRE_CSR_SRCB_SLOW 2'b01
87`define FIRE_CSR_SRCB_MEDM 2'b10
88`define FIRE_CSR_SRCB_FAST 2'b11
89
90//#######################################################
91// FIRE Defines Used in DCM, Modules
92//#######################################################
93`define FIRE_CSR_ADDR_MAX_WIDTH 27 // Maximum width of supplied address
94`define FIRE_CSR_CHECK_ADDR_BIT_RANGE 4:0 // Bit fields of the supplied address port
95`define FIRE_CSR_CHECK_ADDR_WIDTH 5 // Width of the supplied address port
96`define FIRE_CSR_DATA_14_WIDTH 14 // Width of data in P1
97`define FIRE_CSR_DATA_50_WIDTH 50 // Width of data in P2
98`define FIRE_CSR_DATA_WIDTH 64 // Width of data in a register
99`define FIRE_CSR_HOST_DONE_STATUS_ACCESS_VIO 3'b100 // Access violation occured
100`define FIRE_CSR_HOST_DONE_STATUS_MAP_DONE_TIMEOUT 3'b101 // Timeout values exceeded
101`define FIRE_CSR_HOST_DONE_STATUS_RING_TRANS_ERROR 3'b111 // Error on CSR Ring
102`define FIRE_CSR_HOST_DONE_STATUS_SUCCESS 3'b0 // Transaction completed successfully
103`define FIRE_CSR_HOST_DONE_STATUS_WIDTH 3 // Width of Done status to Host devices
104`define FIRE_CSR_NON_MUTEABLE_BITS 31:0 // Non-muteable bits in P1
105`define FIRE_CSR_NON_MUTEABLE_WIDTH 32 // Width of non-muteable data in P1
106`define FIRE_CSR_PKT_ACC_VIO_BIT 33 // Bit position of the access violation bit
107`define FIRE_CSR_PKT_ADDR_BITS 28:0 // Bit position of the address bits in first CSR packet
108`define FIRE_CSR_PKT_ADDR_WIDTH 29 // Width of the address bits in the packet format
109`define FIRE_CSR_PKT_DATA_14_BIT 49:36 // Bit position of the 14 bits of data
110`define FIRE_CSR_PKT_DATA_50_BIT 49:0 // Bit positions of the 50 bits of data
111`define FIRE_CSR_PKT_DONE_BIT 35 // Bit position of the done bit
112`define FIRE_CSR_PKT_MAPPED_BIT 34 // Bit position of the mapped bit
113`define FIRE_CSR_PKT_RESERVED_BIT 32 // Bit position of the reserved bit
114`define FIRE_CSR_PKT_SRC_BUS_BITS 30:29 // Bit position of the source bus id bits
115`define FIRE_CSR_PKT_SRC_BUS_ID_WIDTH 2 // Width of the src bus id in packet format
116`define FIRE_CSR_PKT_VALID_BIT 50 // Bit position of the valid bit in each CSR packet
117`define FIRE_CSR_PKT_WR_BIT 31 // Bit position of the write command
118`define FIRE_CSR_RING_WIDTH 32 // Width of CSR ring
119`define FIRE_CSR_SRC_BUS_ID_WIDTH 2 // Width of the src bus id ports
120`define FIRE_CSR_TIMEOUT_WIDTH 8 // Width of timeout counter
121
122
123//#######################################################
124// EGL Defines Used in Leveraged DCC and CCC Modules
125//
126// Based on Fire version of `defines
127//#######################################################
128
129
130//`define EGL_CSR_ADDR_MAX_WIDTH `FIRE_CSR_ADDR_MAX_WIDTH
131`define EGL_CSR_CHECK_ADDR_BIT_RANGE `FIRE_CSR_CHECK_ADDR_BIT_RANGE
132`define EGL_CSR_CHECK_ADDR_WIDTH `FIRE_CSR_CHECK_ADDR_WIDTH
133`define EGL_CSR_DATA_14_WIDTH `FIRE_CSR_DATA_14_WIDTH
134`define EGL_CSR_DATA_50_WIDTH `FIRE_CSR_DATA_50_WIDTH
135`define EGL_CSR_DATA_WIDTH `FIRE_CSR_DATA_WIDTH
136`define EGL_CSR_HOST_DONE_STATUS_ACCESS_VIO `FIRE_CSR_HOST_DONE_STATUS_ACCESS_VIO
137`define EGL_CSR_HOST_DONE_STATUS_MAP_DONE_TIMEOUT `FIRE_CSR_HOST_DONE_STATUS_MAP_DONE_TIMEOUT
138`define EGL_CSR_HOST_DONE_STATUS_RING_TRANS_ERROR `FIRE_CSR_HOST_DONE_STATUS_RING_TRANS_ERROR
139`define EGL_CSR_HOST_DONE_STATUS_SUCCESS `FIRE_CSR_HOST_DONE_STATUS_SUCCESS
140`define EGL_CSR_HOST_DONE_STATUS_WIDTH `FIRE_CSR_HOST_DONE_STATUS_WIDTH
141`define EGL_CSR_NON_MUTEABLE_BITS `FIRE_CSR_NON_MUTEABLE_BITS
142`define EGL_CSR_NON_MUTEABLE_WIDTH `FIRE_CSR_NON_MUTEABLE_WIDTH
143`define EGL_CSR_PKT_ACC_VIO_BIT `FIRE_CSR_PKT_ACC_VIO_BIT
144`define EGL_CSR_PKT_ADDR_BITS `FIRE_CSR_PKT_ADDR_BITS
145`define EGL_CSR_PKT_ADDR_WIDTH `FIRE_CSR_PKT_ADDR_WIDTH
146`define EGL_CSR_PKT_DATA_14_BIT `FIRE_CSR_PKT_DATA_14_BIT
147`define EGL_CSR_PKT_DATA_50_BIT `FIRE_CSR_PKT_DATA_50_BIT
148`define EGL_CSR_PKT_DONE_BIT `FIRE_CSR_PKT_DONE_BIT
149`define EGL_CSR_PKT_MAPPED_BIT `FIRE_CSR_PKT_MAPPED_BIT
150`define EGL_CSR_PKT_RESERVED_BIT `FIRE_CSR_PKT_RESERVED_BIT
151`define EGL_CSR_PKT_SRC_BUS_BITS `FIRE_CSR_PKT_SRC_BUS_BITS
152`define EGL_CSR_PKT_SRC_BUS_ID_WIDTH `FIRE_CSR_PKT_SRC_BUS_ID_WIDTH
153`define EGL_CSR_PKT_VALID_BIT `FIRE_CSR_PKT_VALID_BIT
154`define EGL_CSR_PKT_WR_BIT `FIRE_CSR_PKT_WR_BIT
155`define EGL_CSR_RING_WIDTH `FIRE_CSR_RING_WIDTH
156`define EGL_CSR_SRC_BUS_ID_WIDTH `FIRE_CSR_SRC_BUS_ID_WIDTH
157`define EGL_CSR_TIMEOUT_WIDTH `FIRE_CSR_TIMEOUT_WIDTH
158
159//-----------------------------------------------------------------------------
160//************************ DTL-JBC INTERFACE ************************
161//-----------------------------------------------------------------------------
162`define FIRE_DTL_PDQ_WDTH 2
163`define FIRE_DTL_LPDQ_WDTH 9
164`define FIRE_DTL_OVERIDE_WDTH 7
165
166//-----------------------------------------------------------------------------
167//************************ EXT Interrupt-JBC INTERFACE ************************
168//-----------------------------------------------------------------------------
169`define FIRE_EXT_INT_WDTH 40
170
171
172//-----------------------------------------------------------------------------
173//****************************** EBUS-JBC INTERFACE ****************************
174//-----------------------------------------------------------------------------
175`define FIRE_EBUS_AD_WDTH 8
176`define FIRE_EBUS_A_WDTH 8
177
178//-----------------------------------------------------------------------------
179//****************************** GPIO-JBC INTERFACE ****************************
180//-----------------------------------------------------------------------------
181`define FIRE_GPIO_WDTH 4
182
183//-----------------------------------------------------------------------------
184//****************************** JTAG-JBC INTERFACE ****************************
185//-----------------------------------------------------------------------------
186`define FIRE_DEVID_WDTH 16
187
188//-----------------------------------------------------------------------------
189//****************************** JBC-PLLC INTERFACE ****************************
190//-----------------------------------------------------------------------------
191`define FIRE_PLL_JIT_WDTH 2
192`define FIRE_PLL_CNT_WDTH 2
193
194//-----------------------------------------------------------------------------
195//****************************** DMC-JBC INTERFACE ****************************
196//-----------------------------------------------------------------------------
197
198//#######################################################
199// DMC-to-JBC Interface (D2J)
200//#######################################################
201
202// ~~~~~~~~~~ Ingress Command Interface ~~~~~~~~~~~~~~~~~
203
204`define FIRE_D2J_CMD_WDTH 4 // d2j_cmd[3:0]
205`define FIRE_D2J_ADDR_WDTH `FIRE_PA_MSB - 5 // d2j_addr[42:6]
206`define FIRE_D2J_CTAG_WDTH 16 // d2j_ctag[15:0]
207
208// ~~~~~~~~~~ Ingress Data Interface ~~~~~~~~~~~~~~~~~~~~
209
210`define FIRE_D2J_DATA_WDTH 128 // d2j_data[127:0]
211`define FIRE_D2J_BMSK_WDTH 16 // d2j_bmsk[15:0]
212`define FIRE_D2J_DPAR_WDTH 5 // d2j_data_par[4:0]
213
214// ~~~~~~~~~~ PIO Wrack Interface ~~~~~~~~~~~~~~~~~~~~~~~
215
216`define FIRE_D2J_P_WRACK_WDTH 4 // d2j_p_wrack_tag[3:0]
217
218// ~~~~~~~~~~ MMU Interface ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
219
220`define FIRE_D2J_TSB_BASE_WDTH `FIRE_PA_MSB - 12 // d2j_tsb_base[42:13]
221`define FIRE_D2J_TSB_BASE_BITS `FIRE_PA_MSB:13
222`define FIRE_D2J_TSB_SIZE_WDTH 4 // d2j_tsb_size[3:0]
223`define FIRE_D2J_TSB_SIZE_BITS 3:0
224
225// ~~~~~~~~~~ To JBC Spares ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
226
227`define FIRE_D2J_SPARE_WDTH 5 // d2j_spare[4:0]
228
229//#######################################################
230// JBC-to-DMC Interface (J2D)
231//#######################################################
232
233// ~~~~~~~~~~ CSR Interface~~~~~~~~~~~~~~~~ ~~~~~~~~~~
234`define FIRE_J2D_INSTANCE_ID_WDTH 1 // j2d_instance_id
235`define FIRE_J2D_INSTANCE_ID_BITS 0:0
236
237// ~~~~~~~~~~ Egress DMA/INT Command Interface ~~~~~~~~~~
238
239`define FIRE_J2D_DI_CMD_WDTH 2 // j2d_di_cmd[1:0]
240`define FIRE_J2D_DI_CTAG_WDTH 16 // j2d_di_ctag[15:0]
241
242// ~~~~~~~~~~ Egress PIO Command Interface ~~~~~~~~~~~~~~
243
244`define FIRE_J2D_P_CMD_WDTH 4 // j2d_p_cmd[3:0]
245`define FIRE_J2D_P_ADDR_WDTH 36 // j2d_p_addr[35:0]
246`define FIRE_J2D_P_BMSK_WDTH 16 // j2d_p_bmsk[15:0]
247//BP n2 6-01-04 keep bits packed, even though on d2j_ctag there is a 0 inbetween fields
248`define FIRE_J2D_P_CTAG_WDTH 11 // j2d_p_ctag[10:0]
249
250// ~~~~~~~~~~ Egress DMA Data Interface ~~~~~~~~~~~~~~~~~
251
252`define FIRE_J2D_D_DATA_WDTH 128 // j2d_d_data[127:0]
253`define FIRE_J2D_D_DPAR_WDTH 4 // j2d_d_data_par[3:0]
254
255// ~~~~~~~~~~ Egress PIO Data Interface ~~~~~~~~~~~~~~~~~
256
257`define FIRE_J2D_P_DATA_WDTH 128 // j2d_p_data[127:0]
258`define FIRE_J2D_P_DPAR_WDTH 4 // j2d_p_data_par[3:0]
259
260// ~~~~~~~~~~ DMA Wrack Interface ~~~~~~~~~~~~~~~~~~~~~~~
261
262`define FIRE_J2D_D_WRACK_WDTH 4 // j2d_d_wrack_tag[3:0]
263
264// ~~~~~~~~~~ MMU Interface ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
265
266`define FIRE_J2D_MMU_ADDR_WDTH `FIRE_PA_MSB - 5 // j2d_mmu_addr[42:6]
267`define FIRE_J2D_MMU_ADDR_BITS `FIRE_PA_MSB:6
268
269// ~~~~~~~~~~ IMU Interface ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
270
271`define FIRE_J2D_EXT_INT_WDTH 20 // j2d_ext_int_l[19:0]
272`define FIRE_J2D_JID_WDTH 1 // j2d_jid
273
274// ~~~~~~~~~~ To DMC Spares ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
275
276`define FIRE_J2D_SPARE_WDTH 5 // j2d_spare[4:0]
277
278
279//-----------------------------------------------------------------------------
280//****************************** DMC-PEC INTERFACE ****************************
281//-----------------------------------------------------------------------------
282
283//#######################################################
284// Ingress Interface
285//#######################################################
286
287// ~~~~~~~~~~ Ingress IHB Interface ~~~~~~~~~~~~~~~~~
288
289`define FIRE_D2P_IHB_PTR_WDTH 7
290`define FIRE_D2P_IHB_PTR_BITS `FIRE_D2P_IHB_PTR_WDTH-1:0
291
292`define FIRE_P2D_IHB_WPTR_WDTH 7
293`define FIRE_P2D_IHB_WPTR_BITS `FIRE_P2D_IHB_WPTR_WDTH-1:0
294
295`define FIRE_D2P_IHB_ADDR_WDTH 6
296`define FIRE_D2P_IHB_ADDR_BITS `FIRE_D2P_IHB_ADDR_WDTH-1:0
297
298`define FIRE_P2D_IHB_DATA_WDTH 128
299`define FIRE_P2D_IHB_DATA_BITS `FIRE_P2D_IHB_DATA_WDTH-1:0
300
301`define FIRE_P2D_IHB_DPAR_WDTH 4
302`define FIRE_P2D_IHB_DPAR_BITS `FIRE_P2D_IHB_DPAR_WDTH-1:0
303
304// ~~~~~~~~~~ Ingress IDB Interface ~~~~~~~~~~~~~~~~~
305
306`define FIRE_D2P_IDB_ADDR_WDTH 8 // d2p_idb_addr
307`define FIRE_D2P_IDB_ADDR_BITS `FIRE_D2P_IDB_ADDR_WDTH-1:0
308
309`define FIRE_P2D_IDB_DATA_WDTH 128 // p2d_idb_data
310`define FIRE_P2D_IDB_DATA_BITS `FIRE_P2D_IDB_DATA_WDTH-1:0
311
312`define FIRE_P2D_IDB_DPAR_WDTH 4 // p2d_idb_dpar
313`define FIRE_P2D_IDB_DPAR_BITS `FIRE_P2D_IDB_DPAR_WDTH-1:0
314
315// ~~~~~~~~~~ Ingress IBC Interface ~~~~~~~~~~~~~~~~~
316
317`define FIRE_D2P_IBC_DC_WDTH 12
318`define FIRE_D2P_IBC_DC_BITS `FIRE_D2P_IBC_DC_WDTH-1:0
319
320`define FIRE_D2P_IBC_HC_WDTH 8
321`define FIRE_D2P_IBC_HC_BITS `FIRE_D2P_IBC_HC_WDTH-1:0
322
323`define FIRE_D2P_IBC_NHC_WDTH 8 // d2p_ibc_nhc
324`define FIRE_D2P_IBC_NHC_BITS `FIRE_D2P_IBC_NHC_WDTH-1:0
325
326`define FIRE_D2P_IBC_PHC_WDTH 8 // d2p_ibc_phc
327`define FIRE_D2P_IBC_PHC_BITS `FIRE_D2P_IBC_PHC_WDTH-1:0
328
329`define FIRE_D2P_IBC_PDC_WDTH 12 // d2p_ibc_pdc
330`define FIRE_D2P_IBC_PDC_BITS `FIRE_D2P_IBC_PDC_WDTH-1:0
331
332// ~~~~~~~~~~ Ingress CTO Interface ~~~~~~~~~~~~~~~~~
333
334`define FIRE_P2D_CTO_TAG_WDTH 5 // p2d_cto_tag
335`define FIRE_P2D_CTO_TAG_BITS `FIRE_P2D_CTO_TAG_WDTH-1:0
336
337//#######################################################
338// Egress Interface
339//#######################################################
340
341// ~~~~~~~~~~ Egress EHB Interface ~~~~~~~~~~~~~~~~~
342
343`define FIRE_D2P_EHB_ADDR_WDTH 6 // d2p_ehb_addr[5:0]
344`define FIRE_D2P_EHB_ADDR_BITS `FIRE_D2P_EHB_ADDR_WDTH-1:0
345
346`define FIRE_D2P_EHB_DATA_WDTH 128 // d2p_ehb_data[127:0]
347`define FIRE_D2P_EHB_DATA_BITS `FIRE_D2P_EHB_DATA_WDTH-1:0
348
349`define FIRE_D2P_EHB_DPAR_WDTH 4 // d2p_ehb_dpar[3:0]
350`define FIRE_D2P_EHB_DPAR_BITS `FIRE_D2P_EHB_DPAR_WDTH-1:0
351
352// ~~~~~~~~~~ Egress EDB Interface ~~~~~~~~~~~~~~~~~
353
354`define FIRE_D2P_EDB_ADDR_WDTH 8 // d2p_edb_addr[7:0]
355`define FIRE_D2P_EDB_ADDR_BITS `FIRE_D2P_EDB_ADDR_WDTH-1:0
356
357`define FIRE_D2P_EDB_DATA_DW4_LSB 0
358`define FIRE_D2P_EDB_DATA_DW4_WDTH 32
359`define FIRE_D2P_EDB_DATA_DW4_MSB `FIRE_D2P_EDB_DATA_DW4_LSB + `FIRE_D2P_EDB_DATA_DW4_WDTH - 1
360
361`define FIRE_D2P_EDB_DATA_DW3_LSB `FIRE_D2P_EDB_DATA_DW4_LSB + `FIRE_D2P_EDB_DATA_DW4_WDTH
362`define FIRE_D2P_EDB_DATA_DW3_WDTH 32
363`define FIRE_D2P_EDB_DATA_DW3_MSB `FIRE_D2P_EDB_DATA_DW3_LSB + `FIRE_D2P_EDB_DATA_DW3_WDTH - 1
364
365`define FIRE_D2P_EDB_DATA_DW2_LSB `FIRE_D2P_EDB_DATA_DW3_LSB + `FIRE_D2P_EDB_DATA_DW3_WDTH
366`define FIRE_D2P_EDB_DATA_DW2_WDTH 32
367`define FIRE_D2P_EDB_DATA_DW2_MSB `FIRE_D2P_EDB_DATA_DW2_LSB + `FIRE_D2P_EDB_DATA_DW2_WDTH - 1
368
369`define FIRE_D2P_EDB_DATA_DW1_LSB `FIRE_D2P_EDB_DATA_DW2_LSB + `FIRE_D2P_EDB_DATA_DW2_WDTH
370`define FIRE_D2P_EDB_DATA_DW1_WDTH 32
371`define FIRE_D2P_EDB_DATA_DW1_MSB `FIRE_D2P_EDB_DATA_DW1_LSB + `FIRE_D2P_EDB_DATA_DW1_WDTH - 1
372
373`define FIRE_D2P_EDB_DATA_WDTH `FIRE_D2P_EDB_DATA_DW1_LSB + `FIRE_D2P_EDB_DATA_DW1_WDTH
374`define FIRE_D2P_EDB_DATA_BITS `FIRE_D2P_EDB_DATA_WDTH-1:0
375 // d2p_edb_data[127:0]
376`define FIRE_D2P_EDB_DPAR_WDTH 4 // d2p_edb_dpar[3:0]
377`define FIRE_D2P_EDB_DPAR_BITS `FIRE_D2P_EDB_DPAR_WDTH-1:0
378
379// ~~~~~~~~~~ Egress CREDIT Interface ~~~~~~~~~~~~~~~~~
380
381`define FIRE_P2D_ECH_RPTR_WDTH 6 // p2d_ech_rptr[5:0]
382`define FIRE_P2D_ECH_RPTR_BITS `FIRE_P2D_ECH_RPTR_WDTH-1:0
383
384`define FIRE_P2D_ERH_RPTR_WDTH 6 // p2d_erh_rptr[5:0]
385`define FIRE_P2D_ERH_RPTR_BITS `FIRE_P2D_ERH_RPTR_WDTH-1:0
386
387`define FIRE_D2P_ECH_WPTR_WDTH 6 // d2p_ech_wptr[5:0]
388`define FIRE_D2P_ECH_WPTR_BITS `FIRE_D2P_ECH_WPTR_WDTH-1:0
389
390`define FIRE_D2P_ERH_WPTR_WDTH 6 // d2p_erh_wptr[5:0]
391`define FIRE_D2P_ERH_WPTR_BITS `FIRE_D2P_ERH_WPTR_WDTH-1:0
392
393`define FIRE_P2D_ECD_RPTR_WDTH 8 // p2d_ecd_rptr[7:0]
394`define FIRE_P2D_ECD_RPTR_BITS `FIRE_P2D_ECD_RPTR_WDTH-1:0
395
396`define FIRE_P2D_ERD_RPTR_WDTH 8 // p2d_erd_rptr[7:0]
397`define FIRE_P2D_ERD_RPTR_BITS `FIRE_P2D_ERD_RPTR_WDTH-1:0
398
399//#######################################################
400// Ingress Interface
401//#######################################################
402
403//#######################################################
404// CSR Interface
405//#######################################################
406
407`define FIRE_P2D_MPS_WDTH 3 // p2d_mps[2:0]
408`define FIRE_P2D_MPS_BITS `FIRE_P2D_MPS_WDTH-1:0
409
410`define FIRE_D2P_CSR_RING_WDTH 96 // d2p_csr_ring[99:0]
411`define FIRE_P2D_CSR_RING_WDTH 96 // p2d_csr_ring[99:0]
412
413//#######################################################
414// DMC<->PEC (ILU<->TLU) spares
415//#######################################################
416
417`define FIRE_D2P_SPARE_WDTH 5 // d2p_spare[4:0]
418`define FIRE_P2D_SPARE_WDTH 5 // p2d_spare[4:0]
419
420
421//-----------------------------------------------------------------------------
422//********************* DMC-PEC (ILU-TLU) Interface Records *******************
423//-----------------------------------------------------------------------------
424
425//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
426// NOTE: In the IHB and EHB defines,
427// *_4DWH_* represents header byte 12 - 15 in PCIE spec.
428// *_3DWH_* represents header byte 8 - 11 in PCIE spec.
429// *_2DWH_* represents header byte 4 - 7 in PCIE spec.
430// *_1DWH_* represents header byte 0 - 3 in PCIE spec.
431//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
432
433//####################################
434// Ingress Header Buffer Record (IHB)
435// From IHB to DIM
436//####################################
437
438`define FIRE_IHB_4DWH_LSB 0 // Start of Field
439`define FIRE_IHB_4DWH_WDTH 32 // Width of Field
440`define FIRE_IHB_4DWH_MSB `FIRE_IHB_4DWH_LSB + `FIRE_IHB_4DWH_WDTH -1 // MSB of Field
441
442`define FIRE_IHB_3DWH_LSB `FIRE_IHB_4DWH_LSB + `FIRE_IHB_4DWH_WDTH // Start of Field
443`define FIRE_IHB_3DWH_WDTH 32 // Width of Field
444`define FIRE_IHB_3DWH_MSB `FIRE_IHB_3DWH_LSB + `FIRE_IHB_3DWH_WDTH -1 // MSB of Field
445
446`define FIRE_IHB_2DWH_LSB `FIRE_IHB_3DWH_LSB + `FIRE_IHB_3DWH_WDTH // Start of Field
447`define FIRE_IHB_2DWH_WDTH 32 // Width of Field
448`define FIRE_IHB_2DWH_MSB `FIRE_IHB_2DWH_LSB + `FIRE_IHB_2DWH_WDTH -1 // MSB of Field
449
450`define FIRE_IHB_1DWH_LSB `FIRE_IHB_2DWH_LSB + `FIRE_IHB_2DWH_WDTH // Start of Field
451`define FIRE_IHB_1DWH_WDTH 32 // Width of Field
452`define FIRE_IHB_1DWH_MSB `FIRE_IHB_1DWH_LSB + `FIRE_IHB_1DWH_WDTH -1 // MSB of Field
453
454`define FIRE_IHB_REC_WDTH `FIRE_IHB_1DWH_LSB + `FIRE_IHB_1DWH_WDTH // Complete Record Width
455
456
457//####################################
458// Egress Header Buffer Record (EHB)
459// From DEM to EHB
460//####################################
461
462`define FIRE_EHB_4DWH_LSB 0 // Start of Field
463`define FIRE_EHB_4DWH_WDTH 32 // Width of Field
464`define FIRE_EHB_4DWH_MSB `FIRE_EHB_4DWH_LSB + `FIRE_EHB_4DWH_WDTH -1 // MSB of Field
465
466`define FIRE_EHB_3DWH_LSB `FIRE_EHB_4DWH_LSB + `FIRE_EHB_4DWH_WDTH // Start of Field
467`define FIRE_EHB_3DWH_WDTH 32 // Width of Field
468`define FIRE_EHB_3DWH_MSB `FIRE_EHB_3DWH_LSB + `FIRE_EHB_3DWH_WDTH -1 // MSB of Field
469
470`define FIRE_EHB_2DWH_LSB `FIRE_EHB_3DWH_LSB + `FIRE_EHB_3DWH_WDTH // Start of Field
471`define FIRE_EHB_2DWH_WDTH 32 // Width of Field
472`define FIRE_EHB_2DWH_MSB `FIRE_EHB_2DWH_LSB + `FIRE_EHB_2DWH_WDTH -1 // MSB of Field
473
474`define FIRE_EHB_1DWH_LSB `FIRE_EHB_2DWH_LSB + `FIRE_EHB_2DWH_WDTH // Start of Field
475`define FIRE_EHB_1DWH_WDTH 32 // Width of Field
476`define FIRE_EHB_1DWH_MSB `FIRE_EHB_1DWH_LSB + `FIRE_EHB_1DWH_WDTH -1 // MSB of Field
477
478`define FIRE_EHB_REC_WDTH `FIRE_EHB_1DWH_LSB + `FIRE_EHB_1DWH_WDTH // Complete Record Width
479
480//#######################################################
481// PCI Express
482//#######################################################
483
484`define FIRE_PCIE_HDR_FMT_BITS 126:125
485`define FIRE_PCIE_HDR_TYPE_BITS 124:120
486`define FIRE_PCIE_HDR_TC_BITS 118:116
487`define FIRE_PCIE_HDR_TD_BITS 111
488`define FIRE_PCIE_HDR_EP_BITS 110
489`define FIRE_PCIE_HDR_LEN_BITS 105:96
490`define FIRE_PCIE_HDR_MSG_BITS 71:64
491
492`define FIRE_PCIE_FMT_WDTH 2
493`define FIRE_PCIE_FMT_BITS `FIRE_PCIE_FMT_WDTH-1:0
494
495`define FIRE_PCIE_TYPE_WDTH 5
496`define FIRE_PCIE_TYPE_BITS `FIRE_PCIE_TYPE_WDTH-1:0
497
498`define FIRE_PCIE_TC_WDTH 3
499`define FIRE_PCIE_TC_BITS `FIRE_PCIE_TC_WDTH-1:0
500
501`define FIRE_PCIE_LEN_WDTH 10
502`define FIRE_PCIE_LEN_BITS `FIRE_PCIE_LEN_WDTH-1:0
503
504`define FIRE_PCIE_MSG_WDTH 8
505`define FIRE_PCIE_MSG_BITS `FIRE_PCIE_MSG_WDTH-1:0
506
507`define FIRE_PCIE_BUS_NUM_WDTH 8
508`define FIRE_PCIE_BUS_NUM_BITS `FIRE_PCIE_BUS_NUM_WDTH-1:0
509
510`define FIRE_PCIE_REQ_ID_WDTH 16
511`define FIRE_PCIE_REQ_ID_BITS `FIRE_PCIE_REQ_ID_WDTH-1:0
Full OpenSPARC design & verification tarball including full HDL.