projects / OpenSPARC-T2-DV / blame
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1 | // ========== Copyright Header Begin ========================================== |
| 2 | // | |
| 3 | // OpenSPARC T2 Processor File: pcie_common_dcs.v | |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
| 6 | // | |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
| 8 | // | |
| 9 | // This program is free software; you can redistribute it and/or modify | |
| 10 | // it under the terms of the GNU General Public License as published by | |
| 11 | // the Free Software Foundation; version 2 of the License. | |
| 12 | // | |
| 13 | // This program is distributed in the hope that it will be useful, | |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 16 | // GNU General Public License for more details. | |
| 17 | // | |
| 18 | // You should have received a copy of the GNU General Public License | |
| 19 | // along with this program; if not, write to the Free Software | |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
| 21 | // | |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license | |
| 23 | // choice is available it will apply instead, Sun elects to use only | |
| 24 | // the General Public License version 2 (GPLv2) at this time for any | |
| 25 | // software where a choice of GPL license versions is made | |
| 26 | // available with the language indicating that GPLv2 or any later version | |
| 27 | // may be used, or where a choice of which version of the GPL is applied is | |
| 28 | // otherwise unspecified. | |
| 29 | // | |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
| 32 | // have any questions. | |
| 33 | // | |
| 34 | // ========== Copyright Header End ============================================ | |
| 35 | module pcie_common_dcs | |
| 36 | ( | |
| 37 | clk, // source clock | |
| 38 | rst_l, // reset | |
| 39 | csr_rng_data, // ring data | |
| 40 | csr_pkt_ack, // packet acknowledge | |
| 41 | csr_pkt_data, // packet data | |
| 42 | csr_pkt_req // packet request | |
| 43 | ); | |
| 44 | ||
| 45 | // ---------------------------------------------------------------------------- | |
| 46 | // Parameters | |
| 47 | // ---------------------------------------------------------------------------- | |
| 48 | parameter QD = 3, // queue depth | |
| 49 | QW = `FIRE_CSR_RING_WDTH; // queue width | |
| 50 | ||
| 51 | // ---------------------------------------------------------------------------- | |
| 52 | // Ports | |
| 53 | // ---------------------------------------------------------------------------- | |
| 54 | input clk; | |
| 55 | input rst_l; | |
| 56 | input [`FIRE_CSR_RING_BITS] csr_rng_data; | |
| 57 | input csr_pkt_ack; | |
| 58 | ||
| 59 | output [`FIRE_CSR_PCKT_BITS] csr_pkt_data; | |
| 60 | output csr_pkt_req; | |
| 61 | ||
| 62 | // ---------------------------------------------------------------------------- | |
| 63 | // Variables | |
| 64 | // ---------------------------------------------------------------------------- | |
| 65 | wire [`FIRE_CSR_PCKT_BITS] csr_pkt_data; | |
| 66 | wire csr_pkt_req; | |
| 67 | wire ism2osm_vld; | |
| 68 | wire [QD-2:0] ism2sdp_ds; | |
| 69 | wire [QD-1:0] ism2sdp_ld; | |
| 70 | wire osm2ism_deq; | |
| 71 | wire [2:0] osm2sdp_ld; | |
| 72 | ||
| 73 | // ---------------------------------------------------------------------------- | |
| 74 | // Zero In Checkers | |
| 75 | // ---------------------------------------------------------------------------- | |
| 76 | ||
| 77 | // ---------------------------------------------------------------------------- | |
| 78 | // Instantiations | |
| 79 | // ---------------------------------------------------------------------------- | |
| 80 | pcie_common_dcs_ism #(QD) ism | |
| 81 | ( | |
| 82 | .clk (clk), | |
| 83 | .rst_l (rst_l), | |
| 84 | .csr_rng_cmd (csr_rng_data[`FIRE_CSR_RING_CMND_BITS]), | |
| 85 | .osm2ism_deq (osm2ism_deq), | |
| 86 | .ism2osm_vld (ism2osm_vld), | |
| 87 | .ism2sdp_ds (ism2sdp_ds), | |
| 88 | .ism2sdp_ld (ism2sdp_ld) | |
| 89 | ); | |
| 90 | ||
| 91 | pcie_common_dcs_osm osm | |
| 92 | ( | |
| 93 | .clk (clk), | |
| 94 | .rst_l (rst_l), | |
| 95 | .csr_pkt_ack (csr_pkt_ack), | |
| 96 | .ism2osm_vld (ism2osm_vld), | |
| 97 | .csr_pkt_req (csr_pkt_req), | |
| 98 | .osm2ism_deq (osm2ism_deq), | |
| 99 | .osm2sdp_ld (osm2sdp_ld) | |
| 100 | ); | |
| 101 | ||
| 102 | pcie_common_dcs_sdp #(QD, QW) sdp | |
| 103 | ( | |
| 104 | .clk (clk), | |
| 105 | .rst_l (rst_l), | |
| 106 | .csr_rng_data (csr_rng_data), | |
| 107 | .ism2sdp_ld (ism2sdp_ld), | |
| 108 | .ism2sdp_ds (ism2sdp_ds), | |
| 109 | .osm2sdp_ld (osm2sdp_ld), | |
| 110 | .csr_pkt_data (csr_pkt_data) | |
| 111 | ); | |
| 112 | ||
| 113 | endmodule // pcie_common_dcs |