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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: rdp_clkgen_rdp_io.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | /////////////////////////// | |
36 | // This file is a wrapper instantiating the cluster | |
37 | // headers and 1 l1clk header | |
38 | //////////////////////////////// | |
39 | module rdp_clkgen_rdp_io ( | |
40 | array_wr_inhibit, | |
41 | tcu_atpg_mode, | |
42 | tcu_wr_inhibit, | |
43 | l1clk, | |
44 | iol2clk, | |
45 | aclk, | |
46 | bclk, | |
47 | scan_out, | |
48 | pce_ov, | |
49 | wmr_protect, | |
50 | wmr_, | |
51 | por_, | |
52 | cmp_slow_sync_en, | |
53 | slow_cmp_sync_en, | |
54 | aclk_wmr, | |
55 | tcu_clk_stop, | |
56 | tcu_pce_ov, | |
57 | rst_wmr_protect, | |
58 | rst_wmr_, | |
59 | rst_por_, | |
60 | cluster_arst_l, | |
61 | ccu_cmp_slow_sync_en, | |
62 | ccu_slow_cmp_sync_en, | |
63 | //removed ccu_serdes_dtm, | |
64 | tcu_div_bypass, | |
65 | ccu_div_ph, | |
66 | cluster_div_en, | |
67 | gclk, | |
68 | // removed clk_ext, | |
69 | tcu_aclk, | |
70 | tcu_bclk, | |
71 | tcu_scan_en, | |
72 | scan_in | |
73 | ); | |
74 | ||
75 | // ************************** | |
76 | // port declaration | |
77 | // ************************** | |
78 | ||
79 | // New ports 8/05 due to new clstr_hdr | |
80 | output array_wr_inhibit; | |
81 | input tcu_atpg_mode; | |
82 | input tcu_wr_inhibit; | |
83 | ||
84 | // clock & test out | |
85 | output l1clk; // assume we do not need aclk, bclk outputs | |
86 | output iol2clk; | |
87 | output aclk; // buffered version of aclk | |
88 | output bclk; // buffered version of bclk | |
89 | output scan_out; // unused as of today - feb 10, 05 | |
90 | ||
91 | // pipelined out | |
92 | output pce_ov; // pce override to l1 header | |
93 | output wmr_protect; // warm reset protect | |
94 | output wmr_; // warm reset (active low) | |
95 | output por_; // power-on-reset | |
96 | output cmp_slow_sync_en; // cmp->slow clk sync pulse | |
97 | output slow_cmp_sync_en; // slow->cmp clk sync pulse | |
98 | output aclk_wmr; // New output for cluster header | |
99 | ||
100 | // ctrl in (for pipelining) | |
101 | input tcu_clk_stop; | |
102 | input tcu_pce_ov; | |
103 | input rst_wmr_protect; | |
104 | input rst_wmr_; | |
105 | input rst_por_; | |
106 | input cluster_arst_l; | |
107 | input ccu_cmp_slow_sync_en; | |
108 | input ccu_slow_cmp_sync_en; | |
109 | // input ccu_serdes_dtm; // New input for cluster header | |
110 | ||
111 | // ctrl in (for clock gen) | |
112 | input tcu_div_bypass; // bypasses clk divider to mux in ext clk | |
113 | input ccu_div_ph; // phase signal from ccu (div/4 or div/2) | |
114 | input cluster_div_en; // if enabled, l2clk is divided down | |
115 | ||
116 | // clock & test in | |
117 | input gclk; // global clk - this is either cmp or dr | |
118 | // input clk_ext; // external clk muxed in for ioclk bypass | |
119 | input tcu_scan_en; // unused as of today - feb 10, 05 | |
120 | input scan_in; // unused as of today - feb 10, 05 | |
121 | input tcu_aclk; | |
122 | input tcu_bclk; | |
123 | ||
124 | // ************************** | |
125 | // wire declaration | |
126 | // ************************** | |
127 | //wire l2clk; | |
128 | wire aclk; | |
129 | wire bclk; | |
130 | wire scan_out; | |
131 | wire pce_ov; | |
132 | wire wmr_protect; | |
133 | wire wmr_; | |
134 | wire por_; | |
135 | wire cmp_slow_sync_en; | |
136 | wire slow_cmp_sync_en; | |
137 | wire tcu_clk_stop; | |
138 | wire tcu_pce_ov; | |
139 | wire rst_wmr_protect; | |
140 | wire rst_wmr_; | |
141 | wire rst_por_; | |
142 | wire cluster_arst_l; | |
143 | wire ccu_cmp_slow_sync_en; | |
144 | wire ccu_slow_cmp_sync_en; | |
145 | // wire ccu_serdes_dtm; | |
146 | wire tcu_div_bypass; | |
147 | wire ccu_div_ph; | |
148 | wire cluster_div_en; | |
149 | wire gclk; | |
150 | // wire clk_ext; | |
151 | wire tcu_scan_en; // tie-low, unused as of today - feb 10, 05 | |
152 | wire scan_in; // tie-low, unused as of today - feb 10, 05 | |
153 | wire tcu_aclk; | |
154 | wire tcu_bclk; | |
155 | wire iol2clk; | |
156 | ||
157 | //////////////////////////////////// | |
158 | // cluster Header | |
159 | //////////////////////////////////// | |
160 | ||
161 | clkgen_rdp_io clkgen_rdp_io ( | |
162 | .array_wr_inhibit (array_wr_inhibit), // New for I6.1 | |
163 | .tcu_atpg_mode (tcu_atpg_mode), // New for I6.1 | |
164 | .tcu_wr_inhibit (tcu_wr_inhibit), // New for I6.1 | |
165 | .l2clk (iol2clk), | |
166 | .aclk (aclk), | |
167 | .bclk (bclk), | |
168 | ||
169 | .scan_out (scan_out), | |
170 | .pce_ov (pce_ov), | |
171 | .aclk_wmr (aclk_wmr), | |
172 | .wmr_protect (wmr_protect), | |
173 | .wmr_ (wmr_), | |
174 | .por_ (por_), | |
175 | .cmp_slow_sync_en (cmp_slow_sync_en), | |
176 | .slow_cmp_sync_en (slow_cmp_sync_en), | |
177 | .tcu_clk_stop (tcu_clk_stop), | |
178 | .tcu_pce_ov (tcu_pce_ov), | |
179 | .rst_wmr_protect (rst_wmr_protect), | |
180 | .rst_wmr_ (rst_wmr_), | |
181 | .rst_por_ (rst_por_), | |
182 | .ccu_cmp_slow_sync_en (ccu_cmp_slow_sync_en), | |
183 | .ccu_slow_cmp_sync_en (ccu_slow_cmp_sync_en), | |
184 | .tcu_div_bypass (tcu_div_bypass), | |
185 | .ccu_div_ph (ccu_div_ph), | |
186 | .cluster_div_en (cluster_div_en), | |
187 | .gclk (gclk), | |
188 | .cluster_arst_l (cluster_arst_l), | |
189 | .clk_ext (1'b0), // port left doesn't do anything | |
190 | .ccu_serdes_dtm (1'b0), | |
191 | .tcu_aclk (tcu_aclk), | |
192 | .tcu_bclk (tcu_bclk), | |
193 | .scan_en (tcu_scan_en), | |
194 | .scan_in (scan_in) | |
195 | ); | |
196 | ||
197 | //////////////////////////////////// | |
198 | // l1clk Header | |
199 | ///////////////////////////////////// | |
200 | cl_a1_l1hdr_12x iol2clk_cl_a1_l1hdr_12x ( | |
201 | .l2clk (iol2clk), // This is the input | |
202 | .se (tcu_scan_en), | |
203 | .pce (1'b1), | |
204 | .pce_ov (pce_ov), | |
205 | .stop (1'b0), | |
206 | .l1clk (l1clk) // This is output | |
207 | ); | |
208 | ||
209 | endmodule |