Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / design / sys / iop / rst / rst_rtl.flist
CommitLineData
86530b38
AT
1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: rst_rtl.flist
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
19// along with this program; if not, write to the Free Software
20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
23// choice is available it will apply instead, Sun elects to use only
24// the General Public License version 2 (GPLv2) at this time for any
25// software where a choice of GPL license versions is made
26// available with the language indicating that GPLv2 or any later version
27// may be used, or where a choice of which version of the GPL is applied is
28// otherwise unspecified.
29//
30// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
31// CA 95054 USA or visit www.sun.com if you need additional information or
32// have any questions.
33//
34// ========== Copyright Header End ============================================
35$DV_ROOT/design/sys/iop/rst/rtl/rst.v
36-v $DV_ROOT/design/sys/iop/rst/rtl/rst_cmp_ctl.v
37-v $DV_ROOT/design/sys/iop/rst/rtl/rst_fsm_ctl.v
38-v $DV_ROOT/design/sys/iop/rst/rtl/rst_io_ctl.v
39-v $DV_ROOT/design/sys/iop/rst/rtl/rst_l1clkhdr_ctl_macro.v
40-v $DV_ROOT/design/sys/iop/rst/rtl/rst_spare_ctl_macro__num_1.v
41-v $DV_ROOT/design/sys/iop/rst/rtl/rst_spare_ctl_macro__num_4.v
42-v $DV_ROOT/design/sys/iop/rst/rtl/rst_spare_ctl_macro__num_6.v
43-v $DV_ROOT/design/sys/iop/rst/rtl/rst_ucbbusin4_ctl.v
44-v $DV_ROOT/design/sys/iop/rst/rtl/rst_ucbbusout4_ctl.v
45-v $DV_ROOT/design/sys/iop/rst/rtl/rst_ucbflow_ctl.v