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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: rst.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module rst ( | |
36 | ccu_rst_sys_clk, | |
37 | gclk, | |
38 | ccu_io_out, | |
39 | scan_in, | |
40 | scan_out, | |
41 | tcu_div_bypass, | |
42 | tcu_atpg_mode, | |
43 | tcu_rst_clk_stop, | |
44 | tcu_rst_io_clk_stop, | |
45 | tcu_pce_ov, | |
46 | tcu_aclk, | |
47 | tcu_bclk, | |
48 | tcu_scan_en, | |
49 | ccu_cmp_sys_sync_en, | |
50 | ccu_sys_cmp_sync_en, | |
51 | ccu_cmp_io_sync_en, | |
52 | ccu_io_cmp_sync_en, | |
53 | ncu_rst_vld, | |
54 | ncu_rst_data, | |
55 | rst_ncu_stall, | |
56 | rst_ncu_vld, | |
57 | rst_ncu_data, | |
58 | ncu_rst_stall, | |
59 | mio_rst_pwron_rst_l, | |
60 | mio_rst_button_xir_l, | |
61 | ncu_rst_xir_done, | |
62 | tcu_rst_flush_init_ack, | |
63 | tcu_rst_flush_stop_ack, | |
64 | tcu_rst_asicflush_stop_ack, | |
65 | mio_rst_pb_rst_l, | |
66 | ccu_rst_change, | |
67 | tcu_bisx_done, | |
68 | tcu_rst_efu_done, | |
69 | l2t0_rst_fatal_error, | |
70 | l2t1_rst_fatal_error, | |
71 | l2t2_rst_fatal_error, | |
72 | l2t3_rst_fatal_error, | |
73 | l2t4_rst_fatal_error, | |
74 | l2t5_rst_fatal_error, | |
75 | l2t6_rst_fatal_error, | |
76 | l2t7_rst_fatal_error, | |
77 | ncu_rst_fatal_error, | |
78 | tcu_rst_scan_mode, | |
79 | ccu_rst_sync_stable, | |
80 | tcu_test_protect, | |
81 | rst_l2_por_, | |
82 | rst_l2_wmr_, | |
83 | rst_ccu_pll_, | |
84 | rst_ccu_, | |
85 | rst_wmr_protect, | |
86 | rst_tcu_clk_stop, | |
87 | rst_mcu_selfrsh, | |
88 | rst_tcu_flush_init_req, | |
89 | rst_tcu_flush_stop_req, | |
90 | rst_tcu_asicflush_stop_req, | |
91 | rst_niu_mac_, | |
92 | rst_niu_wmr_, | |
93 | rst_dmu_peu_por_, | |
94 | rst_dmu_peu_wmr_, | |
95 | rst_ncu_unpark_thread, | |
96 | rst_ncu_xir_, | |
97 | rst_mio_pex_reset_l, | |
98 | rst_mio_ssi_sync_l, | |
99 | rst_mio_rst_state, | |
100 | cluster_arst_l, | |
101 | rst_tcu_dbr_gen, | |
102 | rst_dmu_async_por_, | |
103 | rst_tcu_pwron_rst_l); | |
104 | wire clkgen_rst_cmp_scanin; | |
105 | wire clkgen_rst_cmp_scanout; | |
106 | wire l2clk; | |
107 | wire clkgen_rst_cmp_aclk_wmr_unused; | |
108 | wire clkgen_rst_cmp_wmr_protect_unused; | |
109 | wire clkgen_rst_cmp_wmr_unused; | |
110 | wire clkgen_rst_cmp_por_unused; | |
111 | wire cmp_io_sync_en; | |
112 | wire io_cmp_sync_en; | |
113 | wire clkgen_rst_cmp_array_wr_inhibit_unused; | |
114 | wire pwron_rst_h_scan_mode_en; | |
115 | wire clkgen_rst_io_scanin; | |
116 | wire clkgen_rst_io_scanout; | |
117 | wire iol2clk; | |
118 | wire tcu_aclk_gen; | |
119 | wire clkgen_rst_io_aclk_wmr_unused; | |
120 | wire tcu_bclk_gen; | |
121 | wire tcu_pce_ov_gen; | |
122 | wire clkgen_rst_io_wmr_protect_unused; | |
123 | wire clkgen_rst_io_wmr_unused; | |
124 | wire clkgen_rst_io_por_unused; | |
125 | wire clkgen_rst_io_cmp_slow_sync_en_unused; | |
126 | wire clkgen_rst_io_slow_cmp_sync_en_unused; | |
127 | wire clkgen_rst_io_array_wr_inhibit_unused; | |
128 | wire rst_tcu_clk_stop_io; | |
129 | wire rst_fsm_ctl_scanout; | |
130 | wire rst_fsm_ctl_scanin; | |
131 | wire rst_ucbflow_ctl_scanin; | |
132 | wire rst_ucbflow_ctl_scanout; | |
133 | wire rst_rst_wmr_io_; | |
134 | wire rd_req_vld; | |
135 | wire wr_req_vld; | |
136 | wire [5:0] thr_id_in; | |
137 | wire [1:0] buf_id_in; | |
138 | wire [39:0] addr_in; | |
139 | wire [63:0] data_in; | |
140 | wire req_acpted; | |
141 | wire rd_ack_vld; | |
142 | wire rd_nack_vld; | |
143 | wire [5:0] thr_id_out; | |
144 | wire [1:0] buf_id_out; | |
145 | wire [63:0] data_out; | |
146 | wire ack_busy; | |
147 | wire rst_cmp_ctl_scanin; | |
148 | wire rst_cmp_ctl_scanout; | |
149 | wire rst_io_ctl_scanin; | |
150 | wire rst_io_ctl_scanout; | |
151 | wire aclk; | |
152 | wire bclk; | |
153 | wire pce_ov; | |
154 | wire req_acpted_sys; | |
155 | wire rd_req_vld_sys; | |
156 | wire wr_req_vld_sys; | |
157 | wire [39:0] addr_in_sys; | |
158 | wire [15:0] data_in_sys; | |
159 | wire [5:0] thr_id_in_sys; | |
160 | wire [1:0] buf_id_in_sys; | |
161 | wire ack_busy_sys; | |
162 | wire rd_ack_vld_sys; | |
163 | wire rd_nack_vld_sys; | |
164 | wire [15:0] data_out_sys2; | |
165 | wire [5:0] thr_id_out_sys; | |
166 | wire [1:0] buf_id_out_sys; | |
167 | wire ncu_rst_xir_done_sys; | |
168 | wire ccu_rst_change_cmp; | |
169 | wire tcu_bisx_done_cmp; | |
170 | wire tcu_rst_efu_done_cmp; | |
171 | wire tr_flush_init_ack_cmp; | |
172 | wire tr_flush_stop_ack_cmp; | |
173 | wire tr_asicflush_stop_ack_cmp; | |
174 | wire ncu_rst_fatal_error_cmp; | |
175 | wire l2t0_rst_fatal_error_cmp; | |
176 | wire l2t1_rst_fatal_error_cmp; | |
177 | wire l2t2_rst_fatal_error_cmp; | |
178 | wire l2t3_rst_fatal_error_cmp; | |
179 | wire l2t4_rst_fatal_error_cmp; | |
180 | wire l2t5_rst_fatal_error_cmp; | |
181 | wire l2t6_rst_fatal_error_cmp; | |
182 | wire l2t7_rst_fatal_error_cmp; | |
183 | wire mio_rst_pb_rst_sys2_; | |
184 | wire tcu_test_protect_cmp; | |
185 | wire rst_l2_por_sys2_; | |
186 | wire rst_l2_wmr_sys2_; | |
187 | wire rst_cmp_ctl_wmr_sys2_; | |
188 | wire rst_tcu_clk_stop_sys2; | |
189 | wire rst_mcu_selfrsh_sys2; | |
190 | wire rst_dmu_peu_por_sys2_; | |
191 | wire rst_dmu_peu_wmr_sys2_; | |
192 | wire rt_flush_init_req_sys2; | |
193 | wire rt_flush_stop_req_sys2; | |
194 | wire rt_asicflush_stop_req_sys2; | |
195 | wire rst_niu_mac_sys2_; | |
196 | wire rst_niu_wmr_sys2_; | |
197 | wire rst_ncu_unpark_thread_sys2; | |
198 | wire rst_ncu_xir_sys2_; | |
199 | wire rst_rst_pwron_rst_l_sys2_; | |
200 | wire reset_gen_dbr_gen_q; | |
201 | wire rst_rst_por_sys2_; | |
202 | wire rst_rst_wmr_sys2_; | |
203 | wire mio_rst_pb_rst_sys_; | |
204 | wire ncu_rst_xir_done_io; | |
205 | wire tcu_test_protect_io; | |
206 | wire ccu_rst_change_io; | |
207 | wire [7:0] l2ta_rst_fatal_error_io; | |
208 | wire ncu_rst_fatal_error_io; | |
209 | wire rd_req_vld_io; | |
210 | wire wr_req_vld_io; | |
211 | wire [39:0] addr_in_io; | |
212 | wire [15:0] data_in_io; | |
213 | wire [5:0] thr_id_in_io; | |
214 | wire [1:0] buf_id_in_io; | |
215 | wire ack_busy_io; | |
216 | wire req_acpted_cmp2; | |
217 | wire rd_ack_vld_cmp2; | |
218 | wire rd_nack_vld_cmp2; | |
219 | wire [15:0] data_out_cmp2; | |
220 | wire [5:0] thr_id_out_cmp2; | |
221 | wire [1:0] buf_id_out_cmp2; | |
222 | wire rst_mcu_selfrsh_cmp2; | |
223 | wire rst_ncu_unpark_thread_cmp2; | |
224 | wire rst_ncu_xir_cmp2_; | |
225 | wire rst_rst_pwron_rst_l_io0_; | |
226 | wire rst_rst_por_io0_; | |
227 | wire rst_rst_wmr_io0_; | |
228 | ||
229 | //________________________________________________________________ | |
230 | ||
231 | // Globals | |
232 | input ccu_rst_sys_clk ;// Was io_ref_clk. | |
233 | // | |
234 | // ut iol2clk ;// Now driven by clkgen_rst_io. | |
235 | // This is now the input to clkgen_rst_io, which drives io_ref_clk. | |
236 | input gclk ; | |
237 | input ccu_io_out ; | |
238 | input scan_in ; | |
239 | output scan_out ; | |
240 | input tcu_div_bypass ; | |
241 | ||
242 | input tcu_atpg_mode ; | |
243 | input tcu_rst_clk_stop ;// Was tcu_soc4cmp_clk_stop. | |
244 | input tcu_rst_io_clk_stop ;// Was tcu_clk_stop. | |
245 | // Unused as of Nov 19 '05. | |
246 | input tcu_pce_ov ; | |
247 | input tcu_aclk ; | |
248 | input tcu_bclk ; | |
249 | input tcu_scan_en ; | |
250 | input ccu_cmp_sys_sync_en ;// rst_cmp_ctl cross from cmp to sys. | |
251 | input ccu_sys_cmp_sync_en ;// rst_cmp_ctl cross from sys to cmp. | |
252 | input ccu_cmp_io_sync_en ;// rst_cmp_ctl cross from cmp to io. | |
253 | input ccu_io_cmp_sync_en ;// rst_cmp_ctl cross from io to cmp. | |
254 | // RST: UCB downstream from NCU | |
255 | input ncu_rst_vld ; | |
256 | input [ 3:0] ncu_rst_data ; | |
257 | output rst_ncu_stall ; | |
258 | ||
259 | // RST: UCB upstream to NCU | |
260 | output rst_ncu_vld ; | |
261 | output [ 3:0] rst_ncu_data ; | |
262 | input ncu_rst_stall ; | |
263 | ||
264 | input mio_rst_pwron_rst_l ;// PWRON_RST_L | |
265 | input mio_rst_button_xir_l ;// BUTTON_XIR_L | |
266 | input ncu_rst_xir_done ;// Active for one clock. | |
267 | input tcu_rst_flush_init_ack ;// Request TCU to assert se. | |
268 | input tcu_rst_flush_stop_ack ;// Request TCU to deassert se. | |
269 | input tcu_rst_asicflush_stop_ack;// Request TCU to deassert se. | |
270 | input mio_rst_pb_rst_l ;// PB_RST_L | |
271 | input ccu_rst_change ;// | |
272 | input tcu_bisx_done ;// Active for one clock. | |
273 | input tcu_rst_efu_done ;// | |
274 | input l2t0_rst_fatal_error ;// | |
275 | input l2t1_rst_fatal_error ;// | |
276 | input l2t2_rst_fatal_error ;// | |
277 | input l2t3_rst_fatal_error ;// | |
278 | input l2t4_rst_fatal_error ;// | |
279 | input l2t5_rst_fatal_error ;// | |
280 | input l2t6_rst_fatal_error ;// | |
281 | input l2t7_rst_fatal_error ;// | |
282 | input ncu_rst_fatal_error ;// | |
283 | input tcu_rst_scan_mode ;// Indicates scan is active. | |
284 | input ccu_rst_sync_stable ; | |
285 | input tcu_test_protect ; | |
286 | // During mbist, lbist, jtag scan, trans test may want | |
287 | // to block tcu, rst and ccu from seeing random activity | |
288 | // from ucb (NCU), SPC's, etc. | |
289 | // This signal synch'd to ioclk & set via jtag id for blocking | |
290 | ||
291 | output rst_l2_por_ ;// Data Path Reset. | |
292 | output rst_l2_wmr_ ;// State Machine Reset. | |
293 | output rst_ccu_pll_ ;// Reset PLL in Clock Control Unit. | |
294 | output rst_ccu_ ;// Reset logic in Clock Control Unit. | |
295 | output rst_wmr_protect ;// | |
296 | output rst_tcu_clk_stop ;// Protect tcu from clk while PLL resets. | |
297 | output rst_mcu_selfrsh ;// Self-refresh bit of RESET_SSYS reg. | |
298 | output rst_tcu_flush_init_req ;// Request TCU to assert se. | |
299 | output rst_tcu_flush_stop_req ;// Request TCU to deassert se. | |
300 | output rst_tcu_asicflush_stop_req;// Request TCU to deassert se. | |
301 | output rst_niu_mac_ ;// Formerly rst_niu_. | |
302 | output rst_niu_wmr_ ;// Formerly rst_niu_. | |
303 | output rst_dmu_peu_por_ ;// | |
304 | output rst_dmu_peu_wmr_ ;// | |
305 | output rst_ncu_unpark_thread;// | |
306 | output rst_ncu_xir_ ;// | |
307 | output rst_mio_pex_reset_l ;// Added Nov 11 '04. | |
308 | output rst_mio_ssi_sync_l ;// Takes the place of rst_mio_fatal_error. | |
309 | output [ 5:0] rst_mio_rst_state ;// Added Apr 26 '05. | |
310 | output cluster_arst_l ;// Added May 02 '05. | |
311 | output rst_tcu_dbr_gen ;// Added Aug 04 '05. | |
312 | output rst_dmu_async_por_ ;// BP Aug 05 '05. | |
313 | output rst_tcu_pwron_rst_l ;// = rst_tcu_pwron_rst_l_cmp_ & | |
314 | // rst_rst_pwron_rst_l_sys2_; | |
315 | // Async assert, cmp-sync deassert. | |
316 | //________________________________________________________________ | |
317 | // | |
318 | // Last Action Date: 12/13/2005 03:12:23 PM | |
319 | // Model Name: @fc_scan_latest | |
320 | // Rev Open: 1.515 | |
321 | // FoundByTool: VCS | |
322 | // Short Description: clock stop goes directly to flop header in rst_fsm_ctl | |
323 | // Command Line: sims -sys=fc_mfg_scan -sunv_run -vcs_build | |
324 | // -novera_build -vcs_run -config_cpp_args=-DCORES1 | |
325 | // -vcs_run_args=+scanCapture | |
326 | // -vcs_run_args=+chainsel=00000001 | |
327 | // ====================================================================== | |
328 | // Inside the rst unit, the tcu_rst_clk_stop goes to the following mux | |
329 | // inside rst_fsm_ctl: | |
330 | // | |
331 | // assign tcu_clk_stop = tcu_rst_scan_mode ? rst_clk_stop : 1'b0; | |
332 | // | |
333 | // Because tcu_rst_clk_stop is pipelined with non-scannable flops, it will | |
334 | // be 'x' during atpg scan capture. It goes directly to the flop header | |
335 | // inside rst_fsm_ctl, which breaks scan capture for all of the flops | |
336 | // inside that macro. | |
337 | // | |
338 | // I talked to Tom Z., and according to him the tcu_rst_clk_stop comes from | |
339 | // a scannable flop in the tcu and was only put in there as a "may be nice | |
340 | // to have." | |
341 | // Since the clocks to the rst unit are never stopped during functional | |
342 | // mode, and since we don't need to stop the clock during atpg mode, the | |
343 | // equation above can be changed to: | |
344 | // | |
345 | // assign tcu_clk_stop = tcu_rst_scan_mode ? 1'b0 : 1'b0; | |
346 | // | |
347 | // or just tied tcu_clk_stop to 1'b0; | |
348 | //________________________________________________________________ | |
349 | ||
350 | clkgen_rst_cmp clkgen_rst_cmp ( | |
351 | // Clock & test out | |
352 | .scan_in(clkgen_rst_cmp_scanin), | |
353 | .scan_out(clkgen_rst_cmp_scanout), | |
354 | .l2clk (l2clk ),// Assume we do not need aclk,bclk outputs | |
355 | //.aclk ( ),// Buffered version of aclk | |
356 | .aclk_wmr (clkgen_rst_cmp_aclk_wmr_unused), | |
357 | // Reset Unit uses sync reset, not flush. | |
358 | //.bclk ( ),// Buffered version of bclk | |
359 | ||
360 | // Pipelined out | |
361 | //.clk_stop ( ),// Allows clk stop in flop-header | |
362 | //.pce_ov ( ),// pce override to l1 header | |
363 | ||
364 | // rst is not reset by flush reset. | |
365 | .wmr_protect (clkgen_rst_cmp_wmr_protect_unused), | |
366 | .wmr_ (clkgen_rst_cmp_wmr_unused ), | |
367 | .por_ (clkgen_rst_cmp_por_unused ), | |
368 | // Must assign, else mult drivers.) | |
369 | ||
370 | .cmp_slow_sync_en(cmp_io_sync_en ),// Use for cmp->slow clk sync pulse | |
371 | .slow_cmp_sync_en(io_cmp_sync_en ),// Use for slow->cmp clk sync pulse | |
372 | .array_wr_inhibit(clkgen_rst_cmp_array_wr_inhibit_unused), | |
373 | // (Reset Unit has no SRam array. | |
374 | // but must assign, else mult drivers.) | |
375 | ||
376 | // Ctrl in (for pipelining ) | |
377 | //.tcu_clk_stop (tcu_clk_stop_scan_mode),// = tcu_rst_scan_mode ? | |
378 | // tcu_rst_clk_stop : 1'b0; | |
379 | // 1'b0 : 1'b0; | |
380 | .tcu_clk_stop (1'b0 ),// | |
381 | //.tcu_atpg_mode (tcu_atpg_mode ),// | |
382 | .tcu_wr_inhibit (1'b0 ),// (Reset Unit has no SRam array.) | |
383 | .tcu_pce_ov (tcu_pce_ov ),// "Connect to tcu_pce_ov port on TCU." | |
384 | //.rst_wmr_protect (rst_wmr_protect ),// No cmp flops are WMR protected. | |
385 | .rst_wmr_ (1'b1 ),// No IP modules. | |
386 | .rst_por_ (1'b1 ),// No IP modules. | |
387 | ||
388 | .ccu_cmp_slow_sync_en | |
389 | (ccu_cmp_io_sync_en ),// "Connect to ccu_cmp_<slow>_sync_en." | |
390 | .ccu_slow_cmp_sync_en | |
391 | (ccu_io_cmp_sync_en ),// "Connect to ccu_<slow>_cmp_sync_en." | |
392 | // "Cluster Heder Usage, Niagara 2", | |
393 | // Version 1.41, Apr 29, 2005, Section | |
394 | // 4.1, "CMP Domain Example", page 6. | |
395 | ||
396 | // Ctrl in (for clock gen ) | |
397 | .tcu_div_bypass (tcu_div_bypass ),// Bypasses clk divider to mux in ext clk | |
398 | // "Connect to TBD port on TCU." | |
399 | // CH Hdr Usage in RTL, v1.2 Feb 16 '05 | |
400 | .ccu_div_ph (1'b1 ),// Phase signal from ccu (div/4 or div/2) | |
401 | // "Tie high." | |
402 | .cluster_div_en (1'b0 ),// If enabled, l2clk is divided down | |
403 | // Clock & test in | |
404 | // "Tie low." | |
405 | .gclk (gclk ),// Global clk - this is either cmp or dr | |
406 | .cluster_arst_l (1'b1 ),// Need to be able to provide a | |
407 | // free-running version of l1clk | |
408 | // for rst_tcu_clk_stop, | |
409 | // ccu_cmp_sys_cync_en2, _en3, | |
410 | // ccu_sys_cmp_sync_en2, and _en3. | |
411 | .clk_ext (1'b0 ),// External clk muxed in for ioclk bypass | |
412 | // "Unused - tie low." | |
413 | // ".clk_ext and .ccu_serdes_dtm have | |
414 | // been removed from the cluster_header | |
415 | // but still exist in the wrapper for | |
416 | // minimal disruption. They will have no | |
417 | // effect on RTL/simulation. They can be | |
418 | // taken out later on." | |
419 | .ccu_serdes_dtm (1'b0 ),// (See above.) | |
420 | .scan_en (pwron_rst_h_scan_mode_en),// = (~mio_rst_pwron_rst_l ) | | |
421 | // ( tcu_rst_scan_mode&rst_scan_en) | |
422 | // Was tcu_scan_en, but always 1. | |
423 | // "Tie low." | |
424 | .tcu_aclk (tcu_aclk ), | |
425 | .tcu_bclk (tcu_bclk ), | |
426 | .tcu_atpg_mode(tcu_atpg_mode), | |
427 | .aclk(aclk), | |
428 | .bclk(bclk), | |
429 | .pce_ov(pce_ov), | |
430 | .rst_wmr_protect(rst_wmr_protect) | |
431 | ); | |
432 | //________________________________________________________________ | |
433 | ||
434 | clkgen_rst_io clkgen_rst_io ( | |
435 | // Clock & test out | |
436 | .scan_in(clkgen_rst_io_scanin), | |
437 | .scan_out(clkgen_rst_io_scanout), | |
438 | .l2clk (iol2clk ),// Assume we do not need aclk,bclk outputs | |
439 | // Later, change to iol2clk, and | |
440 | // drive fsm directly from pll_ref_clk. | |
441 | .aclk (tcu_aclk_gen ),// Buffered version of aclk | |
442 | .aclk_wmr (clkgen_rst_io_aclk_wmr_unused), | |
443 | // Reset Unit uses sync reset, not flush. | |
444 | .bclk (tcu_bclk_gen ),// Buffered version of bclk | |
445 | ||
446 | // Pipelined out | |
447 | .pce_ov (tcu_pce_ov_gen ),// pce override to l1 header | |
448 | ||
449 | //.rst_wmr_protect (rst_wmr_protect ),// No UCB flops are WMR protected. | |
450 | //.wmr_ ( ),// Warm reset (active low) | |
451 | //.por_ ( ),// Power-on-reset | |
452 | .wmr_protect (clkgen_rst_io_wmr_protect_unused), | |
453 | .wmr_ (clkgen_rst_io_wmr_unused ), | |
454 | .por_ (clkgen_rst_io_por_unused ), | |
455 | // Must assign, else mult drivers.) | |
456 | ||
457 | .cmp_slow_sync_en(clkgen_rst_io_cmp_slow_sync_en_unused), | |
458 | // See cmp_slow_sync_en on clkgen_rst_cmp. | |
459 | .slow_cmp_sync_en(clkgen_rst_io_slow_cmp_sync_en_unused), | |
460 | // See slow_cmp_sync_en on clkgen_rst_cmp. | |
461 | // "Tie low (use corresponding port on | |
462 | // CMP cluster header, clkgen_rst_cmp.)", | |
463 | // "Cluster Heder Usage, Niagara 2", | |
464 | // Version 1.41, Apr 29, 2005, Section | |
465 | // 4.3, "CMP and DR Domains Example", | |
466 | // page 9. | |
467 | .array_wr_inhibit(clkgen_rst_io_array_wr_inhibit_unused), | |
468 | // (Reset Unit has no SRam array. | |
469 | // but must assign, else mult drivers.) | |
470 | ||
471 | // Ctrl in (for pipelining ) | |
472 | //.tcu_clk_stop (tcu_rst_io_clk_stop | |
473 | .tcu_clk_stop (rst_tcu_clk_stop_io),// Stop clocks when pll locking, to | |
474 | // allow rst_mcu_selfrsh to hold value. | |
475 | //.tcu_atpg_mode (tcu_atpg_mode ),// | |
476 | .tcu_wr_inhibit (1'b0 ),// (Reset Unit has no SRam array.) | |
477 | .tcu_pce_ov (tcu_pce_ov ), | |
478 | .rst_wmr_protect (1'b0 ),// rst is not reset by flush reset. | |
479 | .rst_wmr_ (1'b1 ), | |
480 | .rst_por_ (1'b1 ), | |
481 | .ccu_cmp_slow_sync_en | |
482 | (1'b0 ),// "Tie low." | |
483 | .ccu_slow_cmp_sync_en | |
484 | (1'b0 ),// "Tie low." | |
485 | // "Tie low (use corresponding port on | |
486 | // CMP cluster header, clkgen_rst_cmp.)", | |
487 | // "Cluster Heder Usage, Niagara 2", | |
488 | // Version 1.41, Apr 29, 2005, Section | |
489 | // 4.3, "CMP and DR Domains Example", | |
490 | // page 9. | |
491 | ||
492 | // Ctrl in (for clock gen ) | |
493 | .tcu_div_bypass (tcu_div_bypass ),// Bypasses clk divider to mux in ext clk | |
494 | // "Connect to TBD port on TCU." | |
495 | // CH Hdr Usage in RTL, v1.2 Feb 16 '05 | |
496 | .ccu_div_ph (ccu_io_out ),// Phase signal from ccu (div/4 or div/2) | |
497 | .cluster_div_en (1'b1 ),// If enabled, l2clk is divided down | |
498 | // Clock & test in | |
499 | .gclk (gclk ),// Global clk - this is either cmp or dr | |
500 | //.cluster_arst_l (cluster_arst_l ),// SunV connect by name. | |
501 | .clk_ext (1'b0 ),// External clk muxed in for ioclk bypass | |
502 | // ".clk_ext and .ccu_serdes_dtm have | |
503 | // been removed from the cluster_header | |
504 | // but still exist in the wrapper for | |
505 | // minimal disruption. They will have no | |
506 | // effect on RTL/simulation. They can be | |
507 | // taken out later on." | |
508 | .ccu_serdes_dtm (1'b0 ),// (See above.) | |
509 | .scan_en (pwron_rst_h_scan_mode_en),// = (~mio_rst_pwron_rst_l ) | | |
510 | // ( tcu_rst_scan_mode&rst_scan_en) | |
511 | // Was tcu_scan_en, but always 1. | |
512 | // "Tie low." | |
513 | //.scan_en (tcu_scan_en ),// Was: stop clocks for flush reset. | |
514 | .tcu_aclk (tcu_aclk ), | |
515 | .tcu_bclk (tcu_bclk ), | |
516 | .tcu_atpg_mode(tcu_atpg_mode), | |
517 | .cluster_arst_l(cluster_arst_l) | |
518 | ); | |
519 | //________________________________________________________________ | |
520 | ||
521 | rst_fsm_ctl rst_fsm_ctl ( | |
522 | ||
523 | .ref_clk (ccu_rst_sys_clk/*iol2clk*/ ),// (Was io_ref_clk.) | |
524 | .rst_fsm_ctl_scanout(rst_fsm_ctl_scanout), | |
525 | ||
526 | // If you run fixscan rst.sv, you will get the following: | |
527 | //.scan_out(rst_fsm_ctl_scanout), | |
528 | // If you run fixscan rst.sv, be sure to | |
529 | // comment out the preceding line, so that the: | |
530 | //.rst_fsm_ctl_scanout(rst_fsm_ctl_scanout) | |
531 | // port above will be used. | |
532 | ||
533 | .scan_in(rst_fsm_ctl_scanin), | |
534 | .rst_aclk (tcu_aclk_gen ),// Called rst_ here... | |
535 | .rst_bclk (tcu_bclk_gen ),// to allow assign stmt. | |
536 | .rst_scan_en (tcu_scan_en ),// Assign stmt. | |
537 | .tcu_pce_ov (tcu_pce_ov_gen ),// (No assign needed.) | |
538 | .rst_clk_stop (tcu_rst_clk_stop ),// Assign stmt. | |
539 | //.rst_rst_por_sys2_ (rst_rst_por_sys2_ ),// BP 8-22-05 sync rst ucb | |
540 | //.rst_rst_wmr_sys2_ (rst_rst_wmr_sys2_ ),// BP 8-22-05 sync rst ucb | |
541 | // Was ucb_clr_sys2_. | |
542 | //.req_acpted (req_acpted ),// Acceptance of CSR wr,rd cmd. | |
543 | // Commands to RST | |
544 | //.rd_req_vld (rd_req_vld ),// | |
545 | //.wr_req_vld (wr_req_vld ),// | |
546 | //.addr_in (addr_in[39:0] ),// | |
547 | //.data_in (data_in[63:0] ),// | |
548 | //.thr_id_in (thr_id_in[ 5:0] ),// | |
549 | //.buf_id_in (buf_id_in[ 1:0] ),// | |
550 | //.ack_busy (ack_busy ),// | |
551 | // Ack-Nack from RST | |
552 | //.rd_ack_vld (rd_ack_vld ),// | |
553 | //.rd_nack_vld (rd_nack_vld ),// | |
554 | ||
555 | //.data_out (data_out[63:0] ),// Return data. | |
556 | //.thr_id_out (thr_id_out[ 5:0] ),// | |
557 | //.buf_id_out (buf_id_out[ 1:0] ),// | |
558 | ||
559 | //.mio_rst_pwron_rst_l (mio_rst_pwron_rst_l ),// SunV implicit connect. | |
560 | //.mio_rst_button_xir_l (mio_rst_button_xir_l ),// SunV implicit connect. | |
561 | //.ncu_rst_xir_done_sys (ncu_rst_xir_done_sys ),// SunV connect by name. | |
562 | //.mio_rst_pb_rst_l (mio_rst_pb_rst_l ),// SunV implicit connect. | |
563 | //.ccu_rst_change_cmp (ccu_rst_change_cmp ),// To be connect by name. | |
564 | //.tcu_bisx_done_cmp (tcu_bisx_done_cmp ),// SunV connect by name. | |
565 | //.tcu_rst_efu_done_cmp (tcu_rst_efu_done_cmp ),// SunV connect by name. | |
566 | ||
567 | //.l2t0_rst_fatal_error_cmp(l2t0_rst_fatal_error_cmp),// SunV connect by name. | |
568 | //.l2t1_rst_fatal_error_cmp(l2t1_rst_fatal_error_cmp),// SunV connect by name. | |
569 | //.l2t2_rst_fatal_error_cmp(l2t2_rst_fatal_error_cmp),// SunV connect by name. | |
570 | //.l2t3_rst_fatal_error_cmp(l2t3_rst_fatal_error_cmp),// SunV connect by name. | |
571 | //.l2t4_rst_fatal_error_cmp(l2t4_rst_fatal_error_cmp),// SunV connect by name. | |
572 | //.l2t5_rst_fatal_error_cmp(l2t5_rst_fatal_error_cmp),// SunV connect by name. | |
573 | //.l2t6_rst_fatal_error_cmp(l2t6_rst_fatal_error_cmp),// SunV connect by name. | |
574 | //.l2t7_rst_fatal_error_cmp(l2t7_rst_fatal_error_cmp),// SunV connect by name. | |
575 | ||
576 | //.rst_l2_por_ (rst_l2_por_ ),// SunV connect by name. | |
577 | //.rst_l2_wmr_ (rst_l2_wmr_ ),// SunV connect by name. | |
578 | ||
579 | //.rst_niu_wmr_ (rst_niu_wmr_ ),// SunV implicit connect. | |
580 | //.rst_ncu_unpark_thread_sys2(rst_ncu_unpark_thread_sys2),//Sunv connect. | |
581 | //.rst_ncu_xir_sys2 (rst_ncu_xir_sys2 ),// Sunv implicit connect. | |
582 | .rst_mio_pex_reset_l (rst_mio_pex_reset_l ), | |
583 | .req_acpted_sys(req_acpted_sys), | |
584 | .rd_req_vld_sys(rd_req_vld_sys), | |
585 | .wr_req_vld_sys(wr_req_vld_sys), | |
586 | .addr_in_sys(addr_in_sys[39:0]), | |
587 | .data_in_sys(data_in_sys[15:0]), | |
588 | .thr_id_in_sys(thr_id_in_sys[5:0]), | |
589 | .buf_id_in_sys(buf_id_in_sys[1:0]), | |
590 | .ack_busy_sys(ack_busy_sys), | |
591 | .rd_ack_vld_sys(rd_ack_vld_sys), | |
592 | .rd_nack_vld_sys(rd_nack_vld_sys), | |
593 | .data_out_sys2(data_out_sys2[15:0]), | |
594 | .thr_id_out_sys(thr_id_out_sys[5:0]), | |
595 | .buf_id_out_sys(buf_id_out_sys[1:0]), | |
596 | .mio_rst_pwron_rst_l(mio_rst_pwron_rst_l), | |
597 | .mio_rst_button_xir_l(mio_rst_button_xir_l), | |
598 | .ncu_rst_xir_done_sys(ncu_rst_xir_done_sys), | |
599 | .mio_rst_pb_rst_l(mio_rst_pb_rst_l), | |
600 | .ccu_rst_change_cmp(ccu_rst_change_cmp), | |
601 | .tcu_bisx_done_cmp(tcu_bisx_done_cmp), | |
602 | .tcu_rst_efu_done_cmp(tcu_rst_efu_done_cmp), | |
603 | .tr_flush_init_ack_cmp(tr_flush_init_ack_cmp), | |
604 | .tr_flush_stop_ack_cmp(tr_flush_stop_ack_cmp), | |
605 | .tr_asicflush_stop_ack_cmp(tr_asicflush_stop_ack_cmp), | |
606 | .ncu_rst_fatal_error_cmp(ncu_rst_fatal_error_cmp), | |
607 | .l2t0_rst_fatal_error_cmp(l2t0_rst_fatal_error_cmp), | |
608 | .l2t1_rst_fatal_error_cmp(l2t1_rst_fatal_error_cmp), | |
609 | .l2t2_rst_fatal_error_cmp(l2t2_rst_fatal_error_cmp), | |
610 | .l2t3_rst_fatal_error_cmp(l2t3_rst_fatal_error_cmp), | |
611 | .l2t4_rst_fatal_error_cmp(l2t4_rst_fatal_error_cmp), | |
612 | .l2t5_rst_fatal_error_cmp(l2t5_rst_fatal_error_cmp), | |
613 | .l2t6_rst_fatal_error_cmp(l2t6_rst_fatal_error_cmp), | |
614 | .l2t7_rst_fatal_error_cmp(l2t7_rst_fatal_error_cmp), | |
615 | .tcu_rst_scan_mode(tcu_rst_scan_mode), | |
616 | .mio_rst_pb_rst_sys2_(mio_rst_pb_rst_sys2_), | |
617 | .tcu_test_protect_cmp(tcu_test_protect_cmp), | |
618 | .rst_ccu_pll_(rst_ccu_pll_), | |
619 | .rst_ccu_(rst_ccu_), | |
620 | .rst_l2_por_sys2_(rst_l2_por_sys2_), | |
621 | .rst_l2_wmr_sys2_(rst_l2_wmr_sys2_), | |
622 | .rst_cmp_ctl_wmr_sys2_(rst_cmp_ctl_wmr_sys2_), | |
623 | .rst_wmr_protect(rst_wmr_protect), | |
624 | .rst_tcu_clk_stop_sys2(rst_tcu_clk_stop_sys2), | |
625 | .rst_mcu_selfrsh_sys2(rst_mcu_selfrsh_sys2), | |
626 | .rst_dmu_peu_por_sys2_(rst_dmu_peu_por_sys2_), | |
627 | .rst_dmu_peu_wmr_sys2_(rst_dmu_peu_wmr_sys2_), | |
628 | .rt_flush_init_req_sys2(rt_flush_init_req_sys2), | |
629 | .rt_flush_stop_req_sys2(rt_flush_stop_req_sys2), | |
630 | .rt_asicflush_stop_req_sys2(rt_asicflush_stop_req_sys2), | |
631 | .rst_niu_mac_sys2_(rst_niu_mac_sys2_), | |
632 | .rst_niu_wmr_sys2_(rst_niu_wmr_sys2_), | |
633 | .rst_ncu_unpark_thread_sys2(rst_ncu_unpark_thread_sys2), | |
634 | .rst_ncu_xir_sys2_(rst_ncu_xir_sys2_), | |
635 | .rst_mio_ssi_sync_l(rst_mio_ssi_sync_l), | |
636 | .rst_mio_rst_state(rst_mio_rst_state[5:0]), | |
637 | .cluster_arst_l(cluster_arst_l), | |
638 | .rst_dmu_async_por_(rst_dmu_async_por_), | |
639 | .rst_rst_pwron_rst_l_sys2_(rst_rst_pwron_rst_l_sys2_), | |
640 | .reset_gen_dbr_gen_q(reset_gen_dbr_gen_q), | |
641 | .rst_rst_por_sys2_(rst_rst_por_sys2_), | |
642 | .rst_rst_wmr_sys2_(rst_rst_wmr_sys2_), | |
643 | .mio_rst_pb_rst_sys_(mio_rst_pb_rst_sys_)// Added Nov 11 '04. | |
644 | //.rst_mio_ssi_sync_l (rst_mio_ssi_sync_l ),// Sunv implicit connect. | |
645 | // Replaces rst_mio_fatal_error. | |
646 | ); | |
647 | //________________________________________________________________ | |
648 | ||
649 | rst_ucbflow_ctl rst_ucbflow_ctl ( | |
650 | // Globals | |
651 | .scan_in(rst_ucbflow_ctl_scanin), | |
652 | .ucb_ctl_scanout(rst_ucbflow_ctl_scanout), | |
653 | .iol2clk (iol2clk ), | |
654 | .tcu_pce_ov (tcu_pce_ov_gen ), | |
655 | .rst_clk_stop (1'b0 ),// BP 8-22-05 | |
656 | .rst_aclk (tcu_aclk_gen ),// BP 8-22-05 | |
657 | .rst_bclk (tcu_bclk_gen ),// BP 8-22-05 | |
658 | .rst_scan_en (tcu_scan_en ),// BP 8-22-05 | |
659 | .ucb_clr_io_ (rst_rst_wmr_io_ ),// BP 8-22-05 | |
660 | // Should be (rst_rst_wmr_io2_ ),// BP 8-22-05 | |
661 | // Downstream from NCU | |
662 | .ncu_rst_vld (ncu_rst_vld ), | |
663 | .ncu_rst_data (ncu_rst_data[3:0] ), | |
664 | .rst_ncu_stall (rst_ncu_stall ), | |
665 | // Upstream to NCU | |
666 | .rst_ncu_vld (rst_ncu_vld ), | |
667 | .rst_ncu_data (rst_ncu_data[3:0] ), | |
668 | .ncu_rst_stall (ncu_rst_stall ), | |
669 | // CMDs to local unit | |
670 | .rd_req_vld (rd_req_vld ), | |
671 | .wr_req_vld (wr_req_vld ), | |
672 | .thr_id_in (thr_id_in[5:0] ), | |
673 | .buf_id_in (buf_id_in[1:0] ), | |
674 | .addr_in (addr_in[39:0] ), | |
675 | .data_in (data_in[63:0] ), | |
676 | .req_acpted (req_acpted ), | |
677 | // Ack/Nack from local unit | |
678 | .rd_ack_vld (rd_ack_vld ),// | |
679 | .rd_nack_vld (rd_nack_vld ), | |
680 | .thr_id_out (thr_id_out[5:0] ), | |
681 | .buf_id_out (buf_id_out[1:0] ), | |
682 | .data_out (data_out[63:0] ), | |
683 | .ack_busy (ack_busy ), | |
684 | .tcu_rst_scan_mode(tcu_rst_scan_mode) | |
685 | ); | |
686 | //________________________________________________________________ | |
687 | ||
688 | rst_cmp_ctl rst_cmp_ctl ( | |
689 | .scan_in(rst_cmp_ctl_scanin), | |
690 | .scan_out(rst_cmp_ctl_scanout), | |
691 | .rst_aclk (tcu_aclk_gen ),// Called rst_ here... | |
692 | .rst_bclk (tcu_bclk_gen ),// to allow assign stmt. | |
693 | .rst_scan_en (tcu_scan_en ),// Assign stmt. | |
694 | .tcu_pce_ov (tcu_pce_ov_gen ),// (No assign needed.) | |
695 | .rst_clk_stop (1'b0 ), | |
696 | .l2clk(l2clk), | |
697 | .tcu_rst_scan_mode(tcu_rst_scan_mode), | |
698 | .ccu_cmp_sys_sync_en(ccu_cmp_sys_sync_en), | |
699 | .ccu_sys_cmp_sync_en(ccu_sys_cmp_sync_en), | |
700 | .cmp_io_sync_en(cmp_io_sync_en), | |
701 | .io_cmp_sync_en(io_cmp_sync_en), | |
702 | .rst_cmp_ctl_wmr_sys2_(rst_cmp_ctl_wmr_sys2_), | |
703 | .mio_rst_pwron_rst_l(mio_rst_pwron_rst_l), | |
704 | .tcu_rst_flush_init_ack(tcu_rst_flush_init_ack), | |
705 | .tcu_rst_flush_stop_ack(tcu_rst_flush_stop_ack), | |
706 | .tcu_rst_asicflush_stop_ack(tcu_rst_asicflush_stop_ack), | |
707 | .rst_mcu_selfrsh_sys2(rst_mcu_selfrsh_sys2), | |
708 | .rst_l2_por_sys2_(rst_l2_por_sys2_), | |
709 | .rst_l2_wmr_sys2_(rst_l2_wmr_sys2_), | |
710 | .rst_dmu_peu_por_sys2_(rst_dmu_peu_por_sys2_), | |
711 | .rst_dmu_peu_wmr_sys2_(rst_dmu_peu_wmr_sys2_), | |
712 | .rst_niu_mac_sys2_(rst_niu_mac_sys2_), | |
713 | .rst_niu_wmr_sys2_(rst_niu_wmr_sys2_), | |
714 | .rst_tcu_clk_stop_sys2(rst_tcu_clk_stop_sys2), | |
715 | .rst_ncu_unpark_thread_sys2(rst_ncu_unpark_thread_sys2), | |
716 | .rst_ncu_xir_sys2_(rst_ncu_xir_sys2_), | |
717 | .ncu_rst_xir_done_io(ncu_rst_xir_done_io), | |
718 | .tcu_rst_efu_done(tcu_rst_efu_done), | |
719 | .tcu_bisx_done(tcu_bisx_done), | |
720 | .tcu_test_protect_io(tcu_test_protect_io), | |
721 | .ccu_rst_change_io(ccu_rst_change_io), | |
722 | .l2ta_rst_fatal_error_io(l2ta_rst_fatal_error_io[7:0]), | |
723 | .ncu_rst_fatal_error_io(ncu_rst_fatal_error_io), | |
724 | .tr_flush_init_ack_cmp(tr_flush_init_ack_cmp), | |
725 | .tr_flush_stop_ack_cmp(tr_flush_stop_ack_cmp), | |
726 | .tr_asicflush_stop_ack_cmp(tr_asicflush_stop_ack_cmp), | |
727 | .rt_flush_init_req_sys2(rt_flush_init_req_sys2), | |
728 | .rt_flush_stop_req_sys2(rt_flush_stop_req_sys2), | |
729 | .rt_asicflush_stop_req_sys2(rt_asicflush_stop_req_sys2), | |
730 | .rst_tcu_flush_init_req(rst_tcu_flush_init_req), | |
731 | .rst_tcu_flush_stop_req(rst_tcu_flush_stop_req), | |
732 | .rst_tcu_asicflush_stop_req(rst_tcu_asicflush_stop_req), | |
733 | .rd_req_vld_io(rd_req_vld_io), | |
734 | .wr_req_vld_io(wr_req_vld_io), | |
735 | .req_acpted_sys(req_acpted_sys), | |
736 | .rd_ack_vld_sys(rd_ack_vld_sys), | |
737 | .rd_nack_vld_sys(rd_nack_vld_sys), | |
738 | .addr_in_io(addr_in_io[39:0]), | |
739 | .data_in_io(data_in_io[15:0]), | |
740 | .thr_id_in_io(thr_id_in_io[5:0]), | |
741 | .buf_id_in_io(buf_id_in_io[1:0]), | |
742 | .ack_busy_io(ack_busy_io), | |
743 | .data_out_sys2(data_out_sys2[15:0]), | |
744 | .thr_id_out_sys(thr_id_out_sys[5:0]), | |
745 | .buf_id_out_sys(buf_id_out_sys[1:0]), | |
746 | .reset_gen_dbr_gen_q(reset_gen_dbr_gen_q), | |
747 | .rd_req_vld_sys(rd_req_vld_sys), | |
748 | .wr_req_vld_sys(wr_req_vld_sys), | |
749 | .req_acpted_cmp2(req_acpted_cmp2), | |
750 | .rd_ack_vld_cmp2(rd_ack_vld_cmp2), | |
751 | .rd_nack_vld_cmp2(rd_nack_vld_cmp2), | |
752 | .addr_in_sys(addr_in_sys[39:0]), | |
753 | .data_in_sys(data_in_sys[15:0]), | |
754 | .thr_id_in_sys(thr_id_in_sys[5:0]), | |
755 | .buf_id_in_sys(buf_id_in_sys[1:0]), | |
756 | .ack_busy_sys(ack_busy_sys), | |
757 | .data_out_cmp2(data_out_cmp2[15:0]), | |
758 | .thr_id_out_cmp2(thr_id_out_cmp2[5:0]), | |
759 | .buf_id_out_cmp2(buf_id_out_cmp2[1:0]), | |
760 | .rst_mcu_selfrsh_cmp2(rst_mcu_selfrsh_cmp2), | |
761 | .rst_dmu_peu_por_(rst_dmu_peu_por_), | |
762 | .rst_dmu_peu_wmr_(rst_dmu_peu_wmr_), | |
763 | .rst_niu_mac_(rst_niu_mac_), | |
764 | .rst_niu_wmr_(rst_niu_wmr_), | |
765 | .rst_tcu_clk_stop(rst_tcu_clk_stop), | |
766 | .rst_tcu_clk_stop_io(rst_tcu_clk_stop_io), | |
767 | .rst_l2_por_(rst_l2_por_), | |
768 | .rst_l2_wmr_(rst_l2_wmr_), | |
769 | .rst_ncu_unpark_thread_cmp2(rst_ncu_unpark_thread_cmp2), | |
770 | .rst_ncu_xir_cmp2_(rst_ncu_xir_cmp2_), | |
771 | .ncu_rst_xir_done_sys(ncu_rst_xir_done_sys), | |
772 | .tcu_rst_efu_done_cmp(tcu_rst_efu_done_cmp), | |
773 | .tcu_bisx_done_cmp(tcu_bisx_done_cmp), | |
774 | .ncu_rst_fatal_error_cmp(ncu_rst_fatal_error_cmp), | |
775 | .tcu_test_protect_cmp(tcu_test_protect_cmp), | |
776 | .ccu_rst_change_cmp(ccu_rst_change_cmp), | |
777 | .l2t7_rst_fatal_error_cmp(l2t7_rst_fatal_error_cmp), | |
778 | .l2t6_rst_fatal_error_cmp(l2t6_rst_fatal_error_cmp), | |
779 | .l2t5_rst_fatal_error_cmp(l2t5_rst_fatal_error_cmp), | |
780 | .l2t4_rst_fatal_error_cmp(l2t4_rst_fatal_error_cmp), | |
781 | .l2t3_rst_fatal_error_cmp(l2t3_rst_fatal_error_cmp), | |
782 | .l2t2_rst_fatal_error_cmp(l2t2_rst_fatal_error_cmp), | |
783 | .l2t1_rst_fatal_error_cmp(l2t1_rst_fatal_error_cmp), | |
784 | .l2t0_rst_fatal_error_cmp(l2t0_rst_fatal_error_cmp), | |
785 | .pwron_rst_h_scan_mode_en(pwron_rst_h_scan_mode_en), | |
786 | .rst_tcu_dbr_gen(rst_tcu_dbr_gen), | |
787 | .rst_rst_pwron_rst_l_sys2_(rst_rst_pwron_rst_l_sys2_), | |
788 | .rst_tcu_pwron_rst_l(rst_tcu_pwron_rst_l), | |
789 | .rst_rst_pwron_rst_l_io0_(rst_rst_pwron_rst_l_io0_), | |
790 | .mio_rst_pb_rst_sys_(mio_rst_pb_rst_sys_), | |
791 | .mio_rst_pb_rst_sys2_(mio_rst_pb_rst_sys2_), | |
792 | .rst_rst_por_sys2_(rst_rst_por_sys2_), | |
793 | .rst_rst_por_io0_(rst_rst_por_io0_), | |
794 | .rst_rst_wmr_sys2_(rst_rst_wmr_sys2_), | |
795 | .rst_rst_wmr_io0_(rst_rst_wmr_io0_) // Assign stmt. | |
796 | //.rst_tcu_clk_stop_io (rst_tcu_clk_stop_io ) // Implicit SunV connect. | |
797 | //.pwron_rst_h_scan_mode_en | |
798 | // (pwron_rst_h_scan_mode_en ),// Implicit SunV connect. | |
799 | //.tcu_rst_asicflush_stop_ack // Implicit SunV connect. | |
800 | // (tcu_rst_asicflush_stop_ack),// Implicit SunV connect. | |
801 | // (1'b1 ),// Until tcu drives. | |
802 | //.rst_rst_por_sys2_ (rst_rst_por_sys2_ ),// Implicit SunV connect. | |
803 | //.rst_rst_wmr_sys2_ (rst_rst_wmr_sys2_ ),// Implicit SunV connect. | |
804 | // Was ucb_clr_sys2_. | |
805 | //.rst_rst_wmr_io_ (rst_rst_wmr_io_ ) // Implicit SunV connect. | |
806 | // Was ucb_clr_io_. | |
807 | ); | |
808 | //________________________________________________________________ | |
809 | ||
810 | rst_io_ctl rst_io_ctl ( | |
811 | .scan_in(rst_io_ctl_scanin), | |
812 | .scan_out(rst_io_ctl_scanout), | |
813 | .rst_aclk (tcu_aclk_gen ),// Called rst_ here... | |
814 | .rst_bclk (tcu_bclk_gen ),// to allow assign stmt. | |
815 | //.rst_scan_en (tcu_scan_en ),// Assign stmt. | |
816 | // Don't protect from flush, | |
817 | // so pass tcu_scan_en. | |
818 | //.rst_rst_por_io_ (rst_rst_por_io_ ),// | |
819 | //.rst_rst_wmr_io_ (rst_rst_wmr_io_ ),// BP 8-22-05 Was ucb_clr_io_. | |
820 | // Should add: (rst_rst_wmr_io2_ ),// BP 8-22-05 | |
821 | .tcu_pce_ov (tcu_pce_ov_gen ),// (No assign needed.) | |
822 | .rst_clk_stop (1'b0 ), | |
823 | .iol2clk(iol2clk), | |
824 | .tcu_scan_en(tcu_scan_en), | |
825 | .tcu_rst_scan_mode(tcu_rst_scan_mode), | |
826 | .rst_rst_por_io0_(rst_rst_por_io0_), | |
827 | .rst_rst_wmr_io0_(rst_rst_wmr_io0_), | |
828 | .rd_req_vld(rd_req_vld), | |
829 | .wr_req_vld(wr_req_vld), | |
830 | .req_acpted_cmp2(req_acpted_cmp2), | |
831 | .rd_ack_vld_cmp2(rd_ack_vld_cmp2), | |
832 | .rd_nack_vld_cmp2(rd_nack_vld_cmp2), | |
833 | .addr_in(addr_in[39:0]), | |
834 | .data_in(data_in[63:0]), | |
835 | .thr_id_in(thr_id_in[5:0]), | |
836 | .buf_id_in(buf_id_in[1:0]), | |
837 | .ack_busy(ack_busy), | |
838 | .data_out_cmp2(data_out_cmp2[15:0]), | |
839 | .thr_id_out_cmp2(thr_id_out_cmp2[5:0]), | |
840 | .buf_id_out_cmp2(buf_id_out_cmp2[1:0]), | |
841 | .rst_ncu_unpark_thread_cmp2(rst_ncu_unpark_thread_cmp2), | |
842 | .rst_ncu_xir_cmp2_(rst_ncu_xir_cmp2_), | |
843 | .ncu_rst_xir_done(ncu_rst_xir_done), | |
844 | .ccu_rst_change(ccu_rst_change), | |
845 | .l2t0_rst_fatal_error(l2t0_rst_fatal_error), | |
846 | .l2t1_rst_fatal_error(l2t1_rst_fatal_error), | |
847 | .l2t2_rst_fatal_error(l2t2_rst_fatal_error), | |
848 | .l2t3_rst_fatal_error(l2t3_rst_fatal_error), | |
849 | .l2t4_rst_fatal_error(l2t4_rst_fatal_error), | |
850 | .l2t5_rst_fatal_error(l2t5_rst_fatal_error), | |
851 | .l2t6_rst_fatal_error(l2t6_rst_fatal_error), | |
852 | .l2t7_rst_fatal_error(l2t7_rst_fatal_error), | |
853 | .ncu_rst_fatal_error(ncu_rst_fatal_error), | |
854 | .tcu_test_protect(tcu_test_protect), | |
855 | .rst_mcu_selfrsh_cmp2(rst_mcu_selfrsh_cmp2), | |
856 | .rst_rst_pwron_rst_l_io0_(rst_rst_pwron_rst_l_io0_), | |
857 | .rd_req_vld_io(rd_req_vld_io), | |
858 | .wr_req_vld_io(wr_req_vld_io), | |
859 | .req_acpted(req_acpted), | |
860 | .rd_ack_vld(rd_ack_vld), | |
861 | .rd_nack_vld(rd_nack_vld), | |
862 | .addr_in_io(addr_in_io[39:0]), | |
863 | .data_in_io(data_in_io[15:0]), | |
864 | .thr_id_in_io(thr_id_in_io[5:0]), | |
865 | .buf_id_in_io(buf_id_in_io[1:0]), | |
866 | .ack_busy_io(ack_busy_io), | |
867 | .data_out(data_out[63:0]), | |
868 | .thr_id_out(thr_id_out[5:0]), | |
869 | .buf_id_out(buf_id_out[1:0]), | |
870 | .rst_ncu_unpark_thread(rst_ncu_unpark_thread), | |
871 | .rst_ncu_xir_(rst_ncu_xir_), | |
872 | .ncu_rst_xir_done_io(ncu_rst_xir_done_io), | |
873 | .ccu_rst_change_io(ccu_rst_change_io), | |
874 | .l2ta_rst_fatal_error_io(l2ta_rst_fatal_error_io[7:0]), | |
875 | .ncu_rst_fatal_error_io(ncu_rst_fatal_error_io), | |
876 | .tcu_test_protect_io(tcu_test_protect_io), | |
877 | .rst_rst_wmr_io_(rst_rst_wmr_io_), | |
878 | .rst_mcu_selfrsh(rst_mcu_selfrsh) // Assign stmt. | |
879 | ); | |
880 | //________________________________________________________________ | |
881 | ||
882 | // The following three lines used to be in rst.sv: | |
883 | // | |
884 | // rst_fsm_ctl(.scan_out(rst_fsm_ctl_scanout), ... | |
885 | // assign rst_ucbflow_ctl_scanin = tcu_rst_scan_mode ? rst_fsm_ctl_scanout | |
886 | // : 1'b0 ; | |
887 | // moved that logic to rst_fsm_ctl.sv, Mar 2 '05. | |
888 | // .scan_out output port replaced by: | |
889 | // .rst_fsm_ctl_scanout output port, which has the | |
890 | // tcu_rst_scan_mode logic already performed. | |
891 | // Now, in rst.sv: | |
892 | // rst_fsm_ctl(.rst_fsm_ctl_scanout(rst_fsm_ctl_scanout), ... | |
893 | // assign rst_ucbflow_ctl_scanin = rst_fsm_ctl_scanout; | |
894 | ||
895 | // assign rst_ucbflow_ctl_scanin = tcu_rst_scan_mode ? rst_fsm_ctl_scanout | |
896 | // : 1'b0; (See above.) | |
897 | // fixscan start: | |
898 | assign clkgen_rst_cmp_scanin = scan_in ; | |
899 | assign clkgen_rst_io_scanin = clkgen_rst_cmp_scanout ; | |
900 | assign rst_fsm_ctl_scanin = clkgen_rst_io_scanout ; | |
901 | assign rst_ucbflow_ctl_scanin = rst_fsm_ctl_scanout ; | |
902 | assign rst_cmp_ctl_scanin = rst_ucbflow_ctl_scanout ; | |
903 | assign rst_io_ctl_scanin = rst_cmp_ctl_scanout ; | |
904 | assign scan_out = rst_io_ctl_scanout ; | |
905 | // fixscan end: | |
906 | endmodule // rst | |
907 |