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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: rst_ucbflow_ctl.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module rst_ucbflow_ctl ( | |
36 | iol2clk, | |
37 | ucb_clr_io_, | |
38 | scan_in, | |
39 | ucb_ctl_scanout, | |
40 | tcu_pce_ov, | |
41 | rst_clk_stop, | |
42 | rst_aclk, | |
43 | rst_bclk, | |
44 | rst_scan_en, | |
45 | tcu_rst_scan_mode, | |
46 | ncu_rst_vld, | |
47 | ncu_rst_data, | |
48 | rst_ncu_stall, | |
49 | rst_ncu_vld, | |
50 | rst_ncu_data, | |
51 | ncu_rst_stall, | |
52 | rd_req_vld, | |
53 | wr_req_vld, | |
54 | thr_id_in, | |
55 | buf_id_in, | |
56 | addr_in, | |
57 | data_in, | |
58 | req_acpted, | |
59 | rd_ack_vld, | |
60 | rd_nack_vld, | |
61 | thr_id_out, | |
62 | buf_id_out, | |
63 | data_out, | |
64 | ack_busy) ; | |
65 | wire indata_buf_vld; | |
66 | wire [127:0] indata_buf; | |
67 | wire rst_ucbbusin4_ctl_scanin; | |
68 | wire rst_ucbbusin4_ctl_scanout; | |
69 | wire tcu_clk_stop; | |
70 | wire tcu_aclk; | |
71 | wire tcu_bclk; | |
72 | wire tcu_scan_en; | |
73 | wire rst_ncu_stall_a1; | |
74 | wire read_pending; | |
75 | wire write_pending; | |
76 | wire buf_full; | |
77 | wire rd_buf; | |
78 | wire [1:0] buf_head_next; | |
79 | wire [1:0] buf_head; | |
80 | wire buf_head_next0_; | |
81 | wire buf_head0_; | |
82 | wire buf_head_ff0_scanin; | |
83 | wire buf_head_ff0_scanout; | |
84 | wire l1clk; | |
85 | wire buf_head_ff1_scanin; | |
86 | wire buf_head_ff1_scanout; | |
87 | wire wr_buf; | |
88 | wire [1:0] buf_tail_next; | |
89 | wire [1:0] buf_tail; | |
90 | wire buf_tail_next0_; | |
91 | wire buf_tail0_; | |
92 | wire buf_tail_ff0_scanin; | |
93 | wire buf_tail_ff0_scanout; | |
94 | wire buf_tail_ff1_scanin; | |
95 | wire buf_tail_ff1_scanout; | |
96 | wire buf_full_next; | |
97 | wire buf_full_ff_scanin; | |
98 | wire buf_full_ff_scanout; | |
99 | wire buf_empty_next; | |
100 | wire buf_empty_next_; | |
101 | wire buf_empty; | |
102 | wire buf_empty_; | |
103 | wire buf_empty_ff_scanin; | |
104 | wire buf_empty_ff_scanout; | |
105 | wire [116:0] req_in; | |
106 | wire [8:0] unconnected_rsvd; | |
107 | wire buf0_en; | |
108 | wire buf0_ff_scanin; | |
109 | wire buf0_ff_scanout; | |
110 | wire [116:0] buf0; | |
111 | wire buf1_en; | |
112 | wire buf1_ff_scanin; | |
113 | wire buf1_ff_scanout; | |
114 | wire [116:0] buf1; | |
115 | wire [116:0] req_out; | |
116 | wire [2:0] unconnected_size_in; | |
117 | wire wr_req_vld_nq; | |
118 | wire rd_req_vld_nq; | |
119 | wire ack_buf_wr; | |
120 | wire ack_buf_vld_next; | |
121 | wire ack_buf_rd; | |
122 | wire ack_buf_vld; | |
123 | wire ack_buf_vld_ff_scanin; | |
124 | wire ack_buf_vld_ff_scanout; | |
125 | wire ack_buf_is_nack_ff_scanin; | |
126 | wire ack_buf_is_nack_ff_scanout; | |
127 | wire ack_buf_is_nack; | |
128 | wire [3:0] ack_typ_out; | |
129 | wire [75:0] ack_buf_in; | |
130 | wire ack_buf_ff_scanin; | |
131 | wire ack_buf_ff_scanout; | |
132 | wire [75:0] ack_buf; | |
133 | wire [31:0] ack_buf_vec; | |
134 | wire outdata_buf_busy; | |
135 | wire outdata_buf_wr; | |
136 | wire [127:0] outdata_buf_in; | |
137 | wire [31:0] outdata_vec_in; | |
138 | wire rst_ucbbusout4_ctl_scanin; | |
139 | wire rst_ucbbusout4_ctl_scanout; | |
140 | wire spares_scanin; | |
141 | wire spares_scanout; | |
142 | wire scan_out; | |
143 | wire se; | |
144 | wire siclk; | |
145 | wire soclk; | |
146 | wire pce_ov; | |
147 | wire stop; | |
148 | ||
149 | ||
150 | ||
151 | // Globals | |
152 | input iol2clk; | |
153 | input ucb_clr_io_; //BP 8-19-05 | |
154 | input scan_in; | |
155 | output ucb_ctl_scanout; | |
156 | input tcu_pce_ov; | |
157 | input rst_clk_stop; //BP 8-22-05 | |
158 | input rst_aclk ; //BP 8-22-05 | |
159 | input rst_bclk ; //BP 8-22-05 | |
160 | input rst_scan_en ; //BP 8-22-05 | |
161 | input tcu_rst_scan_mode ; //BP 8-22-05 | |
162 | ||
163 | // Downstream from NCU | |
164 | input ncu_rst_vld; | |
165 | input [3:0] ncu_rst_data; | |
166 | output rst_ncu_stall; | |
167 | ||
168 | // Upstream to NCU | |
169 | output rst_ncu_vld; | |
170 | output [3:0] rst_ncu_data; | |
171 | input ncu_rst_stall; | |
172 | ||
173 | // CMDs to local unit | |
174 | output rd_req_vld; | |
175 | output wr_req_vld; | |
176 | output [5:0] thr_id_in; | |
177 | output [1:0] buf_id_in; | |
178 | output [39:0] addr_in; | |
179 | output [63:0] data_in; | |
180 | input req_acpted; | |
181 | ||
182 | // Ack/Nack from local unit | |
183 | input rd_ack_vld; | |
184 | input rd_nack_vld; | |
185 | input [5:0] thr_id_out; | |
186 | input [1:0] buf_id_out; | |
187 | input [63:0] data_out; | |
188 | output ack_busy; | |
189 | ||
190 | ||
191 | ||
192 | ||
193 | // Local signals | |
194 | ||
195 | ||
196 | ||
197 | ||
198 | //wire int_buf_rd; | |
199 | //wire int_buf_wr; | |
200 | //wire int_buf_vld; | |
201 | //wire int_buf_vld_next; | |
202 | //wire [6:0] int_buf_in; | |
203 | //wire [6:0] int_buf; | |
204 | //wire [3:0] int_buf_vec; | |
205 | ||
206 | //wire int_last_rd; | |
207 | ||
208 | ||
209 | //////////////////////////////////////////////////////////////////////// | |
210 | // Code starts here | |
211 | //////////////////////////////////////////////////////////////////////// | |
212 | /************************************************************ | |
213 | * Inbound Data | |
214 | ************************************************************/ | |
215 | /*rst_ucbbusin4_ctl auto_template ( .scan_in(rst_ucbbusin4_ctl_scanin), | |
216 | .vld(ncu_rst_vld), | |
217 | .data(ncu_rst_data[3:0]), | |
218 | .stall(rst_ncu_stall), | |
219 | .stall_a1(rst_ncu_stall_a1) ); | |
220 | */ | |
221 | rst_ucbbusin4_ctl rst_ucbbusin4_ctl (/*autoinst*/ | |
222 | // Outputs | |
223 | .stall(rst_ncu_stall), // Templated | |
224 | .indata_buf_vld(indata_buf_vld), | |
225 | .indata_buf(indata_buf[127:0]), | |
226 | // Inputs | |
227 | .scan_in(rst_ucbbusin4_ctl_scanin), | |
228 | .scan_out(rst_ucbbusin4_ctl_scanout), | |
229 | .iol2clk(iol2clk), | |
230 | .ucb_clr_io_(ucb_clr_io_), //BP 8-19-05 | |
231 | .tcu_pce_ov(tcu_pce_ov), | |
232 | .tcu_clk_stop(tcu_clk_stop), | |
233 | .tcu_aclk (tcu_aclk ), | |
234 | .tcu_bclk (tcu_bclk ), | |
235 | .tcu_scan_en (tcu_scan_en ), | |
236 | .vld(ncu_rst_vld), // Templated | |
237 | .data(ncu_rst_data[3:0]), // Templated | |
238 | .stall_a1(rst_ncu_stall_a1)); // Templated | |
239 | ||
240 | /************************************************************ | |
241 | * Decode inbound packet type | |
242 | ************************************************************/ | |
243 | assign read_pending = (indata_buf[3:0] == 4'b0100) & indata_buf_vld; | |
244 | ||
245 | assign write_pending = (indata_buf[3:0] == 4'b0101) & indata_buf_vld; | |
246 | ||
247 | assign rst_ncu_stall_a1 = (read_pending | write_pending) & buf_full; | |
248 | ||
249 | /************************************************************ | |
250 | * Inbound buffer | |
251 | ************************************************************/ | |
252 | // Head pointer | |
253 | assign rd_buf = req_acpted; | |
254 | assign buf_head_next[1:0] = rd_buf ? {buf_head[0],buf_head[1]} : buf_head[1:0]; | |
255 | ||
256 | assign buf_head_next0_ = ~buf_head_next[0] ; | |
257 | assign buf_head[0] = ~buf_head0_ ; | |
258 | rst_ucbflow_ctl_msff_ctl_macro__clr__1__width_1 buf_head_ff0 | |
259 | ( | |
260 | .scan_in(buf_head_ff0_scanin), | |
261 | .scan_out(buf_head_ff0_scanout), | |
262 | .dout (buf_head0_), | |
263 | .clr_ (ucb_clr_io_), //BP 8-19-05 | |
264 | .l1clk (l1clk), | |
265 | .din (buf_head_next0_), | |
266 | .siclk(siclk), | |
267 | .soclk(soclk) | |
268 | ); | |
269 | ||
270 | rst_ucbflow_ctl_msff_ctl_macro__clr__1__width_1 buf_head_ff1 | |
271 | ( | |
272 | .scan_in(buf_head_ff1_scanin), | |
273 | .scan_out(buf_head_ff1_scanout), | |
274 | .dout (buf_head[1]), | |
275 | .clr_ (ucb_clr_io_), //BP 8-19-05 | |
276 | .l1clk (l1clk), | |
277 | .din (buf_head_next[1]), | |
278 | .siclk(siclk), | |
279 | .soclk(soclk) | |
280 | ); | |
281 | ||
282 | // Tail pointer | |
283 | assign wr_buf = (read_pending | write_pending) & ~buf_full; | |
284 | ||
285 | assign buf_tail_next[1:0] = wr_buf ? {buf_tail[0], buf_tail[1]} : buf_tail[1:0]; | |
286 | ||
287 | assign buf_tail_next0_ = ~buf_tail_next[0]; | |
288 | assign buf_tail[0] = ~buf_tail0_ ; | |
289 | rst_ucbflow_ctl_msff_ctl_macro__clr__1__width_1 buf_tail_ff0 | |
290 | ( | |
291 | .scan_in(buf_tail_ff0_scanin), | |
292 | .scan_out(buf_tail_ff0_scanout), | |
293 | .dout (buf_tail0_), | |
294 | .clr_ (ucb_clr_io_), //BP 8-19-05 | |
295 | .l1clk (l1clk), | |
296 | .din (buf_tail_next0_), | |
297 | .siclk(siclk), | |
298 | .soclk(soclk) | |
299 | ); | |
300 | ||
301 | rst_ucbflow_ctl_msff_ctl_macro__clr__1__width_1 buf_tail_ff1 | |
302 | ( | |
303 | .scan_in(buf_tail_ff1_scanin), | |
304 | .scan_out(buf_tail_ff1_scanout), | |
305 | .dout (buf_tail[1]), | |
306 | .clr_ (ucb_clr_io_), //BP 8-19-05 | |
307 | .l1clk (l1clk), | |
308 | .din (buf_tail_next[1]), | |
309 | .siclk(siclk), | |
310 | .soclk(soclk) | |
311 | ); | |
312 | ||
313 | // Buffer full | |
314 | assign buf_full_next = (buf_head_next[1:0] == buf_tail_next[1:0]) & wr_buf; | |
315 | rst_ucbflow_ctl_msff_ctl_macro__clr__1__en_1__width_1 buf_full_ff | |
316 | ( | |
317 | .scan_in(buf_full_ff_scanin), | |
318 | .scan_out(buf_full_ff_scanout), | |
319 | .dout (buf_full), | |
320 | .clr_ (ucb_clr_io_), //BP 8-19-05 | |
321 | .l1clk (l1clk), | |
322 | .en (rd_buf|wr_buf), | |
323 | .din (buf_full_next), | |
324 | .siclk(siclk), | |
325 | .soclk(soclk) | |
326 | ); | |
327 | ||
328 | // Buffer empty | |
329 | assign buf_empty_next = ((buf_head_next[1:0] == buf_tail_next[1:0]) & rd_buf) ; | |
330 | assign buf_empty_next_ = ~buf_empty_next ; | |
331 | assign buf_empty = ~buf_empty_ ; | |
332 | rst_ucbflow_ctl_msff_ctl_macro__clr__1__en_1__width_1 buf_empty_ff | |
333 | ( | |
334 | .scan_in(buf_empty_ff_scanin), | |
335 | .scan_out(buf_empty_ff_scanout), | |
336 | .dout (buf_empty_), | |
337 | .clr_ (ucb_clr_io_), //BP 8-19-05 | |
338 | .l1clk (l1clk), | |
339 | .en (rd_buf|wr_buf), | |
340 | .din (buf_empty_next_), | |
341 | .siclk(siclk), | |
342 | .soclk(soclk) | |
343 | ); | |
344 | ||
345 | assign { req_in[116:53], | |
346 | unconnected_rsvd[8:0], | |
347 | req_in[52:0] } = { indata_buf[127:64], | |
348 | indata_buf[63:55], | |
349 | indata_buf[54:15], | |
350 | indata_buf[14:12], | |
351 | indata_buf[11:10], | |
352 | indata_buf[9:4], | |
353 | write_pending, | |
354 | read_pending }; | |
355 | ||
356 | // Buffer 0 | |
357 | assign buf0_en = buf_tail[0] & wr_buf; | |
358 | rst_ucbflow_ctl_msff_ctl_macro__clr__1__en_1__width_117 buf0_ff | |
359 | ( | |
360 | .scan_in(buf0_ff_scanin), | |
361 | .scan_out(buf0_ff_scanout), | |
362 | .dout (buf0[116:0]), | |
363 | .clr_ (ucb_clr_io_), //BP 8-19-05 | |
364 | .l1clk (l1clk), | |
365 | .en (buf0_en), | |
366 | .din (req_in[116:0]), | |
367 | .siclk(siclk), | |
368 | .soclk(soclk) | |
369 | ); | |
370 | // Buffer 1 | |
371 | assign buf1_en = buf_tail[1] & wr_buf; | |
372 | rst_ucbflow_ctl_msff_ctl_macro__clr__1__en_1__width_117 buf1_ff | |
373 | ( | |
374 | .scan_in(buf1_ff_scanin), | |
375 | .scan_out(buf1_ff_scanout), | |
376 | .dout (buf1[116:0]), | |
377 | .clr_ (ucb_clr_io_), //BP 8-19-05 | |
378 | .l1clk (l1clk), | |
379 | .en (buf1_en), | |
380 | .din (req_in[116:0]), | |
381 | .siclk(siclk), | |
382 | .soclk(soclk) | |
383 | ); | |
384 | ||
385 | assign req_out[116:0] = buf_head[0] ? buf0[116:0] : | |
386 | buf_head[1] ? buf1[116:0] : 117'b0; | |
387 | ||
388 | ||
389 | /************************************************************ | |
390 | * Inbound interface to local unit | |
391 | ************************************************************/ | |
392 | assign {data_in[63:0], | |
393 | addr_in[39:0], | |
394 | unconnected_size_in[2:0], | |
395 | buf_id_in[1:0], | |
396 | thr_id_in[5:0], | |
397 | wr_req_vld_nq, | |
398 | rd_req_vld_nq} = req_out[116:0]; | |
399 | ||
400 | assign rd_req_vld = rd_req_vld_nq & ~buf_empty; | |
401 | assign wr_req_vld = wr_req_vld_nq & ~buf_empty; | |
402 | ||
403 | ||
404 | /************************************************************ | |
405 | * Outbound Ack/Nack | |
406 | ************************************************************/ | |
407 | assign ack_buf_wr = rd_ack_vld | rd_nack_vld; | |
408 | ||
409 | assign ack_buf_vld_next = ack_buf_wr ? 1'b1 : | |
410 | ack_buf_rd ? 1'b0 : ack_buf_vld; | |
411 | ||
412 | rst_ucbflow_ctl_msff_ctl_macro__clr__1__width_1 ack_buf_vld_ff | |
413 | ( | |
414 | .scan_in(ack_buf_vld_ff_scanin), | |
415 | .scan_out(ack_buf_vld_ff_scanout), | |
416 | .dout (ack_buf_vld), | |
417 | .clr_ (ucb_clr_io_), //BP 8-19-05 | |
418 | .l1clk (l1clk), | |
419 | .din (ack_buf_vld_next), | |
420 | .siclk(siclk), | |
421 | .soclk(soclk) | |
422 | ); | |
423 | ||
424 | rst_ucbflow_ctl_msff_ctl_macro__clr__1__en_1__width_1 ack_buf_is_nack_ff | |
425 | ( | |
426 | .scan_in(ack_buf_is_nack_ff_scanin), | |
427 | .scan_out(ack_buf_is_nack_ff_scanout), | |
428 | .dout (ack_buf_is_nack), | |
429 | .clr_ (ucb_clr_io_), //BP 8-19-05 | |
430 | .l1clk (l1clk), | |
431 | .en (ack_buf_wr), | |
432 | .din (rd_nack_vld), | |
433 | .siclk(siclk), | |
434 | .soclk(soclk) | |
435 | ); | |
436 | ||
437 | assign ack_typ_out[3:0] = rd_ack_vld ? 4'b0001: //UCB_READ_ACK | |
438 | 4'b0000; //UCB_READ_NACK | |
439 | ||
440 | assign ack_buf_in[75:0] = { data_out[63:0], | |
441 | buf_id_out[1:0], | |
442 | thr_id_out[5:0], | |
443 | ack_typ_out[3:0] }; | |
444 | ||
445 | rst_ucbflow_ctl_msff_ctl_macro__clr__1__en_1__width_76 ack_buf_ff | |
446 | ( | |
447 | .scan_in(ack_buf_ff_scanin), | |
448 | .scan_out(ack_buf_ff_scanout), | |
449 | .dout (ack_buf[75:0]), | |
450 | .clr_ (ucb_clr_io_), //BP 8-19-05 | |
451 | .l1clk (l1clk), | |
452 | .en (ack_buf_wr), | |
453 | .din (ack_buf_in[75:0]), | |
454 | .siclk(siclk), | |
455 | .soclk(soclk) | |
456 | ); | |
457 | ||
458 | assign ack_buf_vec[31:0] = ack_buf_is_nack ? {16'h0000,16'hffff} : {32'hffff_ffff} ; | |
459 | ||
460 | assign ack_busy = ack_buf_vld; | |
461 | ||
462 | assign ack_buf_rd = ~outdata_buf_busy & ack_buf_vld ; | |
463 | ||
464 | assign outdata_buf_wr = ack_buf_rd ; | |
465 | ||
466 | assign outdata_buf_in[127:0] = {ack_buf[75:12], //payload 64bit | |
467 | 9'b0, //reserved [63:55] | |
468 | 40'h00_0000_0000, //40bit addr [54:15] | |
469 | 3'b000, //size [14:12] | |
470 | ack_buf[11:10], //buf_id 2bit | |
471 | ack_buf[9:4], //thr_id 6bit | |
472 | ack_buf[3:0]}; //type 4bit | |
473 | ||
474 | assign outdata_vec_in[31:0] = ack_buf_vec[31:0] ; | |
475 | ||
476 | ||
477 | /*rst_ucbbusout4_ctl auto_template ( | |
478 | .vld(rst_ncu_vld), | |
479 | .data(rst_ncu_data[3:0]), | |
480 | .stall(ncu_rst_stall), | |
481 | .outdata_vec_in(outdata_vec_in[31:0]) ); | |
482 | */ | |
483 | rst_ucbbusout4_ctl rst_ucbbusout4_ctl (/*autoinst*/ | |
484 | // Outputs | |
485 | .vld(rst_ncu_vld), // Templated | |
486 | .data(rst_ncu_data[3:0]), // Templated | |
487 | .outdata_buf_busy(outdata_buf_busy), | |
488 | // Inputs | |
489 | .scan_in(rst_ucbbusout4_ctl_scanin), | |
490 | .scan_out(rst_ucbbusout4_ctl_scanout), | |
491 | .iol2clk(iol2clk), | |
492 | .ucb_clr_io_(ucb_clr_io_), //BP 8-19-05 | |
493 | .tcu_pce_ov(tcu_pce_ov), | |
494 | .tcu_clk_stop(tcu_clk_stop), | |
495 | .tcu_aclk (tcu_aclk ), | |
496 | .tcu_bclk (tcu_bclk ), | |
497 | .tcu_scan_en (tcu_scan_en ), | |
498 | .stall(ncu_rst_stall), // Templated | |
499 | .outdata_buf_in(outdata_buf_in[127:0]), | |
500 | .outdata_vec_in(outdata_vec_in[31:0]), // Templated | |
501 | .outdata_buf_wr(outdata_buf_wr)); | |
502 | ||
503 | ||
504 | /**** adding clock header ****/ | |
505 | rst_ucbflow_ctl_l1clkhdr_ctl_macro clkgen ( | |
506 | .l2clk (iol2clk), | |
507 | .l1en (1'b1), | |
508 | // .pce_ov (1'b0 ), | |
509 | .stop (1'b0 ), | |
510 | // .se (1'b0 ), | |
511 | .l1clk (l1clk), | |
512 | .pce_ov(pce_ov), | |
513 | .se(se) | |
514 | ); | |
515 | // grep "Number of cells:" rst_*_l/*/scf/dc/rpt/syn_area.rpt | |
516 | // Number of cells/450 = spare gate macros | |
517 | // rst_ucbflow_l/rst_ucbflow_ctl/scf/dc/rpt/syn_area.rpt:Num:2555 /450=6 | |
518 | ||
519 | rst_ucbflow_ctl_spare_ctl_macro__num_6 spares ( | |
520 | .scan_in(spares_scanin), | |
521 | .scan_out(spares_scanout), | |
522 | .l1clk (l1clk), | |
523 | .siclk(siclk), | |
524 | .soclk(soclk) ); | |
525 | ||
526 | ||
527 | /*** BP 8-22-05 copy scan force similar to rst_fsm_ctl ***/ | |
528 | assign ucb_ctl_scanout | |
529 | = tcu_rst_scan_mode ? scan_out : 1'b0; | |
530 | assign tcu_aclk = tcu_rst_scan_mode ? rst_aclk : 1'b0; | |
531 | assign tcu_bclk = tcu_rst_scan_mode ? rst_bclk : 1'b0; | |
532 | assign tcu_scan_en = tcu_rst_scan_mode ? rst_scan_en : 1'b0; | |
533 | assign tcu_clk_stop = tcu_rst_scan_mode ? rst_clk_stop : 1'b0; | |
534 | ||
535 | // scan renames | |
536 | assign se = tcu_scan_en; | |
537 | // end scan | |
538 | ||
539 | ||
540 | ||
541 | /*** building tcu port ***/ | |
542 | assign siclk = tcu_aclk ; | |
543 | assign soclk = tcu_bclk ; | |
544 | assign pce_ov = tcu_pce_ov; | |
545 | assign stop = tcu_clk_stop; | |
546 | ||
547 | // fixscan start: | |
548 | assign rst_ucbbusin4_ctl_scanin = scan_in ; | |
549 | assign buf_head_ff0_scanin = rst_ucbbusin4_ctl_scanout; | |
550 | assign buf_head_ff1_scanin = buf_head_ff0_scanout ; | |
551 | assign buf_tail_ff0_scanin = buf_head_ff1_scanout ; | |
552 | assign buf_tail_ff1_scanin = buf_tail_ff0_scanout ; | |
553 | assign buf_full_ff_scanin = buf_tail_ff1_scanout ; | |
554 | assign buf_empty_ff_scanin = buf_full_ff_scanout ; | |
555 | assign buf0_ff_scanin = buf_empty_ff_scanout ; | |
556 | assign buf1_ff_scanin = buf0_ff_scanout ; | |
557 | assign ack_buf_vld_ff_scanin = buf1_ff_scanout ; | |
558 | assign ack_buf_is_nack_ff_scanin = ack_buf_vld_ff_scanout ; | |
559 | assign ack_buf_ff_scanin = ack_buf_is_nack_ff_scanout; | |
560 | assign rst_ucbbusout4_ctl_scanin = ack_buf_ff_scanout ; | |
561 | assign spares_scanin = rst_ucbbusout4_ctl_scanout; | |
562 | //assign scan_out = spares_scanout ; | |
563 | assign scan_out = spares_scanout ; | |
564 | // fixscan end: | |
565 | endmodule // ucb_flow_rst | |
566 | ||
567 | // verilog-library-directories:(".") | |
568 | ||
569 | ||
570 | ||
571 | ||
572 | // any PARAMS parms go into naming of macro | |
573 | ||
574 | module rst_ucbflow_ctl_msff_ctl_macro__clr__1__en_1__width_1 ( | |
575 | din, | |
576 | en, | |
577 | clr_, | |
578 | l1clk, | |
579 | scan_in, | |
580 | siclk, | |
581 | soclk, | |
582 | dout, | |
583 | scan_out); | |
584 | wire [0:0] fdin; | |
585 | ||
586 | input [0:0] din; | |
587 | input en; | |
588 | input clr_; | |
589 | input l1clk; | |
590 | input scan_in; | |
591 | ||
592 | ||
593 | input siclk; | |
594 | input soclk; | |
595 | ||
596 | output [0:0] dout; | |
597 | output scan_out; | |
598 | assign fdin[0:0] = (din[0:0] & {1{en}} & ~{1{(~clr_)}}) | (dout[0:0] & ~{1{en}} & ~{1{(~clr_)}}); | |
599 | ||
600 | ||
601 | ||
602 | ||
603 | ||
604 | ||
605 | dff #(1) d0_0 ( | |
606 | .l1clk(l1clk), | |
607 | .siclk(siclk), | |
608 | .soclk(soclk), | |
609 | .d(fdin[0:0]), | |
610 | .si(scan_in), | |
611 | .so(scan_out), | |
612 | .q(dout[0:0]) | |
613 | ); | |
614 | ||
615 | ||
616 | ||
617 | ||
618 | ||
619 | ||
620 | ||
621 | ||
622 | ||
623 | ||
624 | ||
625 | ||
626 | endmodule | |
627 | ||
628 | ||
629 | ||
630 | ||
631 | ||
632 | ||
633 | ||
634 | ||
635 | ||
636 | ||
637 | ||
638 | ||
639 | ||
640 | // any PARAMS parms go into naming of macro | |
641 | ||
642 | module rst_ucbflow_ctl_msff_ctl_macro__clr__1__en_1__width_4 ( | |
643 | din, | |
644 | en, | |
645 | clr_, | |
646 | l1clk, | |
647 | scan_in, | |
648 | siclk, | |
649 | soclk, | |
650 | dout, | |
651 | scan_out); | |
652 | wire [3:0] fdin; | |
653 | wire [2:0] so; | |
654 | ||
655 | input [3:0] din; | |
656 | input en; | |
657 | input clr_; | |
658 | input l1clk; | |
659 | input scan_in; | |
660 | ||
661 | ||
662 | input siclk; | |
663 | input soclk; | |
664 | ||
665 | output [3:0] dout; | |
666 | output scan_out; | |
667 | assign fdin[3:0] = (din[3:0] & {4{en}} & ~{4{(~clr_)}}) | (dout[3:0] & ~{4{en}} & ~{4{(~clr_)}}); | |
668 | ||
669 | ||
670 | ||
671 | ||
672 | ||
673 | ||
674 | dff #(4) d0_0 ( | |
675 | .l1clk(l1clk), | |
676 | .siclk(siclk), | |
677 | .soclk(soclk), | |
678 | .d(fdin[3:0]), | |
679 | .si({scan_in,so[2:0]}), | |
680 | .so({so[2:0],scan_out}), | |
681 | .q(dout[3:0]) | |
682 | ); | |
683 | ||
684 | ||
685 | ||
686 | ||
687 | ||
688 | ||
689 | ||
690 | ||
691 | ||
692 | ||
693 | ||
694 | ||
695 | endmodule | |
696 | ||
697 | ||
698 | ||
699 | ||
700 | ||
701 | ||
702 | ||
703 | ||
704 | ||
705 | ||
706 | ||
707 | ||
708 | ||
709 | // any PARAMS parms go into naming of macro | |
710 | ||
711 | module rst_ucbflow_ctl_msff_ctl_macro__clr__1__width_1 ( | |
712 | din, | |
713 | clr_, | |
714 | l1clk, | |
715 | scan_in, | |
716 | siclk, | |
717 | soclk, | |
718 | dout, | |
719 | scan_out); | |
720 | wire [0:0] fdin; | |
721 | ||
722 | input [0:0] din; | |
723 | input clr_; | |
724 | input l1clk; | |
725 | input scan_in; | |
726 | ||
727 | ||
728 | input siclk; | |
729 | input soclk; | |
730 | ||
731 | output [0:0] dout; | |
732 | output scan_out; | |
733 | assign fdin[0:0] = din[0:0] & ~{1{(~clr_)}}; | |
734 | ||
735 | ||
736 | ||
737 | ||
738 | ||
739 | ||
740 | dff #(1) d0_0 ( | |
741 | .l1clk(l1clk), | |
742 | .siclk(siclk), | |
743 | .soclk(soclk), | |
744 | .d(fdin[0:0]), | |
745 | .si(scan_in), | |
746 | .so(scan_out), | |
747 | .q(dout[0:0]) | |
748 | ); | |
749 | ||
750 | ||
751 | ||
752 | ||
753 | ||
754 | ||
755 | ||
756 | ||
757 | ||
758 | ||
759 | ||
760 | ||
761 | endmodule | |
762 | ||
763 | ||
764 | ||
765 | ||
766 | ||
767 | ||
768 | ||
769 | ||
770 | ||
771 | ||
772 | ||
773 | ||
774 | ||
775 | // any PARAMS parms go into naming of macro | |
776 | ||
777 | module rst_ucbflow_ctl_msff_ctl_macro__clr__1__en_1__width_32 ( | |
778 | din, | |
779 | en, | |
780 | clr_, | |
781 | l1clk, | |
782 | scan_in, | |
783 | siclk, | |
784 | soclk, | |
785 | dout, | |
786 | scan_out); | |
787 | wire [31:0] fdin; | |
788 | wire [30:0] so; | |
789 | ||
790 | input [31:0] din; | |
791 | input en; | |
792 | input clr_; | |
793 | input l1clk; | |
794 | input scan_in; | |
795 | ||
796 | ||
797 | input siclk; | |
798 | input soclk; | |
799 | ||
800 | output [31:0] dout; | |
801 | output scan_out; | |
802 | assign fdin[31:0] = (din[31:0] & {32{en}} & ~{32{(~clr_)}}) | (dout[31:0] & ~{32{en}} & ~{32{(~clr_)}}); | |
803 | ||
804 | ||
805 | ||
806 | ||
807 | ||
808 | ||
809 | dff #(32) d0_0 ( | |
810 | .l1clk(l1clk), | |
811 | .siclk(siclk), | |
812 | .soclk(soclk), | |
813 | .d(fdin[31:0]), | |
814 | .si({scan_in,so[30:0]}), | |
815 | .so({so[30:0],scan_out}), | |
816 | .q(dout[31:0]) | |
817 | ); | |
818 | ||
819 | ||
820 | ||
821 | ||
822 | ||
823 | ||
824 | ||
825 | ||
826 | ||
827 | ||
828 | ||
829 | ||
830 | endmodule | |
831 | ||
832 | ||
833 | ||
834 | ||
835 | ||
836 | ||
837 | ||
838 | ||
839 | ||
840 | ||
841 | ||
842 | ||
843 | ||
844 | // any PARAMS parms go into naming of macro | |
845 | ||
846 | module rst_ucbflow_ctl_msff_ctl_macro__clr__1__en_1__width_128 ( | |
847 | din, | |
848 | en, | |
849 | clr_, | |
850 | l1clk, | |
851 | scan_in, | |
852 | siclk, | |
853 | soclk, | |
854 | dout, | |
855 | scan_out); | |
856 | wire [127:0] fdin; | |
857 | wire [126:0] so; | |
858 | ||
859 | input [127:0] din; | |
860 | input en; | |
861 | input clr_; | |
862 | input l1clk; | |
863 | input scan_in; | |
864 | ||
865 | ||
866 | input siclk; | |
867 | input soclk; | |
868 | ||
869 | output [127:0] dout; | |
870 | output scan_out; | |
871 | assign fdin[127:0] = (din[127:0] & {128{en}} & ~{128{(~clr_)}}) | (dout[127:0] & ~{128{en}} & ~{128{(~clr_)}}); | |
872 | ||
873 | ||
874 | ||
875 | ||
876 | ||
877 | ||
878 | dff #(128) d0_0 ( | |
879 | .l1clk(l1clk), | |
880 | .siclk(siclk), | |
881 | .soclk(soclk), | |
882 | .d(fdin[127:0]), | |
883 | .si({scan_in,so[126:0]}), | |
884 | .so({so[126:0],scan_out}), | |
885 | .q(dout[127:0]) | |
886 | ); | |
887 | ||
888 | ||
889 | ||
890 | ||
891 | ||
892 | ||
893 | ||
894 | ||
895 | ||
896 | ||
897 | ||
898 | ||
899 | endmodule | |
900 | ||
901 | ||
902 | ||
903 | ||
904 | ||
905 | ||
906 | ||
907 | ||
908 | ||
909 | ||
910 | ||
911 | ||
912 | ||
913 | // any PARAMS parms go into naming of macro | |
914 | ||
915 | module rst_ucbflow_ctl_l1clkhdr_ctl_macro ( | |
916 | l2clk, | |
917 | l1en, | |
918 | pce_ov, | |
919 | stop, | |
920 | se, | |
921 | l1clk); | |
922 | ||
923 | ||
924 | input l2clk; | |
925 | input l1en; | |
926 | input pce_ov; | |
927 | input stop; | |
928 | input se; | |
929 | output l1clk; | |
930 | ||
931 | ||
932 | ||
933 | ||
934 | ||
935 | cl_sc1_l1hdr_8x c_0 ( | |
936 | ||
937 | ||
938 | .l2clk(l2clk), | |
939 | .pce(l1en), | |
940 | .l1clk(l1clk), | |
941 | .se(se), | |
942 | .pce_ov(pce_ov), | |
943 | .stop(stop) | |
944 | ); | |
945 | ||
946 | ||
947 | ||
948 | endmodule | |
949 | ||
950 | ||
951 | ||
952 | ||
953 | ||
954 | ||
955 | ||
956 | ||
957 | ||
958 | ||
959 | ||
960 | ||
961 | ||
962 | // any PARAMS parms go into naming of macro | |
963 | ||
964 | module rst_ucbflow_ctl_msff_ctl_macro__clr__1__en_1__width_117 ( | |
965 | din, | |
966 | en, | |
967 | clr_, | |
968 | l1clk, | |
969 | scan_in, | |
970 | siclk, | |
971 | soclk, | |
972 | dout, | |
973 | scan_out); | |
974 | wire [116:0] fdin; | |
975 | wire [115:0] so; | |
976 | ||
977 | input [116:0] din; | |
978 | input en; | |
979 | input clr_; | |
980 | input l1clk; | |
981 | input scan_in; | |
982 | ||
983 | ||
984 | input siclk; | |
985 | input soclk; | |
986 | ||
987 | output [116:0] dout; | |
988 | output scan_out; | |
989 | assign fdin[116:0] = (din[116:0] & {117{en}} & ~{117{(~clr_)}}) | (dout[116:0] & ~{117{en}} & ~{117{(~clr_)}}); | |
990 | ||
991 | ||
992 | ||
993 | ||
994 | ||
995 | ||
996 | dff #(117) d0_0 ( | |
997 | .l1clk(l1clk), | |
998 | .siclk(siclk), | |
999 | .soclk(soclk), | |
1000 | .d(fdin[116:0]), | |
1001 | .si({scan_in,so[115:0]}), | |
1002 | .so({so[115:0],scan_out}), | |
1003 | .q(dout[116:0]) | |
1004 | ); | |
1005 | ||
1006 | ||
1007 | ||
1008 | ||
1009 | ||
1010 | ||
1011 | ||
1012 | ||
1013 | ||
1014 | ||
1015 | ||
1016 | ||
1017 | endmodule | |
1018 | ||
1019 | ||
1020 | ||
1021 | ||
1022 | ||
1023 | ||
1024 | ||
1025 | ||
1026 | ||
1027 | ||
1028 | ||
1029 | ||
1030 | ||
1031 | // any PARAMS parms go into naming of macro | |
1032 | ||
1033 | module rst_ucbflow_ctl_msff_ctl_macro__clr__1__en_1__width_76 ( | |
1034 | din, | |
1035 | en, | |
1036 | clr_, | |
1037 | l1clk, | |
1038 | scan_in, | |
1039 | siclk, | |
1040 | soclk, | |
1041 | dout, | |
1042 | scan_out); | |
1043 | wire [75:0] fdin; | |
1044 | wire [74:0] so; | |
1045 | ||
1046 | input [75:0] din; | |
1047 | input en; | |
1048 | input clr_; | |
1049 | input l1clk; | |
1050 | input scan_in; | |
1051 | ||
1052 | ||
1053 | input siclk; | |
1054 | input soclk; | |
1055 | ||
1056 | output [75:0] dout; | |
1057 | output scan_out; | |
1058 | assign fdin[75:0] = (din[75:0] & {76{en}} & ~{76{(~clr_)}}) | (dout[75:0] & ~{76{en}} & ~{76{(~clr_)}}); | |
1059 | ||
1060 | ||
1061 | ||
1062 | ||
1063 | ||
1064 | ||
1065 | dff #(76) d0_0 ( | |
1066 | .l1clk(l1clk), | |
1067 | .siclk(siclk), | |
1068 | .soclk(soclk), | |
1069 | .d(fdin[75:0]), | |
1070 | .si({scan_in,so[74:0]}), | |
1071 | .so({so[74:0],scan_out}), | |
1072 | .q(dout[75:0]) | |
1073 | ); | |
1074 | ||
1075 | ||
1076 | ||
1077 | ||
1078 | ||
1079 | ||
1080 | ||
1081 | ||
1082 | ||
1083 | ||
1084 | ||
1085 | ||
1086 | endmodule | |
1087 | ||
1088 | ||
1089 | ||
1090 | ||
1091 | ||
1092 | ||
1093 | // any PARAMS parms go into naming of macro | |
1094 | ||
1095 | module rst_ucbflow_ctl_msff_ctl_macro__clr__1__width_32 ( | |
1096 | din, | |
1097 | clr_, | |
1098 | l1clk, | |
1099 | scan_in, | |
1100 | siclk, | |
1101 | soclk, | |
1102 | dout, | |
1103 | scan_out); | |
1104 | wire [31:0] fdin; | |
1105 | wire [30:0] so; | |
1106 | ||
1107 | input [31:0] din; | |
1108 | input clr_; | |
1109 | input l1clk; | |
1110 | input scan_in; | |
1111 | ||
1112 | ||
1113 | input siclk; | |
1114 | input soclk; | |
1115 | ||
1116 | output [31:0] dout; | |
1117 | output scan_out; | |
1118 | assign fdin[31:0] = din[31:0] & ~{32{(~clr_)}}; | |
1119 | ||
1120 | ||
1121 | ||
1122 | ||
1123 | ||
1124 | ||
1125 | dff #(32) d0_0 ( | |
1126 | .l1clk(l1clk), | |
1127 | .siclk(siclk), | |
1128 | .soclk(soclk), | |
1129 | .d(fdin[31:0]), | |
1130 | .si({scan_in,so[30:0]}), | |
1131 | .so({so[30:0],scan_out}), | |
1132 | .q(dout[31:0]) | |
1133 | ); | |
1134 | ||
1135 | ||
1136 | ||
1137 | ||
1138 | ||
1139 | ||
1140 | ||
1141 | ||
1142 | ||
1143 | ||
1144 | ||
1145 | ||
1146 | endmodule | |
1147 | ||
1148 | ||
1149 | ||
1150 | ||
1151 | ||
1152 | ||
1153 | ||
1154 | ||
1155 | ||
1156 | ||
1157 | ||
1158 | ||
1159 | ||
1160 | // any PARAMS parms go into naming of macro | |
1161 | ||
1162 | module rst_ucbflow_ctl_msff_ctl_macro__clr__1__width_128 ( | |
1163 | din, | |
1164 | clr_, | |
1165 | l1clk, | |
1166 | scan_in, | |
1167 | siclk, | |
1168 | soclk, | |
1169 | dout, | |
1170 | scan_out); | |
1171 | wire [127:0] fdin; | |
1172 | wire [126:0] so; | |
1173 | ||
1174 | input [127:0] din; | |
1175 | input clr_; | |
1176 | input l1clk; | |
1177 | input scan_in; | |
1178 | ||
1179 | ||
1180 | input siclk; | |
1181 | input soclk; | |
1182 | ||
1183 | output [127:0] dout; | |
1184 | output scan_out; | |
1185 | assign fdin[127:0] = din[127:0] & ~{128{(~clr_)}}; | |
1186 | ||
1187 | ||
1188 | ||
1189 | ||
1190 | ||
1191 | ||
1192 | dff #(128) d0_0 ( | |
1193 | .l1clk(l1clk), | |
1194 | .siclk(siclk), | |
1195 | .soclk(soclk), | |
1196 | .d(fdin[127:0]), | |
1197 | .si({scan_in,so[126:0]}), | |
1198 | .so({so[126:0],scan_out}), | |
1199 | .q(dout[127:0]) | |
1200 | ); | |
1201 | ||
1202 | ||
1203 | ||
1204 | ||
1205 | ||
1206 | ||
1207 | ||
1208 | ||
1209 | ||
1210 | ||
1211 | ||
1212 | ||
1213 | endmodule | |
1214 | ||
1215 | ||
1216 | ||
1217 | ||
1218 | ||
1219 | ||
1220 | ||
1221 | ||
1222 | ||
1223 | // Description: Spare gate macro for control blocks | |
1224 | // | |
1225 | // Param num controls the number of times the macro is added | |
1226 | // flops=0 can be used to use only combination spare logic | |
1227 | ||
1228 | ||
1229 | module rst_ucbflow_ctl_spare_ctl_macro__num_6 ( | |
1230 | l1clk, | |
1231 | scan_in, | |
1232 | siclk, | |
1233 | soclk, | |
1234 | scan_out); | |
1235 | wire si_0; | |
1236 | wire so_0; | |
1237 | wire spare0_flop_unused; | |
1238 | wire spare0_buf_32x_unused; | |
1239 | wire spare0_nand3_8x_unused; | |
1240 | wire spare0_inv_8x_unused; | |
1241 | wire spare0_aoi22_4x_unused; | |
1242 | wire spare0_buf_8x_unused; | |
1243 | wire spare0_oai22_4x_unused; | |
1244 | wire spare0_inv_16x_unused; | |
1245 | wire spare0_nand2_16x_unused; | |
1246 | wire spare0_nor3_4x_unused; | |
1247 | wire spare0_nand2_8x_unused; | |
1248 | wire spare0_buf_16x_unused; | |
1249 | wire spare0_nor2_16x_unused; | |
1250 | wire spare0_inv_32x_unused; | |
1251 | wire si_1; | |
1252 | wire so_1; | |
1253 | wire spare1_flop_unused; | |
1254 | wire spare1_buf_32x_unused; | |
1255 | wire spare1_nand3_8x_unused; | |
1256 | wire spare1_inv_8x_unused; | |
1257 | wire spare1_aoi22_4x_unused; | |
1258 | wire spare1_buf_8x_unused; | |
1259 | wire spare1_oai22_4x_unused; | |
1260 | wire spare1_inv_16x_unused; | |
1261 | wire spare1_nand2_16x_unused; | |
1262 | wire spare1_nor3_4x_unused; | |
1263 | wire spare1_nand2_8x_unused; | |
1264 | wire spare1_buf_16x_unused; | |
1265 | wire spare1_nor2_16x_unused; | |
1266 | wire spare1_inv_32x_unused; | |
1267 | wire si_2; | |
1268 | wire so_2; | |
1269 | wire spare2_flop_unused; | |
1270 | wire spare2_buf_32x_unused; | |
1271 | wire spare2_nand3_8x_unused; | |
1272 | wire spare2_inv_8x_unused; | |
1273 | wire spare2_aoi22_4x_unused; | |
1274 | wire spare2_buf_8x_unused; | |
1275 | wire spare2_oai22_4x_unused; | |
1276 | wire spare2_inv_16x_unused; | |
1277 | wire spare2_nand2_16x_unused; | |
1278 | wire spare2_nor3_4x_unused; | |
1279 | wire spare2_nand2_8x_unused; | |
1280 | wire spare2_buf_16x_unused; | |
1281 | wire spare2_nor2_16x_unused; | |
1282 | wire spare2_inv_32x_unused; | |
1283 | wire si_3; | |
1284 | wire so_3; | |
1285 | wire spare3_flop_unused; | |
1286 | wire spare3_buf_32x_unused; | |
1287 | wire spare3_nand3_8x_unused; | |
1288 | wire spare3_inv_8x_unused; | |
1289 | wire spare3_aoi22_4x_unused; | |
1290 | wire spare3_buf_8x_unused; | |
1291 | wire spare3_oai22_4x_unused; | |
1292 | wire spare3_inv_16x_unused; | |
1293 | wire spare3_nand2_16x_unused; | |
1294 | wire spare3_nor3_4x_unused; | |
1295 | wire spare3_nand2_8x_unused; | |
1296 | wire spare3_buf_16x_unused; | |
1297 | wire spare3_nor2_16x_unused; | |
1298 | wire spare3_inv_32x_unused; | |
1299 | wire si_4; | |
1300 | wire so_4; | |
1301 | wire spare4_flop_unused; | |
1302 | wire spare4_buf_32x_unused; | |
1303 | wire spare4_nand3_8x_unused; | |
1304 | wire spare4_inv_8x_unused; | |
1305 | wire spare4_aoi22_4x_unused; | |
1306 | wire spare4_buf_8x_unused; | |
1307 | wire spare4_oai22_4x_unused; | |
1308 | wire spare4_inv_16x_unused; | |
1309 | wire spare4_nand2_16x_unused; | |
1310 | wire spare4_nor3_4x_unused; | |
1311 | wire spare4_nand2_8x_unused; | |
1312 | wire spare4_buf_16x_unused; | |
1313 | wire spare4_nor2_16x_unused; | |
1314 | wire spare4_inv_32x_unused; | |
1315 | wire si_5; | |
1316 | wire so_5; | |
1317 | wire spare5_flop_unused; | |
1318 | wire spare5_buf_32x_unused; | |
1319 | wire spare5_nand3_8x_unused; | |
1320 | wire spare5_inv_8x_unused; | |
1321 | wire spare5_aoi22_4x_unused; | |
1322 | wire spare5_buf_8x_unused; | |
1323 | wire spare5_oai22_4x_unused; | |
1324 | wire spare5_inv_16x_unused; | |
1325 | wire spare5_nand2_16x_unused; | |
1326 | wire spare5_nor3_4x_unused; | |
1327 | wire spare5_nand2_8x_unused; | |
1328 | wire spare5_buf_16x_unused; | |
1329 | wire spare5_nor2_16x_unused; | |
1330 | wire spare5_inv_32x_unused; | |
1331 | ||
1332 | ||
1333 | input l1clk; | |
1334 | input scan_in; | |
1335 | input siclk; | |
1336 | input soclk; | |
1337 | output scan_out; | |
1338 | ||
1339 | cl_sc1_msff_8x spare0_flop (.l1clk(l1clk), | |
1340 | .siclk(siclk), | |
1341 | .soclk(soclk), | |
1342 | .si(si_0), | |
1343 | .so(so_0), | |
1344 | .d(1'b0), | |
1345 | .q(spare0_flop_unused)); | |
1346 | assign si_0 = scan_in; | |
1347 | ||
1348 | cl_u1_buf_32x spare0_buf_32x (.in(1'b1), | |
1349 | .out(spare0_buf_32x_unused)); | |
1350 | cl_u1_nand3_8x spare0_nand3_8x (.in0(1'b1), | |
1351 | .in1(1'b1), | |
1352 | .in2(1'b1), | |
1353 | .out(spare0_nand3_8x_unused)); | |
1354 | cl_u1_inv_8x spare0_inv_8x (.in(1'b1), | |
1355 | .out(spare0_inv_8x_unused)); | |
1356 | cl_u1_aoi22_4x spare0_aoi22_4x (.in00(1'b1), | |
1357 | .in01(1'b1), | |
1358 | .in10(1'b1), | |
1359 | .in11(1'b1), | |
1360 | .out(spare0_aoi22_4x_unused)); | |
1361 | cl_u1_buf_8x spare0_buf_8x (.in(1'b1), | |
1362 | .out(spare0_buf_8x_unused)); | |
1363 | cl_u1_oai22_4x spare0_oai22_4x (.in00(1'b1), | |
1364 | .in01(1'b1), | |
1365 | .in10(1'b1), | |
1366 | .in11(1'b1), | |
1367 | .out(spare0_oai22_4x_unused)); | |
1368 | cl_u1_inv_16x spare0_inv_16x (.in(1'b1), | |
1369 | .out(spare0_inv_16x_unused)); | |
1370 | cl_u1_nand2_16x spare0_nand2_16x (.in0(1'b1), | |
1371 | .in1(1'b1), | |
1372 | .out(spare0_nand2_16x_unused)); | |
1373 | cl_u1_nor3_4x spare0_nor3_4x (.in0(1'b0), | |
1374 | .in1(1'b0), | |
1375 | .in2(1'b0), | |
1376 | .out(spare0_nor3_4x_unused)); | |
1377 | cl_u1_nand2_8x spare0_nand2_8x (.in0(1'b1), | |
1378 | .in1(1'b1), | |
1379 | .out(spare0_nand2_8x_unused)); | |
1380 | cl_u1_buf_16x spare0_buf_16x (.in(1'b1), | |
1381 | .out(spare0_buf_16x_unused)); | |
1382 | cl_u1_nor2_16x spare0_nor2_16x (.in0(1'b0), | |
1383 | .in1(1'b0), | |
1384 | .out(spare0_nor2_16x_unused)); | |
1385 | cl_u1_inv_32x spare0_inv_32x (.in(1'b1), | |
1386 | .out(spare0_inv_32x_unused)); | |
1387 | ||
1388 | cl_sc1_msff_8x spare1_flop (.l1clk(l1clk), | |
1389 | .siclk(siclk), | |
1390 | .soclk(soclk), | |
1391 | .si(si_1), | |
1392 | .so(so_1), | |
1393 | .d(1'b0), | |
1394 | .q(spare1_flop_unused)); | |
1395 | assign si_1 = so_0; | |
1396 | ||
1397 | cl_u1_buf_32x spare1_buf_32x (.in(1'b1), | |
1398 | .out(spare1_buf_32x_unused)); | |
1399 | cl_u1_nand3_8x spare1_nand3_8x (.in0(1'b1), | |
1400 | .in1(1'b1), | |
1401 | .in2(1'b1), | |
1402 | .out(spare1_nand3_8x_unused)); | |
1403 | cl_u1_inv_8x spare1_inv_8x (.in(1'b1), | |
1404 | .out(spare1_inv_8x_unused)); | |
1405 | cl_u1_aoi22_4x spare1_aoi22_4x (.in00(1'b1), | |
1406 | .in01(1'b1), | |
1407 | .in10(1'b1), | |
1408 | .in11(1'b1), | |
1409 | .out(spare1_aoi22_4x_unused)); | |
1410 | cl_u1_buf_8x spare1_buf_8x (.in(1'b1), | |
1411 | .out(spare1_buf_8x_unused)); | |
1412 | cl_u1_oai22_4x spare1_oai22_4x (.in00(1'b1), | |
1413 | .in01(1'b1), | |
1414 | .in10(1'b1), | |
1415 | .in11(1'b1), | |
1416 | .out(spare1_oai22_4x_unused)); | |
1417 | cl_u1_inv_16x spare1_inv_16x (.in(1'b1), | |
1418 | .out(spare1_inv_16x_unused)); | |
1419 | cl_u1_nand2_16x spare1_nand2_16x (.in0(1'b1), | |
1420 | .in1(1'b1), | |
1421 | .out(spare1_nand2_16x_unused)); | |
1422 | cl_u1_nor3_4x spare1_nor3_4x (.in0(1'b0), | |
1423 | .in1(1'b0), | |
1424 | .in2(1'b0), | |
1425 | .out(spare1_nor3_4x_unused)); | |
1426 | cl_u1_nand2_8x spare1_nand2_8x (.in0(1'b1), | |
1427 | .in1(1'b1), | |
1428 | .out(spare1_nand2_8x_unused)); | |
1429 | cl_u1_buf_16x spare1_buf_16x (.in(1'b1), | |
1430 | .out(spare1_buf_16x_unused)); | |
1431 | cl_u1_nor2_16x spare1_nor2_16x (.in0(1'b0), | |
1432 | .in1(1'b0), | |
1433 | .out(spare1_nor2_16x_unused)); | |
1434 | cl_u1_inv_32x spare1_inv_32x (.in(1'b1), | |
1435 | .out(spare1_inv_32x_unused)); | |
1436 | ||
1437 | cl_sc1_msff_8x spare2_flop (.l1clk(l1clk), | |
1438 | .siclk(siclk), | |
1439 | .soclk(soclk), | |
1440 | .si(si_2), | |
1441 | .so(so_2), | |
1442 | .d(1'b0), | |
1443 | .q(spare2_flop_unused)); | |
1444 | assign si_2 = so_1; | |
1445 | ||
1446 | cl_u1_buf_32x spare2_buf_32x (.in(1'b1), | |
1447 | .out(spare2_buf_32x_unused)); | |
1448 | cl_u1_nand3_8x spare2_nand3_8x (.in0(1'b1), | |
1449 | .in1(1'b1), | |
1450 | .in2(1'b1), | |
1451 | .out(spare2_nand3_8x_unused)); | |
1452 | cl_u1_inv_8x spare2_inv_8x (.in(1'b1), | |
1453 | .out(spare2_inv_8x_unused)); | |
1454 | cl_u1_aoi22_4x spare2_aoi22_4x (.in00(1'b1), | |
1455 | .in01(1'b1), | |
1456 | .in10(1'b1), | |
1457 | .in11(1'b1), | |
1458 | .out(spare2_aoi22_4x_unused)); | |
1459 | cl_u1_buf_8x spare2_buf_8x (.in(1'b1), | |
1460 | .out(spare2_buf_8x_unused)); | |
1461 | cl_u1_oai22_4x spare2_oai22_4x (.in00(1'b1), | |
1462 | .in01(1'b1), | |
1463 | .in10(1'b1), | |
1464 | .in11(1'b1), | |
1465 | .out(spare2_oai22_4x_unused)); | |
1466 | cl_u1_inv_16x spare2_inv_16x (.in(1'b1), | |
1467 | .out(spare2_inv_16x_unused)); | |
1468 | cl_u1_nand2_16x spare2_nand2_16x (.in0(1'b1), | |
1469 | .in1(1'b1), | |
1470 | .out(spare2_nand2_16x_unused)); | |
1471 | cl_u1_nor3_4x spare2_nor3_4x (.in0(1'b0), | |
1472 | .in1(1'b0), | |
1473 | .in2(1'b0), | |
1474 | .out(spare2_nor3_4x_unused)); | |
1475 | cl_u1_nand2_8x spare2_nand2_8x (.in0(1'b1), | |
1476 | .in1(1'b1), | |
1477 | .out(spare2_nand2_8x_unused)); | |
1478 | cl_u1_buf_16x spare2_buf_16x (.in(1'b1), | |
1479 | .out(spare2_buf_16x_unused)); | |
1480 | cl_u1_nor2_16x spare2_nor2_16x (.in0(1'b0), | |
1481 | .in1(1'b0), | |
1482 | .out(spare2_nor2_16x_unused)); | |
1483 | cl_u1_inv_32x spare2_inv_32x (.in(1'b1), | |
1484 | .out(spare2_inv_32x_unused)); | |
1485 | ||
1486 | cl_sc1_msff_8x spare3_flop (.l1clk(l1clk), | |
1487 | .siclk(siclk), | |
1488 | .soclk(soclk), | |
1489 | .si(si_3), | |
1490 | .so(so_3), | |
1491 | .d(1'b0), | |
1492 | .q(spare3_flop_unused)); | |
1493 | assign si_3 = so_2; | |
1494 | ||
1495 | cl_u1_buf_32x spare3_buf_32x (.in(1'b1), | |
1496 | .out(spare3_buf_32x_unused)); | |
1497 | cl_u1_nand3_8x spare3_nand3_8x (.in0(1'b1), | |
1498 | .in1(1'b1), | |
1499 | .in2(1'b1), | |
1500 | .out(spare3_nand3_8x_unused)); | |
1501 | cl_u1_inv_8x spare3_inv_8x (.in(1'b1), | |
1502 | .out(spare3_inv_8x_unused)); | |
1503 | cl_u1_aoi22_4x spare3_aoi22_4x (.in00(1'b1), | |
1504 | .in01(1'b1), | |
1505 | .in10(1'b1), | |
1506 | .in11(1'b1), | |
1507 | .out(spare3_aoi22_4x_unused)); | |
1508 | cl_u1_buf_8x spare3_buf_8x (.in(1'b1), | |
1509 | .out(spare3_buf_8x_unused)); | |
1510 | cl_u1_oai22_4x spare3_oai22_4x (.in00(1'b1), | |
1511 | .in01(1'b1), | |
1512 | .in10(1'b1), | |
1513 | .in11(1'b1), | |
1514 | .out(spare3_oai22_4x_unused)); | |
1515 | cl_u1_inv_16x spare3_inv_16x (.in(1'b1), | |
1516 | .out(spare3_inv_16x_unused)); | |
1517 | cl_u1_nand2_16x spare3_nand2_16x (.in0(1'b1), | |
1518 | .in1(1'b1), | |
1519 | .out(spare3_nand2_16x_unused)); | |
1520 | cl_u1_nor3_4x spare3_nor3_4x (.in0(1'b0), | |
1521 | .in1(1'b0), | |
1522 | .in2(1'b0), | |
1523 | .out(spare3_nor3_4x_unused)); | |
1524 | cl_u1_nand2_8x spare3_nand2_8x (.in0(1'b1), | |
1525 | .in1(1'b1), | |
1526 | .out(spare3_nand2_8x_unused)); | |
1527 | cl_u1_buf_16x spare3_buf_16x (.in(1'b1), | |
1528 | .out(spare3_buf_16x_unused)); | |
1529 | cl_u1_nor2_16x spare3_nor2_16x (.in0(1'b0), | |
1530 | .in1(1'b0), | |
1531 | .out(spare3_nor2_16x_unused)); | |
1532 | cl_u1_inv_32x spare3_inv_32x (.in(1'b1), | |
1533 | .out(spare3_inv_32x_unused)); | |
1534 | ||
1535 | cl_sc1_msff_8x spare4_flop (.l1clk(l1clk), | |
1536 | .siclk(siclk), | |
1537 | .soclk(soclk), | |
1538 | .si(si_4), | |
1539 | .so(so_4), | |
1540 | .d(1'b0), | |
1541 | .q(spare4_flop_unused)); | |
1542 | assign si_4 = so_3; | |
1543 | ||
1544 | cl_u1_buf_32x spare4_buf_32x (.in(1'b1), | |
1545 | .out(spare4_buf_32x_unused)); | |
1546 | cl_u1_nand3_8x spare4_nand3_8x (.in0(1'b1), | |
1547 | .in1(1'b1), | |
1548 | .in2(1'b1), | |
1549 | .out(spare4_nand3_8x_unused)); | |
1550 | cl_u1_inv_8x spare4_inv_8x (.in(1'b1), | |
1551 | .out(spare4_inv_8x_unused)); | |
1552 | cl_u1_aoi22_4x spare4_aoi22_4x (.in00(1'b1), | |
1553 | .in01(1'b1), | |
1554 | .in10(1'b1), | |
1555 | .in11(1'b1), | |
1556 | .out(spare4_aoi22_4x_unused)); | |
1557 | cl_u1_buf_8x spare4_buf_8x (.in(1'b1), | |
1558 | .out(spare4_buf_8x_unused)); | |
1559 | cl_u1_oai22_4x spare4_oai22_4x (.in00(1'b1), | |
1560 | .in01(1'b1), | |
1561 | .in10(1'b1), | |
1562 | .in11(1'b1), | |
1563 | .out(spare4_oai22_4x_unused)); | |
1564 | cl_u1_inv_16x spare4_inv_16x (.in(1'b1), | |
1565 | .out(spare4_inv_16x_unused)); | |
1566 | cl_u1_nand2_16x spare4_nand2_16x (.in0(1'b1), | |
1567 | .in1(1'b1), | |
1568 | .out(spare4_nand2_16x_unused)); | |
1569 | cl_u1_nor3_4x spare4_nor3_4x (.in0(1'b0), | |
1570 | .in1(1'b0), | |
1571 | .in2(1'b0), | |
1572 | .out(spare4_nor3_4x_unused)); | |
1573 | cl_u1_nand2_8x spare4_nand2_8x (.in0(1'b1), | |
1574 | .in1(1'b1), | |
1575 | .out(spare4_nand2_8x_unused)); | |
1576 | cl_u1_buf_16x spare4_buf_16x (.in(1'b1), | |
1577 | .out(spare4_buf_16x_unused)); | |
1578 | cl_u1_nor2_16x spare4_nor2_16x (.in0(1'b0), | |
1579 | .in1(1'b0), | |
1580 | .out(spare4_nor2_16x_unused)); | |
1581 | cl_u1_inv_32x spare4_inv_32x (.in(1'b1), | |
1582 | .out(spare4_inv_32x_unused)); | |
1583 | ||
1584 | cl_sc1_msff_8x spare5_flop (.l1clk(l1clk), | |
1585 | .siclk(siclk), | |
1586 | .soclk(soclk), | |
1587 | .si(si_5), | |
1588 | .so(so_5), | |
1589 | .d(1'b0), | |
1590 | .q(spare5_flop_unused)); | |
1591 | assign si_5 = so_4; | |
1592 | ||
1593 | cl_u1_buf_32x spare5_buf_32x (.in(1'b1), | |
1594 | .out(spare5_buf_32x_unused)); | |
1595 | cl_u1_nand3_8x spare5_nand3_8x (.in0(1'b1), | |
1596 | .in1(1'b1), | |
1597 | .in2(1'b1), | |
1598 | .out(spare5_nand3_8x_unused)); | |
1599 | cl_u1_inv_8x spare5_inv_8x (.in(1'b1), | |
1600 | .out(spare5_inv_8x_unused)); | |
1601 | cl_u1_aoi22_4x spare5_aoi22_4x (.in00(1'b1), | |
1602 | .in01(1'b1), | |
1603 | .in10(1'b1), | |
1604 | .in11(1'b1), | |
1605 | .out(spare5_aoi22_4x_unused)); | |
1606 | cl_u1_buf_8x spare5_buf_8x (.in(1'b1), | |
1607 | .out(spare5_buf_8x_unused)); | |
1608 | cl_u1_oai22_4x spare5_oai22_4x (.in00(1'b1), | |
1609 | .in01(1'b1), | |
1610 | .in10(1'b1), | |
1611 | .in11(1'b1), | |
1612 | .out(spare5_oai22_4x_unused)); | |
1613 | cl_u1_inv_16x spare5_inv_16x (.in(1'b1), | |
1614 | .out(spare5_inv_16x_unused)); | |
1615 | cl_u1_nand2_16x spare5_nand2_16x (.in0(1'b1), | |
1616 | .in1(1'b1), | |
1617 | .out(spare5_nand2_16x_unused)); | |
1618 | cl_u1_nor3_4x spare5_nor3_4x (.in0(1'b0), | |
1619 | .in1(1'b0), | |
1620 | .in2(1'b0), | |
1621 | .out(spare5_nor3_4x_unused)); | |
1622 | cl_u1_nand2_8x spare5_nand2_8x (.in0(1'b1), | |
1623 | .in1(1'b1), | |
1624 | .out(spare5_nand2_8x_unused)); | |
1625 | cl_u1_buf_16x spare5_buf_16x (.in(1'b1), | |
1626 | .out(spare5_buf_16x_unused)); | |
1627 | cl_u1_nor2_16x spare5_nor2_16x (.in0(1'b0), | |
1628 | .in1(1'b0), | |
1629 | .out(spare5_nor2_16x_unused)); | |
1630 | cl_u1_inv_32x spare5_inv_32x (.in(1'b1), | |
1631 | .out(spare5_inv_32x_unused)); | |
1632 | assign scan_out = so_5; | |
1633 | ||
1634 | ||
1635 | ||
1636 | endmodule | |
1637 |