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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / design / sys / iop / rtx / rtl / rtx.v
CommitLineData
86530b38
AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: rtx.v
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
19// along with this program; if not, write to the Free Software
20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
23// choice is available it will apply instead, Sun elects to use only
24// the General Public License version 2 (GPLv2) at this time for any
25// software where a choice of GPL license versions is made
26// available with the language indicating that GPLv2 or any later version
27// may be used, or where a choice of which version of the GPL is applied is
28// otherwise unspecified.
29//
30// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
31// CA 95054 USA or visit www.sun.com if you need additional information or
32// have any questions.
33//
34// ========== Copyright Header End ============================================
35
36// VPERL: PERL_BEG
37//
38// $VPERL_PORT_COMM = 1;
39// #$VPERL_INST_COMM = 2;
40//
41//
42// &MODULE ("rtx");
43//
44// &INSTANCE ("clkgen_rtx.v", "clkgen_rtx");
45// &INSTANCE ("/vobs/neptune/design/niu/n2_lib/clkgen_rtx_io2x.v", "clkgen2x_rtx");
46// &INSTANCE ("./rtx_n2_efuhdr3_p0_ctl.v", "efuhdr_ipp0");
47// &INSTANCE ("./rtx_n2_efuhdr3_p1_ctl.v", "efuhdr_ipp1");
48// &INSTANCE ("./rtx_n2_efuhdr1b_p0_ctl.v", "efuhdr_txc0_re");
49// &INSTANCE ("./rtx_n2_efuhdr1a_p0_ctl.v", "efuhdr_txc0_st");
50// &INSTANCE ("./rtx_n2_efuhdr1b_p1_ctl.v", "efuhdr_txc1_re");
51// &INSTANCE ("./rtx_n2_efuhdr1a_p1_ctl.v", "efuhdr_txc1_st");
52// &INSTANCE ("./rtx_n2_efuhdr6_ctl.v", "efuhdr_vlan");
53// &INSTANCE ("./rtx_n2_efuhdr7_p0_ctl.v", "efuhdr_zcp0");
54// &INSTANCE ("./rtx_n2_efuhdr7_p1_ctl.v", "efuhdr_zcp1");
55// &INSTANCE ("gates/niu_rxc_shell.v.new", "rxc");
56// &INSTANCE ("gates/niu_txc_shell.v.new", "txc");
57// &INSTANCE ("rtx_dmo_mux.v", "rtx_dmo_mux");
58// # &FORCE ("input", "ccu_io2x_out", "ccu_io_out");
59// # I6.1 changes
60// &FORCE ("input", "gl_rtx_io_out", "gl_rtx_io2x_out");
61// &FORCE ("input", "cmp_gclk_c0_rtx");
62// &FORCE ("input", "tcu_atpg_mode");
63// &FORCE ("input", "tcu_wr_inhibit");
64// &FORCE ("input", "meta_dmc_resp_trans_id[5:0]");
65
66// &FORCE ("wire", "rtx_array_wr_inhibit");
67// &FORCE ("wire","rtx_rxc_ipp0_mb3_mbist_scan_out");
68// &FORCE ("wire","rtx_rxc_ipp1_mb3_mbist_scan_out");
69// &FORCE ("wire","rtx_rxc_tcam_cntrl_mbist_scan_out");
70// &FORCE ("wire","rtx_rxc_tcam_vlan_mbist_scan_out");
71// &FORCE ("wire","rtx_rxc_zcp0_mb7_mbist_scan_out");
72// &FORCE ("wire","rtx_rxc_zcp1_mb7_mbist_scan_out");
73// &FORCE ("wire","rtx_txc_txe0_mbist_scan_out");
74// &FORCE ("wire","niu_mb3_rx_data_fifo_scan_out");
75// &FORCE ("wire","niu_mb4_rx_data_fifo_scan_out");
76// &FORCE ("wire","niu_mb3_prebuf_header_scan_out");
77// &FORCE ("wire","niu_mb4_prebuf_header_scan_out");
78// &FORCE ("wire","niu_mb5_tcam_cntrl_scan_out");
79// &FORCE ("wire","niu_mb6_tcam_array_scan_out");
80// &FORCE ("wire","niu_mb6_vlan_scan_out");
81// &FORCE ("wire","niu_mb7_cntrl_fifo_zcp_scan_out");
82// &FORCE ("wire","efuhdr_ipp0_scan_out");
83// &FORCE ("wire","efuhdr_ipp1_scan_out");
84// &FORCE ("wire","efuhdr_txc0_re_scan_out");
85// &FORCE ("wire","efuhdr_txc0_st_scan_out");
86// &FORCE ("wire","efuhdr_txc1_re_scan_out");
87// &FORCE ("wire","efuhdr_txc1_st_scan_out");
88// &FORCE ("wire","efuhdr_vlan_scan_out");
89// &FORCE ("wire","efuhdr_zcp0_scan_out");
90
91// &FORCE ("input", "scan_in", "rtx_mbist_scan_in", "tcu_rtx_io_clk_stop", "rst_por_");
92// &FORCE ("output", "scan_out", "rtx_mbist_scan_out");
93// # New pins I6.1
94// &CONNECT ("clkgen_rtx.gclk", "cmp_gclk_c0_rtx");
95// &CONNECT ("clkgen_rtx.tcu_wr_inhibit", "tcu_wr_inhibit");
96// &CONNECT ("clkgen_rtx.array_wr_inhibit", "rtx_array_wr_inhibit");
97// &CONNECT ("clkgen_rtx.tcu_atpg_mode", "tcu_atpg_mode");
98// &CONNECT ("clkgen2x_rtx.tcu_atpg_mode", "tcu_atpg_mode");
99// &CONNECT ("clkgen2x_rtx.gclk", "cmp_gclk_c0_rtx");
100// &CONNECT ("clkgen2x_rtx.array_wr_inhibit", "");
101// &CONNECT ("clkgen2x_rtx.tcu_wr_inhibit", "1'b0");
102// &CONNECT ("clkgen2x_rtx.tcu_atpg_mode", "tcu_atpg_mode");
103
104
105// &CONNECT ("clkgen2x_rtx.l2clk", "l1clk_2x");
106// &CONNECT ("clkgen2x_rtx.tcu_aclk", "aclk");
107// &CONNECT ("clkgen2x_rtx.tcu_bclk", "bclk");
108// &CONNECT ("clkgen2x_rtx.tcu_pce_ov", "pce_ov");
109// &CONNECT ("clkgen2x_rtx.aclk", "");
110// &CONNECT ("clkgen2x_rtx.bclk", "");
111// &CONNECT ("clkgen2x_rtx.scan_out", "clkgen2x_rtx_scan_out");
112// &CONNECT ("clkgen2x_rtx.wmr_protect", "");
113// &CONNECT ("clkgen2x_rtx.aclk_wmr", "");
114// &CONNECT ("clkgen2x_rtx.wmr_", "");
115// &CONNECT ("clkgen2x_rtx.por_", "");
116// &CONNECT ("clkgen2x_rtx.pce_ov", "");
117// &CONNECT ("clkgen2x_rtx.cmp_slow_sync_en", "");
118// &CONNECT ("clkgen2x_rtx.slow_cmp_sync_en", "");
119
120// &CONNECT ("clkgen2x_rtx.ccu_serdes_dtm", "1'b0");
121// &CONNECT ("clkgen2x_rtx.clk_ext", "1'b0");
122// &CONNECT ("clkgen2x_rtx.tcu_clk_stop", "tcu_rtx_io_clk_stop");
123// &CONNECT ("clkgen2x_rtx.rst_wmr_protect","1'b0");
124// &CONNECT ("clkgen2x_rtx.rst_wmr_", "1'b1");
125// &CONNECT ("clkgen2x_rtx.rst_por_", "rst_por_");
126// &CONNECT ("clkgen2x_rtx.ccu_cmp_slow_sync_en", "1'b0");
127// &CONNECT ("clkgen2x_rtx.ccu_slow_cmp_sync_en", "1'b0");
128// &CONNECT ("clkgen2x_rtx.ccu_div_ph", "gl_rtx_io2x_out");
129// &CONNECT ("clkgen2x_rtx.cluster_div_en","1'b1");
130// &CONNECT ("clkgen2x_rtx.scan_en","tcu_scan_en");
131// &CONNECT ("clkgen2x_rtx.scan_in","clkgen_rtx_scan_out");
132
133// &CONNECT ("clkgen_rtx.l1clk", "l1clk");
134// &CONNECT ("clkgen_rtx.scan_out", "clkgen_rtx_scan_out");
135// &CONNECT ("clkgen_rtx.pce_ov", "pce_ov");
136// &CONNECT ("clkgen_rtx.wmr_protect", "");
137// &CONNECT ("clkgen_rtx.aclk_wmr", "");
138// &CONNECT ("clkgen_rtx.wmr_", "");
139// &CONNECT ("clkgen_rtx.por_", "reset_l");
140// &CONNECT ("clkgen_rtx.cmp_slow_sync_en", "");
141// &CONNECT ("clkgen_rtx.slow_cmp_sync_en", "");
142
143// &CONNECT ("clkgen_rtx.tcu_clk_stop", "tcu_rtx_io_clk_stop");
144// &CONNECT ("clkgen_rtx.rst_wmr_protect","1'b0");
145// &CONNECT ("clkgen_rtx.rst_wmr_", "1'b1");
146// &CONNECT ("clkgen_rtx.rst_por_", "rst_por_");
147// # &CONNECT ("clkgen_rtx.ccu_cmp_slow_sync_en", "1'b0");
148// # &CONNECT ("clkgen_rtx.ccu_slow_cmp_sync_en", "1'b0");
149// &CONNECT ("clkgen_rtx.ccu_div_ph", "gl_rtx_io_out");
150// &CONNECT ("clkgen_rtx.cluster_div_en","1'b1");
151// &CONNECT ("clkgen_rtx.scan_en","tcu_scan_en");
152// &CONNECT ("clkgen_rtx.scan_in","scan_in");
153
154// &CONNECT ("rxc.tcu_aclk", "aclk");
155// &CONNECT ("rxc.tcu_bclk", "bclk");
156// &CONNECT ("rxc.niu_clk", "l1clk");
157// &CONNECT ("rxc.iol2clk_2x", "l1clk_2x");
158// &CONNECT ("txc.l2clk_2x", "l1clk_2x");
159// &CONNECT ("txc.tcu_aclk", "aclk");
160// &CONNECT ("txc.tcu_bclk", "bclk");
161// &CONNECT ("txc.niu_clk", "l1clk");
162// &CONNECT ("rxc.niu_reset_l", "reset_l");
163// &CONNECT ("txc.niu_reset_l", "reset_l");
164// &CONNECT ("rxc.rtx_rxc_ipp0_mb3_mbist_scan_in","rtx_mbist_scan_in");
165// &CONNECT ("rxc.rtx_rxc_ipp1_mb3_mbist_scan_in","rtx_rxc_ipp0_mb3_mbist_scan_out");
166// &CONNECT ("rxc.rtx_rxc_tcam_cntrl_mbist_scan_in","rtx_rxc_ipp1_mb3_mbist_scan_out");
167// &CONNECT ("rxc.rtx_rxc_tcam_vlan_mbist_scan_in","rtx_rxc_tcam_cntrl_mbist_scan_out");
168// &CONNECT ("rxc.rtx_rxc_zcp0_mb7_mbist_scan_in","rtx_rxc_tcam_vlan_mbist_scan_out");
169// &CONNECT ("rxc.rtx_rxc_zcp1_mb7_mbist_scan_in","rtx_rxc_zcp0_mb7_mbist_scan_out");
170// &CONNECT ("rxc.tcu_array_wr_inhibit", "rtx_array_wr_inhibit");
171// &CONNECT ("txc.tcu_array_wr_inhibit", "rtx_array_wr_inhibit");
172// &CONNECT ("txc.rtx_txc_txe0_mbist_scan_in","rtx_rxc_zcp1_mb7_mbist_scan_out");
173// &CONNECT ("txc.rtx_txc_txe1_mbist_scan_in","rtx_txc_txe0_mbist_scan_out");
174// &CONNECT ("txc.rtx_txc_txe1_mbist_scan_out","rtx_mbist_scan_out");
175
176
177// &CONNECT ("efuhdr_ipp0.scan_out", "efuhdr_ipp0_scan_out");
178// &CONNECT ("efuhdr_ipp1.scan_out", "efuhdr_ipp1_scan_out");
179// &CONNECT ("efuhdr_txc0_re.scan_out", "efuhdr_txc0_re_scan_out");
180// &CONNECT ("efuhdr_txc0_st.scan_out", "efuhdr_txc0_st_scan_out");
181// &CONNECT ("efuhdr_txc1_re.scan_out", "efuhdr_txc1_re_scan_out");
182// &CONNECT ("efuhdr_txc1_st.scan_out", "efuhdr_txc1_st_scan_out");
183// &CONNECT ("efuhdr_vlan.scan_out", "efuhdr_vlan_scan_out");
184// &CONNECT ("efuhdr_zcp0.scan_out", "efuhdr_zcp0_scan_out");
185// &CONNECT ("efuhdr_zcp1.scan_out", "efuhdr_zcp1_scan_out");
186
187// &CONNECT ("efuhdr_ipp0.scan_in","clkgen2x_rtx_scan_out");
188// &CONNECT ("efuhdr_ipp1.scan_in","efuhdr_ipp0_scan_out");
189// &CONNECT ("efuhdr_txc0_re.scan_in","efuhdr_ipp1_scan_out");
190// &CONNECT ("efuhdr_txc0_st.scan_in","efuhdr_txc0_re_scan_out");
191// &CONNECT ("efuhdr_txc1_re.scan_in","efuhdr_txc0_st_scan_out");
192// &CONNECT ("efuhdr_txc1_st.scan_in","efuhdr_txc1_re_scan_out");
193// &CONNECT ("efuhdr_vlan.scan_in","efuhdr_txc1_st_scan_out");
194// &CONNECT ("efuhdr_zcp0.scan_in","efuhdr_vlan_scan_out");
195// &CONNECT ("efuhdr_zcp1.scan_in","efuhdr_zcp0_scan_out");
196
197// &CONNECT ("rxc.niu_mb3_rx_data_fifo_scan_in","efuhdr_zcp1_scan_out");
198// &CONNECT ("rxc.niu_mb3_prebuf_header_scan_in","niu_mb3_rx_data_fifo_scan_out");
199// &CONNECT ("rxc.niu_mb4_rx_data_fifo_scan_in","niu_mb3_prebuf_header_scan_out");
200// &CONNECT ("rxc.niu_mb4_prebuf_header_scan_in","niu_mb4_rx_data_fifo_scan_out");
201// &CONNECT ("rxc.niu_mb5_tcam_cntrl_scan_in","niu_mb4_prebuf_header_scan_out");
202// &CONNECT ("rxc.niu_mb6_tcam_array_scan_in","niu_mb5_tcam_cntrl_scan_out");
203// &CONNECT ("rxc.niu_mb6_vlan_scan_in","niu_mb6_tcam_array_scan_out");
204// &CONNECT ("rxc.niu_mb7_cntrl_fifo_zcp_scan_in","niu_mb6_vlan_scan_out");
205// &CONNECT ("rxc.niu_mb8_cntrl_fifo_zcp_scan_in","niu_mb7_cntrl_fifo_zcp_scan_out");
206// &CONNECT ("rxc.niu_mb8_cntrl_fifo_zcp_scan_out","scan_out");
207
208// &FORCE ("wire", "nc40[3:0]", "nc41[3:0]", "nc42[3:0]", "nc43[3:0]", "nc44[3:0]", "nc45[3:0]", "nc46[3:0]", "nc47[3:0]", "nc50[4:0]", "nc80[7:0]", "nc81[7:0]", "nc82[7:0]", "nc83[7:0]", "nc84[7:0]", "nc85[7:0]", "nc90[8:0]", "nc91[8:0]", "nc100[9:0]");
209// &CONNECT ("efuhdr_ipp0.hdr_sram_rvalue","{nc40,hdr_sram_rvalue_ipp0[6:0]}");
210// &CONNECT ("efuhdr_ipp1.hdr_sram_rvalue","{nc41,hdr_sram_rvalue_ipp1[6:0]}");
211// &CONNECT ("efuhdr_txc0_re.hdr_sram_rvalue","{nc42,hdr_sram_rvalue_txc0_re[6:0]}");
212// &CONNECT ("efuhdr_txc1_re.hdr_sram_rvalue","{nc43,hdr_sram_rvalue_txc1_re[6:0]}");
213// &CONNECT ("efuhdr_txc0_st.hdr_sram_rvalue","{nc44,hdr_sram_rvalue_txc0_st[6:0]}");
214// &CONNECT ("efuhdr_txc1_st.hdr_sram_rvalue","{nc45,hdr_sram_rvalue_txc1_st[6:0]}");
215// &CONNECT ("efuhdr_vlan.hdr_sram_rvalue","{nc50,hdr_sram_rvalue_vlan[5:0]}");
216// &CONNECT ("efuhdr_zcp0.hdr_sram_rvalue","{nc46,hdr_sram_rvalue_zcp0[6:0]}");
217// &CONNECT ("efuhdr_zcp1.hdr_sram_rvalue","{nc47,hdr_sram_rvalue_zcp1[6:0]}");
218
219// &CONNECT ("efuhdr_ipp0.hdr_sram_rid","{nc80,hdr_sram_rid_ipp0[2:0]}");
220// &CONNECT ("efuhdr_ipp1.hdr_sram_rid","{nc81,hdr_sram_rid_ipp1[2:0]}");
221// &CONNECT ("efuhdr_txc0_re.hdr_sram_rid","{nc82,hdr_sram_rid_txc0_re[2:0]}");
222// &CONNECT ("efuhdr_txc1_re.hdr_sram_rid","{nc83,hdr_sram_rid_txc1_re[2:0]}");
223// &CONNECT ("efuhdr_txc0_st.hdr_sram_rid","{nc84,hdr_sram_rid_txc0_st[2:0]}");
224// &CONNECT ("efuhdr_txc1_st.hdr_sram_rid","{nc85,hdr_sram_rid_txc1_st[2:0]}");
225// &CONNECT ("efuhdr_vlan.hdr_sram_rid","{nc100,hdr_sram_rid_vlan}");
226// &CONNECT ("efuhdr_zcp0.hdr_sram_rid","{nc90,hdr_sram_rid_zcp0[1:0]}");
227// &CONNECT ("efuhdr_zcp1.hdr_sram_rid","{nc91,hdr_sram_rid_zcp1[1:0]}");
228
229// &CONNECT ("efuhdr_ipp0.hdr_sram_red_clr","hdr_sram_red_clr_ipp0");
230// &CONNECT ("efuhdr_ipp1.hdr_sram_red_clr","hdr_sram_red_clr_ipp1");
231// &CONNECT ("efuhdr_txc0_re.hdr_sram_red_clr","hdr_sram_red_clr_txc0_re");
232// &CONNECT ("efuhdr_txc1_re.hdr_sram_red_clr","hdr_sram_red_clr_txc1_re");
233// &CONNECT ("efuhdr_txc0_st.hdr_sram_red_clr","hdr_sram_red_clr_txc0_st");
234// &CONNECT ("efuhdr_txc1_st.hdr_sram_red_clr","hdr_sram_red_clr_txc1_st");
235// &CONNECT ("efuhdr_vlan.hdr_sram_red_clr","hdr_sram_red_clr_vlan");
236// &CONNECT ("efuhdr_zcp0.hdr_sram_red_clr","hdr_sram_red_clr_zcp0");
237// &CONNECT ("efuhdr_zcp1.hdr_sram_red_clr","hdr_sram_red_clr_zcp1");
238
239// #&CONNECT ("rxc.tcu_clk_stop","tcu_rtx_io_clk_stop");
240// #&CONNECT ("txc.tcu_clk_stop","tcu_rtx_io_clk_stop");
241// &CONNECT ("efuhdr_ipp0.tcu_clk_stop","tcu_rtx_io_clk_stop");
242// &CONNECT ("efuhdr_ipp1.tcu_clk_stop","tcu_rtx_io_clk_stop");
243// &CONNECT ("efuhdr_txc0_re.tcu_clk_stop","tcu_rtx_io_clk_stop");
244// &CONNECT ("efuhdr_txc1_re.tcu_clk_stop","tcu_rtx_io_clk_stop");
245// &CONNECT ("efuhdr_txc0_st.tcu_clk_stop","tcu_rtx_io_clk_stop");
246// &CONNECT ("efuhdr_txc1_st.tcu_clk_stop","tcu_rtx_io_clk_stop");
247// &CONNECT ("efuhdr_vlan.tcu_clk_stop","tcu_rtx_io_clk_stop");
248// &CONNECT ("efuhdr_zcp0.tcu_clk_stop","tcu_rtx_io_clk_stop");
249// &CONNECT ("efuhdr_zcp1.tcu_clk_stop","tcu_rtx_io_clk_stop");
250
251
252// &CONNECT ("efuhdr_ipp0.hdr_sram_wr_en","hdr_sram_wr_en_ipp0");
253// &CONNECT ("efuhdr_ipp1.hdr_sram_wr_en","hdr_sram_wr_en_ipp1");
254// &CONNECT ("efuhdr_txc0_re.hdr_sram_wr_en","hdr_sram_wr_en_txc0_re");
255// &CONNECT ("efuhdr_txc1_re.hdr_sram_wr_en","hdr_sram_wr_en_txc1_re");
256// &CONNECT ("efuhdr_txc0_st.hdr_sram_wr_en","hdr_sram_wr_en_txc0_st");
257// &CONNECT ("efuhdr_txc1_st.hdr_sram_wr_en","hdr_sram_wr_en_txc1_st");
258// &CONNECT ("efuhdr_vlan.hdr_sram_wr_en","hdr_sram_wr_en_vlan");
259// &CONNECT ("efuhdr_zcp0.hdr_sram_wr_en","hdr_sram_wr_en_zcp0");
260// &CONNECT ("efuhdr_zcp1.hdr_sram_wr_en","hdr_sram_wr_en_zcp1");
261
262// &CONNECT ("efuhdr_ipp0.sram_hdr_read_data","{4'b0,sram_hdr_read_data_ipp0[6:0]}");
263// &CONNECT ("efuhdr_ipp1.sram_hdr_read_data","{4'b0,sram_hdr_read_data_ipp1[6:0]}");
264// &CONNECT ("efuhdr_txc0_re.sram_hdr_read_data","{4'b0,sram_hdr_read_data_txc0_re[6:0]}");
265// &CONNECT ("efuhdr_txc1_re.sram_hdr_read_data","{4'b0,sram_hdr_read_data_txc1_re[6:0]}");
266// &CONNECT ("efuhdr_txc0_st.sram_hdr_read_data","{4'b0,sram_hdr_read_data_txc0_st[6:0]}");
267// &CONNECT ("efuhdr_txc1_st.sram_hdr_read_data","{4'b0,sram_hdr_read_data_txc1_st[6:0]}");
268// &CONNECT ("efuhdr_vlan.sram_hdr_read_data","{5'b0,sram_hdr_read_data_vlan[5:0]}");
269// &CONNECT ("efuhdr_zcp0.sram_hdr_read_data","{4'b0,sram_hdr_read_data_zcp0[6:0]}");
270// &CONNECT ("efuhdr_zcp1.sram_hdr_read_data","{4'b0,sram_hdr_read_data_zcp1[6:0]}");
271
272// &CONNECT ("efuhdr_ipp0.l2clk","l1clk");
273// &CONNECT ("efuhdr_ipp1.l2clk","l1clk");
274// &CONNECT ("efuhdr_txc0_re.l2clk","l1clk");
275// &CONNECT ("efuhdr_txc0_st.l2clk","l1clk");
276// &CONNECT ("efuhdr_txc1_re.l2clk","l1clk");
277// &CONNECT ("efuhdr_txc1_st.l2clk","l1clk");
278// &CONNECT ("efuhdr_vlan.l2clk","l1clk");
279// &CONNECT ("efuhdr_zcp0.l2clk","l1clk");
280// &CONNECT ("efuhdr_zcp1.l2clk","l1clk");
281
282// &CONNECT ("efuhdr_ipp0.tcu_aclk","aclk");
283// &CONNECT ("efuhdr_ipp1.tcu_aclk","aclk");
284// &CONNECT ("efuhdr_txc0_re.tcu_aclk","aclk");
285// &CONNECT ("efuhdr_txc0_st.tcu_aclk","aclk");
286// &CONNECT ("efuhdr_txc1_re.tcu_aclk","aclk");
287// &CONNECT ("efuhdr_txc1_st.tcu_aclk","aclk");
288// &CONNECT ("efuhdr_vlan.tcu_aclk","aclk");
289// &CONNECT ("efuhdr_zcp0.tcu_aclk","aclk");
290// &CONNECT ("efuhdr_zcp1.tcu_aclk","aclk");
291
292// &CONNECT ("efuhdr_ipp0.tcu_bclk","bclk");
293// &CONNECT ("efuhdr_ipp1.tcu_bclk","bclk");
294// &CONNECT ("efuhdr_txc0_re.tcu_bclk","bclk");
295// &CONNECT ("efuhdr_txc0_st.tcu_bclk","bclk");
296// &CONNECT ("efuhdr_txc1_re.tcu_bclk","bclk");
297// &CONNECT ("efuhdr_txc1_st.tcu_bclk","bclk");
298// &CONNECT ("efuhdr_vlan.tcu_bclk","bclk");
299// &CONNECT ("efuhdr_zcp0.tcu_bclk","bclk");
300// &CONNECT ("efuhdr_zcp1.tcu_bclk","bclk");
301
302
303
304// &CONNECT ("efuhdr_ipp0.efu_hdr_write_data","efu_niu_mac01_sfro_data");
305// &CONNECT ("efuhdr_ipp0.efu_hdr_xfer_en","efu_niu_ipp0_xfer_en");
306// &CONNECT ("efuhdr_ipp0.efu_hdr_clr","efu_niu_ipp0_clr");
307// &CONNECT ("efuhdr_ipp0.hdr_efu_read_data","niu_efu_ipp0_data");
308// &CONNECT ("efuhdr_ipp0.hdr_efu_xfer_en","niu_efu_ipp0_xfer_en");
309
310// &CONNECT ("efuhdr_ipp1.efu_hdr_write_data","efu_niu_mac01_sfro_data");
311// &CONNECT ("efuhdr_ipp1.efu_hdr_xfer_en","efu_niu_ipp1_xfer_en");
312// &CONNECT ("efuhdr_ipp1.efu_hdr_clr","efu_niu_ipp1_clr");
313// &CONNECT ("efuhdr_ipp1.hdr_efu_read_data","niu_efu_ipp1_data");
314// &CONNECT ("efuhdr_ipp1.hdr_efu_xfer_en","niu_efu_ipp1_xfer_en");
315
316// &CONNECT ("efuhdr_txc0_re.efu_hdr_write_data","efu_niu_mac01_sfro_data");
317// &CONNECT ("efuhdr_txc0_re.efu_hdr_xfer_en","efu_niu_mac0_ro_xfer_en");
318// &CONNECT ("efuhdr_txc0_re.efu_hdr_clr","efu_niu_mac0_ro_clr");
319// &CONNECT ("efuhdr_txc0_re.hdr_efu_read_data","niu_efu_mac0_ro_data");
320// &CONNECT ("efuhdr_txc0_re.hdr_efu_xfer_en","niu_efu_mac0_ro_xfer_en");
321
322// &CONNECT ("efuhdr_txc0_st.efu_hdr_write_data","efu_niu_mac01_sfro_data");
323// &CONNECT ("efuhdr_txc0_st.efu_hdr_xfer_en","efu_niu_mac0_sf_xfer_en");
324// &CONNECT ("efuhdr_txc0_st.efu_hdr_clr","efu_niu_mac0_sf_clr");
325// &CONNECT ("efuhdr_txc0_st.hdr_efu_read_data","niu_efu_mac0_sf_data");
326// &CONNECT ("efuhdr_txc0_st.hdr_efu_xfer_en","niu_efu_mac0_sf_xfer_en");
327
328// &CONNECT ("efuhdr_txc1_re.efu_hdr_write_data","efu_niu_mac01_sfro_data");
329// &CONNECT ("efuhdr_txc1_re.efu_hdr_xfer_en","efu_niu_mac1_ro_xfer_en");
330// &CONNECT ("efuhdr_txc1_re.efu_hdr_clr","efu_niu_mac1_ro_clr");
331// &CONNECT ("efuhdr_txc1_re.hdr_efu_read_data","niu_efu_mac1_ro_data");
332// &CONNECT ("efuhdr_txc1_re.hdr_efu_xfer_en","niu_efu_mac1_ro_xfer_en");
333
334// &CONNECT ("efuhdr_txc1_st.efu_hdr_write_data","efu_niu_mac01_sfro_data");
335// &CONNECT ("efuhdr_txc1_st.efu_hdr_xfer_en","efu_niu_mac1_sf_xfer_en");
336// &CONNECT ("efuhdr_txc1_st.efu_hdr_clr","efu_niu_mac1_sf_clr");
337// &CONNECT ("efuhdr_txc1_st.hdr_efu_read_data","niu_efu_mac1_sf_data");
338// &CONNECT ("efuhdr_txc1_st.hdr_efu_xfer_en","niu_efu_mac1_sf_xfer_en");
339
340// &CONNECT ("efuhdr_vlan.efu_hdr_write_data","efu_niu_4k_data");
341// &CONNECT ("efuhdr_vlan.efu_hdr_xfer_en","efu_niu_4k_xfer_en");
342// &CONNECT ("efuhdr_vlan.efu_hdr_clr","efu_niu_4k_clr");
343// &CONNECT ("efuhdr_vlan.hdr_efu_read_data","niu_efu_4k_data");
344// &CONNECT ("efuhdr_vlan.hdr_efu_xfer_en","niu_efu_4k_xfer_en");
345
346// &CONNECT ("efuhdr_zcp0.efu_hdr_write_data","efu_niu_cfifo_data");
347// &CONNECT ("efuhdr_zcp0.efu_hdr_xfer_en","efu_niu_cfifo0_xfer_en");
348// &CONNECT ("efuhdr_zcp0.efu_hdr_clr","efu_niu_cfifo0_clr");
349// &CONNECT ("efuhdr_zcp0.hdr_efu_read_data","niu_efu_cfifo0_data");
350// &CONNECT ("efuhdr_zcp0.hdr_efu_xfer_en","niu_efu_cfifo0_xfer_en");
351
352// &CONNECT ("efuhdr_zcp1.efu_hdr_write_data","efu_niu_cfifo_data");
353// &CONNECT ("efuhdr_zcp1.efu_hdr_xfer_en","efu_niu_cfifo1_xfer_en");
354// &CONNECT ("efuhdr_zcp1.efu_hdr_clr","efu_niu_cfifo1_clr");
355// &CONNECT ("efuhdr_zcp1.hdr_efu_read_data","niu_efu_cfifo1_data");
356// &CONNECT ("efuhdr_zcp1.hdr_efu_xfer_en","niu_efu_cfifo1_xfer_en");
357// &CONNECT ("rtx_dmo_mux.in0", "rtx_txc_txe0_dmo_dout");
358// &CONNECT ("rtx_dmo_mux.in1", "rtx_txc_txe1_dmo_dout");
359// &CONNECT ("rtx_dmo_mux.in2", "rtx_rxc_ipp0_mb3_dmo_dout");
360// &CONNECT ("rtx_dmo_mux.in3", "rtx_rxc_ipp1_mb3_dmo_dout");
361// &CONNECT ("rtx_dmo_mux.in4", "rtx_rxc_zcp0_mb7_dmo_dout");
362// &CONNECT ("rtx_dmo_mux.in5", "rtx_rxc_zcp1_mb7_dmo_dout");
363// &CONNECT ("rtx_dmo_mux.in6", "rtx_rxc_vlan_mb6_dmo_dout");
364// &CONNECT ("rtx_dmo_mux.out", "rtx_tcu_dmo_data_out[39:0]");
365// &CONNECT ("rtx_dmo_mux.sel", "tcu_rtx_dmo_ctl[2:0]");
366// &CONNECT ("rtx_dmo_mux.clk", "l1clk");
367// &CONNECT ("txc.meta_dmc_resp_transID", "meta_dmc_resp_trans_id[5:0]");
368
369// VPERL: PERL_END
370// VPERL: GENERATED_BEG
371
372module rtx (
373 arb1_txc_req_accept,
374 arb1_txc_req_transid,
375 cluster_arst_l,
376 cmp_gclk_c0_rtx,
377 dmc_ipp_dat_req0,
378 dmc_ipp_dat_req1,
379 dmc_txc_dma0_active,
380 dmc_txc_dma0_cacheready,
381 dmc_txc_dma0_descriptor,
382 dmc_txc_dma0_eoflist,
383 dmc_txc_dma0_error,
384 dmc_txc_dma0_func_num,
385 dmc_txc_dma0_gotnxtdesc,
386 dmc_txc_dma0_page_handle,
387 dmc_txc_dma0_partial,
388 dmc_txc_dma0_reset_scheduled,
389 dmc_txc_dma10_active,
390 dmc_txc_dma10_cacheready,
391 dmc_txc_dma10_descriptor,
392 dmc_txc_dma10_eoflist,
393 dmc_txc_dma10_error,
394 dmc_txc_dma10_func_num,
395 dmc_txc_dma10_gotnxtdesc,
396 dmc_txc_dma10_page_handle,
397 dmc_txc_dma10_partial,
398 dmc_txc_dma10_reset_scheduled,
399 dmc_txc_dma11_active,
400 dmc_txc_dma11_cacheready,
401 dmc_txc_dma11_descriptor,
402 dmc_txc_dma11_eoflist,
403 dmc_txc_dma11_error,
404 dmc_txc_dma11_func_num,
405 dmc_txc_dma11_gotnxtdesc,
406 dmc_txc_dma11_page_handle,
407 dmc_txc_dma11_partial,
408 dmc_txc_dma11_reset_scheduled,
409 dmc_txc_dma12_active,
410 dmc_txc_dma12_cacheready,
411 dmc_txc_dma12_descriptor,
412 dmc_txc_dma12_eoflist,
413 dmc_txc_dma12_error,
414 dmc_txc_dma12_func_num,
415 dmc_txc_dma12_gotnxtdesc,
416 dmc_txc_dma12_page_handle,
417 dmc_txc_dma12_partial,
418 dmc_txc_dma12_reset_scheduled,
419 dmc_txc_dma13_active,
420 dmc_txc_dma13_cacheready,
421 dmc_txc_dma13_descriptor,
422 dmc_txc_dma13_eoflist,
423 dmc_txc_dma13_error,
424 dmc_txc_dma13_func_num,
425 dmc_txc_dma13_gotnxtdesc,
426 dmc_txc_dma13_page_handle,
427 dmc_txc_dma13_partial,
428 dmc_txc_dma13_reset_scheduled,
429 dmc_txc_dma14_active,
430 dmc_txc_dma14_cacheready,
431 dmc_txc_dma14_descriptor,
432 dmc_txc_dma14_eoflist,
433 dmc_txc_dma14_error,
434 dmc_txc_dma14_func_num,
435 dmc_txc_dma14_gotnxtdesc,
436 dmc_txc_dma14_page_handle,
437 dmc_txc_dma14_partial,
438 dmc_txc_dma14_reset_scheduled,
439 dmc_txc_dma15_active,
440 dmc_txc_dma15_cacheready,
441 dmc_txc_dma15_descriptor,
442 dmc_txc_dma15_eoflist,
443 dmc_txc_dma15_error,
444 dmc_txc_dma15_func_num,
445 dmc_txc_dma15_gotnxtdesc,
446 dmc_txc_dma15_page_handle,
447 dmc_txc_dma15_partial,
448 dmc_txc_dma15_reset_scheduled,
449 dmc_txc_dma1_active,
450 dmc_txc_dma1_cacheready,
451 dmc_txc_dma1_descriptor,
452 dmc_txc_dma1_eoflist,
453 dmc_txc_dma1_error,
454 dmc_txc_dma1_func_num,
455 dmc_txc_dma1_gotnxtdesc,
456 dmc_txc_dma1_page_handle,
457 dmc_txc_dma1_partial,
458 dmc_txc_dma1_reset_scheduled,
459 dmc_txc_dma2_active,
460 dmc_txc_dma2_cacheready,
461 dmc_txc_dma2_descriptor,
462 dmc_txc_dma2_eoflist,
463 dmc_txc_dma2_error,
464 dmc_txc_dma2_func_num,
465 dmc_txc_dma2_gotnxtdesc,
466 dmc_txc_dma2_page_handle,
467 dmc_txc_dma2_partial,
468 dmc_txc_dma2_reset_scheduled,
469 dmc_txc_dma3_active,
470 dmc_txc_dma3_cacheready,
471 dmc_txc_dma3_descriptor,
472 dmc_txc_dma3_eoflist,
473 dmc_txc_dma3_error,
474 dmc_txc_dma3_func_num,
475 dmc_txc_dma3_gotnxtdesc,
476 dmc_txc_dma3_page_handle,
477 dmc_txc_dma3_partial,
478 dmc_txc_dma3_reset_scheduled,
479 dmc_txc_dma4_active,
480 dmc_txc_dma4_cacheready,
481 dmc_txc_dma4_descriptor,
482 dmc_txc_dma4_eoflist,
483 dmc_txc_dma4_error,
484 dmc_txc_dma4_func_num,
485 dmc_txc_dma4_gotnxtdesc,
486 dmc_txc_dma4_page_handle,
487 dmc_txc_dma4_partial,
488 dmc_txc_dma4_reset_scheduled,
489 dmc_txc_dma5_active,
490 dmc_txc_dma5_cacheready,
491 dmc_txc_dma5_descriptor,
492 dmc_txc_dma5_eoflist,
493 dmc_txc_dma5_error,
494 dmc_txc_dma5_func_num,
495 dmc_txc_dma5_gotnxtdesc,
496 dmc_txc_dma5_page_handle,
497 dmc_txc_dma5_partial,
498 dmc_txc_dma5_reset_scheduled,
499 dmc_txc_dma6_active,
500 dmc_txc_dma6_cacheready,
501 dmc_txc_dma6_descriptor,
502 dmc_txc_dma6_eoflist,
503 dmc_txc_dma6_error,
504 dmc_txc_dma6_func_num,
505 dmc_txc_dma6_gotnxtdesc,
506 dmc_txc_dma6_page_handle,
507 dmc_txc_dma6_partial,
508 dmc_txc_dma6_reset_scheduled,
509 dmc_txc_dma7_active,
510 dmc_txc_dma7_cacheready,
511 dmc_txc_dma7_descriptor,
512 dmc_txc_dma7_eoflist,
513 dmc_txc_dma7_error,
514 dmc_txc_dma7_func_num,
515 dmc_txc_dma7_gotnxtdesc,
516 dmc_txc_dma7_page_handle,
517 dmc_txc_dma7_partial,
518 dmc_txc_dma7_reset_scheduled,
519 dmc_txc_dma8_active,
520 dmc_txc_dma8_cacheready,
521 dmc_txc_dma8_descriptor,
522 dmc_txc_dma8_eoflist,
523 dmc_txc_dma8_error,
524 dmc_txc_dma8_func_num,
525 dmc_txc_dma8_gotnxtdesc,
526 dmc_txc_dma8_page_handle,
527 dmc_txc_dma8_partial,
528 dmc_txc_dma8_reset_scheduled,
529 dmc_txc_dma9_active,
530 dmc_txc_dma9_cacheready,
531 dmc_txc_dma9_descriptor,
532 dmc_txc_dma9_eoflist,
533 dmc_txc_dma9_error,
534 dmc_txc_dma9_func_num,
535 dmc_txc_dma9_gotnxtdesc,
536 dmc_txc_dma9_page_handle,
537 dmc_txc_dma9_partial,
538 dmc_txc_dma9_reset_scheduled,
539 dmc_txc_tx_addr_md,
540 dmc_zcp_req0,
541 dmc_zcp_req1,
542 efu_niu_4k_clr,
543 efu_niu_4k_data,
544 efu_niu_4k_xfer_en,
545 efu_niu_cfifo0_clr,
546 efu_niu_cfifo0_xfer_en,
547 efu_niu_cfifo1_clr,
548 efu_niu_cfifo1_xfer_en,
549 efu_niu_cfifo_data,
550 efu_niu_ipp0_clr,
551 efu_niu_ipp0_xfer_en,
552 efu_niu_ipp1_clr,
553 efu_niu_ipp1_xfer_en,
554 efu_niu_mac01_sfro_data,
555 efu_niu_mac0_ro_clr,
556 efu_niu_mac0_ro_xfer_en,
557 efu_niu_mac0_sf_clr,
558 efu_niu_mac0_sf_xfer_en,
559 efu_niu_mac1_ro_clr,
560 efu_niu_mac1_ro_xfer_en,
561 efu_niu_mac1_sf_clr,
562 efu_niu_mac1_sf_xfer_en,
563 gl_rtx_io2x_out,
564 gl_rtx_io_out,
565 mac_rxc_ack0,
566 mac_rxc_ack1,
567 mac_rxc_ctrl0,
568 mac_rxc_ctrl1,
569 mac_rxc_data0,
570 mac_rxc_data1,
571 mac_rxc_stat0,
572 mac_rxc_stat1,
573 mac_rxc_tag0,
574 mac_rxc_tag1,
575 mac_txc_req0,
576 mac_txc_req1,
577 meta_dmc_data,
578 meta_dmc_data_valid,
579 meta_dmc_resp_address,
580 meta_dmc_resp_byteenable,
581 meta_dmc_resp_client,
582 meta_dmc_resp_cmd,
583 meta_dmc_resp_cmd_status,
584 meta_dmc_resp_complete,
585 meta_dmc_resp_data_status,
586 meta_dmc_resp_dma_num,
587 meta_dmc_resp_length,
588 meta_dmc_resp_port_num,
589 meta_dmc_resp_ready,
590 meta_dmc_resp_trans_id,
591 meta_dmc_resp_transfer_cmpl,
592 pio_clients_addr,
593 pio_clients_rd,
594 pio_clients_wdata,
595 pio_fflp_sel,
596 pio_ipp_sel,
597 pio_txc_sel,
598 pio_zcp_sel,
599 rst_por_,
600 rtx_mbist_scan_in,
601 scan_in,
602 tcu_aclk,
603 tcu_atpg_mode,
604 tcu_bclk,
605 tcu_div_bypass,
606 tcu_mbist_bisi_en,
607 tcu_mbist_user_mode,
608 tcu_pce_ov,
609 tcu_rtx_dmo_ctl,
610 tcu_rtx_io_clk_stop,
611 tcu_rtx_rxc_ipp0_mbist_start,
612 tcu_rtx_rxc_ipp1_mbist_start,
613 tcu_rtx_rxc_mb5_mbist_start,
614 tcu_rtx_rxc_mb6_mbist_start,
615 tcu_rtx_rxc_zcp0_mbist_start,
616 tcu_rtx_rxc_zcp1_mbist_start,
617 tcu_rtx_txc_txe0_mbist_start,
618 tcu_rtx_txc_txe1_mbist_start,
619 tcu_scan_en,
620 tcu_se_scancollar_in,
621 tcu_se_scancollar_out,
622 tcu_wr_inhibit,
623 dmc_meta_resp_accept,
624 fflp_debug_port,
625 fflp_pio_ack,
626 fflp_pio_err,
627 fflp_pio_intr,
628 fflp_pio_rdata,
629 ipp_debug_port,
630 ipp_dmc_dat_ack0,
631 ipp_dmc_dat_ack1,
632 ipp_dmc_dat_err0,
633 ipp_dmc_dat_err1,
634 ipp_dmc_data0,
635 ipp_dmc_data1,
636 ipp_dmc_ful_pkt0,
637 ipp_dmc_ful_pkt1,
638 ipp_pio_ack,
639 ipp_pio_err,
640 ipp_pio_intr,
641 ipp_pio_rdata,
642 niu_efu_4k_data,
643 niu_efu_4k_xfer_en,
644 niu_efu_cfifo0_data,
645 niu_efu_cfifo0_xfer_en,
646 niu_efu_cfifo1_data,
647 niu_efu_cfifo1_xfer_en,
648 niu_efu_ipp0_data,
649 niu_efu_ipp0_xfer_en,
650 niu_efu_ipp1_data,
651 niu_efu_ipp1_xfer_en,
652 niu_efu_mac0_ro_data,
653 niu_efu_mac0_ro_xfer_en,
654 niu_efu_mac0_sf_data,
655 niu_efu_mac0_sf_xfer_en,
656 niu_efu_mac1_ro_data,
657 niu_efu_mac1_ro_xfer_en,
658 niu_efu_mac1_sf_data,
659 niu_efu_mac1_sf_xfer_en,
660 niu_txc_interrupts,
661 rtx_mbist_scan_out,
662 rtx_rxc_ipp0_tcu_mbist_done,
663 rtx_rxc_ipp0_tcu_mbist_fail,
664 rtx_rxc_ipp1_tcu_mbist_done,
665 rtx_rxc_ipp1_tcu_mbist_fail,
666 rtx_rxc_mb5_tcu_mbist_done,
667 rtx_rxc_mb5_tcu_mbist_fail,
668 rtx_rxc_mb6_tcu_mbist_done,
669 rtx_rxc_mb6_tcu_mbist_fail,
670 rtx_rxc_zcp0_tcu_mbist_done,
671 rtx_rxc_zcp0_tcu_mbist_fail,
672 rtx_rxc_zcp1_tcu_mbist_done,
673 rtx_rxc_zcp1_tcu_mbist_fail,
674 rtx_tcu_dmo_data_out,
675 rtx_txc_txe0_tcu_mbist_done,
676 rtx_txc_txe0_tcu_mbist_fail,
677 rtx_txc_txe1_tcu_mbist_done,
678 rtx_txc_txe1_tcu_mbist_fail,
679 rxc_mac_req0,
680 rxc_mac_req1,
681 scan_out,
682 txc_arb1_req,
683 txc_arb1_req_address,
684 txc_arb1_req_cmd,
685 txc_arb1_req_dma_num,
686 txc_arb1_req_func_num,
687 txc_arb1_req_length,
688 txc_arb1_req_port_num,
689 txc_debug_port,
690 txc_dmc_dma0_getnxtdesc,
691 txc_dmc_dma0_inc_head,
692 txc_dmc_dma0_inc_pkt_cnt,
693 txc_dmc_dma0_mark_bit,
694 txc_dmc_dma0_reset_done,
695 txc_dmc_dma10_getnxtdesc,
696 txc_dmc_dma10_inc_head,
697 txc_dmc_dma10_inc_pkt_cnt,
698 txc_dmc_dma10_mark_bit,
699 txc_dmc_dma10_reset_done,
700 txc_dmc_dma11_getnxtdesc,
701 txc_dmc_dma11_inc_head,
702 txc_dmc_dma11_inc_pkt_cnt,
703 txc_dmc_dma11_mark_bit,
704 txc_dmc_dma11_reset_done,
705 txc_dmc_dma12_getnxtdesc,
706 txc_dmc_dma12_inc_head,
707 txc_dmc_dma12_inc_pkt_cnt,
708 txc_dmc_dma12_mark_bit,
709 txc_dmc_dma12_reset_done,
710 txc_dmc_dma13_getnxtdesc,
711 txc_dmc_dma13_inc_head,
712 txc_dmc_dma13_inc_pkt_cnt,
713 txc_dmc_dma13_mark_bit,
714 txc_dmc_dma13_reset_done,
715 txc_dmc_dma14_getnxtdesc,
716 txc_dmc_dma14_inc_head,
717 txc_dmc_dma14_inc_pkt_cnt,
718 txc_dmc_dma14_mark_bit,
719 txc_dmc_dma14_reset_done,
720 txc_dmc_dma15_getnxtdesc,
721 txc_dmc_dma15_inc_head,
722 txc_dmc_dma15_inc_pkt_cnt,
723 txc_dmc_dma15_mark_bit,
724 txc_dmc_dma15_reset_done,
725 txc_dmc_dma1_getnxtdesc,
726 txc_dmc_dma1_inc_head,
727 txc_dmc_dma1_inc_pkt_cnt,
728 txc_dmc_dma1_mark_bit,
729 txc_dmc_dma1_reset_done,
730 txc_dmc_dma2_getnxtdesc,
731 txc_dmc_dma2_inc_head,
732 txc_dmc_dma2_inc_pkt_cnt,
733 txc_dmc_dma2_mark_bit,
734 txc_dmc_dma2_reset_done,
735 txc_dmc_dma3_getnxtdesc,
736 txc_dmc_dma3_inc_head,
737 txc_dmc_dma3_inc_pkt_cnt,
738 txc_dmc_dma3_mark_bit,
739 txc_dmc_dma3_reset_done,
740 txc_dmc_dma4_getnxtdesc,
741 txc_dmc_dma4_inc_head,
742 txc_dmc_dma4_inc_pkt_cnt,
743 txc_dmc_dma4_mark_bit,
744 txc_dmc_dma4_reset_done,
745 txc_dmc_dma5_getnxtdesc,
746 txc_dmc_dma5_inc_head,
747 txc_dmc_dma5_inc_pkt_cnt,
748 txc_dmc_dma5_mark_bit,
749 txc_dmc_dma5_reset_done,
750 txc_dmc_dma6_getnxtdesc,
751 txc_dmc_dma6_inc_head,
752 txc_dmc_dma6_inc_pkt_cnt,
753 txc_dmc_dma6_mark_bit,
754 txc_dmc_dma6_reset_done,
755 txc_dmc_dma7_getnxtdesc,
756 txc_dmc_dma7_inc_head,
757 txc_dmc_dma7_inc_pkt_cnt,
758 txc_dmc_dma7_mark_bit,
759 txc_dmc_dma7_reset_done,
760 txc_dmc_dma8_getnxtdesc,
761 txc_dmc_dma8_inc_head,
762 txc_dmc_dma8_inc_pkt_cnt,
763 txc_dmc_dma8_mark_bit,
764 txc_dmc_dma8_reset_done,
765 txc_dmc_dma9_getnxtdesc,
766 txc_dmc_dma9_inc_head,
767 txc_dmc_dma9_inc_pkt_cnt,
768 txc_dmc_dma9_mark_bit,
769 txc_dmc_dma9_reset_done,
770 txc_dmc_dma_nack_pkt_rd,
771 txc_dmc_nack_pkt_rd,
772 txc_dmc_nack_pkt_rd_addr,
773 txc_dmc_p0_dma_pkt_size_err,
774 txc_dmc_p0_pkt_size_err,
775 txc_dmc_p0_pkt_size_err_addr,
776 txc_dmc_p1_dma_pkt_size_err,
777 txc_dmc_p1_pkt_size_err,
778 txc_dmc_p1_pkt_size_err_addr,
779 txc_mac_abort0,
780 txc_mac_abort1,
781 txc_mac_ack0,
782 txc_mac_ack1,
783 txc_mac_data0,
784 txc_mac_data1,
785 txc_mac_stat0,
786 txc_mac_stat1,
787 txc_mac_tag0,
788 txc_mac_tag1,
789 txc_pio_ack,
790 txc_pio_err,
791 txc_pio_rdata,
792 zcp_debug_port,
793 zcp_dmc_ack0,
794 zcp_dmc_ack1,
795 zcp_dmc_dat0,
796 zcp_dmc_dat1,
797 zcp_dmc_dat_err0,
798 zcp_dmc_dat_err1,
799 zcp_dmc_ful_pkt0,
800 zcp_dmc_ful_pkt1,
801 zcp_pio_ack,
802 zcp_pio_err,
803 zcp_pio_intr,
804 zcp_pio_rdata
805 );
806
807input arb1_txc_req_accept;
808input [5:0] arb1_txc_req_transid;
809input cluster_arst_l;
810input cmp_gclk_c0_rtx;
811input dmc_ipp_dat_req0; // dmc request data from rxc_data_fifo_0
812input dmc_ipp_dat_req1; // dmc request data from rxc_data_fifo_1
813input dmc_txc_dma0_active;
814input dmc_txc_dma0_cacheready;
815input [63:0] dmc_txc_dma0_descriptor;
816input dmc_txc_dma0_eoflist;
817input dmc_txc_dma0_error;
818input [1:0] dmc_txc_dma0_func_num;
819input dmc_txc_dma0_gotnxtdesc;
820input [19:0] dmc_txc_dma0_page_handle;
821input dmc_txc_dma0_partial;
822input dmc_txc_dma0_reset_scheduled;
823input dmc_txc_dma10_active;
824input dmc_txc_dma10_cacheready;
825input [63:0] dmc_txc_dma10_descriptor;
826input dmc_txc_dma10_eoflist;
827input dmc_txc_dma10_error;
828input [1:0] dmc_txc_dma10_func_num;
829input dmc_txc_dma10_gotnxtdesc;
830input [19:0] dmc_txc_dma10_page_handle;
831input dmc_txc_dma10_partial;
832input dmc_txc_dma10_reset_scheduled;
833input dmc_txc_dma11_active;
834input dmc_txc_dma11_cacheready;
835input [63:0] dmc_txc_dma11_descriptor;
836input dmc_txc_dma11_eoflist;
837input dmc_txc_dma11_error;
838input [1:0] dmc_txc_dma11_func_num;
839input dmc_txc_dma11_gotnxtdesc;
840input [19:0] dmc_txc_dma11_page_handle;
841input dmc_txc_dma11_partial;
842input dmc_txc_dma11_reset_scheduled;
843input dmc_txc_dma12_active;
844input dmc_txc_dma12_cacheready;
845input [63:0] dmc_txc_dma12_descriptor;
846input dmc_txc_dma12_eoflist;
847input dmc_txc_dma12_error;
848input [1:0] dmc_txc_dma12_func_num;
849input dmc_txc_dma12_gotnxtdesc;
850input [19:0] dmc_txc_dma12_page_handle;
851input dmc_txc_dma12_partial;
852input dmc_txc_dma12_reset_scheduled;
853input dmc_txc_dma13_active;
854input dmc_txc_dma13_cacheready;
855input [63:0] dmc_txc_dma13_descriptor;
856input dmc_txc_dma13_eoflist;
857input dmc_txc_dma13_error;
858input [1:0] dmc_txc_dma13_func_num;
859input dmc_txc_dma13_gotnxtdesc;
860input [19:0] dmc_txc_dma13_page_handle;
861input dmc_txc_dma13_partial;
862input dmc_txc_dma13_reset_scheduled;
863input dmc_txc_dma14_active;
864input dmc_txc_dma14_cacheready;
865input [63:0] dmc_txc_dma14_descriptor;
866input dmc_txc_dma14_eoflist;
867input dmc_txc_dma14_error;
868input [1:0] dmc_txc_dma14_func_num;
869input dmc_txc_dma14_gotnxtdesc;
870input [19:0] dmc_txc_dma14_page_handle;
871input dmc_txc_dma14_partial;
872input dmc_txc_dma14_reset_scheduled;
873input dmc_txc_dma15_active;
874input dmc_txc_dma15_cacheready;
875input [63:0] dmc_txc_dma15_descriptor;
876input dmc_txc_dma15_eoflist;
877input dmc_txc_dma15_error;
878input [1:0] dmc_txc_dma15_func_num;
879input dmc_txc_dma15_gotnxtdesc;
880input [19:0] dmc_txc_dma15_page_handle;
881input dmc_txc_dma15_partial;
882input dmc_txc_dma15_reset_scheduled;
883input dmc_txc_dma1_active;
884input dmc_txc_dma1_cacheready;
885input [63:0] dmc_txc_dma1_descriptor;
886input dmc_txc_dma1_eoflist;
887input dmc_txc_dma1_error;
888input [1:0] dmc_txc_dma1_func_num;
889input dmc_txc_dma1_gotnxtdesc;
890input [19:0] dmc_txc_dma1_page_handle;
891input dmc_txc_dma1_partial;
892input dmc_txc_dma1_reset_scheduled;
893input dmc_txc_dma2_active;
894input dmc_txc_dma2_cacheready;
895input [63:0] dmc_txc_dma2_descriptor;
896input dmc_txc_dma2_eoflist;
897input dmc_txc_dma2_error;
898input [1:0] dmc_txc_dma2_func_num;
899input dmc_txc_dma2_gotnxtdesc;
900input [19:0] dmc_txc_dma2_page_handle;
901input dmc_txc_dma2_partial;
902input dmc_txc_dma2_reset_scheduled;
903input dmc_txc_dma3_active;
904input dmc_txc_dma3_cacheready;
905input [63:0] dmc_txc_dma3_descriptor;
906input dmc_txc_dma3_eoflist;
907input dmc_txc_dma3_error;
908input [1:0] dmc_txc_dma3_func_num;
909input dmc_txc_dma3_gotnxtdesc;
910input [19:0] dmc_txc_dma3_page_handle;
911input dmc_txc_dma3_partial;
912input dmc_txc_dma3_reset_scheduled;
913input dmc_txc_dma4_active;
914input dmc_txc_dma4_cacheready;
915input [63:0] dmc_txc_dma4_descriptor;
916input dmc_txc_dma4_eoflist;
917input dmc_txc_dma4_error;
918input [1:0] dmc_txc_dma4_func_num;
919input dmc_txc_dma4_gotnxtdesc;
920input [19:0] dmc_txc_dma4_page_handle;
921input dmc_txc_dma4_partial;
922input dmc_txc_dma4_reset_scheduled;
923input dmc_txc_dma5_active;
924input dmc_txc_dma5_cacheready;
925input [63:0] dmc_txc_dma5_descriptor;
926input dmc_txc_dma5_eoflist;
927input dmc_txc_dma5_error;
928input [1:0] dmc_txc_dma5_func_num;
929input dmc_txc_dma5_gotnxtdesc;
930input [19:0] dmc_txc_dma5_page_handle;
931input dmc_txc_dma5_partial;
932input dmc_txc_dma5_reset_scheduled;
933input dmc_txc_dma6_active;
934input dmc_txc_dma6_cacheready;
935input [63:0] dmc_txc_dma6_descriptor;
936input dmc_txc_dma6_eoflist;
937input dmc_txc_dma6_error;
938input [1:0] dmc_txc_dma6_func_num;
939input dmc_txc_dma6_gotnxtdesc;
940input [19:0] dmc_txc_dma6_page_handle;
941input dmc_txc_dma6_partial;
942input dmc_txc_dma6_reset_scheduled;
943input dmc_txc_dma7_active;
944input dmc_txc_dma7_cacheready;
945input [63:0] dmc_txc_dma7_descriptor;
946input dmc_txc_dma7_eoflist;
947input dmc_txc_dma7_error;
948input [1:0] dmc_txc_dma7_func_num;
949input dmc_txc_dma7_gotnxtdesc;
950input [19:0] dmc_txc_dma7_page_handle;
951input dmc_txc_dma7_partial;
952input dmc_txc_dma7_reset_scheduled;
953input dmc_txc_dma8_active;
954input dmc_txc_dma8_cacheready;
955input [63:0] dmc_txc_dma8_descriptor;
956input dmc_txc_dma8_eoflist;
957input dmc_txc_dma8_error;
958input [1:0] dmc_txc_dma8_func_num;
959input dmc_txc_dma8_gotnxtdesc;
960input [19:0] dmc_txc_dma8_page_handle;
961input dmc_txc_dma8_partial;
962input dmc_txc_dma8_reset_scheduled;
963input dmc_txc_dma9_active;
964input dmc_txc_dma9_cacheready;
965input [63:0] dmc_txc_dma9_descriptor;
966input dmc_txc_dma9_eoflist;
967input dmc_txc_dma9_error;
968input [1:0] dmc_txc_dma9_func_num;
969input dmc_txc_dma9_gotnxtdesc;
970input [19:0] dmc_txc_dma9_page_handle;
971input dmc_txc_dma9_partial;
972input dmc_txc_dma9_reset_scheduled;
973input dmc_txc_tx_addr_md;
974input dmc_zcp_req0;
975input dmc_zcp_req1;
976input efu_niu_4k_clr;
977input efu_niu_4k_data;
978input efu_niu_4k_xfer_en;
979input efu_niu_cfifo0_clr;
980input efu_niu_cfifo0_xfer_en;
981input efu_niu_cfifo1_clr;
982input efu_niu_cfifo1_xfer_en;
983input efu_niu_cfifo_data;
984input efu_niu_ipp0_clr;
985input efu_niu_ipp0_xfer_en;
986input efu_niu_ipp1_clr;
987input efu_niu_ipp1_xfer_en;
988input efu_niu_mac01_sfro_data;
989input efu_niu_mac0_ro_clr;
990input efu_niu_mac0_ro_xfer_en;
991input efu_niu_mac0_sf_clr;
992input efu_niu_mac0_sf_xfer_en;
993input efu_niu_mac1_ro_clr;
994input efu_niu_mac1_ro_xfer_en;
995input efu_niu_mac1_sf_clr;
996input efu_niu_mac1_sf_xfer_en;
997input gl_rtx_io2x_out;
998input gl_rtx_io_out;
999input mac_rxc_ack0; // xmac sends the ack to ipp
1000input mac_rxc_ack1; // xmac sends the ack to ipp
1001input mac_rxc_ctrl0; // active high for control information
1002input mac_rxc_ctrl1; // active high for control information
1003input [63:0] mac_rxc_data0; // xmac writing the data to ipp
1004input [63:0] mac_rxc_data1; // bmac writing the data to ipp
1005input [22:0] mac_rxc_stat0; // xmac writing the status to ipp
1006input [22:0] mac_rxc_stat1; // bmac writing the status to ipp
1007input mac_rxc_tag0; // xmac identifies the last part packet
1008input mac_rxc_tag1; // bmac identifies the last part packet
1009input mac_txc_req0;
1010input mac_txc_req1;
1011input [127:0] meta_dmc_data;
1012input meta_dmc_data_valid;
1013input [63:0] meta_dmc_resp_address;
1014input [15:0] meta_dmc_resp_byteenable;
1015input meta_dmc_resp_client;
1016input [7:0] meta_dmc_resp_cmd;
1017input [3:0] meta_dmc_resp_cmd_status;
1018input meta_dmc_resp_complete;
1019input [3:0] meta_dmc_resp_data_status;
1020input [4:0] meta_dmc_resp_dma_num;
1021input [13:0] meta_dmc_resp_length;
1022input [1:0] meta_dmc_resp_port_num;
1023input meta_dmc_resp_ready;
1024input [5:0] meta_dmc_resp_trans_id;
1025input meta_dmc_resp_transfer_cmpl;
1026input [19:0] pio_clients_addr;
1027input pio_clients_rd; // rd_wr
1028input [63:0] pio_clients_wdata;
1029input pio_fflp_sel; // select fflp's
1030input pio_ipp_sel; // select ipp's
1031input pio_txc_sel;
1032input pio_zcp_sel; // select zcp's
1033input rst_por_;
1034input rtx_mbist_scan_in;
1035input scan_in; // unused as of today - feb 10, 05
1036input tcu_aclk;
1037input tcu_atpg_mode;
1038input tcu_bclk;
1039input tcu_div_bypass; // bypasses clk divider to mux in ext clk
1040input tcu_mbist_bisi_en;
1041input tcu_mbist_user_mode;
1042input tcu_pce_ov;
1043input [2:0] tcu_rtx_dmo_ctl;
1044input tcu_rtx_io_clk_stop;
1045input tcu_rtx_rxc_ipp0_mbist_start;
1046input tcu_rtx_rxc_ipp1_mbist_start;
1047input tcu_rtx_rxc_mb5_mbist_start;
1048input tcu_rtx_rxc_mb6_mbist_start;
1049input tcu_rtx_rxc_zcp0_mbist_start;
1050input tcu_rtx_rxc_zcp1_mbist_start;
1051input tcu_rtx_txc_txe0_mbist_start;
1052input tcu_rtx_txc_txe1_mbist_start;
1053input tcu_scan_en;
1054input tcu_se_scancollar_in;
1055input tcu_se_scancollar_out;
1056input tcu_wr_inhibit;
1057output dmc_meta_resp_accept;
1058output [31:0] fflp_debug_port;
1059output fflp_pio_ack;
1060output fflp_pio_err;
1061output fflp_pio_intr;
1062output [63:0] fflp_pio_rdata;
1063output [31:0] ipp_debug_port;
1064output ipp_dmc_dat_ack0; // rxc_data_fifo_0 is sending data to dmc
1065output ipp_dmc_dat_ack1; // rxc_data_fifo_1 is sending data to dmc
1066output ipp_dmc_dat_err0; // rxc_data_fifo_0 data has error
1067output ipp_dmc_dat_err1; // rxc_data_fifo_1 data has ewrror
1068output [129:0] ipp_dmc_data0; // rxc_data_fifo_0's data to dmc
1069output [129:0] ipp_dmc_data1; // rxc_data_fifo_1's data to dmc
1070output ipp_dmc_ful_pkt0; // rxc_data_fifo_0 has at least 1 full packet
1071output ipp_dmc_ful_pkt1; // rxc_data_fifo_1 has at least 1 full packet
1072output ipp_pio_ack; // output to cpu
1073output ipp_pio_err;
1074output ipp_pio_intr;
1075output [63:0] ipp_pio_rdata;
1076output niu_efu_4k_data;
1077output niu_efu_4k_xfer_en;
1078output niu_efu_cfifo0_data;
1079output niu_efu_cfifo0_xfer_en;
1080output niu_efu_cfifo1_data;
1081output niu_efu_cfifo1_xfer_en;
1082output niu_efu_ipp0_data;
1083output niu_efu_ipp0_xfer_en;
1084output niu_efu_ipp1_data;
1085output niu_efu_ipp1_xfer_en;
1086output niu_efu_mac0_ro_data;
1087output niu_efu_mac0_ro_xfer_en;
1088output niu_efu_mac0_sf_data;
1089output niu_efu_mac0_sf_xfer_en;
1090output niu_efu_mac1_ro_data;
1091output niu_efu_mac1_ro_xfer_en;
1092output niu_efu_mac1_sf_data;
1093output niu_efu_mac1_sf_xfer_en;
1094output niu_txc_interrupts;
1095output rtx_mbist_scan_out;
1096output rtx_rxc_ipp0_tcu_mbist_done;
1097output rtx_rxc_ipp0_tcu_mbist_fail;
1098output rtx_rxc_ipp1_tcu_mbist_done;
1099output rtx_rxc_ipp1_tcu_mbist_fail;
1100output rtx_rxc_mb5_tcu_mbist_done;
1101output rtx_rxc_mb5_tcu_mbist_fail;
1102output rtx_rxc_mb6_tcu_mbist_done;
1103output rtx_rxc_mb6_tcu_mbist_fail;
1104output rtx_rxc_zcp0_tcu_mbist_done;
1105output rtx_rxc_zcp0_tcu_mbist_fail;
1106output rtx_rxc_zcp1_tcu_mbist_done;
1107output rtx_rxc_zcp1_tcu_mbist_fail;
1108output [39:0] rtx_tcu_dmo_data_out;
1109output rtx_txc_txe0_tcu_mbist_done;
1110output rtx_txc_txe0_tcu_mbist_fail;
1111output rtx_txc_txe1_tcu_mbist_done;
1112output rtx_txc_txe1_tcu_mbist_fail;
1113output rxc_mac_req0; // req(as rdy) from ipp to xmac
1114output rxc_mac_req1; // ack from ipp to bmac
1115output scan_out; // unused as of today - feb 10, 05
1116output txc_arb1_req;
1117output [63:0] txc_arb1_req_address;
1118output [7:0] txc_arb1_req_cmd;
1119output [4:0] txc_arb1_req_dma_num;
1120output [1:0] txc_arb1_req_func_num;
1121output [13:0] txc_arb1_req_length;
1122output [1:0] txc_arb1_req_port_num;
1123output [31:0] txc_debug_port;
1124output txc_dmc_dma0_getnxtdesc;
1125output txc_dmc_dma0_inc_head;
1126output txc_dmc_dma0_inc_pkt_cnt;
1127output txc_dmc_dma0_mark_bit;
1128output txc_dmc_dma0_reset_done;
1129output txc_dmc_dma10_getnxtdesc;
1130output txc_dmc_dma10_inc_head;
1131output txc_dmc_dma10_inc_pkt_cnt;
1132output txc_dmc_dma10_mark_bit;
1133output txc_dmc_dma10_reset_done;
1134output txc_dmc_dma11_getnxtdesc;
1135output txc_dmc_dma11_inc_head;
1136output txc_dmc_dma11_inc_pkt_cnt;
1137output txc_dmc_dma11_mark_bit;
1138output txc_dmc_dma11_reset_done;
1139output txc_dmc_dma12_getnxtdesc;
1140output txc_dmc_dma12_inc_head;
1141output txc_dmc_dma12_inc_pkt_cnt;
1142output txc_dmc_dma12_mark_bit;
1143output txc_dmc_dma12_reset_done;
1144output txc_dmc_dma13_getnxtdesc;
1145output txc_dmc_dma13_inc_head;
1146output txc_dmc_dma13_inc_pkt_cnt;
1147output txc_dmc_dma13_mark_bit;
1148output txc_dmc_dma13_reset_done;
1149output txc_dmc_dma14_getnxtdesc;
1150output txc_dmc_dma14_inc_head;
1151output txc_dmc_dma14_inc_pkt_cnt;
1152output txc_dmc_dma14_mark_bit;
1153output txc_dmc_dma14_reset_done;
1154output txc_dmc_dma15_getnxtdesc;
1155output txc_dmc_dma15_inc_head;
1156output txc_dmc_dma15_inc_pkt_cnt;
1157output txc_dmc_dma15_mark_bit;
1158output txc_dmc_dma15_reset_done;
1159output txc_dmc_dma1_getnxtdesc;
1160output txc_dmc_dma1_inc_head;
1161output txc_dmc_dma1_inc_pkt_cnt;
1162output txc_dmc_dma1_mark_bit;
1163output txc_dmc_dma1_reset_done;
1164output txc_dmc_dma2_getnxtdesc;
1165output txc_dmc_dma2_inc_head;
1166output txc_dmc_dma2_inc_pkt_cnt;
1167output txc_dmc_dma2_mark_bit;
1168output txc_dmc_dma2_reset_done;
1169output txc_dmc_dma3_getnxtdesc;
1170output txc_dmc_dma3_inc_head;
1171output txc_dmc_dma3_inc_pkt_cnt;
1172output txc_dmc_dma3_mark_bit;
1173output txc_dmc_dma3_reset_done;
1174output txc_dmc_dma4_getnxtdesc;
1175output txc_dmc_dma4_inc_head;
1176output txc_dmc_dma4_inc_pkt_cnt;
1177output txc_dmc_dma4_mark_bit;
1178output txc_dmc_dma4_reset_done;
1179output txc_dmc_dma5_getnxtdesc;
1180output txc_dmc_dma5_inc_head;
1181output txc_dmc_dma5_inc_pkt_cnt;
1182output txc_dmc_dma5_mark_bit;
1183output txc_dmc_dma5_reset_done;
1184output txc_dmc_dma6_getnxtdesc;
1185output txc_dmc_dma6_inc_head;
1186output txc_dmc_dma6_inc_pkt_cnt;
1187output txc_dmc_dma6_mark_bit;
1188output txc_dmc_dma6_reset_done;
1189output txc_dmc_dma7_getnxtdesc;
1190output txc_dmc_dma7_inc_head;
1191output txc_dmc_dma7_inc_pkt_cnt;
1192output txc_dmc_dma7_mark_bit;
1193output txc_dmc_dma7_reset_done;
1194output txc_dmc_dma8_getnxtdesc;
1195output txc_dmc_dma8_inc_head;
1196output txc_dmc_dma8_inc_pkt_cnt;
1197output txc_dmc_dma8_mark_bit;
1198output txc_dmc_dma8_reset_done;
1199output txc_dmc_dma9_getnxtdesc;
1200output txc_dmc_dma9_inc_head;
1201output txc_dmc_dma9_inc_pkt_cnt;
1202output txc_dmc_dma9_mark_bit;
1203output txc_dmc_dma9_reset_done;
1204output [15:0] txc_dmc_dma_nack_pkt_rd;
1205output txc_dmc_nack_pkt_rd;
1206output [43:0] txc_dmc_nack_pkt_rd_addr;
1207output [15:0] txc_dmc_p0_dma_pkt_size_err;
1208output txc_dmc_p0_pkt_size_err;
1209output [43:0] txc_dmc_p0_pkt_size_err_addr;
1210output [15:0] txc_dmc_p1_dma_pkt_size_err;
1211output txc_dmc_p1_pkt_size_err;
1212output [43:0] txc_dmc_p1_pkt_size_err_addr;
1213output txc_mac_abort0;
1214output txc_mac_abort1;
1215output txc_mac_ack0;
1216output txc_mac_ack1;
1217output [63:0] txc_mac_data0;
1218output [63:0] txc_mac_data1;
1219output [3:0] txc_mac_stat0;
1220output [3:0] txc_mac_stat1;
1221output txc_mac_tag0;
1222output txc_mac_tag1;
1223output txc_pio_ack;
1224output txc_pio_err;
1225output [63:0] txc_pio_rdata;
1226output [31:0] zcp_debug_port;
1227output zcp_dmc_ack0;
1228output zcp_dmc_ack1;
1229output [129:0] zcp_dmc_dat0;
1230output [129:0] zcp_dmc_dat1;
1231output zcp_dmc_dat_err0;
1232output zcp_dmc_dat_err1;
1233output zcp_dmc_ful_pkt0;
1234output zcp_dmc_ful_pkt1;
1235output zcp_pio_ack;
1236output zcp_pio_err;
1237output zcp_pio_intr;
1238output [63:0] zcp_pio_rdata;
1239
1240wire [39:0] rtx_rxc_ipp0_mb3_dmo_dout;
1241wire [39:0] rtx_rxc_ipp1_mb3_dmo_dout;
1242wire [39:0] rtx_rxc_vlan_mb6_dmo_dout;
1243wire [39:0] rtx_rxc_zcp0_mb7_dmo_dout;
1244wire [39:0] rtx_rxc_zcp1_mb7_dmo_dout;
1245wire [39:0] rtx_txc_txe0_dmo_dout;
1246wire [39:0] rtx_txc_txe1_dmo_dout;
1247wire aclk;
1248wire bclk;
1249wire clkgen2x_rtx_scan_out;
1250wire clkgen_rtx_scan_out;
1251wire efuhdr_ipp0_scan_out;
1252wire efuhdr_ipp1_scan_out;
1253wire efuhdr_txc0_re_scan_out;
1254wire efuhdr_txc0_st_scan_out;
1255wire efuhdr_txc1_re_scan_out;
1256wire efuhdr_txc1_st_scan_out;
1257wire efuhdr_vlan_scan_out;
1258wire efuhdr_zcp0_scan_out;
1259wire efuhdr_zcp1_scan_out;
1260wire hdr_sram_red_clr_ipp0;
1261wire hdr_sram_red_clr_ipp1;
1262wire hdr_sram_red_clr_txc0_re;
1263wire hdr_sram_red_clr_txc0_st;
1264wire hdr_sram_red_clr_txc1_re;
1265wire hdr_sram_red_clr_txc1_st;
1266wire hdr_sram_red_clr_vlan;
1267wire hdr_sram_red_clr_zcp0;
1268wire hdr_sram_red_clr_zcp1;
1269wire [2:0] hdr_sram_rid_ipp0;
1270wire [2:0] hdr_sram_rid_ipp1;
1271wire [2:0] hdr_sram_rid_txc0_re;
1272wire [2:0] hdr_sram_rid_txc0_st;
1273wire [2:0] hdr_sram_rid_txc1_re;
1274wire [2:0] hdr_sram_rid_txc1_st;
1275wire hdr_sram_rid_vlan;
1276wire [1:0] hdr_sram_rid_zcp0;
1277wire [1:0] hdr_sram_rid_zcp1;
1278wire [6:0] hdr_sram_rvalue_ipp0;
1279wire [6:0] hdr_sram_rvalue_ipp1;
1280wire [6:0] hdr_sram_rvalue_txc0_re;
1281wire [6:0] hdr_sram_rvalue_txc0_st;
1282wire [6:0] hdr_sram_rvalue_txc1_re;
1283wire [6:0] hdr_sram_rvalue_txc1_st;
1284wire [5:0] hdr_sram_rvalue_vlan;
1285wire [6:0] hdr_sram_rvalue_zcp0;
1286wire [6:0] hdr_sram_rvalue_zcp1;
1287wire hdr_sram_wr_en_ipp0;
1288wire hdr_sram_wr_en_ipp1;
1289wire hdr_sram_wr_en_txc0_re;
1290wire hdr_sram_wr_en_txc0_st;
1291wire hdr_sram_wr_en_txc1_re;
1292wire hdr_sram_wr_en_txc1_st;
1293wire hdr_sram_wr_en_vlan;
1294wire hdr_sram_wr_en_zcp0;
1295wire hdr_sram_wr_en_zcp1;
1296wire iol2clk;
1297wire l1clk;
1298wire l1clk_2x;
1299wire [9:0] nc100;
1300wire [3:0] nc40;
1301wire [3:0] nc41;
1302wire [3:0] nc42;
1303wire [3:0] nc43;
1304wire [3:0] nc44;
1305wire [3:0] nc45;
1306wire [3:0] nc46;
1307wire [3:0] nc47;
1308wire [4:0] nc50;
1309wire [7:0] nc80;
1310wire [7:0] nc81;
1311wire [7:0] nc82;
1312wire [7:0] nc83;
1313wire [7:0] nc84;
1314wire [7:0] nc85;
1315wire [8:0] nc90;
1316wire [8:0] nc91;
1317wire niu_mb3_prebuf_header_scan_out;
1318wire niu_mb3_rx_data_fifo_scan_out;
1319wire niu_mb4_prebuf_header_scan_out;
1320wire niu_mb4_rx_data_fifo_scan_out;
1321wire niu_mb5_tcam_cntrl_scan_out;
1322wire niu_mb6_tcam_array_scan_out;
1323wire niu_mb6_vlan_scan_out;
1324wire niu_mb7_cntrl_fifo_zcp_scan_out;
1325wire pce_ov;
1326wire reset_l;
1327wire rtx_array_wr_inhibit;
1328wire rtx_rxc_ipp0_mb3_mbist_scan_out;
1329wire rtx_rxc_ipp1_mb3_mbist_scan_out;
1330wire rtx_rxc_tcam_cntrl_mbist_scan_out;
1331wire rtx_rxc_tcam_vlan_mbist_scan_out;
1332wire rtx_rxc_zcp0_mb7_mbist_scan_out;
1333wire rtx_rxc_zcp1_mb7_mbist_scan_out;
1334wire rtx_txc_txe0_mbist_scan_out;
1335wire [6:0] sram_hdr_read_data_ipp0;
1336wire [6:0] sram_hdr_read_data_ipp1;
1337wire [6:0] sram_hdr_read_data_txc0_re;
1338wire [6:0] sram_hdr_read_data_txc0_st;
1339wire [6:0] sram_hdr_read_data_txc1_re;
1340wire [6:0] sram_hdr_read_data_txc1_st;
1341wire [5:0] sram_hdr_read_data_vlan;
1342wire [6:0] sram_hdr_read_data_zcp0;
1343wire [6:0] sram_hdr_read_data_zcp1;
1344
1345clkgen_rtx clkgen_rtx (
1346 .array_wr_inhibit (rtx_array_wr_inhibit),
1347 .l1clk (l1clk),
1348 .iol2clk (iol2clk),
1349 .aclk (aclk),
1350 .bclk (bclk),
1351 .scan_out (clkgen_rtx_scan_out),
1352 .aclk_wmr (),
1353 .pce_ov (pce_ov),
1354 .wmr_protect (),
1355 .wmr_ (),
1356 .por_ (reset_l),
1357 .cmp_slow_sync_en (),
1358 .slow_cmp_sync_en (),
1359 .tcu_wr_inhibit (tcu_wr_inhibit),
1360 .tcu_atpg_mode (tcu_atpg_mode),
1361 .tcu_clk_stop (tcu_rtx_io_clk_stop),
1362 .tcu_pce_ov (tcu_pce_ov),
1363 .rst_wmr_protect (1'b0),
1364 .rst_wmr_ (1'b1),
1365 .rst_por_ (rst_por_),
1366 .tcu_div_bypass (tcu_div_bypass),
1367 .ccu_div_ph (gl_rtx_io_out),
1368 .cluster_div_en (1'b1),
1369 .gclk (cmp_gclk_c0_rtx),
1370 .cluster_arst_l (cluster_arst_l),
1371 .scan_en (tcu_scan_en),
1372 .scan_in (scan_in),
1373 .tcu_aclk (tcu_aclk),
1374 .tcu_bclk (tcu_bclk)
1375 );
1376
1377clkgen_rtx_io2x clkgen2x_rtx (
1378 .l2clk (l1clk_2x),
1379 .aclk (),
1380 .bclk (),
1381 .scan_out (clkgen2x_rtx_scan_out),
1382 .aclk_wmr (),
1383 .pce_ov (),
1384 .wmr_protect (),
1385 .wmr_ (),
1386 .por_ (),
1387 .cmp_slow_sync_en (),
1388 .slow_cmp_sync_en (),
1389 .array_wr_inhibit (),
1390 .tcu_atpg_mode (tcu_atpg_mode),
1391 .tcu_wr_inhibit (1'b0),
1392 .tcu_clk_stop (tcu_rtx_io_clk_stop),
1393 .tcu_pce_ov (pce_ov),
1394 .rst_wmr_protect (1'b0),
1395 .rst_wmr_ (1'b1),
1396 .rst_por_ (rst_por_),
1397 .ccu_cmp_slow_sync_en (1'b0),
1398 .ccu_slow_cmp_sync_en (1'b0),
1399 .tcu_div_bypass (tcu_div_bypass),
1400 .ccu_div_ph (gl_rtx_io2x_out),
1401 .cluster_div_en (1'b1),
1402 .gclk (cmp_gclk_c0_rtx),
1403 .cluster_arst_l (cluster_arst_l),
1404 .ccu_serdes_dtm (1'b0),
1405 .clk_ext (1'b0),
1406 .scan_en (tcu_scan_en),
1407 .scan_in (clkgen_rtx_scan_out),
1408 .tcu_aclk (aclk),
1409 .tcu_bclk (bclk)
1410 );
1411
1412rtx_n2_efuhdr3_p0_ctl efuhdr_ipp0 (
1413 .efu_hdr_write_data (efu_niu_mac01_sfro_data),
1414 .efu_hdr_xfer_en (efu_niu_ipp0_xfer_en),
1415 .efu_hdr_clr (efu_niu_ipp0_clr),
1416 .hdr_efu_read_data (niu_efu_ipp0_data),
1417 .hdr_efu_xfer_en (niu_efu_ipp0_xfer_en),
1418 .hdr_sram_rvalue ({nc40,hdr_sram_rvalue_ipp0[6:0]}),
1419 .hdr_sram_rid ({nc80,hdr_sram_rid_ipp0[2:0]}),
1420 .hdr_sram_wr_en (hdr_sram_wr_en_ipp0),
1421 .hdr_sram_red_clr (hdr_sram_red_clr_ipp0),
1422 .sram_hdr_read_data ({4'b0,sram_hdr_read_data_ipp0[6:0]}),
1423 .l2clk (l1clk),
1424 .reset_l (reset_l),
1425 .tcu_pce_ov (tcu_pce_ov),
1426 .tcu_aclk (aclk),
1427 .tcu_bclk (bclk),
1428 .tcu_scan_en (tcu_scan_en),
1429 .tcu_clk_stop (tcu_rtx_io_clk_stop),
1430 .scan_in (clkgen2x_rtx_scan_out),
1431 .scan_out (efuhdr_ipp0_scan_out)
1432 );
1433
1434rtx_n2_efuhdr3_p1_ctl efuhdr_ipp1 (
1435 .efu_hdr_write_data (efu_niu_mac01_sfro_data),
1436 .efu_hdr_xfer_en (efu_niu_ipp1_xfer_en),
1437 .efu_hdr_clr (efu_niu_ipp1_clr),
1438 .hdr_efu_read_data (niu_efu_ipp1_data),
1439 .hdr_efu_xfer_en (niu_efu_ipp1_xfer_en),
1440 .hdr_sram_rvalue ({nc41,hdr_sram_rvalue_ipp1[6:0]}),
1441 .hdr_sram_rid ({nc81,hdr_sram_rid_ipp1[2:0]}),
1442 .hdr_sram_wr_en (hdr_sram_wr_en_ipp1),
1443 .hdr_sram_red_clr (hdr_sram_red_clr_ipp1),
1444 .sram_hdr_read_data ({4'b0,sram_hdr_read_data_ipp1[6:0]}),
1445 .l2clk (l1clk),
1446 .reset_l (reset_l),
1447 .tcu_pce_ov (tcu_pce_ov),
1448 .tcu_aclk (aclk),
1449 .tcu_bclk (bclk),
1450 .tcu_scan_en (tcu_scan_en),
1451 .tcu_clk_stop (tcu_rtx_io_clk_stop),
1452 .scan_in (efuhdr_ipp0_scan_out),
1453 .scan_out (efuhdr_ipp1_scan_out)
1454 );
1455
1456rtx_n2_efuhdr1b_p0_ctl efuhdr_txc0_re (
1457 .efu_hdr_write_data (efu_niu_mac01_sfro_data),
1458 .efu_hdr_xfer_en (efu_niu_mac0_ro_xfer_en),
1459 .efu_hdr_clr (efu_niu_mac0_ro_clr),
1460 .hdr_efu_read_data (niu_efu_mac0_ro_data),
1461 .hdr_efu_xfer_en (niu_efu_mac0_ro_xfer_en),
1462 .hdr_sram_rvalue ({nc42,hdr_sram_rvalue_txc0_re[6:0]}),
1463 .hdr_sram_rid ({nc82,hdr_sram_rid_txc0_re[2:0]}),
1464 .hdr_sram_wr_en (hdr_sram_wr_en_txc0_re),
1465 .hdr_sram_red_clr (hdr_sram_red_clr_txc0_re),
1466 .sram_hdr_read_data ({4'b0,sram_hdr_read_data_txc0_re[6:0]}),
1467 .l2clk (l1clk),
1468 .reset_l (reset_l),
1469 .tcu_pce_ov (tcu_pce_ov),
1470 .tcu_aclk (aclk),
1471 .tcu_bclk (bclk),
1472 .tcu_scan_en (tcu_scan_en),
1473 .tcu_clk_stop (tcu_rtx_io_clk_stop),
1474 .scan_in (efuhdr_ipp1_scan_out),
1475 .scan_out (efuhdr_txc0_re_scan_out)
1476 );
1477
1478rtx_n2_efuhdr1a_p0_ctl efuhdr_txc0_st (
1479 .efu_hdr_write_data (efu_niu_mac01_sfro_data),
1480 .efu_hdr_xfer_en (efu_niu_mac0_sf_xfer_en),
1481 .efu_hdr_clr (efu_niu_mac0_sf_clr),
1482 .hdr_efu_read_data (niu_efu_mac0_sf_data),
1483 .hdr_efu_xfer_en (niu_efu_mac0_sf_xfer_en),
1484 .hdr_sram_rvalue ({nc44,hdr_sram_rvalue_txc0_st[6:0]}),
1485 .hdr_sram_rid ({nc84,hdr_sram_rid_txc0_st[2:0]}),
1486 .hdr_sram_wr_en (hdr_sram_wr_en_txc0_st),
1487 .hdr_sram_red_clr (hdr_sram_red_clr_txc0_st),
1488 .sram_hdr_read_data ({4'b0,sram_hdr_read_data_txc0_st[6:0]}),
1489 .l2clk (l1clk),
1490 .reset_l (reset_l),
1491 .tcu_pce_ov (tcu_pce_ov),
1492 .tcu_aclk (aclk),
1493 .tcu_bclk (bclk),
1494 .tcu_scan_en (tcu_scan_en),
1495 .tcu_clk_stop (tcu_rtx_io_clk_stop),
1496 .scan_in (efuhdr_txc0_re_scan_out),
1497 .scan_out (efuhdr_txc0_st_scan_out)
1498 );
1499
1500rtx_n2_efuhdr1b_p1_ctl efuhdr_txc1_re (
1501 .efu_hdr_write_data (efu_niu_mac01_sfro_data),
1502 .efu_hdr_xfer_en (efu_niu_mac1_ro_xfer_en),
1503 .efu_hdr_clr (efu_niu_mac1_ro_clr),
1504 .hdr_efu_read_data (niu_efu_mac1_ro_data),
1505 .hdr_efu_xfer_en (niu_efu_mac1_ro_xfer_en),
1506 .hdr_sram_rvalue ({nc43,hdr_sram_rvalue_txc1_re[6:0]}),
1507 .hdr_sram_rid ({nc83,hdr_sram_rid_txc1_re[2:0]}),
1508 .hdr_sram_wr_en (hdr_sram_wr_en_txc1_re),
1509 .hdr_sram_red_clr (hdr_sram_red_clr_txc1_re),
1510 .sram_hdr_read_data ({4'b0,sram_hdr_read_data_txc1_re[6:0]}),
1511 .l2clk (l1clk),
1512 .reset_l (reset_l),
1513 .tcu_pce_ov (tcu_pce_ov),
1514 .tcu_aclk (aclk),
1515 .tcu_bclk (bclk),
1516 .tcu_scan_en (tcu_scan_en),
1517 .tcu_clk_stop (tcu_rtx_io_clk_stop),
1518 .scan_in (efuhdr_txc0_st_scan_out),
1519 .scan_out (efuhdr_txc1_re_scan_out)
1520 );
1521
1522rtx_n2_efuhdr1a_p1_ctl efuhdr_txc1_st (
1523 .efu_hdr_write_data (efu_niu_mac01_sfro_data),
1524 .efu_hdr_xfer_en (efu_niu_mac1_sf_xfer_en),
1525 .efu_hdr_clr (efu_niu_mac1_sf_clr),
1526 .hdr_efu_read_data (niu_efu_mac1_sf_data),
1527 .hdr_efu_xfer_en (niu_efu_mac1_sf_xfer_en),
1528 .hdr_sram_rvalue ({nc45,hdr_sram_rvalue_txc1_st[6:0]}),
1529 .hdr_sram_rid ({nc85,hdr_sram_rid_txc1_st[2:0]}),
1530 .hdr_sram_wr_en (hdr_sram_wr_en_txc1_st),
1531 .hdr_sram_red_clr (hdr_sram_red_clr_txc1_st),
1532 .sram_hdr_read_data ({4'b0,sram_hdr_read_data_txc1_st[6:0]}),
1533 .l2clk (l1clk),
1534 .reset_l (reset_l),
1535 .tcu_pce_ov (tcu_pce_ov),
1536 .tcu_aclk (aclk),
1537 .tcu_bclk (bclk),
1538 .tcu_scan_en (tcu_scan_en),
1539 .tcu_clk_stop (tcu_rtx_io_clk_stop),
1540 .scan_in (efuhdr_txc1_re_scan_out),
1541 .scan_out (efuhdr_txc1_st_scan_out)
1542 );
1543
1544rtx_n2_efuhdr6_ctl efuhdr_vlan (
1545 .efu_hdr_write_data (efu_niu_4k_data),
1546 .efu_hdr_xfer_en (efu_niu_4k_xfer_en),
1547 .efu_hdr_clr (efu_niu_4k_clr),
1548 .hdr_efu_read_data (niu_efu_4k_data),
1549 .hdr_efu_xfer_en (niu_efu_4k_xfer_en),
1550 .hdr_sram_rvalue ({nc50,hdr_sram_rvalue_vlan[5:0]}),
1551 .hdr_sram_rid ({nc100,hdr_sram_rid_vlan}),
1552 .hdr_sram_wr_en (hdr_sram_wr_en_vlan),
1553 .hdr_sram_red_clr (hdr_sram_red_clr_vlan),
1554 .sram_hdr_read_data ({5'b0,sram_hdr_read_data_vlan[5:0]}),
1555 .l2clk (l1clk),
1556 .reset_l (reset_l),
1557 .tcu_pce_ov (tcu_pce_ov),
1558 .tcu_aclk (aclk),
1559 .tcu_bclk (bclk),
1560 .tcu_scan_en (tcu_scan_en),
1561 .tcu_clk_stop (tcu_rtx_io_clk_stop),
1562 .scan_in (efuhdr_txc1_st_scan_out),
1563 .scan_out (efuhdr_vlan_scan_out)
1564 );
1565
1566rtx_n2_efuhdr7_p0_ctl efuhdr_zcp0 (
1567 .efu_hdr_write_data (efu_niu_cfifo_data),
1568 .efu_hdr_xfer_en (efu_niu_cfifo0_xfer_en),
1569 .efu_hdr_clr (efu_niu_cfifo0_clr),
1570 .hdr_efu_read_data (niu_efu_cfifo0_data),
1571 .hdr_efu_xfer_en (niu_efu_cfifo0_xfer_en),
1572 .hdr_sram_rvalue ({nc46,hdr_sram_rvalue_zcp0[6:0]}),
1573 .hdr_sram_rid ({nc90,hdr_sram_rid_zcp0[1:0]}),
1574 .hdr_sram_wr_en (hdr_sram_wr_en_zcp0),
1575 .hdr_sram_red_clr (hdr_sram_red_clr_zcp0),
1576 .sram_hdr_read_data ({4'b0,sram_hdr_read_data_zcp0[6:0]}),
1577 .l2clk (l1clk),
1578 .reset_l (reset_l),
1579 .tcu_pce_ov (tcu_pce_ov),
1580 .tcu_aclk (aclk),
1581 .tcu_bclk (bclk),
1582 .tcu_scan_en (tcu_scan_en),
1583 .tcu_clk_stop (tcu_rtx_io_clk_stop),
1584 .scan_in (efuhdr_vlan_scan_out),
1585 .scan_out (efuhdr_zcp0_scan_out)
1586 );
1587
1588rtx_n2_efuhdr7_p1_ctl efuhdr_zcp1 (
1589 .efu_hdr_write_data (efu_niu_cfifo_data),
1590 .efu_hdr_xfer_en (efu_niu_cfifo1_xfer_en),
1591 .efu_hdr_clr (efu_niu_cfifo1_clr),
1592 .hdr_efu_read_data (niu_efu_cfifo1_data),
1593 .hdr_efu_xfer_en (niu_efu_cfifo1_xfer_en),
1594 .hdr_sram_rvalue ({nc47,hdr_sram_rvalue_zcp1[6:0]}),
1595 .hdr_sram_rid ({nc91,hdr_sram_rid_zcp1[1:0]}),
1596 .hdr_sram_wr_en (hdr_sram_wr_en_zcp1),
1597 .hdr_sram_red_clr (hdr_sram_red_clr_zcp1),
1598 .sram_hdr_read_data ({4'b0,sram_hdr_read_data_zcp1[6:0]}),
1599 .l2clk (l1clk),
1600 .reset_l (reset_l),
1601 .tcu_pce_ov (tcu_pce_ov),
1602 .tcu_aclk (aclk),
1603 .tcu_bclk (bclk),
1604 .tcu_scan_en (tcu_scan_en),
1605 .tcu_clk_stop (tcu_rtx_io_clk_stop),
1606 .scan_in (efuhdr_zcp0_scan_out),
1607 .scan_out (efuhdr_zcp1_scan_out)
1608 );
1609
1610niu_rxc rxc (
1611 .tcu_mbist_user_mode (tcu_mbist_user_mode),
1612 .tcu_scan_en (tcu_scan_en),
1613 .tcu_mbist_bisi_en (tcu_mbist_bisi_en),
1614 .tcu_rtx_rxc_ipp0_mbist_start (tcu_rtx_rxc_ipp0_mbist_start),
1615 .tcu_rtx_rxc_ipp1_mbist_start (tcu_rtx_rxc_ipp1_mbist_start),
1616 .tcu_rtx_rxc_mb5_mbist_start (tcu_rtx_rxc_mb5_mbist_start),
1617 .tcu_rtx_rxc_mb6_mbist_start (tcu_rtx_rxc_mb6_mbist_start),
1618 .tcu_rtx_rxc_zcp0_mbist_start (tcu_rtx_rxc_zcp0_mbist_start),
1619 .tcu_rtx_rxc_zcp1_mbist_start (tcu_rtx_rxc_zcp1_mbist_start),
1620 .rtx_rxc_ipp0_tcu_mbist_fail (rtx_rxc_ipp0_tcu_mbist_fail),
1621 .rtx_rxc_ipp1_tcu_mbist_fail (rtx_rxc_ipp1_tcu_mbist_fail),
1622 .rtx_rxc_mb5_tcu_mbist_fail (rtx_rxc_mb5_tcu_mbist_fail),
1623 .rtx_rxc_mb6_tcu_mbist_fail (rtx_rxc_mb6_tcu_mbist_fail),
1624 .rtx_rxc_zcp0_tcu_mbist_fail (rtx_rxc_zcp0_tcu_mbist_fail),
1625 .rtx_rxc_zcp1_tcu_mbist_fail (rtx_rxc_zcp1_tcu_mbist_fail),
1626 .rtx_rxc_ipp0_tcu_mbist_done (rtx_rxc_ipp0_tcu_mbist_done),
1627 .rtx_rxc_ipp1_tcu_mbist_done (rtx_rxc_ipp1_tcu_mbist_done),
1628 .rtx_rxc_mb5_tcu_mbist_done (rtx_rxc_mb5_tcu_mbist_done),
1629 .rtx_rxc_mb6_tcu_mbist_done (rtx_rxc_mb6_tcu_mbist_done),
1630 .rtx_rxc_zcp0_tcu_mbist_done (rtx_rxc_zcp0_tcu_mbist_done),
1631 .rtx_rxc_zcp1_tcu_mbist_done (rtx_rxc_zcp1_tcu_mbist_done),
1632 .niu_mb3_prebuf_header_scan_in (niu_mb3_rx_data_fifo_scan_out),
1633 .niu_mb3_prebuf_header_scan_out (niu_mb3_prebuf_header_scan_out),
1634 .niu_mb3_rx_data_fifo_scan_in (efuhdr_zcp1_scan_out),
1635 .niu_mb3_rx_data_fifo_scan_out (niu_mb3_rx_data_fifo_scan_out),
1636 .rtx_rxc_ipp0_mb3_mbist_scan_in (rtx_mbist_scan_in),
1637 .rtx_rxc_ipp0_mb3_mbist_scan_out (rtx_rxc_ipp0_mb3_mbist_scan_out),
1638 .rtx_rxc_ipp0_mb3_dmo_dout (rtx_rxc_ipp0_mb3_dmo_dout[39:0]),
1639 .niu_mb4_prebuf_header_scan_in (niu_mb4_rx_data_fifo_scan_out),
1640 .niu_mb4_prebuf_header_scan_out (niu_mb4_prebuf_header_scan_out),
1641 .niu_mb4_rx_data_fifo_scan_in (niu_mb3_prebuf_header_scan_out),
1642 .niu_mb4_rx_data_fifo_scan_out (niu_mb4_rx_data_fifo_scan_out),
1643 .rtx_rxc_ipp1_mb3_mbist_scan_in (rtx_rxc_ipp0_mb3_mbist_scan_out),
1644 .rtx_rxc_ipp1_mb3_mbist_scan_out (rtx_rxc_ipp1_mb3_mbist_scan_out),
1645 .rtx_rxc_ipp1_mb3_dmo_dout (rtx_rxc_ipp1_mb3_dmo_dout[39:0]),
1646 .niu_mb5_tcam_cntrl_scan_in (niu_mb4_prebuf_header_scan_out),
1647 .niu_mb5_tcam_cntrl_scan_out (niu_mb5_tcam_cntrl_scan_out),
1648 .rtx_rxc_tcam_cntrl_mbist_scan_in (rtx_rxc_ipp1_mb3_mbist_scan_out),
1649 .rtx_rxc_tcam_cntrl_mbist_scan_out (rtx_rxc_tcam_cntrl_mbist_scan_out),
1650 .niu_mb6_tcam_array_scan_in (niu_mb5_tcam_cntrl_scan_out),
1651 .niu_mb6_tcam_array_scan_out (niu_mb6_tcam_array_scan_out),
1652 .niu_mb6_vlan_scan_in (niu_mb6_tcam_array_scan_out),
1653 .niu_mb6_vlan_scan_out (niu_mb6_vlan_scan_out),
1654 .rtx_rxc_tcam_vlan_mbist_scan_in (rtx_rxc_tcam_cntrl_mbist_scan_out),
1655 .rtx_rxc_tcam_vlan_mbist_scan_out (rtx_rxc_tcam_vlan_mbist_scan_out),
1656 .rtx_rxc_vlan_mb6_dmo_dout (rtx_rxc_vlan_mb6_dmo_dout[39:0]),
1657 .niu_mb7_cntrl_fifo_zcp_scan_in (niu_mb6_vlan_scan_out),
1658 .niu_mb7_cntrl_fifo_zcp_scan_out (niu_mb7_cntrl_fifo_zcp_scan_out),
1659 .rtx_rxc_zcp0_mb7_mbist_scan_in (rtx_rxc_tcam_vlan_mbist_scan_out),
1660 .rtx_rxc_zcp0_mb7_mbist_scan_out (rtx_rxc_zcp0_mb7_mbist_scan_out),
1661 .rtx_rxc_zcp0_mb7_dmo_dout (rtx_rxc_zcp0_mb7_dmo_dout[39:0]),
1662 .niu_mb8_cntrl_fifo_zcp_scan_in (niu_mb7_cntrl_fifo_zcp_scan_out),
1663 .niu_mb8_cntrl_fifo_zcp_scan_out (scan_out),
1664 .rtx_rxc_zcp1_mb7_mbist_scan_in (rtx_rxc_zcp0_mb7_mbist_scan_out),
1665 .rtx_rxc_zcp1_mb7_mbist_scan_out (rtx_rxc_zcp1_mb7_mbist_scan_out),
1666 .rtx_rxc_zcp1_mb7_dmo_dout (rtx_rxc_zcp1_mb7_dmo_dout[39:0]),
1667 .hdr_sram_rvalue_ipp0 (hdr_sram_rvalue_ipp0[6:0]),
1668 .hdr_sram_rid_ipp0 (hdr_sram_rid_ipp0[2:0]),
1669 .hdr_sram_wr_en_ipp0 (hdr_sram_wr_en_ipp0),
1670 .hdr_sram_red_clr_ipp0 (hdr_sram_red_clr_ipp0),
1671 .sram_hdr_read_data_ipp0 (sram_hdr_read_data_ipp0[6:0]),
1672 .hdr_sram_rvalue_ipp1 (hdr_sram_rvalue_ipp1[6:0]),
1673 .hdr_sram_rid_ipp1 (hdr_sram_rid_ipp1[2:0]),
1674 .hdr_sram_wr_en_ipp1 (hdr_sram_wr_en_ipp1),
1675 .hdr_sram_red_clr_ipp1 (hdr_sram_red_clr_ipp1),
1676 .sram_hdr_read_data_ipp1 (sram_hdr_read_data_ipp1[6:0]),
1677 .hdr_sram_rvalue_zcp0 (hdr_sram_rvalue_zcp0[6:0]),
1678 .hdr_sram_rid_zcp0 (hdr_sram_rid_zcp0[1:0]),
1679 .hdr_sram_wr_en_zcp0 (hdr_sram_wr_en_zcp0),
1680 .hdr_sram_red_clr_zcp0 (hdr_sram_red_clr_zcp0),
1681 .sram_hdr_read_data_zcp0 (sram_hdr_read_data_zcp0[6:0]),
1682 .hdr_sram_rvalue_zcp1 (hdr_sram_rvalue_zcp1[6:0]),
1683 .hdr_sram_rid_zcp1 (hdr_sram_rid_zcp1[1:0]),
1684 .hdr_sram_wr_en_zcp1 (hdr_sram_wr_en_zcp1),
1685 .hdr_sram_red_clr_zcp1 (hdr_sram_red_clr_zcp1),
1686 .sram_hdr_read_data_zcp1 (sram_hdr_read_data_zcp1[6:0]),
1687 .hdr_sram_rvalue_vlan (hdr_sram_rvalue_vlan[5:0]),
1688 .hdr_sram_rid_vlan (hdr_sram_rid_vlan),
1689 .hdr_sram_wr_en_vlan (hdr_sram_wr_en_vlan),
1690 .hdr_sram_red_clr_vlan (hdr_sram_red_clr_vlan),
1691 .sram_hdr_read_data_vlan (sram_hdr_read_data_vlan[5:0]),
1692 .tcu_aclk (aclk),
1693 .tcu_bclk (bclk),
1694 .tcu_se_scancollar_in (tcu_se_scancollar_in),
1695 .tcu_se_scancollar_out (tcu_se_scancollar_out),
1696 .tcu_array_wr_inhibit (rtx_array_wr_inhibit),
1697 .iol2clk (iol2clk),
1698 .iol2clk_2x (l1clk_2x),
1699 .pio_ipp_sel (pio_ipp_sel),
1700 .pio_zcp_sel (pio_zcp_sel),
1701 .pio_fflp_sel (pio_fflp_sel),
1702 .pio_clients_addr (pio_clients_addr[19:0]),
1703 .pio_clients_rd (pio_clients_rd),
1704 .pio_clients_wdata (pio_clients_wdata[63:0]),
1705 .niu_reset_l (reset_l),
1706 .niu_clk (l1clk),
1707 .ipp_pio_ack (ipp_pio_ack),
1708 .ipp_pio_rdata (ipp_pio_rdata[63:0]),
1709 .ipp_pio_err (ipp_pio_err),
1710 .ipp_pio_intr (ipp_pio_intr),
1711 .ipp_debug_port (ipp_debug_port[31:0]),
1712 .zcp_pio_ack (zcp_pio_ack),
1713 .zcp_pio_rdata (zcp_pio_rdata[63:0]),
1714 .zcp_pio_err (zcp_pio_err),
1715 .zcp_pio_intr (zcp_pio_intr),
1716 .zcp_debug_port (zcp_debug_port[31:0]),
1717 .fflp_pio_rdata (fflp_pio_rdata[63:0]),
1718 .fflp_pio_ack (fflp_pio_ack),
1719 .fflp_pio_err (fflp_pio_err),
1720 .fflp_pio_intr (fflp_pio_intr),
1721 .fflp_debug_port (fflp_debug_port[31:0]),
1722 .mac_rxc_ack0 (mac_rxc_ack0),
1723 .mac_rxc_tag0 (mac_rxc_tag0),
1724 .mac_rxc_data0 (mac_rxc_data0[63:0]),
1725 .mac_rxc_ctrl0 (mac_rxc_ctrl0),
1726 .mac_rxc_stat0 (mac_rxc_stat0[22:0]),
1727 .dmc_ipp_dat_req0 (dmc_ipp_dat_req0),
1728 .rxc_mac_req0 (rxc_mac_req0),
1729 .ipp_dmc_dat_ack0 (ipp_dmc_dat_ack0),
1730 .ipp_dmc_data0 (ipp_dmc_data0[129:0]),
1731 .ipp_dmc_ful_pkt0 (ipp_dmc_ful_pkt0),
1732 .ipp_dmc_dat_err0 (ipp_dmc_dat_err0),
1733 .mac_rxc_ack1 (mac_rxc_ack1),
1734 .mac_rxc_tag1 (mac_rxc_tag1),
1735 .mac_rxc_data1 (mac_rxc_data1[63:0]),
1736 .mac_rxc_ctrl1 (mac_rxc_ctrl1),
1737 .mac_rxc_stat1 (mac_rxc_stat1[22:0]),
1738 .dmc_ipp_dat_req1 (dmc_ipp_dat_req1),
1739 .rxc_mac_req1 (rxc_mac_req1),
1740 .ipp_dmc_dat_ack1 (ipp_dmc_dat_ack1),
1741 .ipp_dmc_data1 (ipp_dmc_data1[129:0]),
1742 .ipp_dmc_ful_pkt1 (ipp_dmc_ful_pkt1),
1743 .ipp_dmc_dat_err1 (ipp_dmc_dat_err1),
1744 .dmc_zcp_req0 (dmc_zcp_req0),
1745 .zcp_dmc_ack0 (zcp_dmc_ack0),
1746 .zcp_dmc_dat0 (zcp_dmc_dat0[129:0]),
1747 .zcp_dmc_dat_err0 (zcp_dmc_dat_err0),
1748 .zcp_dmc_ful_pkt0 (zcp_dmc_ful_pkt0),
1749 .dmc_zcp_req1 (dmc_zcp_req1),
1750 .zcp_dmc_ack1 (zcp_dmc_ack1),
1751 .zcp_dmc_dat1 (zcp_dmc_dat1[129:0]),
1752 .zcp_dmc_dat_err1 (zcp_dmc_dat_err1),
1753 .zcp_dmc_ful_pkt1 (zcp_dmc_ful_pkt1)
1754 );
1755
1756niu_txc txc (
1757 .niu_clk (l1clk),
1758 .niu_reset_l (reset_l),
1759 .iol2clk (iol2clk),
1760 .l2clk_2x (l1clk_2x),
1761 .tcu_aclk (aclk),
1762 .tcu_bclk (bclk),
1763 .tcu_mbist_bisi_en (tcu_mbist_bisi_en),
1764 .tcu_scan_en (tcu_scan_en),
1765 .tcu_se_scancollar_in (tcu_se_scancollar_in),
1766 .tcu_se_scancollar_out (tcu_se_scancollar_out),
1767 .tcu_array_wr_inhibit (rtx_array_wr_inhibit),
1768 .tcu_mbist_user_mode (tcu_mbist_user_mode),
1769 .tcu_rtx_txc_txe0_mbist_start (tcu_rtx_txc_txe0_mbist_start),
1770 .rtx_txc_txe0_mbist_scan_in (rtx_rxc_zcp1_mb7_mbist_scan_out),
1771 .rtx_txc_txe0_tcu_mbist_fail (rtx_txc_txe0_tcu_mbist_fail),
1772 .rtx_txc_txe0_tcu_mbist_done (rtx_txc_txe0_tcu_mbist_done),
1773 .rtx_txc_txe0_mbist_scan_out (rtx_txc_txe0_mbist_scan_out),
1774 .rtx_txc_txe0_dmo_dout (rtx_txc_txe0_dmo_dout[39:0]),
1775 .tcu_rtx_txc_txe1_mbist_start (tcu_rtx_txc_txe1_mbist_start),
1776 .rtx_txc_txe1_mbist_scan_in (rtx_txc_txe0_mbist_scan_out),
1777 .rtx_txc_txe1_tcu_mbist_fail (rtx_txc_txe1_tcu_mbist_fail),
1778 .rtx_txc_txe1_tcu_mbist_done (rtx_txc_txe1_tcu_mbist_done),
1779 .rtx_txc_txe1_mbist_scan_out (rtx_mbist_scan_out),
1780 .rtx_txc_txe1_dmo_dout (rtx_txc_txe1_dmo_dout[39:0]),
1781 .hdr_sram_wr_en_txc0_re (hdr_sram_wr_en_txc0_re),
1782 .hdr_sram_red_clr_txc0_re (hdr_sram_red_clr_txc0_re),
1783 .hdr_sram_wr_en_txc0_st (hdr_sram_wr_en_txc0_st),
1784 .hdr_sram_red_clr_txc0_st (hdr_sram_red_clr_txc0_st),
1785 .hdr_sram_rid_txc0_re (hdr_sram_rid_txc0_re[2:0]),
1786 .hdr_sram_rid_txc0_st (hdr_sram_rid_txc0_st[2:0]),
1787 .hdr_sram_rvalue_txc0_re (hdr_sram_rvalue_txc0_re[6:0]),
1788 .hdr_sram_rvalue_txc0_st (hdr_sram_rvalue_txc0_st[6:0]),
1789 .sram_hdr_read_data_txc0_re (sram_hdr_read_data_txc0_re[6:0]),
1790 .sram_hdr_read_data_txc0_st (sram_hdr_read_data_txc0_st[6:0]),
1791 .hdr_sram_wr_en_txc1_re (hdr_sram_wr_en_txc1_re),
1792 .hdr_sram_red_clr_txc1_re (hdr_sram_red_clr_txc1_re),
1793 .hdr_sram_wr_en_txc1_st (hdr_sram_wr_en_txc1_st),
1794 .hdr_sram_red_clr_txc1_st (hdr_sram_red_clr_txc1_st),
1795 .hdr_sram_rid_txc1_re (hdr_sram_rid_txc1_re[2:0]),
1796 .hdr_sram_rid_txc1_st (hdr_sram_rid_txc1_st[2:0]),
1797 .hdr_sram_rvalue_txc1_re (hdr_sram_rvalue_txc1_re[6:0]),
1798 .hdr_sram_rvalue_txc1_st (hdr_sram_rvalue_txc1_st[6:0]),
1799 .sram_hdr_read_data_txc1_re (sram_hdr_read_data_txc1_re[6:0]),
1800 .sram_hdr_read_data_txc1_st (sram_hdr_read_data_txc1_st[6:0]),
1801 .txc_debug_port (txc_debug_port[31:0]),
1802 .pio_clients_rd (pio_clients_rd),
1803 .pio_txc_sel (pio_txc_sel),
1804 .pio_clients_addr (pio_clients_addr[19:0]),
1805 .pio_clients_wdata (pio_clients_wdata[31:0]),
1806 .txc_pio_ack (txc_pio_ack),
1807 .txc_pio_err (txc_pio_err),
1808 .niu_txc_interrupts (niu_txc_interrupts),
1809 .txc_pio_rdata (txc_pio_rdata[63:0]),
1810 .mac_txc_req0 (mac_txc_req0),
1811 .txc_mac_ack0 (txc_mac_ack0),
1812 .txc_mac_tag0 (txc_mac_tag0),
1813 .txc_mac_abort0 (txc_mac_abort0),
1814 .txc_mac_stat0 (txc_mac_stat0[3:0]),
1815 .txc_mac_data0 (txc_mac_data0[63:0]),
1816 .mac_txc_req1 (mac_txc_req1),
1817 .txc_mac_ack1 (txc_mac_ack1),
1818 .txc_mac_tag1 (txc_mac_tag1),
1819 .txc_mac_abort1 (txc_mac_abort1),
1820 .txc_mac_stat1 (txc_mac_stat1[3:0]),
1821 .txc_mac_data1 (txc_mac_data1[63:0]),
1822 .txc_dmc_p0_pkt_size_err (txc_dmc_p0_pkt_size_err),
1823 .txc_dmc_p0_pkt_size_err_addr (txc_dmc_p0_pkt_size_err_addr[43:0]),
1824 .txc_dmc_p1_pkt_size_err (txc_dmc_p1_pkt_size_err),
1825 .txc_dmc_p1_pkt_size_err_addr (txc_dmc_p1_pkt_size_err_addr[43:0]),
1826 .txc_dmc_nack_pkt_rd (txc_dmc_nack_pkt_rd),
1827 .txc_dmc_nack_pkt_rd_addr (txc_dmc_nack_pkt_rd_addr[43:0]),
1828 .txc_dmc_p0_dma_pkt_size_err (txc_dmc_p0_dma_pkt_size_err[15:0]),
1829 .txc_dmc_p1_dma_pkt_size_err (txc_dmc_p1_dma_pkt_size_err[15:0]),
1830 .txc_dmc_dma_nack_pkt_rd (txc_dmc_dma_nack_pkt_rd[15:0]),
1831 .dmc_txc_tx_addr_md (dmc_txc_tx_addr_md),
1832 .dmc_txc_dma0_active (dmc_txc_dma0_active),
1833 .dmc_txc_dma0_eoflist (dmc_txc_dma0_eoflist),
1834 .dmc_txc_dma0_error (dmc_txc_dma0_error),
1835 .dmc_txc_dma0_gotnxtdesc (dmc_txc_dma0_gotnxtdesc),
1836 .dmc_txc_dma0_cacheready (dmc_txc_dma0_cacheready),
1837 .dmc_txc_dma0_partial (dmc_txc_dma0_partial),
1838 .dmc_txc_dma0_reset_scheduled (dmc_txc_dma0_reset_scheduled),
1839 .dmc_txc_dma0_func_num (dmc_txc_dma0_func_num[1:0]),
1840 .dmc_txc_dma0_page_handle (dmc_txc_dma0_page_handle[19:0]),
1841 .dmc_txc_dma0_descriptor (dmc_txc_dma0_descriptor[63:0]),
1842 .txc_dmc_dma0_getnxtdesc (txc_dmc_dma0_getnxtdesc),
1843 .txc_dmc_dma0_inc_head (txc_dmc_dma0_inc_head),
1844 .txc_dmc_dma0_reset_done (txc_dmc_dma0_reset_done),
1845 .txc_dmc_dma0_mark_bit (txc_dmc_dma0_mark_bit),
1846 .txc_dmc_dma0_inc_pkt_cnt (txc_dmc_dma0_inc_pkt_cnt),
1847 .dmc_txc_dma1_active (dmc_txc_dma1_active),
1848 .dmc_txc_dma1_eoflist (dmc_txc_dma1_eoflist),
1849 .dmc_txc_dma1_error (dmc_txc_dma1_error),
1850 .dmc_txc_dma1_gotnxtdesc (dmc_txc_dma1_gotnxtdesc),
1851 .dmc_txc_dma1_cacheready (dmc_txc_dma1_cacheready),
1852 .dmc_txc_dma1_partial (dmc_txc_dma1_partial),
1853 .dmc_txc_dma1_reset_scheduled (dmc_txc_dma1_reset_scheduled),
1854 .dmc_txc_dma1_func_num (dmc_txc_dma1_func_num[1:0]),
1855 .dmc_txc_dma1_page_handle (dmc_txc_dma1_page_handle[19:0]),
1856 .dmc_txc_dma1_descriptor (dmc_txc_dma1_descriptor[63:0]),
1857 .txc_dmc_dma1_getnxtdesc (txc_dmc_dma1_getnxtdesc),
1858 .txc_dmc_dma1_inc_head (txc_dmc_dma1_inc_head),
1859 .txc_dmc_dma1_reset_done (txc_dmc_dma1_reset_done),
1860 .txc_dmc_dma1_mark_bit (txc_dmc_dma1_mark_bit),
1861 .txc_dmc_dma1_inc_pkt_cnt (txc_dmc_dma1_inc_pkt_cnt),
1862 .dmc_txc_dma2_active (dmc_txc_dma2_active),
1863 .dmc_txc_dma2_eoflist (dmc_txc_dma2_eoflist),
1864 .dmc_txc_dma2_error (dmc_txc_dma2_error),
1865 .dmc_txc_dma2_gotnxtdesc (dmc_txc_dma2_gotnxtdesc),
1866 .dmc_txc_dma2_cacheready (dmc_txc_dma2_cacheready),
1867 .dmc_txc_dma2_partial (dmc_txc_dma2_partial),
1868 .dmc_txc_dma2_reset_scheduled (dmc_txc_dma2_reset_scheduled),
1869 .dmc_txc_dma2_func_num (dmc_txc_dma2_func_num[1:0]),
1870 .dmc_txc_dma2_page_handle (dmc_txc_dma2_page_handle[19:0]),
1871 .dmc_txc_dma2_descriptor (dmc_txc_dma2_descriptor[63:0]),
1872 .txc_dmc_dma2_getnxtdesc (txc_dmc_dma2_getnxtdesc),
1873 .txc_dmc_dma2_inc_head (txc_dmc_dma2_inc_head),
1874 .txc_dmc_dma2_reset_done (txc_dmc_dma2_reset_done),
1875 .txc_dmc_dma2_mark_bit (txc_dmc_dma2_mark_bit),
1876 .txc_dmc_dma2_inc_pkt_cnt (txc_dmc_dma2_inc_pkt_cnt),
1877 .dmc_txc_dma3_active (dmc_txc_dma3_active),
1878 .dmc_txc_dma3_eoflist (dmc_txc_dma3_eoflist),
1879 .dmc_txc_dma3_error (dmc_txc_dma3_error),
1880 .dmc_txc_dma3_gotnxtdesc (dmc_txc_dma3_gotnxtdesc),
1881 .dmc_txc_dma3_cacheready (dmc_txc_dma3_cacheready),
1882 .dmc_txc_dma3_partial (dmc_txc_dma3_partial),
1883 .dmc_txc_dma3_reset_scheduled (dmc_txc_dma3_reset_scheduled),
1884 .dmc_txc_dma3_func_num (dmc_txc_dma3_func_num[1:0]),
1885 .dmc_txc_dma3_page_handle (dmc_txc_dma3_page_handle[19:0]),
1886 .dmc_txc_dma3_descriptor (dmc_txc_dma3_descriptor[63:0]),
1887 .txc_dmc_dma3_getnxtdesc (txc_dmc_dma3_getnxtdesc),
1888 .txc_dmc_dma3_inc_head (txc_dmc_dma3_inc_head),
1889 .txc_dmc_dma3_reset_done (txc_dmc_dma3_reset_done),
1890 .txc_dmc_dma3_mark_bit (txc_dmc_dma3_mark_bit),
1891 .txc_dmc_dma3_inc_pkt_cnt (txc_dmc_dma3_inc_pkt_cnt),
1892 .dmc_txc_dma4_active (dmc_txc_dma4_active),
1893 .dmc_txc_dma4_eoflist (dmc_txc_dma4_eoflist),
1894 .dmc_txc_dma4_error (dmc_txc_dma4_error),
1895 .dmc_txc_dma4_gotnxtdesc (dmc_txc_dma4_gotnxtdesc),
1896 .dmc_txc_dma4_cacheready (dmc_txc_dma4_cacheready),
1897 .dmc_txc_dma4_partial (dmc_txc_dma4_partial),
1898 .dmc_txc_dma4_reset_scheduled (dmc_txc_dma4_reset_scheduled),
1899 .dmc_txc_dma4_func_num (dmc_txc_dma4_func_num[1:0]),
1900 .dmc_txc_dma4_page_handle (dmc_txc_dma4_page_handle[19:0]),
1901 .dmc_txc_dma4_descriptor (dmc_txc_dma4_descriptor[63:0]),
1902 .txc_dmc_dma4_getnxtdesc (txc_dmc_dma4_getnxtdesc),
1903 .txc_dmc_dma4_inc_head (txc_dmc_dma4_inc_head),
1904 .txc_dmc_dma4_reset_done (txc_dmc_dma4_reset_done),
1905 .txc_dmc_dma4_mark_bit (txc_dmc_dma4_mark_bit),
1906 .txc_dmc_dma4_inc_pkt_cnt (txc_dmc_dma4_inc_pkt_cnt),
1907 .dmc_txc_dma5_active (dmc_txc_dma5_active),
1908 .dmc_txc_dma5_eoflist (dmc_txc_dma5_eoflist),
1909 .dmc_txc_dma5_error (dmc_txc_dma5_error),
1910 .dmc_txc_dma5_gotnxtdesc (dmc_txc_dma5_gotnxtdesc),
1911 .dmc_txc_dma5_cacheready (dmc_txc_dma5_cacheready),
1912 .dmc_txc_dma5_partial (dmc_txc_dma5_partial),
1913 .dmc_txc_dma5_reset_scheduled (dmc_txc_dma5_reset_scheduled),
1914 .dmc_txc_dma5_func_num (dmc_txc_dma5_func_num[1:0]),
1915 .dmc_txc_dma5_page_handle (dmc_txc_dma5_page_handle[19:0]),
1916 .dmc_txc_dma5_descriptor (dmc_txc_dma5_descriptor[63:0]),
1917 .txc_dmc_dma5_getnxtdesc (txc_dmc_dma5_getnxtdesc),
1918 .txc_dmc_dma5_inc_head (txc_dmc_dma5_inc_head),
1919 .txc_dmc_dma5_reset_done (txc_dmc_dma5_reset_done),
1920 .txc_dmc_dma5_mark_bit (txc_dmc_dma5_mark_bit),
1921 .txc_dmc_dma5_inc_pkt_cnt (txc_dmc_dma5_inc_pkt_cnt),
1922 .dmc_txc_dma6_active (dmc_txc_dma6_active),
1923 .dmc_txc_dma6_eoflist (dmc_txc_dma6_eoflist),
1924 .dmc_txc_dma6_error (dmc_txc_dma6_error),
1925 .dmc_txc_dma6_gotnxtdesc (dmc_txc_dma6_gotnxtdesc),
1926 .dmc_txc_dma6_cacheready (dmc_txc_dma6_cacheready),
1927 .dmc_txc_dma6_partial (dmc_txc_dma6_partial),
1928 .dmc_txc_dma6_reset_scheduled (dmc_txc_dma6_reset_scheduled),
1929 .dmc_txc_dma6_func_num (dmc_txc_dma6_func_num[1:0]),
1930 .dmc_txc_dma6_page_handle (dmc_txc_dma6_page_handle[19:0]),
1931 .dmc_txc_dma6_descriptor (dmc_txc_dma6_descriptor[63:0]),
1932 .txc_dmc_dma6_getnxtdesc (txc_dmc_dma6_getnxtdesc),
1933 .txc_dmc_dma6_inc_head (txc_dmc_dma6_inc_head),
1934 .txc_dmc_dma6_reset_done (txc_dmc_dma6_reset_done),
1935 .txc_dmc_dma6_mark_bit (txc_dmc_dma6_mark_bit),
1936 .txc_dmc_dma6_inc_pkt_cnt (txc_dmc_dma6_inc_pkt_cnt),
1937 .dmc_txc_dma7_active (dmc_txc_dma7_active),
1938 .dmc_txc_dma7_eoflist (dmc_txc_dma7_eoflist),
1939 .dmc_txc_dma7_error (dmc_txc_dma7_error),
1940 .dmc_txc_dma7_gotnxtdesc (dmc_txc_dma7_gotnxtdesc),
1941 .dmc_txc_dma7_cacheready (dmc_txc_dma7_cacheready),
1942 .dmc_txc_dma7_partial (dmc_txc_dma7_partial),
1943 .dmc_txc_dma7_reset_scheduled (dmc_txc_dma7_reset_scheduled),
1944 .dmc_txc_dma7_func_num (dmc_txc_dma7_func_num[1:0]),
1945 .dmc_txc_dma7_page_handle (dmc_txc_dma7_page_handle[19:0]),
1946 .dmc_txc_dma7_descriptor (dmc_txc_dma7_descriptor[63:0]),
1947 .txc_dmc_dma7_getnxtdesc (txc_dmc_dma7_getnxtdesc),
1948 .txc_dmc_dma7_inc_head (txc_dmc_dma7_inc_head),
1949 .txc_dmc_dma7_reset_done (txc_dmc_dma7_reset_done),
1950 .txc_dmc_dma7_mark_bit (txc_dmc_dma7_mark_bit),
1951 .txc_dmc_dma7_inc_pkt_cnt (txc_dmc_dma7_inc_pkt_cnt),
1952 .dmc_txc_dma8_active (dmc_txc_dma8_active),
1953 .dmc_txc_dma8_eoflist (dmc_txc_dma8_eoflist),
1954 .dmc_txc_dma8_error (dmc_txc_dma8_error),
1955 .dmc_txc_dma8_gotnxtdesc (dmc_txc_dma8_gotnxtdesc),
1956 .dmc_txc_dma8_cacheready (dmc_txc_dma8_cacheready),
1957 .dmc_txc_dma8_partial (dmc_txc_dma8_partial),
1958 .dmc_txc_dma8_reset_scheduled (dmc_txc_dma8_reset_scheduled),
1959 .dmc_txc_dma8_func_num (dmc_txc_dma8_func_num[1:0]),
1960 .dmc_txc_dma8_page_handle (dmc_txc_dma8_page_handle[19:0]),
1961 .dmc_txc_dma8_descriptor (dmc_txc_dma8_descriptor[63:0]),
1962 .txc_dmc_dma8_getnxtdesc (txc_dmc_dma8_getnxtdesc),
1963 .txc_dmc_dma8_inc_head (txc_dmc_dma8_inc_head),
1964 .txc_dmc_dma8_reset_done (txc_dmc_dma8_reset_done),
1965 .txc_dmc_dma8_mark_bit (txc_dmc_dma8_mark_bit),
1966 .txc_dmc_dma8_inc_pkt_cnt (txc_dmc_dma8_inc_pkt_cnt),
1967 .dmc_txc_dma9_active (dmc_txc_dma9_active),
1968 .dmc_txc_dma9_eoflist (dmc_txc_dma9_eoflist),
1969 .dmc_txc_dma9_error (dmc_txc_dma9_error),
1970 .dmc_txc_dma9_gotnxtdesc (dmc_txc_dma9_gotnxtdesc),
1971 .dmc_txc_dma9_cacheready (dmc_txc_dma9_cacheready),
1972 .dmc_txc_dma9_partial (dmc_txc_dma9_partial),
1973 .dmc_txc_dma9_reset_scheduled (dmc_txc_dma9_reset_scheduled),
1974 .dmc_txc_dma9_func_num (dmc_txc_dma9_func_num[1:0]),
1975 .dmc_txc_dma9_page_handle (dmc_txc_dma9_page_handle[19:0]),
1976 .dmc_txc_dma9_descriptor (dmc_txc_dma9_descriptor[63:0]),
1977 .txc_dmc_dma9_getnxtdesc (txc_dmc_dma9_getnxtdesc),
1978 .txc_dmc_dma9_inc_head (txc_dmc_dma9_inc_head),
1979 .txc_dmc_dma9_reset_done (txc_dmc_dma9_reset_done),
1980 .txc_dmc_dma9_mark_bit (txc_dmc_dma9_mark_bit),
1981 .txc_dmc_dma9_inc_pkt_cnt (txc_dmc_dma9_inc_pkt_cnt),
1982 .dmc_txc_dma10_active (dmc_txc_dma10_active),
1983 .dmc_txc_dma10_eoflist (dmc_txc_dma10_eoflist),
1984 .dmc_txc_dma10_error (dmc_txc_dma10_error),
1985 .dmc_txc_dma10_gotnxtdesc (dmc_txc_dma10_gotnxtdesc),
1986 .dmc_txc_dma10_cacheready (dmc_txc_dma10_cacheready),
1987 .dmc_txc_dma10_partial (dmc_txc_dma10_partial),
1988 .dmc_txc_dma10_reset_scheduled (dmc_txc_dma10_reset_scheduled),
1989 .dmc_txc_dma10_func_num (dmc_txc_dma10_func_num[1:0]),
1990 .dmc_txc_dma10_page_handle (dmc_txc_dma10_page_handle[19:0]),
1991 .dmc_txc_dma10_descriptor (dmc_txc_dma10_descriptor[63:0]),
1992 .txc_dmc_dma10_getnxtdesc (txc_dmc_dma10_getnxtdesc),
1993 .txc_dmc_dma10_inc_head (txc_dmc_dma10_inc_head),
1994 .txc_dmc_dma10_reset_done (txc_dmc_dma10_reset_done),
1995 .txc_dmc_dma10_mark_bit (txc_dmc_dma10_mark_bit),
1996 .txc_dmc_dma10_inc_pkt_cnt (txc_dmc_dma10_inc_pkt_cnt),
1997 .dmc_txc_dma11_active (dmc_txc_dma11_active),
1998 .dmc_txc_dma11_eoflist (dmc_txc_dma11_eoflist),
1999 .dmc_txc_dma11_error (dmc_txc_dma11_error),
2000 .dmc_txc_dma11_gotnxtdesc (dmc_txc_dma11_gotnxtdesc),
2001 .dmc_txc_dma11_cacheready (dmc_txc_dma11_cacheready),
2002 .dmc_txc_dma11_partial (dmc_txc_dma11_partial),
2003 .dmc_txc_dma11_reset_scheduled (dmc_txc_dma11_reset_scheduled),
2004 .dmc_txc_dma11_func_num (dmc_txc_dma11_func_num[1:0]),
2005 .dmc_txc_dma11_page_handle (dmc_txc_dma11_page_handle[19:0]),
2006 .dmc_txc_dma11_descriptor (dmc_txc_dma11_descriptor[63:0]),
2007 .txc_dmc_dma11_getnxtdesc (txc_dmc_dma11_getnxtdesc),
2008 .txc_dmc_dma11_inc_head (txc_dmc_dma11_inc_head),
2009 .txc_dmc_dma11_reset_done (txc_dmc_dma11_reset_done),
2010 .txc_dmc_dma11_mark_bit (txc_dmc_dma11_mark_bit),
2011 .txc_dmc_dma11_inc_pkt_cnt (txc_dmc_dma11_inc_pkt_cnt),
2012 .dmc_txc_dma12_active (dmc_txc_dma12_active),
2013 .dmc_txc_dma12_eoflist (dmc_txc_dma12_eoflist),
2014 .dmc_txc_dma12_error (dmc_txc_dma12_error),
2015 .dmc_txc_dma12_gotnxtdesc (dmc_txc_dma12_gotnxtdesc),
2016 .dmc_txc_dma12_cacheready (dmc_txc_dma12_cacheready),
2017 .dmc_txc_dma12_partial (dmc_txc_dma12_partial),
2018 .dmc_txc_dma12_reset_scheduled (dmc_txc_dma12_reset_scheduled),
2019 .dmc_txc_dma12_func_num (dmc_txc_dma12_func_num[1:0]),
2020 .dmc_txc_dma12_page_handle (dmc_txc_dma12_page_handle[19:0]),
2021 .dmc_txc_dma12_descriptor (dmc_txc_dma12_descriptor[63:0]),
2022 .txc_dmc_dma12_getnxtdesc (txc_dmc_dma12_getnxtdesc),
2023 .txc_dmc_dma12_inc_head (txc_dmc_dma12_inc_head),
2024 .txc_dmc_dma12_reset_done (txc_dmc_dma12_reset_done),
2025 .txc_dmc_dma12_mark_bit (txc_dmc_dma12_mark_bit),
2026 .txc_dmc_dma12_inc_pkt_cnt (txc_dmc_dma12_inc_pkt_cnt),
2027 .dmc_txc_dma13_active (dmc_txc_dma13_active),
2028 .dmc_txc_dma13_eoflist (dmc_txc_dma13_eoflist),
2029 .dmc_txc_dma13_error (dmc_txc_dma13_error),
2030 .dmc_txc_dma13_gotnxtdesc (dmc_txc_dma13_gotnxtdesc),
2031 .dmc_txc_dma13_cacheready (dmc_txc_dma13_cacheready),
2032 .dmc_txc_dma13_partial (dmc_txc_dma13_partial),
2033 .dmc_txc_dma13_reset_scheduled (dmc_txc_dma13_reset_scheduled),
2034 .dmc_txc_dma13_func_num (dmc_txc_dma13_func_num[1:0]),
2035 .dmc_txc_dma13_page_handle (dmc_txc_dma13_page_handle[19:0]),
2036 .dmc_txc_dma13_descriptor (dmc_txc_dma13_descriptor[63:0]),
2037 .txc_dmc_dma13_getnxtdesc (txc_dmc_dma13_getnxtdesc),
2038 .txc_dmc_dma13_inc_head (txc_dmc_dma13_inc_head),
2039 .txc_dmc_dma13_reset_done (txc_dmc_dma13_reset_done),
2040 .txc_dmc_dma13_mark_bit (txc_dmc_dma13_mark_bit),
2041 .txc_dmc_dma13_inc_pkt_cnt (txc_dmc_dma13_inc_pkt_cnt),
2042 .dmc_txc_dma14_active (dmc_txc_dma14_active),
2043 .dmc_txc_dma14_eoflist (dmc_txc_dma14_eoflist),
2044 .dmc_txc_dma14_error (dmc_txc_dma14_error),
2045 .dmc_txc_dma14_gotnxtdesc (dmc_txc_dma14_gotnxtdesc),
2046 .dmc_txc_dma14_cacheready (dmc_txc_dma14_cacheready),
2047 .dmc_txc_dma14_partial (dmc_txc_dma14_partial),
2048 .dmc_txc_dma14_reset_scheduled (dmc_txc_dma14_reset_scheduled),
2049 .dmc_txc_dma14_func_num (dmc_txc_dma14_func_num[1:0]),
2050 .dmc_txc_dma14_page_handle (dmc_txc_dma14_page_handle[19:0]),
2051 .dmc_txc_dma14_descriptor (dmc_txc_dma14_descriptor[63:0]),
2052 .txc_dmc_dma14_getnxtdesc (txc_dmc_dma14_getnxtdesc),
2053 .txc_dmc_dma14_inc_head (txc_dmc_dma14_inc_head),
2054 .txc_dmc_dma14_reset_done (txc_dmc_dma14_reset_done),
2055 .txc_dmc_dma14_mark_bit (txc_dmc_dma14_mark_bit),
2056 .txc_dmc_dma14_inc_pkt_cnt (txc_dmc_dma14_inc_pkt_cnt),
2057 .dmc_txc_dma15_active (dmc_txc_dma15_active),
2058 .dmc_txc_dma15_eoflist (dmc_txc_dma15_eoflist),
2059 .dmc_txc_dma15_error (dmc_txc_dma15_error),
2060 .dmc_txc_dma15_gotnxtdesc (dmc_txc_dma15_gotnxtdesc),
2061 .dmc_txc_dma15_cacheready (dmc_txc_dma15_cacheready),
2062 .dmc_txc_dma15_partial (dmc_txc_dma15_partial),
2063 .dmc_txc_dma15_reset_scheduled (dmc_txc_dma15_reset_scheduled),
2064 .dmc_txc_dma15_func_num (dmc_txc_dma15_func_num[1:0]),
2065 .dmc_txc_dma15_page_handle (dmc_txc_dma15_page_handle[19:0]),
2066 .dmc_txc_dma15_descriptor (dmc_txc_dma15_descriptor[63:0]),
2067 .txc_dmc_dma15_getnxtdesc (txc_dmc_dma15_getnxtdesc),
2068 .txc_dmc_dma15_inc_head (txc_dmc_dma15_inc_head),
2069 .txc_dmc_dma15_reset_done (txc_dmc_dma15_reset_done),
2070 .txc_dmc_dma15_mark_bit (txc_dmc_dma15_mark_bit),
2071 .txc_dmc_dma15_inc_pkt_cnt (txc_dmc_dma15_inc_pkt_cnt),
2072 .arb1_txc_req_accept (arb1_txc_req_accept),
2073 .arb1_txc_req_transid (arb1_txc_req_transid[5:0]),
2074 .txc_arb1_req (txc_arb1_req),
2075 .txc_arb1_req_func_num (txc_arb1_req_func_num[1:0]),
2076 .txc_arb1_req_port_num (txc_arb1_req_port_num[1:0]),
2077 .txc_arb1_req_dma_num (txc_arb1_req_dma_num[4:0]),
2078 .txc_arb1_req_cmd (txc_arb1_req_cmd[7:0]),
2079 .txc_arb1_req_length (txc_arb1_req_length[13:0]),
2080 .txc_arb1_req_address (txc_arb1_req_address[63:0]),
2081 .meta_dmc_resp_ready (meta_dmc_resp_ready),
2082 .meta_dmc_resp_complete (meta_dmc_resp_complete),
2083 .meta_dmc_resp_transfer_cmpl (meta_dmc_resp_transfer_cmpl),
2084 .meta_dmc_data_valid (meta_dmc_data_valid),
2085 .meta_dmc_resp_client (meta_dmc_resp_client),
2086 .meta_dmc_resp_port_num (meta_dmc_resp_port_num[1:0]),
2087 .meta_dmc_resp_cmd_status (meta_dmc_resp_cmd_status[3:0]),
2088 .meta_dmc_resp_data_status (meta_dmc_resp_data_status[3:0]),
2089 .meta_dmc_resp_dma_num (meta_dmc_resp_dma_num[4:0]),
2090 .meta_dmc_resp_transID (meta_dmc_resp_trans_id[5:0]),
2091 .meta_dmc_resp_cmd (meta_dmc_resp_cmd[7:0]),
2092 .meta_dmc_resp_byteenable (meta_dmc_resp_byteenable[15:0]),
2093 .meta_dmc_resp_length (meta_dmc_resp_length[13:0]),
2094 .meta_dmc_resp_address (meta_dmc_resp_address[63:0]),
2095 .meta_dmc_data (meta_dmc_data[127:0]),
2096 .dmc_meta_resp_accept (dmc_meta_resp_accept)
2097 );
2098
2099rtx_dmo_mux rtx_dmo_mux (
2100 .clk (l1clk),
2101 .in0 (rtx_txc_txe0_dmo_dout),
2102 .in1 (rtx_txc_txe1_dmo_dout),
2103 .in2 (rtx_rxc_ipp0_mb3_dmo_dout),
2104 .in3 (rtx_rxc_ipp1_mb3_dmo_dout),
2105 .in4 (rtx_rxc_zcp0_mb7_dmo_dout),
2106 .in5 (rtx_rxc_zcp1_mb7_dmo_dout),
2107 .in6 (rtx_rxc_vlan_mb6_dmo_dout),
2108 .sel (tcu_rtx_dmo_ctl[2:0]),
2109 .out (rtx_tcu_dmo_data_out[39:0])
2110 );
2111// VPERL: GENERATED_END
2112
2113
2114endmodule
Full OpenSPARC design & verification tarball including full HDL.