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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: rtx_n2_efuhdr6_ctl.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | ||
36 | module rtx_n2_efuhdr6_ctl ( | |
37 | efu_hdr_write_data, | |
38 | efu_hdr_xfer_en, | |
39 | efu_hdr_clr, | |
40 | hdr_efu_read_data, | |
41 | hdr_efu_xfer_en, | |
42 | hdr_sram_rvalue, | |
43 | hdr_sram_rid, | |
44 | hdr_sram_wr_en, | |
45 | hdr_sram_red_clr, | |
46 | sram_hdr_read_data, | |
47 | l2clk, | |
48 | reset_l, | |
49 | tcu_pce_ov, | |
50 | tcu_aclk, | |
51 | tcu_bclk, | |
52 | tcu_scan_en, | |
53 | tcu_clk_stop, | |
54 | scan_in, | |
55 | scan_out) ; | |
56 | wire stop; | |
57 | wire se; | |
58 | wire ff_input_all_enable_scanin; | |
59 | wire ff_input_all_enable_scanout; | |
60 | wire efu_hdr_xfer_en_r1; | |
61 | wire efu_hdr_write_data_r1; | |
62 | wire efu_hdr_clr_r1; | |
63 | wire efu_hdr_xfer_en_r2; | |
64 | wire [21:0] efu_instr; | |
65 | wire [21:0] instr; | |
66 | wire [21:0] sram_read_data; | |
67 | wire [21:0] received_instr; | |
68 | wire [4:0] rdcount; | |
69 | wire [21:0] sync_read; | |
70 | wire dispatch_read_data; | |
71 | wire [21:0] reset_bus; | |
72 | wire load_shift_reg; | |
73 | wire ff_receiver_instr_slice_scanin; | |
74 | wire ff_receiver_instr_slice_scanout; | |
75 | wire wr_en; | |
76 | wire [4:0] count; | |
77 | wire [21:0] sync_instr; | |
78 | wire ff_sync_sram_data_scanin; | |
79 | wire ff_sync_sram_data_scanout; | |
80 | wire ff_sync_read_data_scanin; | |
81 | wire ff_sync_read_data_scanout; | |
82 | wire ff_sync_sram_clr_scanin; | |
83 | wire ff_sync_sram_clr_scanout; | |
84 | wire sync_clr; | |
85 | wire ff_sync_sram_wr_scanin; | |
86 | wire ff_sync_sram_wr_scanout; | |
87 | wire sync_wr; | |
88 | wire load_en; | |
89 | wire ld_rd_en; | |
90 | wire reset_count; | |
91 | wire rdreset_count; | |
92 | wire [4:0] count_in; | |
93 | wire [4:0] rdcount_in; | |
94 | wire ff_counter_slice_scanin; | |
95 | wire ff_counter_slice_scanout; | |
96 | wire ff_rd_counter_scanin; | |
97 | wire ff_rd_counter_scanout; | |
98 | ||
99 | ||
100 | // EFU to SRAM header | |
101 | input efu_hdr_write_data; | |
102 | input efu_hdr_xfer_en; | |
103 | input efu_hdr_clr; | |
104 | ||
105 | // SRAM header to EFU | |
106 | output hdr_efu_read_data; | |
107 | output hdr_efu_xfer_en; | |
108 | ||
109 | // SRAM header to SRAM | |
110 | output [10:0] hdr_sram_rvalue; | |
111 | output [10:0] hdr_sram_rid; | |
112 | output hdr_sram_wr_en; | |
113 | output hdr_sram_red_clr; | |
114 | ||
115 | // SRAM to SRAM header | |
116 | input [10:0] sram_hdr_read_data; | |
117 | ||
118 | ||
119 | // other common signals | |
120 | ||
121 | input l2clk; | |
122 | input reset_l; | |
123 | input tcu_pce_ov; | |
124 | input tcu_aclk; | |
125 | input tcu_bclk; | |
126 | input tcu_scan_en; | |
127 | input tcu_clk_stop; | |
128 | input scan_in; | |
129 | output scan_out; | |
130 | ||
131 | ||
132 | ||
133 | // scan renames | |
134 | wire pce_ov; | |
135 | wire siclk; | |
136 | wire soclk; | |
137 | ||
138 | assign pce_ov = tcu_pce_ov; | |
139 | assign stop = tcu_clk_stop; | |
140 | assign siclk = tcu_aclk; | |
141 | assign soclk = tcu_bclk; | |
142 | assign se = tcu_scan_en; | |
143 | // end scan renames | |
144 | ||
145 | ||
146 | //l1clkhdr_ctl_macro clkgen_l1clk | |
147 | // ( | |
148 | // .l2clk( l2clk ), | |
149 | // .l1en ( 1'b1 ), | |
150 | // .l1clk( l1clk_efu ) | |
151 | // ); | |
152 | ||
153 | ||
154 | rtx_n2_efuhdr6_msff_ctl_macro__library_a1__width_4 ff_input_all_enable | |
155 | ( | |
156 | .scan_in(ff_input_all_enable_scanin), | |
157 | .scan_out(ff_input_all_enable_scanout), | |
158 | .dout ({efu_hdr_xfer_en_r1,efu_hdr_write_data_r1,efu_hdr_clr_r1,efu_hdr_xfer_en_r2}), | |
159 | .din ({efu_hdr_xfer_en, efu_hdr_write_data ,efu_hdr_clr, efu_hdr_xfer_en_r1}), | |
160 | .l1clk (l2clk), | |
161 | .siclk(siclk), | |
162 | .soclk(soclk) | |
163 | ); | |
164 | ||
165 | ||
166 | assign efu_instr[21:0] = {instr[20:0],efu_hdr_write_data_r1}; | |
167 | ||
168 | assign sram_read_data[21:0] = {instr[21:11],sram_hdr_read_data[10:0]}; | |
169 | ||
170 | assign received_instr[21:0] = efu_hdr_xfer_en_r1 ? efu_instr[21:0] | |
171 | : rdcount == 5'd23 ? sync_read | |
172 | : dispatch_read_data ? ({instr[20:0],1'b0}) : 22'b0; | |
173 | ||
174 | assign reset_bus[21:0] = {reset_l, reset_l, reset_l, reset_l, reset_l, reset_l, | |
175 | reset_l, reset_l, reset_l, reset_l, reset_l, reset_l, | |
176 | reset_l, reset_l, reset_l, reset_l, reset_l, reset_l, | |
177 | reset_l, reset_l, reset_l, reset_l}; | |
178 | ||
179 | ||
180 | //assign received_instr[21:0] = efu_hdr_xfer_en_r1 ? efu_instr[21:0] : | |
181 | // (count==5'd6) ? sram_read_data[21:0] : | |
182 | // dispatch_read_data ? ({instr[20:0],1'b0}) : 22'b0; | |
183 | ||
184 | //assign load_shift_reg = efu_hdr_xfer_en_r1 | dispatch_read_data; | |
185 | assign load_shift_reg = efu_hdr_xfer_en_r1 | dispatch_read_data | rdcount == 5'd23; | |
186 | ||
187 | rtx_n2_efuhdr6_msff_ctl_macro__en_1__library_a1__width_22 ff_receiver_instr_slice | |
188 | ( | |
189 | .scan_in(ff_receiver_instr_slice_scanin), | |
190 | .scan_out(ff_receiver_instr_slice_scanout), | |
191 | .dout (instr[21:0]), | |
192 | .din (reset_bus[21:0] & received_instr[21:0]), | |
193 | .en (~reset_l | load_shift_reg), | |
194 | .l1clk (l2clk), | |
195 | .siclk(siclk), | |
196 | .soclk(soclk) | |
197 | ); | |
198 | ||
199 | // generate wr_en after 1 cycle of setup and enable bits are valid | |
200 | //assign wr_en = (count==5'd7) & sync_instr[11] & sync_instr[0]; | |
201 | assign wr_en = reset_l & (count==5'd7) & ~sync_instr[21]; | |
202 | ||
203 | rtx_n2_efuhdr6_msff_ctl_macro__en_1__library_a1__width_22 ff_sync_sram_data | |
204 | ( | |
205 | .scan_in(ff_sync_sram_data_scanin), | |
206 | .scan_out(ff_sync_sram_data_scanout), | |
207 | .dout (sync_instr[21:0]), | |
208 | .din (reset_bus[21:0] & instr[21:0]), | |
209 | .en (~reset_l | count==5'd8), | |
210 | .l1clk (l2clk), | |
211 | .siclk(siclk), | |
212 | .soclk(soclk) | |
213 | ); | |
214 | ||
215 | rtx_n2_efuhdr6_msff_ctl_macro__en_1__library_a1__width_22 ff_sync_read_data | |
216 | ( | |
217 | .scan_in(ff_sync_read_data_scanin), | |
218 | .scan_out(ff_sync_read_data_scanout), | |
219 | .dout (sync_read[21:0]), | |
220 | .din (reset_bus[21:0] & sram_read_data[21:0]), | |
221 | .en (~reset_l | count==5'd1), | |
222 | .l1clk (l2clk), | |
223 | .siclk(siclk), | |
224 | .soclk(soclk) | |
225 | ); | |
226 | ||
227 | rtx_n2_efuhdr6_msff_ctl_macro__library_a1__width_1 ff_sync_sram_clr | |
228 | ( | |
229 | .scan_in(ff_sync_sram_clr_scanin), | |
230 | .scan_out(ff_sync_sram_clr_scanout), | |
231 | .dout (sync_clr), | |
232 | .din (efu_hdr_clr_r1), | |
233 | .l1clk (l2clk), | |
234 | .siclk(siclk), | |
235 | .soclk(soclk) | |
236 | ); | |
237 | ||
238 | rtx_n2_efuhdr6_msff_ctl_macro__library_a1__width_1 ff_sync_sram_wr | |
239 | ( | |
240 | .scan_in(ff_sync_sram_wr_scanin), | |
241 | .scan_out(ff_sync_sram_wr_scanout), | |
242 | .dout (sync_wr), | |
243 | .din (wr_en), | |
244 | .l1clk (l2clk), | |
245 | .siclk(siclk), | |
246 | .soclk(soclk) | |
247 | ); | |
248 | ||
249 | ||
250 | assign load_en = (~efu_hdr_xfer_en_r2 & efu_hdr_xfer_en_r1); | |
251 | assign ld_rd_en = (count==5'd1); | |
252 | ||
253 | assign reset_count = ( count == 5'd0 ); | |
254 | assign rdreset_count = ( rdcount == 5'd0 ); | |
255 | ||
256 | assign count_in = ~reset_l ? 5'b0 : load_en ? 5'd29 : reset_count ? 5'b0 : ( count - 5'b1); | |
257 | assign rdcount_in = ~reset_l ? 5'b0 : ld_rd_en ? 5'd23 : rdreset_count ? 5'b0 : (rdcount - 5'b1); | |
258 | ||
259 | rtx_n2_efuhdr6_msff_ctl_macro__library_a1__width_5 ff_counter_slice | |
260 | ( | |
261 | .scan_in(ff_counter_slice_scanin), | |
262 | .scan_out(ff_counter_slice_scanout), | |
263 | .dout (count[4:0]), | |
264 | .din (count_in[4:0]), | |
265 | .l1clk (l2clk), | |
266 | .siclk(siclk), | |
267 | .soclk(soclk) | |
268 | ); | |
269 | ||
270 | rtx_n2_efuhdr6_msff_ctl_macro__library_a1__width_5 ff_rd_counter | |
271 | ( | |
272 | .scan_in(ff_rd_counter_scanin), | |
273 | .scan_out(ff_rd_counter_scanout), | |
274 | .dout (rdcount[4:0]), | |
275 | .din (rdcount_in[4:0]), | |
276 | .l1clk (l2clk), | |
277 | .siclk(siclk), | |
278 | .soclk(soclk) | |
279 | ); | |
280 | ||
281 | //spare_ctl_macro spares (num=4) ( | |
282 | // .scan_in(spares_scanin), | |
283 | // .scan_out(spares_scanout), | |
284 | // .l1clk (l2clk) | |
285 | //); | |
286 | ||
287 | ||
288 | ||
289 | //assign hdr_sram_rvalue[10:0] = instr[10:0]; | |
290 | //assign hdr_sram_rid[10:0] = instr[21:11]; | |
291 | //assign hdr_sram_red_clr = efu_hdr_clr_r1; | |
292 | //assign hdr_sram_wr_en = |(count[1:0]); | |
293 | assign hdr_sram_rvalue[10:0] = sync_instr[10:0]; | |
294 | assign hdr_sram_rid[10:0] = {sync_instr[21],1'b0,sync_instr[20:12]}; | |
295 | assign hdr_sram_red_clr = sync_clr; | |
296 | assign hdr_sram_wr_en = sync_wr; | |
297 | ||
298 | ||
299 | //assign dispatch_read_data = (count[4:0]>5'd7); | |
300 | assign dispatch_read_data = (rdcount[4:0] < 5'd23 & rdcount[4:0] != 5'd0); | |
301 | ||
302 | assign hdr_efu_read_data = instr[21]; | |
303 | assign hdr_efu_xfer_en = dispatch_read_data; | |
304 | ||
305 | // fixscan start: | |
306 | assign ff_input_all_enable_scanin = scan_in; | |
307 | assign ff_receiver_instr_slice_scanin = ff_input_all_enable_scanout; | |
308 | assign ff_counter_slice_scanin = ff_receiver_instr_slice_scanout; | |
309 | assign ff_sync_sram_data_scanin = ff_counter_slice_scanout; | |
310 | assign ff_sync_read_data_scanin = ff_sync_sram_data_scanout; | |
311 | assign ff_sync_sram_clr_scanin = ff_sync_read_data_scanout; | |
312 | assign ff_sync_sram_wr_scanin = ff_sync_sram_clr_scanout; | |
313 | assign ff_rd_counter_scanin = ff_sync_sram_wr_scanout; | |
314 | assign scan_out = ff_rd_counter_scanout; | |
315 | ||
316 | //assign spares_scanin = ff_rd_counter_scanout ; | |
317 | //assign scan_out = spares_scanout ; | |
318 | // fixscan end: | |
319 | endmodule | |
320 | ||
321 | ||
322 | ||
323 | ||
324 | ||
325 | ||
326 | // any PARAMS parms go into naming of macro | |
327 | ||
328 | module rtx_n2_efuhdr6_msff_ctl_macro__library_a1__width_4 ( | |
329 | din, | |
330 | l1clk, | |
331 | scan_in, | |
332 | siclk, | |
333 | soclk, | |
334 | dout, | |
335 | scan_out); | |
336 | wire [3:0] fdin; | |
337 | wire [3:1] sout; | |
338 | ||
339 | input [3:0] din; | |
340 | input l1clk; | |
341 | input scan_in; | |
342 | ||
343 | ||
344 | input siclk; | |
345 | input soclk; | |
346 | ||
347 | output [3:0] dout; | |
348 | output scan_out; | |
349 | assign fdin[3:0] = din[3:0]; | |
350 | ||
351 | ||
352 | ||
353 | ||
354 | ||
355 | ||
356 | ||
357 | ||
358 | ||
359 | ||
360 | ||
361 | ||
362 | ||
363 | ||
364 | ||
365 | ||
366 | ||
367 | cl_a1_msff_4x d0_0 ( | |
368 | .l1clk(l1clk), | |
369 | .siclk(siclk), | |
370 | .soclk(soclk), | |
371 | .d(fdin[0]), | |
372 | .si(sout[1]), | |
373 | .so(scan_out), | |
374 | .q(dout[0]) | |
375 | ); | |
376 | cl_a1_msff_4x d0_1 ( | |
377 | .l1clk(l1clk), | |
378 | .siclk(siclk), | |
379 | .soclk(soclk), | |
380 | .d(fdin[1]), | |
381 | .si(sout[2]), | |
382 | .so(sout[1]), | |
383 | .q(dout[1]) | |
384 | ); | |
385 | cl_a1_msff_4x d0_2 ( | |
386 | .l1clk(l1clk), | |
387 | .siclk(siclk), | |
388 | .soclk(soclk), | |
389 | .d(fdin[2]), | |
390 | .si(sout[3]), | |
391 | .so(sout[2]), | |
392 | .q(dout[2]) | |
393 | ); | |
394 | cl_a1_msff_4x d0_3 ( | |
395 | .l1clk(l1clk), | |
396 | .siclk(siclk), | |
397 | .soclk(soclk), | |
398 | .d(fdin[3]), | |
399 | .si(scan_in), | |
400 | .so(sout[3]), | |
401 | .q(dout[3]) | |
402 | ); | |
403 | ||
404 | ||
405 | ||
406 | ||
407 | endmodule | |
408 | ||
409 | ||
410 | ||
411 | ||
412 | ||
413 | ||
414 | ||
415 | ||
416 | ||
417 | ||
418 | ||
419 | ||
420 | ||
421 | // any PARAMS parms go into naming of macro | |
422 | ||
423 | module rtx_n2_efuhdr6_msff_ctl_macro__en_1__library_a1__width_22 ( | |
424 | din, | |
425 | en, | |
426 | l1clk, | |
427 | scan_in, | |
428 | siclk, | |
429 | soclk, | |
430 | dout, | |
431 | scan_out); | |
432 | wire [21:0] fdin; | |
433 | wire [21:1] sout; | |
434 | ||
435 | input [21:0] din; | |
436 | input en; | |
437 | input l1clk; | |
438 | input scan_in; | |
439 | ||
440 | ||
441 | input siclk; | |
442 | input soclk; | |
443 | ||
444 | output [21:0] dout; | |
445 | output scan_out; | |
446 | assign fdin[21:0] = (din[21:0] & {22{en}}) | (dout[21:0] & ~{22{en}}); | |
447 | ||
448 | ||
449 | ||
450 | ||
451 | ||
452 | ||
453 | ||
454 | ||
455 | ||
456 | ||
457 | ||
458 | ||
459 | ||
460 | ||
461 | ||
462 | ||
463 | ||
464 | cl_a1_msff_4x d0_0 ( | |
465 | .l1clk(l1clk), | |
466 | .siclk(siclk), | |
467 | .soclk(soclk), | |
468 | .d(fdin[0]), | |
469 | .si(sout[1]), | |
470 | .so(scan_out), | |
471 | .q(dout[0]) | |
472 | ); | |
473 | cl_a1_msff_4x d0_1 ( | |
474 | .l1clk(l1clk), | |
475 | .siclk(siclk), | |
476 | .soclk(soclk), | |
477 | .d(fdin[1]), | |
478 | .si(sout[2]), | |
479 | .so(sout[1]), | |
480 | .q(dout[1]) | |
481 | ); | |
482 | cl_a1_msff_4x d0_2 ( | |
483 | .l1clk(l1clk), | |
484 | .siclk(siclk), | |
485 | .soclk(soclk), | |
486 | .d(fdin[2]), | |
487 | .si(sout[3]), | |
488 | .so(sout[2]), | |
489 | .q(dout[2]) | |
490 | ); | |
491 | cl_a1_msff_4x d0_3 ( | |
492 | .l1clk(l1clk), | |
493 | .siclk(siclk), | |
494 | .soclk(soclk), | |
495 | .d(fdin[3]), | |
496 | .si(sout[4]), | |
497 | .so(sout[3]), | |
498 | .q(dout[3]) | |
499 | ); | |
500 | cl_a1_msff_4x d0_4 ( | |
501 | .l1clk(l1clk), | |
502 | .siclk(siclk), | |
503 | .soclk(soclk), | |
504 | .d(fdin[4]), | |
505 | .si(sout[5]), | |
506 | .so(sout[4]), | |
507 | .q(dout[4]) | |
508 | ); | |
509 | cl_a1_msff_4x d0_5 ( | |
510 | .l1clk(l1clk), | |
511 | .siclk(siclk), | |
512 | .soclk(soclk), | |
513 | .d(fdin[5]), | |
514 | .si(sout[6]), | |
515 | .so(sout[5]), | |
516 | .q(dout[5]) | |
517 | ); | |
518 | cl_a1_msff_4x d0_6 ( | |
519 | .l1clk(l1clk), | |
520 | .siclk(siclk), | |
521 | .soclk(soclk), | |
522 | .d(fdin[6]), | |
523 | .si(sout[7]), | |
524 | .so(sout[6]), | |
525 | .q(dout[6]) | |
526 | ); | |
527 | cl_a1_msff_4x d0_7 ( | |
528 | .l1clk(l1clk), | |
529 | .siclk(siclk), | |
530 | .soclk(soclk), | |
531 | .d(fdin[7]), | |
532 | .si(sout[8]), | |
533 | .so(sout[7]), | |
534 | .q(dout[7]) | |
535 | ); | |
536 | cl_a1_msff_4x d0_8 ( | |
537 | .l1clk(l1clk), | |
538 | .siclk(siclk), | |
539 | .soclk(soclk), | |
540 | .d(fdin[8]), | |
541 | .si(sout[9]), | |
542 | .so(sout[8]), | |
543 | .q(dout[8]) | |
544 | ); | |
545 | cl_a1_msff_4x d0_9 ( | |
546 | .l1clk(l1clk), | |
547 | .siclk(siclk), | |
548 | .soclk(soclk), | |
549 | .d(fdin[9]), | |
550 | .si(sout[10]), | |
551 | .so(sout[9]), | |
552 | .q(dout[9]) | |
553 | ); | |
554 | cl_a1_msff_4x d0_10 ( | |
555 | .l1clk(l1clk), | |
556 | .siclk(siclk), | |
557 | .soclk(soclk), | |
558 | .d(fdin[10]), | |
559 | .si(sout[11]), | |
560 | .so(sout[10]), | |
561 | .q(dout[10]) | |
562 | ); | |
563 | cl_a1_msff_4x d0_11 ( | |
564 | .l1clk(l1clk), | |
565 | .siclk(siclk), | |
566 | .soclk(soclk), | |
567 | .d(fdin[11]), | |
568 | .si(sout[12]), | |
569 | .so(sout[11]), | |
570 | .q(dout[11]) | |
571 | ); | |
572 | cl_a1_msff_4x d0_12 ( | |
573 | .l1clk(l1clk), | |
574 | .siclk(siclk), | |
575 | .soclk(soclk), | |
576 | .d(fdin[12]), | |
577 | .si(sout[13]), | |
578 | .so(sout[12]), | |
579 | .q(dout[12]) | |
580 | ); | |
581 | cl_a1_msff_4x d0_13 ( | |
582 | .l1clk(l1clk), | |
583 | .siclk(siclk), | |
584 | .soclk(soclk), | |
585 | .d(fdin[13]), | |
586 | .si(sout[14]), | |
587 | .so(sout[13]), | |
588 | .q(dout[13]) | |
589 | ); | |
590 | cl_a1_msff_4x d0_14 ( | |
591 | .l1clk(l1clk), | |
592 | .siclk(siclk), | |
593 | .soclk(soclk), | |
594 | .d(fdin[14]), | |
595 | .si(sout[15]), | |
596 | .so(sout[14]), | |
597 | .q(dout[14]) | |
598 | ); | |
599 | cl_a1_msff_4x d0_15 ( | |
600 | .l1clk(l1clk), | |
601 | .siclk(siclk), | |
602 | .soclk(soclk), | |
603 | .d(fdin[15]), | |
604 | .si(sout[16]), | |
605 | .so(sout[15]), | |
606 | .q(dout[15]) | |
607 | ); | |
608 | cl_a1_msff_4x d0_16 ( | |
609 | .l1clk(l1clk), | |
610 | .siclk(siclk), | |
611 | .soclk(soclk), | |
612 | .d(fdin[16]), | |
613 | .si(sout[17]), | |
614 | .so(sout[16]), | |
615 | .q(dout[16]) | |
616 | ); | |
617 | cl_a1_msff_4x d0_17 ( | |
618 | .l1clk(l1clk), | |
619 | .siclk(siclk), | |
620 | .soclk(soclk), | |
621 | .d(fdin[17]), | |
622 | .si(sout[18]), | |
623 | .so(sout[17]), | |
624 | .q(dout[17]) | |
625 | ); | |
626 | cl_a1_msff_4x d0_18 ( | |
627 | .l1clk(l1clk), | |
628 | .siclk(siclk), | |
629 | .soclk(soclk), | |
630 | .d(fdin[18]), | |
631 | .si(sout[19]), | |
632 | .so(sout[18]), | |
633 | .q(dout[18]) | |
634 | ); | |
635 | cl_a1_msff_4x d0_19 ( | |
636 | .l1clk(l1clk), | |
637 | .siclk(siclk), | |
638 | .soclk(soclk), | |
639 | .d(fdin[19]), | |
640 | .si(sout[20]), | |
641 | .so(sout[19]), | |
642 | .q(dout[19]) | |
643 | ); | |
644 | cl_a1_msff_4x d0_20 ( | |
645 | .l1clk(l1clk), | |
646 | .siclk(siclk), | |
647 | .soclk(soclk), | |
648 | .d(fdin[20]), | |
649 | .si(sout[21]), | |
650 | .so(sout[20]), | |
651 | .q(dout[20]) | |
652 | ); | |
653 | cl_a1_msff_4x d0_21 ( | |
654 | .l1clk(l1clk), | |
655 | .siclk(siclk), | |
656 | .soclk(soclk), | |
657 | .d(fdin[21]), | |
658 | .si(scan_in), | |
659 | .so(sout[21]), | |
660 | .q(dout[21]) | |
661 | ); | |
662 | ||
663 | ||
664 | ||
665 | ||
666 | endmodule | |
667 | ||
668 | ||
669 | ||
670 | ||
671 | ||
672 | ||
673 | ||
674 | ||
675 | ||
676 | ||
677 | ||
678 | ||
679 | ||
680 | // any PARAMS parms go into naming of macro | |
681 | ||
682 | module rtx_n2_efuhdr6_msff_ctl_macro__library_a1__width_1 ( | |
683 | din, | |
684 | l1clk, | |
685 | scan_in, | |
686 | siclk, | |
687 | soclk, | |
688 | dout, | |
689 | scan_out); | |
690 | wire [0:0] fdin; | |
691 | ||
692 | input [0:0] din; | |
693 | input l1clk; | |
694 | input scan_in; | |
695 | ||
696 | ||
697 | input siclk; | |
698 | input soclk; | |
699 | ||
700 | output [0:0] dout; | |
701 | output scan_out; | |
702 | assign fdin[0:0] = din[0:0]; | |
703 | ||
704 | ||
705 | ||
706 | ||
707 | ||
708 | ||
709 | ||
710 | ||
711 | ||
712 | ||
713 | ||
714 | ||
715 | ||
716 | ||
717 | ||
718 | ||
719 | ||
720 | cl_a1_msff_4x d0_0 ( | |
721 | .l1clk(l1clk), | |
722 | .siclk(siclk), | |
723 | .soclk(soclk), | |
724 | .d(fdin[0]), | |
725 | .si(scan_in), | |
726 | .so(scan_out), | |
727 | .q(dout[0]) | |
728 | ); | |
729 | ||
730 | ||
731 | ||
732 | ||
733 | endmodule | |
734 | ||
735 | ||
736 | ||
737 | ||
738 | ||
739 | ||
740 | ||
741 | ||
742 | ||
743 | ||
744 | ||
745 | ||
746 | ||
747 | // any PARAMS parms go into naming of macro | |
748 | ||
749 | module rtx_n2_efuhdr6_msff_ctl_macro__library_a1__width_5 ( | |
750 | din, | |
751 | l1clk, | |
752 | scan_in, | |
753 | siclk, | |
754 | soclk, | |
755 | dout, | |
756 | scan_out); | |
757 | wire [4:0] fdin; | |
758 | wire [4:1] sout; | |
759 | ||
760 | input [4:0] din; | |
761 | input l1clk; | |
762 | input scan_in; | |
763 | ||
764 | ||
765 | input siclk; | |
766 | input soclk; | |
767 | ||
768 | output [4:0] dout; | |
769 | output scan_out; | |
770 | assign fdin[4:0] = din[4:0]; | |
771 | ||
772 | ||
773 | ||
774 | ||
775 | ||
776 | ||
777 | ||
778 | ||
779 | ||
780 | ||
781 | ||
782 | ||
783 | ||
784 | ||
785 | ||
786 | ||
787 | ||
788 | cl_a1_msff_4x d0_0 ( | |
789 | .l1clk(l1clk), | |
790 | .siclk(siclk), | |
791 | .soclk(soclk), | |
792 | .d(fdin[0]), | |
793 | .si(sout[1]), | |
794 | .so(scan_out), | |
795 | .q(dout[0]) | |
796 | ); | |
797 | cl_a1_msff_4x d0_1 ( | |
798 | .l1clk(l1clk), | |
799 | .siclk(siclk), | |
800 | .soclk(soclk), | |
801 | .d(fdin[1]), | |
802 | .si(sout[2]), | |
803 | .so(sout[1]), | |
804 | .q(dout[1]) | |
805 | ); | |
806 | cl_a1_msff_4x d0_2 ( | |
807 | .l1clk(l1clk), | |
808 | .siclk(siclk), | |
809 | .soclk(soclk), | |
810 | .d(fdin[2]), | |
811 | .si(sout[3]), | |
812 | .so(sout[2]), | |
813 | .q(dout[2]) | |
814 | ); | |
815 | cl_a1_msff_4x d0_3 ( | |
816 | .l1clk(l1clk), | |
817 | .siclk(siclk), | |
818 | .soclk(soclk), | |
819 | .d(fdin[3]), | |
820 | .si(sout[4]), | |
821 | .so(sout[3]), | |
822 | .q(dout[3]) | |
823 | ); | |
824 | cl_a1_msff_4x d0_4 ( | |
825 | .l1clk(l1clk), | |
826 | .siclk(siclk), | |
827 | .soclk(soclk), | |
828 | .d(fdin[4]), | |
829 | .si(scan_in), | |
830 | .so(sout[4]), | |
831 | .q(dout[4]) | |
832 | ); | |
833 | ||
834 | ||
835 | ||
836 | ||
837 | endmodule | |
838 | ||
839 | ||
840 | ||
841 | ||
842 | ||
843 | ||
844 | ||
845 |